áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR JUNE 2001 REV. 1.1.0 GENERAL DESCRIPTION The XRT82L34 is a fully integrated Quad (four channels) short-haul line interface unit for T1(1.544Mbps) 100Ω and E1(2.048Mbps) 75Ω or 120Ω applications. Each channel consists of a receiver with equalizer for reliable data and clock recovery, and a transmitter which accepts either single or dual-rail digital inputs for signal transmission to the line using a low output impedance line driver. The device also includes a crystal-less jitter attenuator which, depending on system requirements, can be selected in the receive or transmit path through the Host or Hardware Mode control. XRT82L34 is a low power CMOS device operating on a single 3.3V supply with 5V tolerant digital inputs. FEATURES • Fully integrated quad, short-haul PCM transceivers for E1 and T1 applications. • On Chip Receive Equalizer and Transmit Pulse Shaper for DS1 Digital Cross Connect (DSX-1) and CEPT 75Ω and 120Ω line terminations • Crystal-less jitter attenuator can be selected in the transmit or receive path • High receiver interference immunity • Per-channel transmit power shutdown • Tri-state transmit output capability • On chip per-channel driver failure monitoring circuit • On chip HDB3/B8ZS/AMI encoder/decoder functions • Transmit return loss meets or exceeds ETSI 300 166 standard • Meets or exceeds specifications in ITU G.703, G.775, G.736 and G.823; Bellcore GR-499-CORE; ANSI T1.403 and ETSI 300-166 • 3.3V or 5.0V Logic level inputs • Single +3.3V Supply Operation APPLICATIONS • Digital cross connects (DSX-1) • Channel Banks • High speed data transmission line cards • On chip clock recovery circuit • T1/E1 Multiplexer • Transformer or capacitor coupled receiver inputs • Public switching systems and PBX interfaces FIGURE 1. BLOCK DIAGRAM OF THE XRT82L34 T1/E1/J1 LIU (HOST MODE) Driver Monitor TxClk[n] TxPOS[n]/TDATA[n] TxNEG[n] HDB3/ B8ZS Encoder Enable/ Disable RxClk[n] RxPOS[n]/RDATA[n] RxNEG[n]/LCV[n] MUX Tx/Rx Jitter Attenuator Tx Timing Control Tx Pulse Shaper Remote LoopBack Digital LoopBack HDB3/ B8ZS Decoder MUX Tx/Rx Jitter Attenuator Timing & Data Recovery TTIP[n] TRing[n] Line Driver Local Analog LoopBack Clock Generator TVDD[n] TGND[n] MClk Peak Detector & Slicer Rx Equalizer RTIP[n] RRing[n] LOS Detect RxLOS[n] Channel 0 Channel 1 Channel 2 Channel 3 INT RDY_DTACK PClk/Codes PTS1/ClkE PTS2/SR_DR Reset ICT µP Controller & Hardware Interface Test ADD [0:3] D[0:7] WR_R/W/TxOFF0 ALE_AS/TxOFF2 CS/TxOFF3 RD_DS/TxOFF1 HW/HOST Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 FIGURE 2. BLOCK DIAGRAM OF THE XRT82L34 T1/E1/J LIU (HARDWARE MODE) Driver Monitor One of four channels TxClk[n] TxPOS [n]/TDATA[n] TxNEG[n] HDB3/ B8ZS Encoder Enable/ Disable RxClk[n] RxPOS[n]/RDATA[n] RxNEG[n]/LCV[n] Tx/Rx Jitter Attenuator Tx Timing Control Tx Pulse Shaper Remote LoopBack Digital LoopBack HDB3/ B8ZS Decoder Tx/Rx Jitter Attenuator Timing & Data Recovery TTIP[n] TRing[n] Local Analog LoopBack Clock Generator MUX Line Driver TGND[n] MClk Peak Detector & Slicer Rx Equalizer RTIP[n] RRing[n] LOS Detect RxLOS[n] INT RDY_DTACK PClk/Codes PTS1/ClkE PTS2/SR/DR Reset WR_R/W/TxOFF0 ALE_AS/TxOFF2 CS/TxOFF3 RD_DS/TxOFF1 HW/HOST ICT MUX TVDD[n] µP Controler & Hardware Interface Test 2 ADD[0]/ECC ADD[1]/ECD ADD[2]/ECA ADD[3]/RxMute D[0]/FIFOS D[1]/LOOPEN0 D[2]/LOOPEN1 D[3]/LOOPEN2 D[4]LOOPEN3 D[5]/LOOPSEL D[6]/RxJA D[7]TxJA áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XRT82L34IV 100 Lead TQFP (14 x 14 x 1.4mm) -40°C to +85°C 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 RxPOS_0/RData_0 RxNEG_0/LCV_0 DVDD DGND AGND RRing_0 RTIP_0 AVDD TGND_0 TRing_0 TVDD_0 TTIP_0 AVDD TTIP_3 TVDD_3 TRing_3 TGND_3 AVDD RTIP_3 RRing_3 AGND DGND DVDD RxNEG_3/LCV_3 RxPOS_3/RData_3 FIGURE 3. PIN OUT OF THE XRT82L34 XRT82L34 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RxPOS_1/RData_1 RxNEG_1/LCV_1 DVDD DGND DGND RRing_1 RTIP_1 DVDD TGND_1 TRing_1 TVDD_1 TTIP_1 AGND TTIP_2 TVDD_2 TRing_2 TGND_2 AVDD RTIP_2 RRing_2 AGND DGND(PLL) DVDD(PLL) RxNEG_2/LCV_2 RxPOS_2/RData_2 RxClk_0 RxLOS_0 TxNEG_0 TxPOS_0/TData_0 TxClk_0 Reset PTS1/ClkE PTS2/SR/DR HW/HOST PClk/Codes DGND DVDD DGND WR_R/W/TxOFF_0 RD_DS/TxOFF_1 ALE_AS/TxOFF_2 CS/TxOFF_3 RDY_DTACK INT ICT TxClk_1 TxPOS_1/TData_1 TxNEG_1 RxLOS_1 RxClk_1 3 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RxClk_3 RxLOS_3 TxNEG_3 TxPOS_3/TData_3 TxClk_3 A[0]/ECC A[1]/ECB A[2]/ECA A[3]/RxMute MClk DGND DVDD D[0]/FIFOS D[1]/LOOPEN_0 D[2]/LOOPEN_1 D[3]/LOOPEN_2 D[4]/LOOPEN_3 D[5]/LOOPSEL D[6]/RxJA D[7]/TxJA TxClk_2 TxPOS_2/TData_2 TxNEG_2 RxLOS_2 RxClk_2 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE OF CONTENTS GENERAL DESCRIPTION ................................................................................................. 1 FEATURES .................................................................................................................................................... APPLICATIONS .............................................................................................................................................. Figure 1. Block Diagram of the XRT82L34 T1/E1/J1 LIU (Host Mode) ................................................. Figure 2. Block Diagram of the XRT82L34 T1/E1/J LIU (Hardware Mode) ........................................... Figure 3. Pin Out of the XRT82L34 .......................................................................................................... 1 1 1 2 3 TABLE OF CONTENTS ....................................................................................................... I PIN DESCRIPTIONS - BY FUNCTION ............................................................................... 4 MICROPROCESSOR PINS ............................................................................................................................... 4 RECEIVER .................................................................................................................................................... 6 TRANSMITTER ............................................................................................................................................... 7 CONTROL, ALARM, AND OTHER ..................................................................................................................... 8 JITTER ATTENUATOR .................................................................................................................................. 10 POWER AND GROUND ................................................................................................................................. 11 SYSTEM-FUNCTIONAL DESCRIPTION ......................................................................... 12 RECEIVER .................................................................................................................................................. 12 JITTER ATTENUATOR .................................................................................................................................. 12 HDB3/B8ZS DECODER .............................................................................................................................. 12 RECEIVER LOSS OF SIGNAL (LOS) .............................................................................................................. 12 CLOCK SIGNALS GENERATED WHEN LOS IS DECLARED ................................................................................ 12 DECLARING AND CLEARING LOS IN THE DS1 MODE. ................................................................................... 13 CONDITIONS FOR DECLARING AND CLEARING LOS IN THE E1 MODE. ............................................................ 13 RECEIVE DATA MUTING .............................................................................................................................. 13 LOOP-BACK MODES .............................................................................................................................. 13 REMOTE LOOP-BACK (RLOOP) MODE ...................................................................................................... 13 DIGITAL LOCAL LOOP-BACK (DLOOP) MODE ............................................................................................... 14 ANALOG LOCAL LOOP-BACK (ALOOP) MODE .............................................................................................. 14 Figure 4. Remote Loop-Back with jitter attenuator selected in receive path .................................... 14 Figure 5. Remote Loop-Back with jitter attenuator selected in transmit path .................................. 14 Figure 6. Digital Local Loop-Back with option to transmit all “ones” to the line (JA selected & in receive path) .............................................................................................................................. 15 Figure 7. Digital Local Loop-Back with option to transmit all “ones” to the line (JA selected & in transmit path) ......................................................................................................................... 15 Figure 8. Analog Local Loop-Back signal flow Jitter Attenuator selected & in Receive path ........ 16 Figure 9. Analog Local Loop-Back signal flow Jitter Attenuator selected & in transmit path ........ 16 RESET OPERATION ..................................................................................................................................... 16 RECEIVER MODES OF OPERATION ............................................................................................................... 16 RECEIVE DATA INVERT MODE ..................................................................................................................... 16 Figure 10. Data changes on rising edge of Clk and Data is sampled on falling edge ..................... 17 Figure 11. Data changes on falling edge of Clk and is sampled on rising edge .............................. 17 TRANSMIT CLOCK SAMPLING EDGE ............................................................................................................. 17 SINGLE RAIL, DUAL RAIL .............................................................................................................................. 17 TRANSMIT ALL ONES (TAOS) ..................................................................................................................... 17 HDB3/B8ZS/AMI ENCODER ....................................................................................................................... 17 TRANSMIT PULSE SHAPER .......................................................................................................................... 18 DRIVER MONITOR ....................................................................................................................................... 18 TRANSMIT OFF CONTROL ............................................................................................................................ 18 TABLE 1: EXAMPLES OF B8ZS ENCODING .................................................................................................. 18 TABLE 2: TRANSMIT EQUALIZER CONTROL ................................................................................................. 18 INTERFACING THE XRT82L34 TO THE LINE ................................................................................................. 18 Figure 12. XRT82L34 Channel_0 in an E1 unbalanced 75 W application - 1:2 or (1:2.45) transformer 19 I áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 Figure 13. XRT82L34 Channel_0 - E1 120 W balanced application - 1:2 or (1:2.45) transformer ... Figure 14. XRT82L34 Channel_0 - DS1 100 W Balanced application ................................................ TABLE 3: E1 RECEIVER ELECTRICAL CHARACTERISTICS ............................................................................. TABLE 4: T1 RECEIVER ELECTRICAL CHARACTERISTICS ............................................................................. TABLE 5: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS ....................................................................... TABLE 6: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS ....................................................................... TABLE 7: TRANSMIT PULSE MASK SPECIFICATION ...................................................................................... Figure 15. ITU G.703 E1 Pulse Template .............................................................................................. TABLE 8: DS1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS. .................................................... Figure 16. DSX-1 Pulse Template ......................................................................................................... TABLE 9: DC ELECTRICAL CHARACTERISTICS ............................................................................................ TABLE 10: POWER DISSIPATION (XRT82L34 ONLY) ................................................................................... TABLE 11: POWER CONSUMPTION (XRT82L34 AND LOAD: PD=VDD X IDD) ............................................... 19 20 21 22 23 23 24 24 25 25 26 26 26 ABSOLUTE MAXIMUM RATINGS ................................................................................... 27 TABLE 12: AC ELECTRICAL CHARACTERISTICS .......................................................................................... 27 Figure 17. Transmit Clock and Input Data Timing .............................................................................. 28 Figure 18. Receive Clock and Output Data Timing. ............................................................................ 28 TABLE 13: MICROPROCESSOR INTERFACE SIGNAL ...................................................................................... 29 TABLE 14: MICROPROCESSOR REGISTER MAP ........................................................................................... 30 TABLE 15: COMMAND CONTROL REGISTER 0 ............................................................................................. 31 TABLE 16: COMMAND CONTROL REGISTER 1 ............................................................................................. 32 TABLE 17: CHANNEL STATUS REGISTER .................................................................................................... 33 TABLE 18: CHANNEL MASK REGISTER ....................................................................................................... 34 TABLE 19: CHANNEL CONTROL REGISTER ................................................................................................ 35 Figure 19. Intel Interface Timing (Read) ............................................................................................... 36 Figure 20. Intel Interface Timing (Write) ............................................................................................... 36 TABLE 20: INTEL INTERFACE TIMING SPECIFICATIONS ................................................................................. 37 Figure 21. Microprocessor Interface Timing - Motorola Type Programmed I/O Read Operation ... 38 Figure 22. Microprocessor Interface Timing - Motorola Type Programmed I/O Write Operation ... 38 Figure 23. Microprocessor Interface Timing - Reset Pulse Width ..................................................... 38 TABLE 21: MOTOROLA INTERFACE TIMING SPECIFICATION .......................................................................... 39 JITTER TOLERANCE IN DS1 APPLICATIONS .................................................................................................. 40 Figure 24. Input Jitter Tolerance performance of the XRT82L34, for DS1 Applications, with the Jitter Attenuator Disabled .............................................................................................................. 40 JITTER ATTENUATOR ENABLED AND CONFIGURED TO OPERATE IN THE RECEIVE PATH ................................. 41 Figure 25. Input Jitter Tolerance Capability of the XRT82L34 for DS1 Applications with the Jitter Attenuator Enabled and operating in the Receive Path ........................................................ 41 JITTER TRANSFER CHARACTERISTICS OF THE XRT82L34 CONFIGURED TO OPERATE IN THE DS1 MODE ...... 42 Figure 26. Jitter Transfer Characteristics of the XRT82L34 for DS1 Applications with the Jitter Attenuator Enabled and Operating in the Receive Path ............................................................. 42 APPENDIX A ..................................................................................................................... 43 XRT82LL34 AND XRT82L24 EVALUATION KIT (XRT82L34/L24EVAL) ...................................................... 43 Figure 27. XRT82L34/L24 GUI Software Interface for Evaluating the XRT82L24/L34EVAL Application Board ...................................................................................................................................... 43 Figure 28. Photograph of the XRT82L34/L24EVAL Application Board ............................................. 44 Figure 29. Block Layout of the XRT82L34/L24EVAL Application Board ........................................... 45 ORDERING INFORMATION ............................................................................................................................ 46 PACKAGE DIMENSIONS 100 LEAD TQFP 14X14MM ..................................................................................... 46 REVISION HISTORY ..................................................................................................................................... 47 II áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 PIN DESCRIPTIONS - BY FUNCTION MICROPROCESSOR PINS PIN # NAME TYPE 7 PTS1 I DESCRIPTION Processor Type Select bit 1: Host Mode In Host Mode the appropriate bits are set in the command mode PTS1 PTS2 0 0 8HC11,8081,80C188 (async.) 1 0 Motorola 68K (async.) 0 1 Intel x86 (sync.) 1 1 Intel i906,Motorola 860 (sync.) 8 PTS2 I Host Mode: Processor Type Select Input bit 2: See description for pin 7. 10 PCLK I Processor Clock Input. Input clock for synchronous microprocessor operation. Maximum clock rate is 16 MHz. This pin is internally pull-up for asynchronous microprocessor interface when no clock is present. 14 WR_R/W I Write Input (Read/Write). With Intel bus timing, a Low pulse on WR selects a write operation when CS pin is Low. When configured in Motorola bus timing, a "High" pulse on R/W selects a read operation and a Low pulse on R/W selects a write operation when CS is Low. 15 RD_DS I Read Input (Data Strobe). With Intel bus timing, a Low pulse on RD selects a read operation when CS pin is Low. When configured in Motorola bus timing, a Low pulse on DS indicates a read or write operation when CS pin is Low. 16 ALE_AS I Address Latch Input (Address Strobe). With Intel bus timing, the address inputs are latched into the internal register on the falling edge of ALE. When configured in Motorola bus timing, the address inputs are latched into the internal register on the falling edge of AS. 17 CS I Chip Select Input. This signal must be Low in order to access the parallel port. 18 RDY_DTACK O Ready Output (Data Transfer Acknowledge Output). With Intel bus timing, RDY is asserted "High" to indicate the device has completed a read or write operation. When configured in Motorola bus timing, DTACK is asserted Low to indicate the device has completed a read or write cycle. NOTE: Internally pulled -up with a 50kΩ resistor. 4 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 MICROPROCESSOR PINS PIN # NAME TYPE 63 62 61 60 59 58 57 56 D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] I/O 70 69 68 67 A[0] A[1] A[2] A[3] I DESCRIPTION Data Bus[7:0]. Microprocessor read/write data bus Host Mode, Microprocessor Interface Address Bus [3:0]. 5 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 RECEIVER PIN # NAME TYPE 1 25 51 75 RxCLK_0 RxCLK_1 RxCLK_2 RxCLK_3 O Receiver_n Clock Output 2 24 52 74 RxLOS_0 RxLOS_1 RxLOS_2 RxLOS_3 O Receiver_n Loss of Signal. This signal is asserted "High" to indicate loss of signal at the receive input. 100 RxPOS_0 O Receiver_n Positive Data Output: In dual-rail mode, p-rail data are sent to the framer. Receiver 0 NRZ Data Output: In single-rail mode, the received data are sent in NRZ format to the framer. O Receiver_n Negative Data Output: In dual-rail mode, n-rail data are sent to the framer. Line Code Violation Output: In single-rail mode, this signal output "High" for one receive clock cycle to indicate a code violation is detected in the received data. If AMI coding is selected, every bipolar violation received will cause this pin to go "High". /RData_0 26 50 76 RxPOS_1/RData_1 RxPOS_2/RData_2 RxPOS_3/RData_3 99 RxNEG_0 /LCV_0 DESCRIPTION 27 49 77 RxNEG_1/LCV_1 RxNEG_2/LCV_2 RxNEG_3/LCV_0 94 32 44 82 RTIP_0 RTIP_1 RTIP_2 RTIP_3 I Receiver_n Differential Positive Input. 95 31 45 81 RRing_0 RRing_1 RRing_2 RRing_3 I Receiver_n Differential Negative Input. 6 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TRANSMITTER PIN # NAME TYPE DESCRIPTION 3 23 53 73 TxNEG_0 TxNEG_1 TxNEG_2 TxNEG_3 I Transmitter_n Negative NRZ Data Input. In dual-rail mode, this signal is the n-rail input data for transmitter n. In single-rail mode, this pin can be left unconnected. NOTE: Internally pulled -up with a 50kΩ resistor. 4 TxPOS_0 I Transmitter_n Positive Data Input. In dual-rail mode, this signal is the p-rail input data for transmitter n. Transmitter 0 Data Input. In single-rail mode, this pin is used as the NRZ input data for transmitter 0. NOTE: Internally pulled -up with a 50kΩ resistor. TData_0 22 54 72 TxPOS_1/TData_1 TxPOS_2/TData_2 TxPOS_3/TData_3 5 21 55 71 TxClk_0 TxClk_1 TxClk_2 TxClk_3 I Transmitter_n Clock Input. E1 rate at 2.048MHz ± 50ppm. T1 rate at 1.544MHz ± 32ppm. During normal operation both in Host Mode and Hardware Mode, TxClk is used for sampling input data at TxPOS/TData and TxNEG, while MCLK is used as the timing reference for the transmit pulse shaping circuit. In Hardware Mode, if TxClk is tied "High" for more than 10 µs, then TAOS (a continuous all one's AMI signal) will be transmitted to the line using MCLK as timing reference. If TxClk_n is tied “Low” for more than 10 µs, the transmitter will be powered down and the output will be tri-stated. NOTES: 1. Internally pulled -up with a 50kΩ resistor. 2. See Figure 10 and Figure 11. 91 35 41 85 TRing_0 TRing_1 TRing_2 TRing_3 O Transmitter_n Ring Output. Negative Differential data output to the line. 89 37 39 87 TTIP_0 TTIP_1 TTIP_2 TTIP_3 O Transmitter_n Tip Output. Positive Differential data output to the line. 7 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 CONTROL, ALARM, AND OTHER PIN # NAME TYPE DESCRIPTION 66 MCLK I Master Clock Input. This signal is an independent 2.048MHz clock for E1 and 1.544Mhz clock for T1 system with accuracy better than ±50ppm and duty cycle within 40% to 60%. The function of MCLK is to provide internal timing for the PLL clock recovery circuit, jitter attenuator block, reference clock during transmit all ones data and timing reference for the microprocessor in Host Mode operation. If MCLK is not present for more than 10 µs the transmitter will be powered down and the output will be tri-stated. NOTE: Internally pulled -up with a 50kΩ resistor. 9 HW/HOST I Mode Control Input: This pin is used to select the operating mode of the device, (Hardware Mode or Host Mode.) In Hardware Mode, the parallel Microprocessor interface is disabled and enables all hardware control pin functions. In Host Mode, the parallel microprocessor interface pins are used for control functions. Pin 9 Operating Mode “Low” Host Mode “High” Hardware Mode NOTE: Internally pulled "High" with 50kΩ. 14 15 16 17 TxOff_0 TxOff_ TxOff_ TxOff_ I Powered-down Transmitter_n. Hardware Mode, tie this pin "High" to power-down channel 0 transmitter and set TTIP_n and TRing_n to high impedance. NOTE: Internally pulled -up with a 50kΩ resistor. 10 Codes I Coding/Decoding Select. In Hardware Mode, if single-rail data format is selected (pin 8 =”1”), connect this pin "High" to select AMI encoding and decoding. Connect this pin Low to select HDB3 in E1 or B8ZS in T1 system. 6 RESET I Hardware Reset (Active Low). When this pin is tied Low for more than 10µS, the device is put in the reset state. NOTE: Internally pulled -up with a 50kΩ resistor. 7 CLKE I Hardware Mode Clock Edge: In Hardware Mode, connect this pin Low to select falling edge of TxClk to sample input data and also select RxPOS/RxNEG data to be valid on falling edge of RxClk. Connect this pin "High" to select rising edge of TxClk to sample input data and also selects RxPOS/RxNEG data to be updated on the rising edge of RxClk. 8 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 CONTROL, ALARM, AND OTHER PIN # NAME TYPE DESCRIPTION 8 SR/DR I Hardware Mode Single rail/Dual Rail Control Connect this pin “Low” to select transmit and receive data format in dualrail mode. In this mode, HDB3 or B8ZS encoder and decoder are not available. Connect this pin "High" to select single-rail data format. NOTE: Internally pulled -up with a 50kΩ resistor. 19 INT O Interrupt Output. This pin is asserted Low to indicate an alarm condition has occurred within the device. Interrupt generation can be globally disabled by setting the GIE bit to a "0" in the command control register. NOTE: This pin is an open drain output and requires an external 10KΩ pull-up resistor. 20 ICT I In-Circuit Testing (Active Low). When this pin is tied Low, all output pins are forced to high impedance state for in-circuit testing. NOTE: Internally pulled -up with 50kΩ. 58 LOOPSEL I Loop-back Mode Select. Hardware Mode: If LOOPEN_(0-3) is “High”, this pin is used for selecting loop-back mode. Connect this pin "High" to select local loop-back . Connect this pin “Low” to select remote loop-back. Digital Loop-back is not supported in Hardware Mode. NOTE: Internally pulled -up with a 50kΩ resistor. 62 61 60 59 LOOPEN_0 LOOPEN_1 LOOPEN_2 LOOPEN_3 I Loop-back Enable: Channel_n In Hardware Mode, connect this pin “High” to enable channel_n loopback operation. Remote or local loop-back is determined by pin 58 setting. Digital Loop-back is not supported in Hardware Mode. NOTE: Internally pulled -up with a 50kΩ resistor. 67 RXMUTE I Hardware Mode, Receive Muting: Connect this pin "High" to mute RxPOS/RxNEG output to a low state upon receive LOS condition to prevent data chattering. Connect Low to disable muting function. NOTE: Internally pulled -up with a 50kΩ resistor. 68 ECA I Hardware Mode, Transmit Equalizer Control A This pin together with ECB and ECC are used for controlling transmit pulse shaping and also selects T1 or E1 Mode of operation. See Table 2 Section 1. NOTES: 1. All transmit channels in T1 mode share the same pulse setting in Hardware Mode. 2. Internally pulled -up with a 50kΩ resistor. 69 ECB I Hardware Mode, Transmit Equalizer Control B This pin together with ECA and ECC are used for controlling transmit pulse shaping and also selects T1 or E1 Mode of operation. NOTE: Internally pulled -up with a 50kΩ resistor. 9 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 CONTROL, ALARM, AND OTHER PIN # NAME TYPE 70 ECC I DESCRIPTION Hardware Mode, Transmit Equalizer Control C This pin together with ECB and ECA are used for controlling transmit pulse shaping and also selects T1 or E1 Mode of operation. NOTE: Internally pulled -up with a 50kΩ resistor. JITTER ATTENUATOR PIN # NAME TYPE DESCRIPTION 56 TXJA I Transmit Jitter Attenuator Select. In Hardware Mode, connect this pin “High” to select jitter attenuator in the transmit path and connect Low to disable jitter attenuator. Setting RXJA simultaneously "High" also disables jitter attenuator selection. NOTE: Internally pulled -up with a 50kΩ resistor. 57 RXJA I Receive Jitter Attenuator Select. In Hardware Mode, connect this pin “High” to select jitter attenuator in the receive path and connect Low to disable jitter attenuator. Setting TXJA simultaneously "High" also disables jitter attenuator selection. NOTE: Internally pulled -up with a 50kΩ resistor. 63 FIFOS I FIFO Size Select. In Hardware Mode, connect this pin "High" selects 64 bit FIFO depth and connect Low to select 32 bit FIFO depth. NOTE: Internally pulled -up with a 50kΩ resistor. 10 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 POWER AND GROUND PIN # NAME TYPE DESCRIPTION 12 DVDD **** Digital Positive Supply(3.3V± 5%) 28 DVDD **** Digital Positive Supply(3.3V± 5%) 33 DVDD **** Digital Positive Supply(3.3V± 5%) 64 DVDD **** Digital Positive Supply(3.3V± 5%) 78 DVDD **** Digital Positive Supply(3.3V± 5%) 98 DVDD **** Digital Positive Supply(3.3V± 5%) 11 DGND **** Digital Ground 13 DGND **** Digital Ground 29 DGND **** Digital Ground 30 DGND **** Digital Ground 65 DGND **** Digital Ground 79 DGND **** Digital Ground 97 DGND **** Digital Ground 90 36 40 86 TVDD_0 TVDD_1 TVDD_2 TVDD_3 **** Transmitter_n Analog Positive Supply(3.3V± 5%) 92 34 42 84 TGND_0 TGND_1 TGND_2 TGND_3 **** Transmitter_n Analog Ground. 48 DVDD(PLL) **** Analog Positive Supply(3.3V± 5%), used for PLL 47 DGND(PLL) **** Analog Ground (used for PLL) 43 AVDD **** Analog Positive Supply(3.3V± 5%) 83 AVDD **** Analog Positive Supply(3.3V± 5%) 88 AVDD **** Analog Positive Supply(3.3V± 5%) 93 AVDD **** Analog Positive Supply(3.3V± 5%) 38 AGND **** Analog Ground 46 AGND **** Analog Ground 80 AGND **** Analog Ground 96 AGND **** Analog Ground 11 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 SYSTEM-FUNCTIONAL DESCRIPTION the narrow bandwidth requirement as specified in ITU- G.736, ITU- I.431 and AT&T Pub 62411 standards. A simplified single channel block diagram of the XRT82L34 is presented in Figure 1. The XRT82L34 consists of four identical transmit and receive channels for E1(2.048 Mbps) and T1(1.544 Mbps) PCM systems. The operational mode of each channel of the line interface can be configured by the microprocessor interface (Host Mode) or by Hardware control. HDB3/B8ZS DECODER The decoder function is only active if the chip has been configured to operate in the single-rail mode. When the single-rail mode is selected, the receive line signal will be decoded according to HDB3 rules for E1 and B8ZS for T1. Further, any bipolar violaHDB3 or B8ZS line coding scheme will be flagged as a Line Code Violation via the LCV output pin. The LCV output pin will be pulsed high for one RxClk cycle for each line code violation that is detected. Excessive number of zeros in the receive data stream are also flagged as a line code violation via the same output pin. If AMI decoding is selected in single-rail mode operation, every bipolar violation in the receive data stream is reported as error at the LCV pin. RECEIVER At the receiver input, cable attenuated AMI signals can be coupled to the receiver using a capacitor or a 2:1 step-down transformer. The receive signal first goes through the equalizer for signal conditioning before being applied to the data recovery circuit. The data recovery circuit includes a peak detector which is set typically at 50% for E1 (65% for T1) of the equalizer output peak amplitude for data slicing. After the data slicers, the digital representation of the AMI signals goes to the clock recovery circuit for timing recovery and subsequently to the HDB3 or B8ZS decoder (if selected) before they are output via the RxPOS/RDATA and RxNEG/LCV pins. The digital data output can be in dual-rail or single-rail mode depending on the option selected. Clock and timing recovery is accomplished by means of a digital PLL scheme which can tolerate high input jitter and meets or exceeds the jitter tolerance requirements as specified in the ITU - G.823 and Bellcore GR-499-CORE standards. RECEIVER LOSS OF SIGNAL (LOS) The receiver loss of signal monitoring function is implemented using both analog and digital detection schemes compatible with ITU G.775 requirements. When the amplitude of the E1 or T1 line signal at RTIP/RRING drops 20dB below the 0dB nominal level, the digital circuit is activated to parse through and check for 32 consecutive zeros in E1 and 175 zeros in T1 modes, before LOS is asserted to indicate loss of input signal. The number of consecutive zeros before LOS is declared can be increased to 4096 bits in both E1 and T1 mode (when operating in the Host Mode). The LOS condition is cleared when the input signal rises above 20dB below 0dB nominal level and meets 12.5% density of 4 ones in a 32 bit window with no more than 16 consecutive zeros for E1 and 16 ones in a 128 bit window with no more than 100 consecutive zeros in the T1 data stream. JITTER ATTENUATOR To reduce jitter in the transmit line signal or recovered clock and data signals, a crystal-less jitter attenuator with a 32x2 bit or 64x2 bit FIFO is provided for each channel. The jitter attenuator can be configured to operate in either the transmit or receive path, or it can be disabled through Host or Hardware Mode control. The jitter attenuator design is based on a digital scheme that uses the MCLK signal as a reference input. No other high frequency clock is necessary. With the jitter attenuator selected, the typical throughput delay is 16 bits for a 32 bit FIFO depth or 32 bit for a 64 bit FIFO depth. The design of the jitter attenuator is such that if the write and read pointers of the FIFO are within two bits of overflowing or underflowing, the bandwidth of the jitter attenuator is automatically widened in order to permit the “Jitter Attenuator” PLL to track the short term input jitter to avoid data corruption. When this situation occurs, the jitter attenuator will not attenuate input jitter until the read/write pointer's position is outside the two bit window. Under normal condition, the jitter transfer characteristic meets CLOCK SIGNALS GENERATED WHEN LOS IS DECLARED The output signal at the RxClk output pin depends upon the type of LOS condition that is occurring. Complete Loss of Signal (Zero Amplitude) If the XRT82L34 experiences a complete Loss of Signal (e.g., no signal amplitude), then the XRT82L34 Clock Recovery PLL enters the Training Mode, an Differentially begins to lock onto the signal applied to the MCLK input pin. As a consequence, the Clock Recovery PLL will begin to drive a clock signal to the Terminal Equipment (via the RxClk output pin), which is derived from the MCLK input pin. 12 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 Degraded Type of Loss of Signal Event (Non-Zero Amplitude) LOS condition, if it determines that the amplitude of the incoming line signal has dropped to less than -15dB (below the nominal pulse amplitude of 3V for twisted-pair, or 2.37V for coaxial-cable) for at least 32 bit-periods. If the XRT82L34 experiences a degraded type of LOS event (e.g., where there is still a small amount of discernible signal amplitude in the line signal, but small enough to qualify as an LOS event) then the Clock Recovery PLL could lock onto this degraded line signal and will subsequently drive the same frequency via the RxClk output pins. The Analog LOS Detector will clear the LOS condition, if it determines that the incoming line signal is no more than 12.5dB below the nominal 3V pulse amplitude. NOTE: The difference in the signal level required to declare and clear LOS is 2.5dB. This 2.5dB hysteresis is designed into the Analog LOS Detector circuitry, in order to prevent chattering in the LOS output pin or bit-field. DECLARING AND CLEARING LOS IN THE DS1 MODE. Each channel of the XRT82L34 has two criteria for LOS Detection, Analog and Digital. A channel will declare an LOS condition when both of these LOS Detectors detects an LOS condition. Digital LOS Detector If a given channel is configured to operate in the E1 Mode, then the Digital LOS Detector will declare an LOS condition, if it detects a string of at least 32 consecutive "0"s. Analog LOS Detector If a given channel is configured to operate in the DS1 Mode, then the Analog LOS Detector will declare an LOS condition, if it determines that the amplitude of the incoming line signal has dropped -15dB (below the nominal pulse amplitude of 3V) for at least 175 consecutive bit-periods. The Digital LOS Detector will clear the LOS condition, if it determines that the incoming E1 line signal has a pulse density of 25% or more, for at least 32 consecutive bit periods. NOTE: The pulse density requirement of 25% accounts for HDB3 coding. Conversely, the Analog LOS Detector will clear the LOS condition, if it determines that the incoming line signal is no more than 12.5dB below the nominal 3V pulse amplitude. RECEIVE DATA MUTING The XRT82L34 permits the user to “MUTE” the recovered data output signals anytime the LOS condition is declared. If the user invokes this function, then the RPOS/RDAT and RNEG output pins will be pulled to GND for the duration that the LOS condition exists. This feature is useful in that it prevents the LIU from routing electrical noise (which has been “recovered” by the Clock Recovery PLL) to the Framer IC and preventing it from declaring an LOS condition. This feature is enabled by setting the RXMUTE bit to a “1” in the Host Mode or by connecting pin 67 High in the Hardware Mode. NOTE: The difference in the signal level required to declare and clear LOS is 2.5dB. This 2.5dB hysteresis is designed into the Analog LOS Detector circuitry, in order to prevent chattering in the LOS output pin or bit-field. Digital LOS Detector If a given channel is configured to operate in the DS1 Mode, then the Digital LOS Detector will declare an LOS condition, if it detects a string of at least 175 consecutive zeroes within the receive data stream. The Digital LOS Detector will clear the LOS condition, if it determines that the incoming DS1 line signal has a pulse density of 12.5% or more. LOOP-BACK MODES Each channel within the XRT82L34 can be configured to operate in any of the following loop-back modes: NOTE: The pulse density requirement of 12.5% accounts for B8ZS coding. CONDITIONS FOR DECLARING AND CLEARING LOS IN THE E1 MODE. Similar to the DS1 mode, each E1 channel of the XRT82L34 has two criteria for LOS Detection, Analog and Digital. A channel will declare an LOS condition when both of these LOS Detectors detect an LOS condition. • Remote Loop-Back Mode • Digital Local Loop-Back Mode • Analog Local Loop-Back Mode Each of these loop-back modes are described in some detail below. REMOTE LOOP-BACK (RLOOP) MODE With Remote Loop-Back activated, received data after the jitter attenuator (if selected) is looped back to the transmit path using RxClk as transmit timing. In Analog LOS Detector If a given channel is configured to operate in the E1 Mode, then the Analog LOS Detector will declare an 13 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 ture allows users to configure the line interface as a pure jitter attenuator. (see Loop-Back Mode in Figure 6 & Figure 7). this mode the data/signals applied to the TxClk, TPOS/TDAT and TNEG input pins are ignored, while RxClk and received data will continue to be available at their respective output pins. Simultaneously setting RLOOP and ALOOP active is not allowed (see LoopBack Mode in Figure 4 & Figure 5). Remote loopback has priority over TAOS. NOTE: Digital Local Loop-Back is not supported in Hardware Mode. ANALOG LOCAL LOOP-BACK (ALOOP) MODE With Analog Local Loop-Back activated, the transmit data at TTIP and TRING are looped-back to the analog input of the receiver. External inputs at RTIP/ RRING in this mode are ignored while valid transmit data continues to be sent to the line. Analog LoopBack exercises most of the functional blocks of the line interface (see Loop-Back Mode in Figure 8 & Figure 9). DIGITAL LOCAL LOOP-BACK (DLOOP) MODE The Digital Local Loop-Back mode allows the transmit clock and data to be looped back to the corresponding receiver output pins through the encoder/ decoder and the jitter attenuator. In this mode, the receive line signal is ignored, but the transmit data will be sent to the line uninterrupted. This loop back fea- FIGURE 4. REMOTE LOOP-BACK WITH JITTER ATTENUATOR SELECTED IN RECEIVE PATH TxPOS TxNEG Timing Control Encoder TTIP Tx TRing TxClk RxClk RxPOS Decoder RTIP Clock & Data Recovery JA Rx RRing RxNEG FIGURE 5. REMOTE LOOP-BACK WITH JITTER ATTENUATOR SELECTED IN TRANSMIT PATH TxPOS TxNEG Encoder Timing Control JA TTIP Tx TRing TxClk RxClk RxPOS Clock & Data Recovery Decoder RxNEG 14 RTIP Rx RRing áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 “ FIGURE 6. DIGITAL LOCAL LOOP-BACK WITH OPTION TO TRANSMIT ALL “ONES” TO THE LINE (JA SELECTED & IN RECEIVE PATH) TAOS TxPOS TxNEG Timing Control Encoder TTIP Tx TRing TxClk RxClk RxPOS Decoder RTIP Clock & Data Recovery JA Rx RRing RxNEG FIGURE 7. DIGITAL LOCAL LOOP-BACK WITH OPTION TO TRANSMIT ALL “ONES” TO THE LINE (JA SELECTED & IN TRANSMIT PATH) TxPOS TxNEG Encoder Timing Control JA TTIP Tx TRing TxClk TAOS RxClk RxPOS Clock & Data Recovery Decoder RxNEG 15 RTIP Rx RRing áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 FIGURE 8. ANALOG LOCAL LOOP-BACK SIGNAL FLOW JITTER ATTENUATOR SELECTED & IN RECEIVE PATH TxPOS TxNEG TTIP Timing Control Encoder Tx TRing TxClk RxClk RxPOS Decoder Clock & Data Recovery JA RTIP Rx RRing RxNEG FIGURE 9. ANALOG LOCAL LOOP-BACK SIGNAL FLOW JITTER ATTENUATOR SELECTED & IN TRANSMIT PATH TxPOS TxNEG Encoder TTIP Timing Control JA Tx TRing TxClk RxClk RxPOS Decoder Clock & Data Recovery RTIP Rx RRing RxNEG RESET OPERATION The XRT82L34 provides both Hardware and Software resets. In Hardware reset, with pin 6 forced to "0" for more than 10µs, the entire state of the device including the microprocessor R/W registers are reset. In Software reset, only the state of the interface is reset (the microprocessor registers are not affected). modes of operation making it flexible for different applications as dictated by the system requirements. RECEIVE DATA INVERT MODE Receive output data by default is active high at RxPOS/RDATA and RxNEG/LCV pins. These signals can be changed to active Low by setting the DATAP bit in the interface register. In single rail mode (DataF=1), LCV output also becomes active Low. Data invert Mode is only available in Host Mode. RECEIVER MODES OF OPERATION Through the microprocessor interface or in Hardware Mode, XRT82L34 offers several alternative receive 16 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 FIGURE 10. DATA CHANGES ON RISING EDGE OF CLK AND DATA IS SAMPLED ON FALLING EDGE Clk Data Data Sampled Data Sampled FIGURE 11. DATA CHANGES ON FALLING EDGE OF CLK AND IS SAMPLED ON RISING EDGE Clk Data Data Sampled Data Sampled TRANSMIT ALL ONES (TAOS) In the Host Mode, individual channels can be programmed to transmit an all “Ones” AMI signal by setting the per channel bit control TAOS=1. In this mode, input data at TxPOS/TDATA and TxNEG are ignored. In Host Mode, reference clock for TAOS is TxClk. If TxClk is not available, MCLK is used for transmission. In Hardware Mode, if TxClk is not present and High for more than 10µs, TAOS is transmitted using MCLK as a reference. Remote Loop-Back has priority over TAOS request. RxClk Clock Sampling Edge The sampling edge of the RxClk output can be changed through control bit RClkE within the interface register for receive output data re-timing. With RClkE=1, data is validated on the rising edge of RxClk and with RClkE=0, receive data is validated on the falling edge of RxClk. In Hardware Mode, the state of pin 7 (ClkE) controls the rising or falling edge of RxClk for data re-timing. TRANSMIT CLOCK SAMPLING EDGE Transmit data at TxPOS/TDATA or TxNEG is clocked serially into the device using TxClk. With the interface register bit 4 (TClk=1), input data is sampled on the rising edge of TxClk. The sampling edge is inverted when TxClk= 0. In Hardware Mode, the state of pin 7 (CLKE) controls the sampling edge of both TxClk and RxClk. HDB3/B8ZS/AMI ENCODER The encoder is only available in single-rail mode (SR/ DR=1) in Host Mode, or pin 8 set High in Hardware Mode. In an E1 system, if interface register CODES=0, HDB3 encoding is selected. Input data applied to TxPOS/TDATA which contains more than four consecutive zeros will be removed and replaced by “000V” or “B00V”, where "B” indicates a pulse conforming with bipolar rule and "V" represents a pulse violating the rule. In a T1 system, input data with more than 8 consecutive zeros will be removed and replaced using B8ZS encoding rule. An example of Bipolar with 8 Zero Substitution (B8ZS) encoding scheme is shown in Table 1. With register CODES=1, AMI coding is selected for both E1 or T1 SINGLE RAIL, DUAL RAIL Transmit data format can be in dual-rail (SR/DR=1) or single-rail modes (SR/DR=0). In Hardware Mode, dual or single-rail format is determined by the state of pin 8. For single-rail mode operation, NRZ data can be applied to TxPOS/TDATA with TxClk, while TxNEG input is left unconnected. The transmitter converts NRZ input data into differential signal for transmission to the line using low impedance output drivers. 17 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 modes. In Hardware Mode, HDB3, B8ZS or AMI coding selection is determined by the state of pin 10. lects active High data and a "1" selects active Low data. This control bit also selects receive output data polarity (see Receive Data Invert Mode description). This feature is not supported in Hardware Mode. TRANSMIT PULSE SHAPER The transmit pulse shaper uses high a speed clock derived from MCLK to synthesize the shape and width of the transmitted pulse applied to TTIP and TRING. The internal high speed timing generator eliminates the need for a tightly controlled transmit clock TxClk duty cycle. In a T1 system, three control bits (ECC, ECB and ECA) are available in the Host Mode, for every channel to select 5 different cable length pulse settings to meet DSX-1 pulse template. Table 2 summaries the function of these control bits. In Hardware Mode, all 4 transmit channels share the same pulse synthesizer control settings. TRANSMIT OFF CONTROL Each transmit channel of the line interface can be shut down by writing a "1" to TxOFF in the channel control interface register. In the “Transmitter off” mode, the entire transmitter is disabled and the outputs at TTIP and TRING are placed in a high impedance state. In Hardware Mode, pins 14 through pin 17 are used for powering down each transmit channel independently. If MCLK is missing, then all transmitters will be powered down and the outputs are tri-stated. DRIVER MONITOR The driver monitor circuit is used for detecting transmit driver failure by monitoring the activity at TTIP and TRING. Driver failure may be caused by a shortcircuit in the primary of the transformer or system problems at the input. TABLE 1: EXAMPLES OF B8ZS ENCODING CASE 1 PRECEDING PULSE Input + B8ZS In the Host Mode, when the driver monitor detects no transitions at TTIP and TRING for more than 128 clock cycles, the DMO bit in the interface register is set and results in an interrupt (INT) to be generated. Driver monitor function is not supported in Hardware Mode. NEXT 8 BITS 00000000 000VB0VB AMI Output + 000+ -0- + - 00000000 Case 2 Input TxPOS/TDATA and TxNEG Polarity B8ZS In HOST Mode, transmit data at TxPOS/TDATA and TxNEG can be configured for active Low or active High operation, by controlling the state of the DATAP bit in the interface register. Writing a "0" to this bit se- 000VB0VB AMI Output - 000- +0+ - TABLE 2: TRANSMIT EQUALIZER CONTROL ECC ECB ECA SYSTEM CABLE LENGTH 0 0 0 T1 0-133 ft. B8ZS/AMI (DS1) 1:2 or (1:2.45) 0 0 1 T1 133-266 ft. B8ZS/AMI (DS1) 1:2 or (1:2.45) 0 1 0 T1 266-399 ft. B8ZS/AMI (DS1) 1:2 or (1:2.45) 0 1 1 T1 399-533 ft. B8ZS/AMI (DS1) 1:2 or (1:2.45) 1 0 0 T1 533-655 ft. B8ZS/AMI (DS1) 1:2 or (1:2.45) 1 0 1 Not used 1 1 0 E1 -- HDB3/AMI (E1) 1:2.45 1 1 1 E1 -- HDB3/AMI (E1) 1:2 INTERFACING THE XRT82L34 TO THE LINE The XRT82L34 in E1 configuration can be transformer coupled to 75Ω coaxial or 120Ω twisted pair lines CODES TRANSFORMER RATIO as shown in Figure 12 and Figure 13 below. For DS1 applications connecting to a 100Ω twisted pair line is shown in Figure 14. 18 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 FIGURE 12. XRT82L34 CHANNEL_0 IN AN E1 UNBALANCED 75 Ω APPLICATION - 1:2 OR (1:2.45) TRANSFORMER TxPOS TxNEG TxLineClk 4 3 5 TxPOS_0 TTIP_0 RxPOS RxNEG RxLineClk Loss of signal 99 1 2 Ω 9.1Ω (6.2Ω) TxNEG_0 1 T1 BNC 5 1 Coaxial Cable 2 TxClk_0 TRing_0 100 R1 89 R2 91 RxPOS_0 RxNEG_0 RTIP_0 4 Ω 9.1Ω (6.2Ω) 94 5 RxClk_0 8 1:2 (1:2.45) T2 1 R3 18.7Ω RxLOS_0 RRing_0 95 BNC 1 Coaxial Cable 2 4 8 1:2 XRT82L34 FIGURE 13. XRT82L34 CHANNEL_0 - E1 120 Ω BALANCED APPLICATION - 1:2 OR (1:2.45) TRANSFORMER TxPOS TxNEG TxLineClk 4 3 5 TxPOS_0 TTIP_0 RxPOS RxNEG RxLineClk Loss of signal 99 1 2 Ω 9.1Ω (6.2Ω) TxNEG_0 TxClk_0 TRing_0 100 R5 89 R6 91 RTIP_0 4 Ω 9.1Ω (6.2Ω) RxPOS_0 RxNEG_0 1 94 5 RxClk_0 T1 5 8 1:2 (1:2.45) T2 1 RRing_0 95 8 4 1:2 XRT82L34 19 Twisted Pair TRING RTIP Twisted Pair RRing R4 30.1Ω RxLOS_0 TTIP áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 FIGURE 14. XRT82L34 CHANNEL_0 - DS1 100 Ω BALANCED APPLICATION TxPOS TxNEG TxLineClk 4 3 5 TxPOS_0 TTIP_0 RxNEG RxLineClk Loss of signal 100 99 1 2 1 : 2 or 1:2.45 1 T1 5 3Ω TxNEG_0 TxClk_0 RxPOS_0 TTIP Twisted Pair TRing_0 RxPOS R2 89 RTIP_0 R3 91 TRING 8 4 3Ω 94 5 T2 1 RTIP RxNEG_0 R1 25 Ω RxClk_0 RxLOS_0 Twisted Pair RRing_0 95 4 8 1:2 XRT82L34 20 RRing áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 3: E1 RECEIVER ELECTRICAL CHARACTERISTICS (Vdd=3.3V±5%, Ta=-40 to 85°C unless otherwise specified) PARAMETER MIN TYP. MAX UNIT TEST CONDITIONS Number of consecutive zeros before LOS is set - 32 - bit Input signal level at LOS 18 20 - dB 12.5 - - % ones Receiver Sensitivity 11 15.5 - dB With nominal pulse amplitude of 3.0V for 120Ω and 2.37V for 75Ω application. With -18dB interference signal added. Interference Margin -18 -15 - dB With 6dB cable loss Input Impedance 15 20 - KΩ Measured across RTIP/RRing Jitter Tolerance: 1 Hz 10KHz---100KHz >64 0.4 - - UIpp ITU G.823 - 20 0.5 KHz dB ITU G.736 - 3 - Hz ITU G.736 12 18 14 18 22 20 - dB dB dB ITU G.703 Receiver loss of signal: LOS De-asserted Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude Jitter Attenuator Corner Frequency(-3dB curve) Return Loss: 51KHz --- 102KHz 102KHz --- 2048KHz 2048KHz --- 3072KHz 21 75 Ω Cable attenuation @1024KHz ITU-G.775, ETS1 300 233 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 4: T1 RECEIVER ELECTRICAL CHARACTERISTICS (Vdd=3.3V±5%, Ta=-40 to 85°C unless otherwise specified) PARAMETER MIN TYP. MAX UNIT TEST CONDITIONS Number of consecutive zeros before LOS is set - 175 - bit Input signal level at LOS 15 20 - dB 12.5 - - % ones Receiver Sensitivity 11 15 - dB With nominal pulse amplitude of 3.0V for 100Ω termination. Interference Margin -18 -14 - dB With 6dB cable loss Input Impedance 5 20 - KΩ Measured across RTIP/RRing Jitter Tolerance: 1 Hz 10KHz---100KHz 138 0.4 - - UIpp - 12 0.1 KHz dB Jitter Attenuator Corner Frequency(-3dB curve) - 3 - Hz Return Loss: 51KHz --- 102KHz 102KHz --- 2048KHz 2048KHz --- 3072KHz - 20 25 25 - dB dB dB Receiver loss of signal: LOS Clear Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude 22 75 Ω Cable attenuation @772KHz ITU-G.775, ETS1 300 233 AT&T Pub 62411 AT&T Pub 62411 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 5: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS (Ta=-40 to 85°C, Vdd=3.3V±5%, unless otherwise specified and 1:2 Transformer with 9.1Ω Ω or 1:2.45 Transformer with 6.2Ω) Ω) PARAMETER MIN TYP. MAX UNIT TEST CONDITIONS AMI Output Pulse Amplitude: 75Ω Application 120Ω Application 2.13 2.70 2.37 3.0 2.60 3.30 V V Output Pulse Width 224 244 264 ns Output Pulse Width Ratio 0.95 - 1.05 - ITU-G.703 Output Pulse Amplitude Ratio 0.95 - 1.05 - ITU-G.703 Jitter Added by the Transmitter Output - 0.025 0.05 UIpp Return Loss: 51KHz --- 102KHz 102KHz --- 2048KHz 2048KHz --- 3072KHz 6 8 8 8 10 10 - dB dB dB Use transformer with 1:2 ratio and 9.1Ω resistor in series with each end of primary. or Use transformer with 1:2.45 ratio and 6.2Ω resistor. Broad Band with jitter free TxClk applied to the input. ETSI 300 166, CHPTT TABLE 6: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS (Vdd=3.3V±5%, Ta=-40 to 85°C unless otherwise specified) PARAMETER MIN TYP. MAX UNIT TEST CONDITIONS 2.4 3.0 3.60 V Use transformer with 1:2.45 ratio and measured at DSX-1. Output Pulse Width 338 350 362 ns ANSI T1.102 Output Pulse Width Ratio 0.95 - 1.05 ANSI T1.102 Output Pulse Amplitude Ratio 0.95 - 1.05 ANSI T1.102 Jitter Added by the Transmitter Output - 0.025 0.05 UIpp Return Loss: 51KHz --- 102KHz 102KHz --- 2048KHz 2048KHz --- 3072KHz - 6.5 6.5 6.5 - dB dB dB Return Loss: 51KHz --- 102KHz 102KHz --- 2048KHz 2048KHz --- 3072KHz - 4.5 4.5 4.5 - dB dB dB AMI Output Pulse Amplitude: 23 Broad Band with jitter free TxClk applied to the input. 1:2.45 transformer ratio, RTIP = RRing= 3Ω, VLine =3.0V 1:2 transformer ratio, RTIP = RRing= 3Ω, VLine =2.7V áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 7: TRANSMIT PULSE MASK SPECIFICATION Test Load Impedance 75 Ω resistive (Coax) 120 Ω resistive (Twisted Pair) Nominal peak voltage of a mark 2.37V 3.0V Peak voltage of a space (no mark) 0 ± 0.237V 0± 0.3V Nominal pulse width 244ns 244ns Ratio of positive and negative pulses imbalance 0.95 to 1.05 0.95 to 1.05 FIGURE 15. ITU G.703 E1 PULSE TEMPLATE 24 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 8: DS1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS. MINIMUM CURVE MAXIMUM CURVE TIME (UI) NORMALIZED AMPLITUDE TIME (UI) NORMALIZED AMPLITUDE -0.77 -0.05V -0.77 0.05V -0.23 -0.05V -0.39 0.05V -0.23 0.5V -0.27 0.8V -0.15 0.95V -0.27 1.15V 0.0 0.95V -0.12 1.15V 0.15 0.9V 0.0 1.05V 0.23 0.5V 0.27 1.05V 0.23 -0.45V 0.35 -0.07V 0.46 -0.45V 0.93 0.05V 0.66 -0.2V 1.16 0.05V 0.93 -0.05V 1.16 -0.05V FIGURE 16. DSX-1 PULSE TEMPLATE Normalized Amplitude 25 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 9: DC ELECTRICAL CHARACTERISTICS (Vdd=3.3V±5%, Ta=25°C unless otherwise specified) PARAMETER SYMBOL MIN TYP. MAX UNITS Power Supply Voltage Vdd 3.13 3.3 3.46 V Input High Voltage VIH 2.0 - 5.0 V Input Low Voltage VIL -0.5 - 0.8 V Output High Voltage @ IOH=-5mA VOH 2.4 - - V Output Low Voltage @IOL=5mA VOL - - 0.4 V Input Leakage Current (except Input pins with Pull-up resistor.) IL - - + 10 µA Input Capacitance CI - 5.0 - pF Output Load Capacitance CL - - 25 pF TABLE 10: POWER DISSIPATION (XRT82L34 ONLY) ( Vdd=3.3V±5%, Ta=-40 to 85°C unless otherwise specified) PARAMETER SYMBO L MIN TYP MAX UNITS CONDITIONS Power Dissipation Pd - 480 530 mW E1(75Ω) load. All four transmitters running with PRBS. Power Dissipation Pd - 380 420 mW E1(120Ω) load. All four transmitters running with PRBS. Power Dissipation Pd - 550 725 mW T1(100Ω) load. All four transmitters running with PRBS. Power Dissipation Pd - 80 100 mW All Transmitters Powered-down. TABLE 11: POWER CONSUMPTION (XRT82L34 AND LOAD: PD=VDD X IDD) ( Vdd=3.3V±5%, Ta=-40 to 85°C unless otherwise specified) PARAMETER SYMBO L MIN TYP MAX UNITS CONDITIONS Power Consumption Pc - 630 700 mW E1(75Ω) load. All four transmitters running with PRBS. Power Consumption Pc - 500 550 mW E1(120Ω) load. All four transmitters running with PRBS. Power Consumption Pc - 725 980 mW T1(100Ω) load. All four transmitters running with PRBS. Power Consumption Pc - 80 100 mW All Transmitters Powered-down. 26 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 ABSOLUTE MAXIMUM RATINGS Storage Temperature -65°C to + 150°C Operating Temperature -40°C to + 85°C Supply Voltage -0.5V to + 6.0V Theta-JA 38° C/W Theta-JC 6° C/W TABLE 12: AC ELECTRICAL CHARACTERISTICS (Vdd=3.3V±5%, Ta=25°C unless otherwise specified) PARAMETER SYMBOL MIN TYP MAX UNITS E1 MCLK Clock Frequency - 2.048 - MHz T1 MCLK Clock Frequency - 1.544 - MHz MCLK Clock Duty Cycle 40 - 60 % MCLK Clock Tolerance - ±50 - ppm E1 TxClk Clock Period TCLKP - 488 - ns T1 TxClk Clock Period TCLKP - 648 - ns TxClk Duty Cycle TCDU 30 50 70 % Transmit Data Setup Time TSU 50 - - ns Transmit Data Hold Time THO 30 - - ns TxClk Rise Time (10%/90%) TCLKR - - 40 ns TxClk Fall Time (90%/10%) TCLKF - - 40 ns RxClk Duty Cycle RCDU 45 50 55 % Receive Data Setup Time RSU 150 - Receive Data Hold Time RHO 150 - - ns RxClk to Data Delay RDY - - 40 ns RxClk Rise Time (10%/90%) with 25pF Loading. RCLKR - - 40 ns 40 ns RxClk Fall Time(90%/10%) with 25pF Loading RCLKF 27 - áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 FIGURE 17. TRANSMIT CLOCK AND INPUT DATA TIMING TCLKR TCLKF TCLKP TxCLK TxPOS/TDATA or TxNEG Data can be active high or active low. THO TSU Note: Set TCLKE bit-4 in Command Control Register 0 to select TxCLK inversion. FIGURE 18. RECEIVE CLOCK AND OUTPUT DATA TIMING. RCLKR RDY RCLKF RxCLK RxPOS or RxNEG RSU Data can be active high or active low. RHO Note: Set RCLKE bit=5 in Command Control Register 0 to select MICROPROCESSOR INTERFACE RxCLK inversion. The device has 4-bit address ADD[3:0] input and 8-bit bi-directional data bus ADD[7:0]. The signals required for a generic microprocessor to access the internal registers are described in Table 13. XRT82L34 is equipped with a microprocessor interface for easy device configuration. The parallel port of the XRT82L34 is compatible with both Intel and Motorola address and data buses. 28 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 13: MICROPROCESSOR INTERFACE SIGNAL D[7:0] Data Input (Output): 8 bits bi-directional data bus for register access. ADD[3:0] Address Input: 4 bit address to select internal register location. PTS1 PTS2 PCLK Processor Type Select: PTS1 PTS2 0 0 8HC11,8081,80C188 (async.) 1 0 Motorola 68K (async.) 0 1 Intel x86 (sync.) 1 1 Intel i906,Motorola 860 (sync.) Process Clock Input: Input clock for synchronous microprocessor operation. Maximum clock speed is 16MHz. This pin is internally pulled down for asynchronous microprocessor operation if no clock is present. ALE_AS Address Latch Input (Address Strobe): With Intel bus timing, the address inputs are latched into the internal register on the falling edge of ALE. When configured in Motorola bus timing, the address inputs are latched into the internal register on the falling edge of AS. CS RD_DS Chip Select Input: This signal must be low in order to access the parallel port. Read Input (Data Strobe): With Intel bus timing, a low pulse on RD selects a read operation when CS pin is low. When configured in Motorola bus timing, a low pulse on DS indicates a read or write operation when CS pin is low. WR_R/W Write Input (Read/Write): With Intel bus timing, a low pulse on WR selects a write operation when CS pin is low. When configured in Motorola bus timing, a high pulse on R/W selects a read operation and a low pulse on R/W selects a write operation when CS pin is low. RDY_DTA Ready Output (Data Transfer Acknowledge Output): With Intel bus timing, RDY is asserted high to indicate the CK device has completed a read or write operation. When configured in Motorola bus timing, DTACK is asserted low to indicate the device has completed a read or write operation. INT Interrupt Output: This pin is asserted low to indicate an interrupt caused by an alarm condition in the device status registers. The activation of this pin can be blocked by the interrupt status register bit. 29 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 14: MICROPROCESSOR REGISTER MAP REGISTER NUMBER ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Command Control Registers (Read/Write) 0 0000 SR/DR ATAOS RCLKE TCLKE DATAP CODES IMASK SRESET 1 0001 Reserved (Set to 0) Reserved (Set to 0) FIFOS RXJA TXJA RXMUTE EXLOS ICT reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 DMO0IS LOS0IS LVC0IS TCKL0IS MDMO0 MLOS0 MLCV0 MTCKL0 Channel 0 Register 2 0010 DMO0 LOS0 LCV0 TCLK0 3 0011 reserved reserved 4 0100 ECA0 ECB0 ECC0 ALOOP0 DLOOP0 RLOOP0 TAOS0 TxOFF0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 DMO1IS LLOSIS1 LCV1 TCKL1IS MDMO1 MLOS1 MLCV1 MTCKL1 reserved reserved Channel 1 Register 5 0101 DMO1 LOS1 LCV1 TCLK1 6 0110 reserved reserved 7 0111 ECA1 ECB1 ECC1 ALOOP1 DLOOP1 RLOOP1 TAOS1 TxOFF1 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 DMO2IS LLOS2IS LCV2 TCKL2IS MDMO2 MLOS2 MLCV2 MTCKL2 reserved reserved Channel 2 Register 8 1000 DMO2 LOS2 LVC2 TCLK2 9 1001 reserved reserved 10 1010 ECA2 ECB2 ECC2 ALOOP2 DLOOP2 RLOOP2 TAOS2 TxOFF2 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 DMO3IS LLOS3IS LCV3 TCKL3IS MDMO3 MLOS3 MLCV3 MTCKL3 reserved reserved Channel 3 Register 11 1011 DMO3 LOS3 LCV3 TCLK3 12 1100 reserved reserved 13 1101 ECA3 ECB3 ECC3 ALOOP3 DLOOP3 RLOOP3 TAOS3 TxOFF3 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reset=0 reserved reserved 30 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 15: COMMAND CONTROL REGISTER 0 COMMAND CONTROL REGISTER 0 PARALLEL PORT ADDRESS: 0000 FUNCTION REGISTER TYPE RESET VALUE R/W 0 BIT NO. NAME 7 SR/DR Single/Dual Rail: Writing a "1" to this bit selects transmit and receive data format in single-rail mode. In this mode, HDB3/B8ZS/AMI encoder and decoder are available. Writing a "0" selects dual-rail mode. 6 ATAOS Automatic Transmit “All Ones”: Writing a “1” in this bit position enables the automatic transmission of an all one AMI pattern from the transmitter of any channel that the receiver of that channel detects an LOS condition. Writing a “0” in this bit position disables this feature. R/W 0 5 RCLKE RxClk Clock Edge: Writing a "1" to this bit selects receive output data to be updated on positive edge of RxClk. Writing a "0" to this bit selects the negative edge of RxClk. R/W 0 4 TCLKE TxClk Clock Edge: Writing a "1" to this bit selects positive edge of TxClk to sample input data. Write "0" to select negative edge. R/W 0 3 DATAP DATA Polarity: Writing a "0" to this bit selects transmit input and receive output data to be active-high. Write "1" to select active-low. R/W 0 2 CODES Coding/Decoding Select: This bit is used in conjunction with SR/DR bit 1. If SR/DR is "1", writing a "0" to this bit selects HDB3 coding in E1 and B8ZS in T1. Writing a "1" to this bit position selects AMI code. R/W 0 1 GIE Global Interrupt Enable: Writing a "0" to this bit globally disables interrupt generation caused by any alarm generated within the line interface. Write a "1" to enable interrupt generation. R/W 0 0 SRESET Software Reset: Writing a "1" to this bit longer than 10µs initiates a device reset through the microprocessor interface. All internal circuits are placed in the reset state with this bit set to a "1" except the microprocessor register bits. R/W 0 31 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 16: COMMAND CONTROL REGISTER 1 COMMAND CONTROL REGISTER 1 PARALLEL PORT ADDRESS: 0001 REGISTER TYPE RESET VALUE Reserved. Must be set to “0” for proper operation. R/W 0 Reserved. Must be set to “0” for proper operation. R/W 0 FIFOS FIFO Size Select: Writing a "1" to this bit selects 64 bit FIFO depth. Write "0" to select 32 bit FIFO depth. R/W 0 4 RxJA Receive Jitter Attenuator Select: Writing a "1" to this bit selects jitter attenuator in the receive path. If bit 3(TxJA) is also set, jitter attenuator is disabled. R/W 0 3 TxJA Transmit Jitter Attenuator Select: Writing a "1" to this bit selects jitter attenuator in the transmit path. If bit 4(RxJA) is also set, jitter attenuator is disabled. R/W 0 2 RXMUTE Receive Muting: Writing a "1" to this bit mutes receive data output to a low state during LOS condition to prevent data chattering. R/W 0 1 EXLOS Extended LOS: Writing a "1" to this bit extends the number of zeros at the input to 4096 bits before LOS is declared. R/W 0 0 ICT In-Circuit-Testing: Writing a "1" to this bit causes all output pins to be in high impedance mode for in-circuit testing. The software ICT function is equivalent to connecting pin 20 to ground. R/W 0 BIT NO. NAME 7 -- 6 -- 5 FUNCTION 32 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 17: CHANNEL STATUS REGISTER CHANNEL STATUS REGISTER PARALLEL PORT ADDRESS CHANNEL 0: 0010 PARALLEL PORT ADDRESS CHANNEL 1: 0101 PARALLEL PORT ADDRESS CHANNEL 2: 1000 PARALLEL PORT ADDRESS CHANNEL 3: 1011 REGISTER TYPE RESET VALUE Driver Monitor Output: This bit is set to a "1" to indicate current DMO is detected. Any change in the state of this bit causes an interrupt to be generated. Reading this register bit does not clear the DMO bit. R 0 LOSn Loss of Signal: This bit is set to a "1" to indicate current LOS condition is detected. Any change in the state of this bit causes an interrupt to be generated. Reading this register bit does not clear the LOS bit. R 0 5 LCVn Line Code Violation: This bit is set to a "1" to indicate current LCV condition is detected. Any change in the state of this bit causes an interrupt to be generated. Reading this register bit does not clear the LCV bit. R 0 4 TCKLn Transmit Clock Loss: This bit is set to a "1" to indicate current TxClk clock loss is detected. Any change in the state of this bit causes an interrupt to be generated. Reading this register bit does not clear the TCKL bit. R 0 BIT NO. SYMBOL 7 DMOn 6 FUNCTION 3 DMOnIS Driver Monitor Output: This bit is set to a "1" every time the state of DMO status changes since last read. This bit is cleared by a read operation. RUR 0 2 LOSnIS Latched- Loss of signal: This bit is set to a "1" every time the state of LOS changes since last read. This bit is cleared by a read operation. RUR 0 1 LCVnIS Latched- Line Code Violation: This bit is set to a "1" every time the state of LCV changes since last read. This bit is cleared by a read operation. RUR 0 0 TCLKnIS Latched-Transmit Clock Loss. This bit is set to a "1" every time the state of TCKL changes since last read. This bit is cleared by a read operation. RUR 0 NOTE: n = channel number 0 to 3. 33 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 18: CHANNEL MASK REGISTER CHANNEL MASK REGISTER PARALLEL PORT ADDRESS CHANNEL 0: 0011 PARALLEL PORT ADDRESS CHANNEL 1: 0110 PARALLEL PORT ADDRESS CHANNEL 2: 1001 PARALLEL PORT ADDRESS CHANNEL 3: 1100 Bit No. Name 7 -- 6 Function Register Type Reset Value This bit is reserved. R/W 0 -- This bit is reserved. R/W 0 5 -- This bit is reserved. R/W 0 4 -- This bit is reserved. R/W 0 3 DMOnIS Driver Monitor Output Interrupt Status: Writing a "1" to this bit enables DMO alarm interrupt generation. R/W 0 2 LOSnIS Loss of Signal Interrupt Status: Writing a "1" to this bit enables LOS alarm interrupt generation. R/W 0 1 LCVnIS Line Code Violation Interrupt Status: Writing a "1" to this bit enables LCV interrupt generation. R/W 0 0 TCKLnIS Transmit Clock Loss Interrupt Status: Writing a "1" to this bit enables TxClk clock loss interrupt generation. R/W 0 NOTE: n = channel number 0 to 3. 34 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 19: CHANNEL CONTROL REGISTER CHANNEL CONTROL REGISTER Parallel Port Address Channel 0: 0100 Parallel Port Address Channel 1: 0111 Parallel Port Address Channel 2: 1010 Parallel Port Address Channel 3: 1101 BIT NO. SYMBOL FUNCTION REGISTER TYPE RESET VALUE 7 ECAn These 3 control bits are used to control the transmit pulse shape for T1 and E1 operations. See Table 2 for details. R/W 0 6 5 ECBn ECCn R/W R/W 0 0 4 LLOOPn Local Loop-Back: Writing a "1" to this bit enables Analog Local Loop-Back. Simultaneously setting RLOOP High is not allowed. R/W 0 3 DLOOPn Digital Loop-Back: Writing a "1" to this bit enables Digital Loop-Back. R/W 0 2 RLOOPn Remote Loop-Back: Writing a "1" to this bit enables Remote Loop-back. Simultaneously setting LLOOP High is not allowed. R/W 0 1 TAOSn Transmit All Ones: Writing a "1" to this bit enables the All Ones AMI signal to be transmitted to the line. R/W 0 0 TxOFFn Transmitter Off: Writing a "1" to this bit powers down the transmitter and places the corresponding output driver in a high impedance mode. R/W 0 NOTE: n = channel number 0 to 3. Microprocessor Interface I/0 Timing minimum external glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency, and with the timings of x86 or I960 family or microprocessors. The interface timing shown in Figure 19 and Figure 20 is described in Table 20. Intel Interface Timing The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD), Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses 35 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 FIGURE 19. INTEL INTERFACE TIMING (READ) t64 t65 ALE_AS A[8:0] Address of Target Register t68 CS t67 D[7:0] Not Valid RD_DS t69 WR_R/W Valid t66 t701 RDY_DTCK t70 FIGURE 20. INTEL INTERFACE TIMING (WRITE) t64 t65 ALE_AS A[8:0] CS D[7:0] Address of Target Register t770 t71 t72 Data to be Written RD_DS t73 t66 WR_R/W 36 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 20: INTEL INTERFACE TIMING SPECIFICATIONS SYMBOL PARAMETER MIN TYP MAX CONDITION t64 A8 - A0 Setup Time to ALE_AS Low 4 ns t65 A8 - A0 Hold Time from ALE_AS Low. 2 ns Intel Type Read Operation t66 RDS_DS Pulse Width 260 ns t67 Data Valid from RDS_DS* Low. 240 ns t68 Data Bus Floating from RDS_DS* High 2 ns t69 ALE to RD Time 4 ns t701 RD Time to "NOT READY" (e.g., RDY_DTCK toggling "Low") t76 Minimum Time between Read Burst Access (e.g., the rising edge of RD to falling edge of RD) 145 ns 60 ns 160 ns Intel Type Write Operations t71 Data Setup Time to WR_R/W High t72 Data Hold Time from WR_R/W High 0 ns t73 High Time between Reads and/ or Writes 60 ns t74 ALE to WR Time 4 ns t77 Min Time between Write Burst Access (e.g., the rising edge of WR to the falling edge of WR) 60 ns t770 CS Assertion to falling edge of WR_R/W 20 ns Motorola Interface Timing with the timing of a Motorola 68000 microprocessor family with up to 16.67 MHz clock frequency. The interface timing is shown in Figure 21, Figure 22 and Figure 23. The I/O specifications are shown in Table 21. The signals used in the Motorola microprocessor interface mode are: Address Strobe (AS), Data Strobe (DS), Read/Write Enable (R/W), Chip Select (CS), Address and Data bits. The interface is compatible 37 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 FIGURE 21. MICROPROCESSOR INTERFACE TIMING - MOTOROLA TYPE PROGRAMMED I/O READ OPERATION t78 ALE_AS A[8:0] Address of Target Register CS D[7:0] Valid Data Not Valid RD_DS WR_RW t79 RDY_DTCK t80 FIGURE 22. MICROPROCESSOR INTERFACE TIMING - MOTOROLA TYPE PROGRAMMED I/O WRITE OPERATION t78 ALE_AS A[8:0] CS D[7:0] Address of Target Register t81 Data to be Written RD_DS WR_RW t82 RDY_DTCK . FIGURE 23. MICROPROCESSOR INTERFACE TIMING - RESET PULSE WIDTH t90 Reset 38 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 TABLE 21: MOTOROLA INTERFACE TIMING SPECIFICATION SYMBOL PARAMETER MIN TYP MAX UNITS Microprocessor Interface - Motorola Read Operations (see Figure 21) t78 A3 - A0 Setup Time to falling edge of ALE_AS 5 ns t79 Rising edge of RD_DS to rising edge of RDY_DTCK delay 0 ns t80 Rising edge of RDY_DTCK to tri-state of D[7:0] 0 ns Microprocessor Interface - Motorola Write Operations (see Figure 22) t78 A3 - A0 Setup Time to falling edge of ALE_AS 5 ns t81 D[7:0] Setup Time to falling edge of RD_DS 10 ns t82 Rising edge of RD_DS to rising edge of RDY_DTCK delay 0 ns 30 ns Reset pulse width - both Motorola and Intel Operations (see Figure 23) t90 Reset pulse width 39 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 3. The "Maximum Tolerable Input Jitter Amplitude" values reflect the amount of Jitter that will cause the XRT82L34 to experience a Bit Error Rate (BER) of 1x10-9. 4. 64UI-pp is the maximum amount of "Input Jitter Amplitude" that the Test Equipment used (W&G ANT-20) can insert into the DS1 line signal. 5. Measurements were performed with 6.4dB of cable loss inserted into the Receive Line signal (between the ANT-20 and the Receive Input of the device). JITTER TOLERANCE IN DS1 APPLICATIONS Input Jitter Tolerance Measurements are presented for the following two situations. 1. The Jitter Attenuator within the Channel-UnderTest is disabled. 2. The Jitter Attenuator within the Channel-UnderTest is enabled and configured to operate in the Receive Path. The results of the Input Jitter Tolerance Measurements are plotted in Figure 24. FIGURE 24. INPUT JITTER TOLERANCE PERFORMANCE OF THE XRT82L34, FOR DS1 APPLICATIONS, WITH THE JITATTENUATOR DISABLED TER DS1 Jitter Tolerance: Jitter Attenuator Disabled Input Jitter Amplitude (UIpp) 100 10 ;57;5/67#'64#-LWWHU#7ROHUDQFH= 1R#-$ Bellcore GR-499-CORE (Cat I): Jitter Tolerance Requirements for DS1 1 Bellcore GR-499-CORE (Cat II): Jitter Tolerance Requirements for DS1 0.1 1 10 100 1000 10000 100000 Jitter Frequency (Hz) Bellcore GR-499-CORE requires that the Jitter Tolerance Measurements always be above both curves. The curve with square boxes and the curve with Triangular boxes are the Jitter Tolerance Requirements per Bellcore Category I and II GR-499-CORE (for DS1 Applications). The Maximum Jitter Tolerance measurements for the XRT82L38 (for DS1 applications) is shown by the curve marked with the Diamond boxes. 40 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 NOTES: 1. The "Maximum Tolerable Input Jitter Amplitude" values reflect the amount of Jitter that will cause the XRT82L34 to experience a Bit Error Rate (BER) of 1x10-9. 2. 64UI-pp is the maximum amount of "Input Jitter Amplitude" that the Test Equipment used (W&G ANT-20) can insert into the DS1 line signal. 3. Measurements were performed with 6.4dB of cable loss inserted into the Receive Line signal (between the ANT-20 and the Receive Input of the device). JITTER ATTENUATOR ENABLED AND CONFIGURED TO OPERATE IN THE RECEIVE PATH The results of the Input Jitter Tolerance Measurements with the Jitter Attenuator enabled and configured to operate in the receive path are plotted in Figure 25. FIGURE 25. INPUT JITTER TOLERANCE CAPABILITY OF THE XRT82L34 FOR DS1 APPLICATIONS WITH THE JITTER ATTENUATOR ENABLED AND OPERATING IN THE RECEIVE PATH DS1/E1 Jitter Tolerance: Jitter Attenuator in Receive Path Input Jitter Amplitude (UIpp) 100 10 ;57;5/67#-LWWHU#7ROHUDQFH 0#'642-$#LQ#5[#SDWK Bellcore GR-499-CORE (Cat I): Jitter Tolerance Requirements for DS1 1 Bellcore GR-499-CORE (Cat II): Jitter Tolerance Requirements for DS1 0.1 1 10 100 1000 10000 Jitter Frequency (Hz) 41 100000 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 NOTE: No cable loss was applied to the Receive Line Signal, during these measurements. JITTER TRANSFER CHARACTERISTICS OF THE XRT82L34 CONFIGURED TO OPERATE IN THE DS1 MODE FIGURE 26. JITTER TRANSFER CHARACTERISTICS OF THE XRT82L34 FOR DS1 APPLICATIONS WITH THE JITTER ATTENUATOR ENABLED AND OPERATING IN THE RECEIVE PATH J i tter Transfer Characteri sti cs o f the XRT8 2 L3 4 Devi c e (DS1 Appl i cati o ns - J A Enabl ed, Rx P ath) 0 -5 -10 Jitte r Gain (dB) -15 -20 -25 Jit ter G ain (dB) -30 -35 -40 -45 -50 1 10 100 Jitte r Fre qu e n cy, Hz 42 1000 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 APPENDIX A contains an executable file called xrt82L24_34.exe. This file contains the executable code used to run the GUI software interface. Figure 27 is a picture of the GUI software interface and its configuration options. For more information on the XRT82L/L24 evaluation kit GUI software, see the XRT82L34/L24EVAL User Manual. XRT82LL34 AND XRT82L24 EVALUATION KIT (XRT82L34/L24EVAL) The XRT82L34/L24EVAL is a complete printed circuit board for characterizing Exar's XRT82L34 or XRT82L24 products. This application board combines a proven PC board layout with optimized analog and digital interface circuitry. The XRT82L34/ L24EVAL comes with a CD ROM or Floppy Disk that FIGURE 27. XRT82L34/L24 GUI SOFTWARE INTERFACE FOR EVALUATING THE XRT82L24/L34EVAL APPLICABOARD TION The Evaluation Kit Contains the Following: · XRT82L34 or XRT82L24 100-Pin TQFP · XRT82L34/L24EVAL Application Board · XRT82L34/L24EVAL User Manual · XRT82L34/L24 GUI Evaluation Software (CD ROM or Floppy Disk) · XRT82L34 Datasheet 43 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 FIGURE 28. PHOTOGRAPH OF THE XRT82L34/L24EVAL APPLICATION BOARD 44 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 FIGURE 29. BLOCK LAYOUT OF THE XRT82L34/L24EVAL APPLICATION BOARD áç + 5.0V CORPORATION AD INFINITUM C Transformer J16 LINE 0 Osillator XRT82L34IV á J14 LINE 1 J13 Transformer PLD µP Emulator ε XILINX GND Transformer 975H 16.3840M M *PC J115 J12 LINE 2 J11 Transformer PC Parallel Connector J18 J17 XRT82L34 XRT82L24 45 EVAL PCB LINE 3 áç XRT82L34 QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 ORDERING INFORMATION PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE XRT82L34IV 100 Lead TQFP (14 x 14 x 1.4mm) -40°C to +85°C PACKAGE DISSIPATION Theta-JA 38° C/W Theta-JC 6° C/W PACKAGE DIMENSIONS 100 LEAD TQFP 14X14MM D D1 75 51 76 50 D1 100 26 1 25 A2 B e C A Seating Plane α A1 L NOTE: The control dimension is the millimeter column INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.055 0.063 1.40 1.60 A1 0.002 0.006 0.05 0.15 A2 0.053 0.057 1.35 1.45 B 0.007 0.011 0.17 0.27 C 0.004 0.008 0.09 0.20 D 0.622 0.638 15.80 16.20 D1 0.547 0.555 13.90 14.10 e 0.020 BSC 0.50 BSC L 0.018 0.030 0.45 0.75 α 0° 7° 0° 7° 46 D XRT82L34 áç QUAD T1/E1/J1 LINE TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR REV. 1.1.0 REVISION HISTORY Rev. P1.0.1 to P1.0.5 editor revisions Rev. P1.0.6 Power Consumption, Table 10, changed to Tables 10 and 11, Power Dissipation and Power Consumption. Changed channel indicators for pin names (example TxClk0 = TxClk_0). Added both 1:2 and 1:2.45 output transformer applications info, modified table 2 and figures 12, 13 and 14. Updated Return Loss numbers in Table 5. Rev. 1.0.0 Removed “Preliminary” designation. Corrected receive side transformer ratio in figures 12, 13 and 14 from 2:1 to 1:2. Rev. 1.1.0 Table 19: Channel Control Register, change bit 7 to ECAn and bit 5 to ECCn. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’s specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2001 EXAR Corporation Datasheet June 2001. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 47