APPLICATION BULLETIN
®
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DDC101 EVALUATION FIXTURE PC INTERFACE BOARD
By Timothy V. Kalthoff
LOCATING THE PC’S PARALLEL
PORT’S ADDRESS
The DDC101 Evaluation Fixture is a modular design. With
the use of the common DDC101 Evaluation Fixture PC
Interface Board, different Device Under Test (DUT) Boards
may be used. Different DUT boards can be used to evaluate
single or up to 32 DDC101s in any package type. Design of
the DUT boards and their use are detailed in the DDC101
Evaluation Fixture product data sheet.
The PC interface board receives its instructions via the PC’s
parallel port. The address for the parallel printer port is
found by reading it from the BIOS memory. LPT1, printer
port 1’s address, is located at hexidecimal address 40H, 08H
(segment, offset). LPT2, printer port 2’s address, is located
at hexidecimal address 40H, 0AH.
This application note focuses on how to communicate directly to the PC Interface Board through a PC’s printer port.
This communication is used to configure the PC Interface
Board as well as to configure and retrieve data from the
DDC101s on the DUT Board. This will allow the user to
write custom software to create user specific, extended
capabilities not available in the standard program.
The software for the DDC101 Evaluation Board was written
in Turbo Pascal®. The code can be readily modified to be
used with other languages. All software examples listed use
Turbo Pascal syntax.
DDC101 EVALUATION FIXTURE—
PC INTERFACE BOARD
The DDC101 Evaluation Fixture’s PC Interface Board is a
data collection board designed to provide full operational
control of the DDC101. The PC Interface Board provides
control signals for the DDC101 and can collect up to 32,768
data words of DDC101 serial output. The PC Interface
Board provides computer communication via the parallel
interface port of an IBM compatible PC. The board can be
used to evaluated up to 32 multiple DDC101s with their
control signals connected in parallel and their outputs/inputs
serially connected.
4
When information is sent to the PC Interface Board from the
PC, bit 7 of the PC’s Parallel Output Port is used to
determine whether it is a register address or data to be
written into a register. To write to a register, first send the
register address with bit 7 low. This enables only the desired
register to be written to. Then send the data with bit 7 high.
5
Note, whenever data is sent to the PC Interface Board (bit 7
high) the last register addressed will be written to. It is
recommended that prior to transmitting each register’s data,
first send the register’s address.
6
INITIALIZATION
The DDC101 PC Interface Board contains seven registers
which must be initialized to establish control and timing for
the DDC101 under test (refer to Table I and II). These
registers control: Data Clock Rate, System Clock Rate,
Integration Time, Data Transfer Delay, Number of DDC101s,
DDC101 Setup Configuration, and PC Interface Board data
collection.
DDC101 DATA COLLECTION MODE
Bit 5 of the Control Register determines the data transfer
mode the DDC101 Evaluation Fixture will be in. The data is
either being collected from the DDC101 under test and
stored into the PC Interface Board’s RAM or the data is
being retrieved from the RAM and read back to the PC.
PC INTERFACE BOARD SCHEMATICS
The PC Interface Board schematic is shown in Figure 1. The
PC Interface Board uses two Xilinx Field Programmable
Logic Arrays. The schematics for these are shown in Figures
2-8. For completeness, a single DDC101 DUT board schematic is shown in Figure 9.
Data Storage—Setting bit 5 of the Control Register high
initiates the data collect function of the PC Interface Board.
At the end of each DDC101 conversion, Data Valid becomes
active. Upon receipt of Data Valid, the PC Interface Board
Turbo Pascal®, Borland International, Inc.
©
1994 Burr-Brown Corporation
AB-097
3
ACCESSING THE PC INTERFACE
BOARD REGISTERS
Table I lists the addresses of the registers which are contained in the PC Interface Board. Table II provides a description of these registers.
Control of the DDC101 from the PC is attained by loading
control data into the PC Interface Board’s registers. These
registers are used for controlling system and data clock rates,
integration time, number of DDC101’s, readback delay, and
the mode of operation. The following contains procedures
for setting up the DDC101, collecting data from the DDC101
and writing to the on board RAM, and reading back the data
from RAM.
1
Printed in U.S.A. November, 1994
initiates Data Transmit after delaying the value contained in
the Read Delay Register. Data Transmit is active while 20
or 21 data clocks are sent per DDC101 (depends on the
output data format). For each DDC101 data word received
by the PC Interface Board, the serial data is fed into a serial
to parallel shift register. Each output word is stored at a
separate RAM address. After the output word is written to
RAM, the RAM address counter is incremented.
The DDC101 PC Interface Board contains 32k by 24 bit
RAM. This provides storage of a twenty-four bit word
containing the DDC101’s serial data in bits 20 to 0 (LSB =
bit 0), output data format (unipolar or BTC) in bit 21, and
overflow positive and negative in bits 23 and 22, respectively. Data is read back to the PC as six four bit nibbles.
Data Retrieval—Setting bit 5 of the Control Register low
initiates the read data function of the PC Interface Board.
Following a completed write cycle, the address counter will
be put in a decrement mode and the RAM enabled for
reading.
The data is read by the PC as six four bit nibbles. Writing to
the desired Read Address outputs the specified nibble (refer
to Table I). When all six nibbles have been read the memory
is then decremented by writing to address $6F and the next
data word can be read. Note that the data is inherently read
last data word recorded first.
During the Read Mode, the PC Interface Board continues to
issue FDS and Data Transmit commands to the DDC101.
However, the data transmitted is not stored in RAM. The
output of the parallel to serial shift register is disabled
allowing the RAM data to be put on the bus for the read.
2
Setup Retrieval—Setting bit 1 of the Control Register low
initiates the Setup Retrieval function of the PC Interface
Board. The PC Interface Board instructs the DDC101(s)
under test to send back their Setup Code information. This
Setup Code information is stored on the PC Interface Boards
RAM. Upon completion of the Setup Code Retrieval from
the DDC101(s), the PC can then retrieve the Setup Code
data from the PC Interface Board via setting control bit 5
low.
Setting control bit 1 low starts a machine in the PC Interface
Board to retrieve the Setup Data from the DDC101(s) under
test. The machine stores each DDC101’s setup code at
individual word locations of the PC Interface Board’s RAM.
The Setup Code is stored in the bottom three nibbles of each
RAM word.
The Setup Data is read back from the PC Interface Board to
the PC in a similar manner to the Data Retrieval operation,
except only the bottom three nibbles need to be read.
SAMPLE PROGRAM
“Turbo Pascal Program Used for PC Interface Board Communications” lists a sample Turbo Pascal program which
can be used with the PC Interface Board. This program may
provide a useful starting point for a user customized application. This sample program is available on the DDC101
Evaluation Fixture’s accompanying floppy diskette.
FUNCTION
ADDRESS
SHORT DESCRIPTION
FUNCTION
Configuration Addresses:
ADDRESS
SHORT DESCRIPTION
Data Retrieval Mode, Read Functions:
DCLKRATE
0 XXX 0000
Set Data Transfer Clock
SCLKRATE
0 XXX 0001
Set System Clock
FDS MSB
FDS MID2
FDS MID1
FDS LSB
0 XXX 0010
0 XXX 0011
0 XXX 0100
0 XXX 0101
Set duration to
Final Data Sample
(Continuous integration,
integration time)
SETUP MSB
SETUP LSB
0 XXX 0110
0 XXX 0111
DDC101 Setup Configuration
RDLY MSB
RDLY LSB
0 XXX 1000
0 XXX 1001
Post reset, system clock
delay until data transfer
NUM DDCS
0 XXX 1010
Number of DDC101s
CTRL
0 XXX 1011
Control Register
DL SET
0 XXX 1100
Select bit transition to
evaluate.
READ ADD0
READ ADD1
READ ADD2
READ ADD3
READ ADD4
READ ADD5
READ ADD6
READ ADD7
0 000 XXXX
0 001 XXXX
0 010 XXXX
0 011 XXXX
0 100 XXXX
0 101 XXXX
0 110 XXXX
0 111 XXXX
D3
D0
D7
D4
D11
D8
D15
D12
D19
D16
D23
D20
decrement memory
no op
X - Indicates Don’t Care:
XXX - can be any value. Use of 111 will prevent selection of a Read Function.
Selecting a Read Function during data collection mode will have no affect on
the data.
XXXX - can be any value. However, use of 1111 will prevent selection of a
Configuration Address. (Selection of a Configuration Address is not a
problem unless data is subsequently written to this address).
TABLE I. Register Addresses.
REGISTER DESCRIPTIONS
SETDCLK—Loading with any other number will result in a Data Clock
frequency according to the following formula.
CTRL—This register controls the functions of the PC Interface Board as
described:
Data Clock = (16MHz/2) / (N + 1)
BIT
FUNCTION
DESCRIPTION
For example, loading N = 1 results in a Data Clock frequency of 4MHz.
6
Data Clock
SETSCLK—Loading with any other number will result in a DDC101 System
Clock frequency according to the following formula.
1 = Data Clock provided externally.
0 = Use PC Interface Board Data Clock.
5
Data Mode
1 = Collect DDC101 data and store in RAM.
0 = Retrieve data from RAM to PC.
4
FDS Trig
1 = FDS Trigger provided externally.
0 = Use PC Interface Board FDS Trigger.
3
R Setup
1 = When strobed to a 1, releases DDC101
R_Setup and Transmits Setup Code stored
in SETUP_MSB and SETUP_LSB registers.
0 = Sets DDC101 R_Setup Low (Active).
2
Test
1 = Sets DDC101 Test pin high. DDC101internal
test current on.
0 = Sets DDC101 Test pin low. DDC101internal
test current off.
1
Read Data/
Setup
1 = Output data retrieved from DDC101.
0 = Setup code retrieved from DDC101.
0
Reset Sys
1 = Sets DDC101 System Reset inactive (high).
0 = Sets DDC101 System Reset active (low).
System = (16MHz/2) / (N + 1)
For example, loading N = 3 results in the DDC101's specified System Clock
frequency of 2MHz.
FDS_MSB, FDS_MID2, FDS_MID1, FDS_LSB—Load these registers with
the number of System Clock cycles between FDS pulses. For example, for
a 1000 clock cycle integration time, load the binary value:
XXXX000 0000000 0000111 1101000
into FDS MSB, FDS MID2, FDS MID1, FDS LSB, respectively. Note, the first
four bits of FDS MSB have no affect on the FDS timing.
SETUP_MSB, SETUP_LSB—Load the 6 LSBs of these registers with bits
11-6 and 5-0 of the DDC101's setup code. (Refer to product data sheet for
setup code specifics). For example, for 16 Acquisition Clocks, 32 Samples/
Integration, 2 Integrations/Conversion, Unipolar Input Signal, and BTC
Output Data Format, load the binary value:
X100101 X000101
DL SET—This register configures the DL Display Output. The DL display is
operated by using the output of the PC Interface Board's DL Display as the
Y-input to an oscilloscope, a ramp or triangle function used as input to the
DDC101 is used as the oscilloscope's X-input.
into SETUP_MSB and SETUP_LSB, respectively. The CTRL register must
be used to pass SETUP_MSB and SETUP_LSB's loaded data on to the
DDC101.
RDLY_LSB, RDLY_MSB—Post DDC101 end of conversion reset, RDLY
MSB and RDLY LSB control how many DDC101 System Clock cycles are
delayed until the data transmission from the DDC101 is directed by the PC
Interface Board (Read Delay clock cycles). For example, to wait 200
DDC101 System Clock cycles post reset, load the binary value:
Bits 5-2 determine the major carry to be evaluated.
1110
1101
•
•
0001
0000
XX00001 1001000
into RDLY_MSB and RDLY_LSB, respectively. Note, the first two bits of
RDLY_MSB have no affect on read delay timing.
MSB
MSB-1
•
•
LSB+1
LSB
Bits 1-0 determine the stairstep LSB load bits 0 and 1 as follows:
NUM_DDC101S—Load this register with the number of DDC101's that are
cascaded. Up to 63 can be loaded. However, the 32k data words of RAM
available on the board will limit the number of data points storable per
DDC101. The DDC101 Evaluation Software limits this value at 32.
00 selects 20 Bit Level
01 selects 18 Bit Level
10 selects 16 Bit Level
TABLE II. Register Descriptions.
3
TURBO PASCAL PROGRAM USED FOR
PC INTERFACE BOARD COMMUNICATIONS
{Procedure XilinxRefresh updates all control registers}
{on the PC Interface Board
}
procedure XilinxRefresh;
begin
Port[strbaddr] := 0;
{Initialize port strobe high}
Delay(1);
{$A+,B–,E+,F+,G–,I+,L–,N+,O+,R+,S–,V–,X+}
program DDCDEMO;
{ Demonstration program to illustrate communications with the DDC101
{ PC Interface Board via an IBM compatible PC.
{ * The setup configurations are programmed at the top of the main
{ program and can be easily altered by the user.
{ * Program outputs are directed to the screen. Simple program
{ modifications will allow the user to direct the outputs elsewhere.
{ * Note that the maximum number of data points retrievable are limited
{ by Turbo Pascal's ability to allocate 64K bytes of data. Using long
{ integers to retrieve the data limits the number of points to 64K/4
{ or 16K bytes of data. To retrieve the full 32K of data points that
{ the PC Interface Board can collect requires the user to create a
{ large array function.
{
{
Tim Kalthoff
{
Last revised August 2, 1994
}
}
}
}
}
}
}
}
}
}
}
}
}
}
}
{Setup Data Clock Rate}
XilinxWrite(0, DataCkCode);
{Data Clock Register}
{Setup System Clock Rate}
XilinxWrite(1, SysCkCode);
{System Clock Register}
{Send Integration Count Code}
XilinxWrite(5,((IntCountCode AND $7F));
{Integration Count
XilinxWrite(4,((IntCountCode SHR 7) AND $7F));
{Integration Count
XilinxWrite(3,((IntCountCode SHR 14) AND $7F));
{Integration Count
XilinxWrite(2,((IntCountCode SHR 21) AND $07));
{Integration Count
LSB Register}
LSB+1 Register}
MSB-1 Register}
MSB Register}
uses Objects, Drivers, Views, Menus, App, Dos, CRT;
{Send DDC Setup Code}
XilinxWrite(6, ((DDCSetupCode AND $FC0) SHR 6));
{DDC Setup 6 MSB Reg}
XilinxWrite(7, (DDCSetupCode AND $3F));
{DDC Setup 6 LSB Reg}
type
RdWordPoint32= ^RdWordArray32;
RdWordArray32= Array[1..32] of Word;
var
XilinxCtrlCode, NumDDCCode,
DataCkCode, SysCkCode, DLCode
: Byte;
DDCSetupCode, strbaddr, wraddr, readdr, I, J, K, Nt : Word;
pPrintPort
: ^Word;
DXmitDelayCode, IntCountCode
: Longint;
PCPort
: String[4];
dataptr, oflowptr
: pointer;
dataTptr
: ^Longint;
oflowTptr
: ^Byte;
PDDCSetup
: RdWordPoint32;
Error
: Boolean;
DDCSetupText
: String[12];
Itxt
: String[2];
Ktxt
: String[4];
dataTtxt
: String[7];
{ Procedure InitializeLPT defines the addresses for printer port
}
{ communication
}
procedure InitializeLPT;
begin
{Get LPT1 or LPT2 Address from BIOS Memory}
if PCPort = 'LPT1' then pPrintPort := Ptr($40,$08);
if PCPort = 'LPT2' then pPrintPort := Ptr($40,$0A);
wraddr := pPrintPort^;
{Parallel Port Write Address}
readdr := wraddr + 1;
{Parallel Port Read Address}
strbaddr := wraddr + 2;
{Parallel Port Strobe Signal Address}
Port[strbaddr] := 0;
{Initialize Strobe High}
end;
{Procedure XilinxWrite sends data to address identified}
procedure XilinxWrite(XilinxAddr, XilinxData : byte);
begin
Port[wraddr] := $7F AND XilinxAddr;
{Send Address}
Delay(2);
{Delay 2ms}
Port[strbaddr] := 1;
{Strobe Low}
Delay(1);
{Delay 1ms}
Port[strbaddr] := 0;
{Strobe High}
Delay(1);
{Delay 1ms}
Port[wraddr] := $80 OR XilinxData;
{Send Data}
Delay(2);
{Delay 2ms}
Port[strbaddr] := 1;
{Strobe Low}
Delay(1);
{Delay 1ms}
Port[strbaddr] := 0;
{Strobe High}
Delay(1);
{Delay 1ms}
end;
4
{Instruct Xilinx to Send Setup Code On To DDC}
XilinxWrite(11, (XilinxCtrlCode AND $F7));
{Xilinx Control Register}
XilinxWrite(11, (XilinxCtrlCode OR $08));
{Strobe DDC Setup Reset}
{Send Data Transmit Delay Count Code}
XilinxWrite(9, ((DXmitDelayCode AND $F80) SHR 7));
{Data Xmit Count 5 MSB Register}
XilinxWrite(8, (DXmitDelayCode AND $7F));
{Data Xmit Count 7 LSB Register}
{Send Add'l DDC Quantity (1 Assumed)}
XilinxWrite(10, NumDDCCode); {DDC Count Register}
{Send DL Select}
XilinxWrite(12, DLCode);
end;
{DL Register}
{Procedure getDataMem allocates memory for data.}
procedure getDataMem(Nsize: Word);
var
memget : Word;
memerr : boolean;
begin
memerr := False;
memget := Nsize*sizeof(Longint);
if MaxAvail >= memget then getmem(dataptr, memget)
else memerr := True;
memget := Nsize*sizeof(Byte);
if MaxAvail >= memget then getmem(oflowptr, memget)
else memerr := True;
if memerr = True then
begin
writeln('Non-Recoverable Memory Shortage—Program Halt');
halt;
end;
end;
nib := ((PORT[readdr] XOR $80) AND $F0) SHR 4;
{XOR Inverts bit 7 (-busy), AND F0 gets rid of 4 lower bits,
Shift right puts the data bits in lower nibble}
Fnum := Fnum SHL 4;
FNum := Fnum OR nib;{Add nibble to final number}
end;
PDDCSetup^[I] := FNum;
end;
end;
XilinxCtrlCode := XilinxCtrlCode OR $22; {Set Wr/Rd Control and}
{R D/S Bits High
}
XilinxWrite(11, XilinxCtrlCode);
{Xilinx Control Register }
Delay(250);
end;
{Procedure freeDataMem releases memory allocated for data.}
procedure freeDataMem(Nsize: Word);
var
memfree : Word;
memerr : boolean;
begin
memfree := Nsize*sizeof(Longint);
freemem(dataptr, memfree);
memfree := Nsize*sizeof(Byte);
freemem(oflowptr, memfree);
end;
{Procedure ReadSetup reads back DDC101 setup data which is copied on}
{execution to PC Interface Board RAM.
}
procedure ReadSetup(NumDDC, XilinxCtrlCode : Byte;
strbaddr, wraddr, readdr : Word;
var SURdError : Boolean;
var PDDCSetup : RdWordPoint32);
var
FNum, J
: Longint;
DFormat, BusyBit3
: Integer;
Nib, PortData, I
: Byte;
iRd, K
: Word;
{Procedure ReadData reads back DDC101 conversion data stored in}
{PC Interface Board RAM.
}
procedure ReadData(dataptr, oflowptr : pointer; Nt : longint;
NumDDC, XilinxCtrlCode : Byte;
DDCSetupCode, strbaddr, wraddr, readdr : Word;
var RdError : Boolean);
{Needs 12 bit setup code from main program. This procedure checks data
valid until ready, reads the data word 4 bits at a time, MSB first, reassembles
it, check for positive or negative overflow, determines data format, (unipolar or
BTC), returns a final 20 bit number (Fnum) in the proper format, then
decrements memory address.}
begin
{Instruct Xilinx to fetch DDC101 setup to PC Interface Board RAM}
XilinxCtrlCode := XilinxCtrlCode AND $FD; {Set R D/S Bit Low}
XilinxWrite(11, XilinxCtrlCode); {Xilinx Control Register}
Delay(250);
XilinxCtrlCode := XilinxCtrlCode AND $DD; {Set Wr/Rd Control Low}
XilinxWrite(11, XilinxCtrlCode); {Xilinx Control Register}
var
DataT
Oflow
FNum, J
DFormat, BusyBit3
Nib, PortData, I
iRd, K
{Wait For PC Interface Board Data Valid}
K := 0;
SURdError := False;
BusyBit3 := (PORT[readdr] AND $08) SHR 3; {Initialize bit 3}
While (BusyBit3 <> 1) AND (K <= 20000) do
begin
BusyBit3 := (PORT[readdr] AND $08) SHR 3;
inc(K);
if (K mod 10) = 0 then delay(1);
if K = 20000 then SURdError := True;
end;
:
:
:
:
:
:
^Longint;
^Byte;
Longint;
Integer;
Byte;
Word;
begin
DataT := dataptr;
{Initialize pointers}
Oflow := oflowptr;
Inc(DataT, Nt*NumDDC-1); {Start pointers at end of memory allocated}
Inc(Oflow, Nt*NumDDC-1);
{Set Control Register to Readback Mode}
XilinxCtrlCode := XilinxCtrlCode AND $DF;{Set Wr/Rd Control Bit Low}
XilinxWrite(11, XilinxCtrlCode);
{Xilinx Control Register}
if SURdError = False then
begin
for I := NumDDC downto 1 do
begin
PortData := $6F; {Decrement Xilinx RAM Memory Address}
PORT[wraddr] := PortData;
PORT[strbaddr] := 1;
PORT[strbaddr] := 0;
PORT[strbaddr] := 1;
PORT[strbaddr] := 0;
Fnum := 0;
PortData := $3F;
{Nibble Pointer}
for iRd := 1 to 3 do
{get 3 nibbles}
begin
PortData := PortData - $10; {LSB+2,LSB+1,LSB nibbles}
PORT[wraddr] := PortData;
PORT[strbaddr] := 1;
PORT[strbaddr] := 0;
{Wait For PC Interface Board Data Valid}
K := 0;
BusyBit3 := (PORT[readdr] AND $08) SHR 3;{Initialize bit 3}
While (BusyBit3 <> 1) AND (K <= 20000) do
begin
BusyBit3 := (PORT[readdr] AND $08) SHR 3;
inc(K);
if (K mod 40) = 0 then delay(1);
if K = 20000 then
begin
SURdError := True;
J := 0;
end;
end;
{Wait For PC Interface Board Data Valid}
K := 0;
RdError := False;
BusyBit3 := (PORT[readdr] AND $08) SHR 3;
{Initialize bit 3}
While (BusyBit3 <> 1) AND (K <= 20000) do
begin
BusyBit3 := (PORT[readdr] AND $08) SHR 3;
inc(K);
if (K mod 10) = 0 then delay(1);
if K = 20000 then RdError := True;
end;
{Get Data Stored in PC Interface Board RAM}
if RdError = False then
begin
for J := Nt-1 downto 0 do
{For-Downto structures put }
begin
{last data at array bottom.}
for I := NumDDC downto 1 do
begin
Fnum := 0;
PortData := $6F;
{Prepare for RAM Memory Address}
Port[wraddr] := PortData;{Decrement XilinxRAM
Mem Address}
Port[strbaddr] := 1;
Port[strbaddr] := 0;
Port[strbaddr] := 1;
Port[strbaddr] := 0;
5
{Prepare for RAM Memory Address (PortData := $6F;)}
for iRd := 1 to 6 do
{Get 6 nibbles}
begin
PortData := PortData - $10;
{MSB, MSB-1,...,LSB nibble}
Port[wraddr] := PortData;
Port[strbaddr] := 1;
Port[strbaddr] := 0;
{Wait For PC Interface Board Data Valid}
BusyBit3 := (Port[readdr] AND $08) SHR 3; {init bit 3}
While (BusyBit3 <> 1) do
BusyBit3 := (Port[readdr] AND $08) SHR 3;
nib := ((Port[readdr] XOR $80) AND $F0) SHR 4;
{XOR Inverts bit 7 (-busy), AND F0 gets rid of 4 lower
bits, shift right puts the data bits in lower nibble}
if iRd = 1 then oflow^ := (nib AND $C) XOR $C;
{bit4 = Oflow+ ; bit3 = Oflow-}
{No overflow:
oflow^ = 0}
{Positive overflow: oflow^ = 8}
{Negative overflow: oflow^= 4}
Fnum := Fnum SHL 4;
FNum := Fnum OR nib; {Add nibble to final number}
end;
{Check setup and bit 20 (BTC): 1=BTC, 0=Straight Binary:}
if (DDCSetupCode AND $1 > 0) then
begin
{BTC Sign Extension}
if (Fnum AND $100000) > 0 then
Fnum := Fnum OR $FFF00000; {bits 31-22 := 1}
if (Fnum AND $100000) = 0 then
Fnum := Fnum AND $000FFFFF; {bits 31-22 := 0}
end
else
{Straight Binary w/Offset}
Fnum :=(Fnum AND $000FFFFF) - $1000;
{bits 31-22 := 0, subtract offset}
{Check and adjust zero for No CDS with Bipolar Input:}
if ((DDCSetupCode AND $C00)= 0) AND
((DDCSetupCode AND $2)> 0)
then Fnum :=Fnum - $80000;
DataT^ := Fnum;
dec(DataT);
dec(Oflow);
end;
end;
end;
{Set Control Register to Data Write Mode}
XilinxCtrlCode := XilinxCtrlCode OR $20; {Set Wr/Rd Control Bit High}
XilinxWrite(11, XilinxCtrlCode);
{Xilinx Control Register}
end;
{Main Program — Uses above units to execute basic PC Interface Board }
{
operations. Suitable for application specific modifactions. }
begin
{Setup Printer Port}
PCPort := 'LPT1';
InitializeLPT;
{Configure Control Registers}
DataCkCode := 1;
{4MHz Data Clock}
{DataCk = 16MHz/(2(SysCkCode+1) — 16MHz is the Xtal freq}
SysCkCode := 3;
{2MHz System Clock}
{SysCk = 16MHz/(2(SysCkCode+1) — 16MHz is the Xtal freq}
IntCountCode := 1000;
{Integration Time=1000 Sys Clocks (500µs)}
DDCSetupCode := $941; {16 Acq, 32 Sam, 1 Int, Uni,BTC}
DXmitDelayCode := 100; {100 Delay Clocks}
NumDDCCode := 1;
{1 DDC Under Test}
XilinxCtrlCode := $2B;
{Internal Data Clock, Collect DDC101
Data, Enable FDS, Reset Setup Off,
DDC101 Test Signal Off, Read Data,
Reset System Off}
DLCode := $3A;
{MSB Major Carry, 16 Bit LSB}
XilinxRefresh;
Nt := 20;
Error := False;
{Retrieve 20 data points from PC Interface Board}
{Set error flag}
6
{Readback DDC101 Setup Code}
ReadSetup(NumDDCCode, XilinxCtrlCode, strbaddr, wraddr, readdr,
Error, PDDCSetup);
ClrScr;
if Error = True then
begin
writeln('Setup Readback Error. Possible causes include: ');
writeln('Power supply off, bad cable, incorrect PC port, ');
writeln('or DDC101 not installed.
');
end
else
{No readback error detected}
begin
for K := 1 to NumDDCCode do
begin
J := 1;
DDCSetupText :='000000000000'; {Initialize text output variable}
for I := 0 to 11 do
begin
if PDDCSetup^[K] AND J > 0 then
DDCSetupText[12-I] := '1'
else
DDCSetupText[12-I] := '0';
J := J SHL 1;
end;
writeln ('Setup DDC #',K,' = ', DDCSetupText);
end;
end;
delay(5000); {5 second delay for data collection to PC interface board}
getDataMem(Nt*NumDDCCode);
{Read DDC101 Data Collected in PC Interface Board}
ReadData(dataptr, oflowptr, Nt, NumDDCCode, XilinxCtrlCode,
DDCSetupCode, strbaddr, wraddr, readdr, Error);
writeln(' ');
if Error = True then
begin
writeln('Data Retrieval Error. Possible causes include:');
writeln('Power supply off, bad cable,incorrect PC port, ');
writeln('DDC101 not installed, or no external FDS trigger');
writeln('(if so configured). ');
end
else
{No readback error detected}
begin
dataTptr := dataptr;
oflowTptr := oflowptr;
for K := 1 to Nt do
begin
for I := 1 to NumDDCCode do
begin
str(K:4,Ktxt);
str(I:2,Itxt);
str(dataTptr^:7,dataTtxt);
writeln('Data Pt',Ktxt,'
DDC #',Itxt,' = ',dataTtxt,
' , ',oflowTptr^); {No overflow:
oflowTptr^ = 0}
{Positive overflow: oflowTptr^ = 8}
{Negative overflow: oflowTptr^ = 4}
inc(dataTptr);
inc(oflowTptr);
end;
end;
end;
freeDataMem(Nt*NumDDCCode);
end.
FIGURE 1. Circuit Diagram of PC Interface Board.
7
IPAD
P24 I
I
IBUF
O
CLK
P6
I
I
O
BNC
P75
I
I
O
STRB
P76
I
I
O
0
P77
I
I
O
1
MCLK
P78
I
I
O
2
DCK_SOURCE
P79
I
I
O
3
P80
I
I
O
4
P81
I
I
O
5
I
GCLK
O
MCLK
BNC
SETDCLK
DDCCKC
SETSCLK
P82
I
I
O
6
P83
I
I
O
Bit_7
SETDCLK
DCK_SOURCE
SETSCLK
SCLK
BNC
DCLK
I_BUS
R_SYS
DL_SET
STRB
FDS
BIT_7
SETUP
DL_SET I
OBUF
O
OPAD
O P30
R_SYS I
O
O
P63
FDS I
O
O
P62
SETUP I
O
O
P59
SETUPCLK I
O
O
P35
RD_D/Sb I
O
O
P44
TEST I
O
O
P56
RDLY_LSB I
O
O
P37
RDLY_MSB I
O
O
P38
NUM_DDCS I
O
O
P39
R_SETUP I
O
O
P58
W/RB I
O
O
P40
WORD_LEN I
O
O
P41
SCLK I
O
O
P47
DCLK I
O
O
P48
DECMEM I
O
O
P42
READ_LSB I
O
O
P49
READ_MID I
O
O
P50
READ_MSB I
O
O
P51
SETUPCLK
I_BUS<0: 6>
I_BUS
DDCDIN
RD_D/Sb
READADD2
TEST
READADD1
RDLY_LSB
READADD0
RDLY_MSB
NUM_DDCS
SCLK
R_SETUP
DCLK
W/RB
Bit 6
P2
O
O
I
Bit 7
P3
O
O
I
Bit 5
RD_D/SB
I
DCLK
O
STRB
O
READADD0
OBUF
P64
READADD1
OPAD
READADD2
WORD_LEN
W/RB
DECMEM
READ_D2
READ_LSB
READ_D3
READ_D1
P4
O
O
I
READ_MID
DDCODC
READ_D0
READ_MSB
RAM_DE
READ_DV
Bit 4
DV
O
O
I
Bit 3
DIN_BUS
P5
DIN BUS<0: 7>
IPAD
P14 I
I
IBUF
O
7
P15
I
I
O
6
P16
I
I
O
5
Dedicated Pins
P17
I
I
O
4
P18
I
I
O
3
Do Not Change
I
OBUF
O
OPAD
O P34
IPAD
P46 I
I
IBUF
O
P52
I
O
I
I
I
O
2
P20
I
I
O
1
P21
I
I
O
0
GND
+5
I
OBUF
O
RAM_OE
IPAD
P45 I
HDC
P19
DV
OPAD
O P36
LDC
FIGURE 2. DDC101 PC Interface, XILINX U1 Setup PROM U5.
8
I
IBUF
O
RD_S
I
OBUF
O
OPAD
O P60
RAM BYTE SELECT AND ADDRESS CONTROL
READADD1
READADD2
A0
00
A1
01
D2-4
READ_LSB
READ_MID
02
READ_MSB
03
D
FD
C
STRB
Q
DECMEM
NIB SELECT OF RAM BYTE
DIN_BUS
HX257
2
2
5
6
11
10
14
13
1
15
0
4
1
5
2
6
3
7
(MSNIB/LSNIB)
READADD0
Y1
A1
B1
A2
B2
A3
B3
A4
B4
AB
GB
Y2
Y3
Y4
4
READ_D0
7
READ_D1
9
READ_D2
12
READ_D3
GND
UXX
PC READBACK DATA VALID GENERATOR
STRB
RAM_OE
(READ_EN)
I
RD_D/SB
0
INV
+5
DATA VALID SETUP DELAY
D
1
2 AND
DV
0
C
1
FDRD
Q
2
OR
0
1
2
3
AND
0
D
C
FDRD
Q
D
C
RD
W/RB
D
C
FD
Q D
C
FD
Q
1
2 AND
0
FDRD
RD
Block READ_DV Unless DV
Transitions During Data
Write Operation “OR”
Setup Readback Executed.
RD
I
0
INV
DCLK
FIGURE 3. DDC101 Setup PROM U5, Output Data Control (DDCODC).
9
Q
READ_DV
I BUS
DATA/ADD
2
AND
O
Q6
READADD2
5
D5
Q5
READADD1
4
D4
Q4
READADD0
3
D3
2
D2
1
D1
PLATCH7
D6
D0
0
REGISTER SELECT
I
Q3
O
INV
Q2
Q1
Q0
2 NOR
07
06
05
74-138
DL_SET 04
CTRL 03
RDLY_LSB 01
RDLY_MSB 00
NUM_DDCS 02
SETUP_LSB 07
SETUP_MSB 06
FDS_LSB 05
FDS_MID1 04
SETSCLK 01
FDS_MID2 03
SETDCLK 00
FDS_MSB 02
CONTROL
REGISTER
GND
E3
E2
E1
A2
A1
A0
E3
E2
E1
A2
A1
O
74-138
STRB
A0
C
1
LOAD SETUP GENERATOR
6
D6
Q6
DCK_SOURCE
5
D5
Q5
W/RB
4
D4
Q4
FDS_SOURCE
D6
Q6
D0
3
D3
Q3
R_SETUP
5
D5
Q5
D1
2
D2
Q2
TEST
4
D4
Q4
D2
1
D1
Q1
RD_D/Sb
3
D3
Q3
D3
0
D0
Q0
R_SYS
2
D2
Q2
S0
1
D1
Q1
S1
0
D0
MSB
C
PLATCH7
1
6
PLATCH7
Bit 7
M4-1
0
Q0
D0
C
D1
D2
D3
0
M4-1
S0
Q6
5
D5
Q5
D0
4
D4
Q4
D1
3
D3
Q3
D2
2
D2
1
D1
0
D0
PLATCH7
D6
S1
Q2
D3
Q1
S0
Q0
S1
D0
D1
M4-1
0
D2
M3-1
SO
S1
C
LSB
WORD_LEN
Q0
Q1
C16BARD
C
FD
Q
I
O
2
RD
0
INV
NAND 1
D
Q2
Q3
C
0
DCLK
SETUPCLK
FDS GENERATOR
D0
D1
D2
D3
UD
Q0
C16BUDRD
Q1
PE
Q2
C
Q3
CE
TC
1
2 AND
BNC
0
I
RD
I
1
O
D1
C
D2
Q5
D3
D4
Q4
UD
Q3
PE
Q2
Q2
C
Q3
Q1
CE
D3
D2
1
D1
0
D0
PLATCH7
Q6
D5
2
0
D
D6
FD
Q
1
1
2
OR
0
Q0
C16BUDRD
Q1
TC
Q0
C
RD
D0
D6
Q6
5
D5
Q5
4
D4
Q4
D3
3
D3
Q3
UD
2
D2
Q2
PE
Q2
1
D1
Q1
C
Q3
0
D0
Q0
CE
PLATCH7
MID2
6
D1
D2
Q0
C16BUDRD
Q1
TC
C
RD
D0
D6
Q6
5
D5
Q5
4
D4
Q4
D3
3
D3
Q3
UD
2
D2
Q2
PE
1
D1
Q1
C
0
D0
Q0
CE
PLATCH7
MID1
6
D1
D2
Q0
C16BUDRD
Q1
Q2
Q3
TC
C
RD
D0
D1
Q6
D5
Q5
D3
D4
Q4
UD
Q3
PE
Q2
Q2
C
Q3
Q1
CE
D3
LSB
D2
D1
PLATCH7
D6
D0
D2
Q0
C16BUDRD
Q1
TC
Q0
C
RD
D0
D1
D2
D3
UD
SCLK
I
ACLK
0
+5
Q0
C16BUDRD
Q1
PE
Q2
C
Q3
CE
2
INV
INV
D0
MSB
3
AND 2
1
TC
RD
GND
FIGURE 4. DDC101 Setup PROM U5, Data In (DDCDIN).
10
2 AND
0
OR
0 FDS
0 SETUP
I_BUS
D_CLK RATE CONTROL
RD
CE
C
Q
FDC
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
MCLK
D
INV
0
I
1
2
0
SETDCLK
Q6
D6
Q5
D5
Q4
D4
Q3
D3
D2 PLATCH7 Q2
Q1
D1
Q0
D0
C
RD
1
2
+5
OR
0
DCLK
I
GND
0
AND
INV
6
5
4
3
2
1
0
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
DCK_SOURCE
1
BNC
2
AND
0
S_CLK RATE CONTROL
6
5
4
3
2
1
0
SETSCLK
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
Q6
D6
Q5
D5
Q4
D4
Q3
D3
D2 PLATCH7 Q2
Q1
D1
Q0
D0
C
RD
CE
C
Q
FDC
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
RD
GND
+5
FIGURE 5. DDC101 Setup PROM U5, Clock Control (DDCCKC).
11
D
INV
0
I
SCLK
FIGURE 6. DDC101 PC Interface, XILINX U2 Setup PROM U6.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
P84
P2
P3
P4
P5
IPAD
P61 I
I
P83
P75
P77
P81
P70
P69
P80
P79
I
I
P66
P6
O
I
I
P68
P67
OPAD
I
I
P76
O
I
I
I
P78
I
I
IPAD
P82 I
SETUPCLK
SCLK
DCLK
RDLY_MSB
RDLY_LSB
O
O
O
O
O
I
OBUF
O
O
O
O
RAM_WE
READ_MSB
READ_MID
READ_LSB
DECMEM
W/RB
NUM_DDCS
O
O
WORD_LEN
RD_D/Sb
6
5
4
3
2
1
0
O
IBUF
O
O
O
O
O
O
O
I_BUS<0: 6>
DECMEM
RAM_WE
READ_MSB
READ_MID
READ_LSB
DCLK
DDCMEM
CE_MSB
CE_MID
CE_LSB
RAM_OE
CS1
CS0
L_DATAo
DXo
RD_S
DCLK
RDLY_MSB
RDLY_LSB
I_BUS
SETUPCLK
DL3
DL2
DL1
DL0
O
O
O
O
CE_MID I
CE_MSB I
D_IN I
O
O
O
O
P53
P8
P9
P10
OPAD
O
P7
I
INV
O
DOUT_BUS<0:7>
CE_LSB I
SCLK
OBUF
O
GND
RD_D/Sb
DDCCDC
WORD_LEN
RAM_OE I
ADD_BUS<0:14>
CS1
CS0
RD_S
RD_S
DXo
L_DATAo
NUM_DDCS
DOUT_BUS
IBUF
O
ADD BUS
12
DL_SET
DXo
RD_S
RD_D/Sb
W/RB
DV
DX
DCLKOUT
SDATA
P_OFLOW
N_OFLOW
OBUF
O
I
N_OFLOW
P_OFLOW
SDATA
DCLKOUT
DX
O
O
O
I
I
IBUF
I
I
I
O
OBUF
O
IBUF
I
I
O
DL_SET
O
O
O
I
DL3
DV
I
O
I
DL2
IBUF
O
I
DL1
I
I
I
O
O
I
O
O
O
O
O
I
DL0
O
OBUF
O
I
RD_S
P48
P46
P52
P51
P49
P50
P63
P11
P60
P59
P58
P57
P62
+5
I
GND
P14
P15
P16
P17
P18
P19
P20
P21
P23
P24
P25
P26
P27
P28
OPAD
P29
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
OBUF
O
O
O
OPAD
P36
LDC
OPAD
P34
HDC
Do Not Change
Dedicated Pins
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
OBUF
I
O
O
O
1 I
0 I
O
O
O
O
O
O
O
O
O
O
O
O
OBUF
O
2 I
3 I
4 I
5 I
6 I
7 I
8 I
9 I
10 I
11 I
12 I
13 I
14 I
0
1
2
3
4
5
6
7
I
T
I
T
I
T
I
T
I
T
I
T
I
T
I
T
O
O
O
O
O
O
O
O
TBUF
O
O
O
O
O
O
O
O
P35
P37
P38
P39
P40
P41
P44
P45
FIGURE 7. DDC101 Setup PROM U6, Memory Control (DDCMEM).
13
RD_S
RD_D/Sb
W/RB
DCLK
2 NOR
1
2 NOR
1
2 NOR
1
WR_DONE
0
0
0
2
1
RD
FDRD
Q
I
0
0
2 NOR
1
0
0
2
1
AND
0
RAMCLK1
2 NOR
1
Set RAM_OE to Read Mode After
END_DATA Received Post RD_D/Sb
Goes Low.
0
2 NOR
2 NOR
1
0
NOR
Send Pulse For
Readback Reset of
Data Write When
RD_D/Sb Goes Low.
AND
1
1
2
3
0
INV
Block W/RB Status Change
While Transmitting Data From
DDC101 or Writing Data Into
RAM.
C
D
Delay WR_DONE 1/2 DCLK Cycle
to Ensure MEMCLK Pulse.
DX o
L_DATAo
+5
C
D
0
2
C
D
C
D
C
D
Q
RD
U9
FDRD
RD
U4
FDRD
Q
Q
RD
Q
CNT_U/DB
2 NAND
1
0
RD
U6
FDRD
WRITE MID
C
D
OUTPUT BYTE SELECT
U5
FDRD
Q
WRITE LSBYTE
C
D
RD
FDRD
RAMCLK2
C
D
3
2
NOR
1
Q
FD
0
RD
FDRD
NOR 1
Q
RD
U7
FDRD
Q
C
D
RAM_OE
RAM_WE
WRITE MSBYTE
C
D
CS0
CS1
RD
U7
FDRD
Q 1
2
OR
0
DECMEM
READ_LSB
READ_MID
READ_MSB
WR_DONE
GND
Out
2
3
5
6
11
10
14
13
1
15
Y4B 12
Y3B 9
Y2B 7
Y1B 4
UO1
A1
B1
A2
B2
A3
B3
A4
B4
AB
GB
INV
0
I
ACLK
0
RAM FUNCTION SELECT
I
CE_LSB
CE_MID
CE_MSB
RAM CHIP SELECT
HX158
+5
MEMCLK
GND
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
MEMORY ADDRESS COUNTER
ADD_BUS<0: 14>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DV
P_OFLOW
N_OFLOW
WORD_LEN
I_BUS
RDLY_LSB
RDLY_MSB
END_DATA
SCLK
I
DOUT_BUS
CS1
CS0
0
2
1
INV
I
2
1
OR
C
D
C
D
6
5
4
3
2
1
0
0
1
0
C
D
FD
FD
Q
Q
RD
FDRD
Q
LDV
FD
FD
Q
Q
Q6
D6
Q5
D5
Q4
D4
Q3
D3
D2 PLATCH7 Q2
Q1
D1
Q0
D0
C
C
D
C
D
INV SCLK
0
OR
0
0
1
2
Q
C
END_DATA
AND
DCLK
RD
Q D
I
FD
RD
FDRD
C
FDRD
INV
Q
RD_So
+5
SCLK
RD
FDRD
GND
0 LDV
C
D
C
Q D
C
DV
INV
C
D
FD
Q
D
D
2
0
D
RD
FTPRD
AND
0
0
Q
READ DELAY
COUNTER
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
RD
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
C
T
PE
2
1
1
2 AND
AND
1
0
S1
S0
D2
D1
D0
0
M3-1
7
RD8
MIDDLE
D
DLY_TC
RD_S_R
FDRD
Q
I
1
RD_S
D
SCLK C
DCLK
END_DATA
RD
LSB
2
0
0
C
D
SDATA
OR
DCLK
INV
DXo
Q
SDCK
2
1
I
OR
5
4
3
2
1
0
D0
D1
D2
S0
S1
DL_SET
Q6
D6
Q5
D5
Q4
D4
Q3
D3
D2 PLATCH7 Q2
Q1
D1
Q0
D0
C
ACQUIRE DATA ON
DCLK FALLING EDGE
RD
FDRD
DX
0
2
1
D0
D1
D2
S0
S1
I
0
0
I
2
1
DX
D
M3-1
DL0
D0
D1
D2
S0
S1
0
FTP
0
Q
0
2
1
RD
M3-1
DL1
0
SETUPCLK
AND
+5
DL2
OR
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
C
T
PE
1 AND
2
BIT COUNTER
BIT LEVEL SELECT
0
INV
DCLK
GND
AND
2 NAND
1
0
0
GCLK
M3-1
0
INV
RD_S
I
RD_D/Sb I
6
M3-1
S1
S0
D2
D1
D0
0
M3-1
5
RS4
Q3
Q2
Q1
Q0
C
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
OF_P
OF_N
WL21
D20
D19
D18
D17
D16
S1
S0
D2
D1
D0
0
C
3
S1
S0
D2
D1
D0
0
RD8
S1
S0
D2
D1
D0
M3-1
0
M3-1
4
RS8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
C
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
D15
D14
D13
D12
D11
D10
D9
D8
1
0
2
0
OR
C
0
2
+5
2
M3-1
S1
S0
D2
D1
D0
0
S1
S0
D2
D1
D0
M3-1
1
RS8
RD8
INV
1
OR
3
2
1
0
0
D0
D1
D2
D3
D4
D5
D6
D7
S0
S1
S2
D0
D1
D2
D3
D4
D5
D6
D7
S0
S1
S2
MB-1
MB-1
DCLKOUT
0
0
DCLK
Q
C
D
T
FTP
2
1
2
1
AND
AND
AND
C
0
Q
0
Q
FTP
AND
0
0
2
1
OR
1
2
Q
RD
AND
RD
FD
MAJOR CARRY SELECT
L_DATA
RD
FD
GND
1
2
D
PE
1
2
3
FDRD
Q
0
DCLK
DL3
RD
FDRD
DDC_TC
L_DATAo
0
C
D
NUMBER OF
DDCS COUNTER
D0
D1
D2
Q0
D3
UD C16BUDRD Q1
Q2
PE
Q3
C
TC
CE
C
T
PE
D
C
D
NOTE: Writing to RAM Sequence
LSB, MIDDLE, MSB.
C
D
DCLK
DCLK
Q6
D6
Q5
D5
Q4
D4
Q3
D3
D2 PLATCH7 Q2
Q1
D1
Q0
D0
C
NUM_DDCS
5
4
3
2
1
0
BC_TC
0
OR
D
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
C
D7
D6
D5
D4
D3
D2
D1
D0
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
D2
D1
D0
0
M3-1
0
INV
14
I
FIGURE 8. DDC101 Setup PROM U6, Collect Data Control (DDCCDC).
Q
END_DATA
FIGURE 9. Circuit Diagram of DDC101-DUT Board.
15
GND
–5VDC
+5VDC
P2 -
NC
NC
NC
GND
Test
GND
R_SET
GND
SET
GND
RD_D/S
GND
R SYS
GND
FDS
GND
S_CLK
GND
OFLOW+
GND
D_XMIT
GND
OFLOW–
GND
D_CLK
GND
D_VAL
GND
D_OUT
GND
D_IN
GND
NC
NC
P1 -
8
3
5
7
9
D_XMIT
D_OUT
D_VALID
OFLOW–
OFLOW+
23
22
21
20
19
3
5
7
SETUP
RESET
TEST
7
6
5
1
2
3
1
2
3
D3
IN5820
8
RD_D/S
8
Y3
Y4
Y5
Y6
Y7
Y8
A4
A5
A6
A7
A8
D4
C8
IN5820
+ 10µF
20V
19
Y2
Y1
2A1
2A2
2A3
2A4
1Y4
1Y3
1Y2
1Y1
A3
EN2
EN1
1
U1
74ALS541
19
2G
1G
1
U2
74ALS244
A2
A1
2Y1
2Y2
2Y3
2Y4
1A4
1A3
1A2
1A1
–5V Analog
9
6
4
4
FDS
R_SYS
10
9
2
S_CLK
11
12
13
14
15
16
17
18
6
4
2
D_CLK
D_IN
24
25
26
27
28
29
30
31
32
33
34
R3
10kΩ
+
C9
10µF
20V
+5V Analog
D2
IN5820
11
12
13
14
15
16
17
18
11
13
15
17
12
14
16
18
R8
10Ω
R7
10Ω
R1
10kΩ
+5V Digital
26
25
24
23
9
10
11
19
18
17
16
20
12
13
DIG
+5V Digital
R2
10kΩ
TEST
RESET
SETUP
RD_D/S
R_SYS
FDS
S_CLK
OFLOW+
OFLOW–
D_VALID
D_OUT
D_XMIT
D_CLK
D IN
GNDD
VDD
VBUF
VREF
VSPA
VSPA
GNDA
INPUT
GNDA
VSNA
15
14
28
27
6
5
4
3
2
1
C5
0.1µF
R6
10Ω
= Analog Ground
= Digital Ground
C6
+ 10µF
R4
1kΩ
C4
0.1µF
C3
0.1µF
C7
+ 10µF
+5V
Analog
–5V
Analog
–5V Analog
J2
BNC
J1
BNC
+5V Analog
D1
–2.5V Ref
REF1004-2.5
R5
24.9kΩ
Z2
Z1
Z3