FREESCALE MAC7200

MAC7200RM
Rev. 2
04/2007
MAC7200 Microcontroller Family
Reference Manual
Devices Supported:
PAC7202
PAC7212
MAC7242
PAC7201
PAC7211
MAC7241
This document covers the following mask sets:
MAC72x2 – 0M34A, 1M34A, 0M84D, 1M84D
MAC72x1 – 0M19G
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
i
MAC7200 Microcontroller Family Reference Manual, Rev. 2
ii
Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
Figures .............................................................................................................................. xli
Tables................................................................................................................................ liii
Preface
Document Structure ......................................................................................................... lxv
How To Use This Document............................................................................................ lxv
Conventions .................................................................................................................... lxvi
Terminology.................................................................................................................... lxvi
Register Descriptions .................................................................................................... lxxiii
Revision History
Content Changes by Document Version ...................................................................... lxxvii
Chapter 1
Introduction
1.1
1.2
1.2.1
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.4
1.5
Overview..............................................................................................................................1
Features ................................................................................................................................1
Performance Summary ....................................................................................................8
Modes of Operation .............................................................................................................9
Single Chip mode (Unsecured)......................................................................................10
Single Chip mode (Secured) ..........................................................................................10
PBL Chip mode (Secured).............................................................................................10
PBL Chip mode (Unsecured).........................................................................................11
Expanded Chip mode (Secured) ....................................................................................11
Expanded Chip mode (Unsecured) ................................................................................11
Low Power Modes .........................................................................................................11
Debug Mode ..................................................................................................................12
Block Diagram ...................................................................................................................13
System Memory Map.........................................................................................................14
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Chapter 2
Modes of Operation
2.1
2.2
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.2
2.3.3
2.3.3.1
2.3.3.2
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.5
2.6
2.7
2.8
2.8.1
2.8.2
2.9
Introduction........................................................................................................................15
MCU Hardware Configuration Summary..........................................................................15
Security ..............................................................................................................................15
Operation of the Secured Microcontroller .....................................................................16
Single Chip Secured Mode ........................................................................................16
Executing from External Memory .............................................................................16
Securing the Microcontroller .........................................................................................16
Unsecuring the Microcontroller.....................................................................................16
Software Unsecure.....................................................................................................17
JTAG Lockout Recovery ...........................................................................................17
MCU Mode Selection ........................................................................................................17
Normal Single Chip Mode.............................................................................................18
Secured Single Chip Mode ............................................................................................18
Normal Primary Bootloader Mode ................................................................................19
Secured Primary Bootloader Mode................................................................................19
Normal Expanded Mode................................................................................................19
Secured Expanded Mode ...............................................................................................20
Oscillator Type Selection...................................................................................................20
Nexus Port Selection..........................................................................................................20
External Bus Configuration ...............................................................................................21
Low Power Modes .............................................................................................................21
Doze ...............................................................................................................................22
Run.................................................................................................................................22
Debug Mode ......................................................................................................................22
Chapter 3
Low Power Modes
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Low Power Modes Introduction ........................................................................................23
Run Mode ..........................................................................................................................23
Doze Mode.........................................................................................................................23
Disabled Mode ...................................................................................................................24
System Wakeup..................................................................................................................25
Low Power Mode Differences from MAC71xx ................................................................25
Low Power Mode Summary ..............................................................................................26
Special Notes on Entering and Exiting Power Modes .......................................................26
Chapter 4
Signal Description
4.1
Device Pinout.....................................................................................................................29
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Freescale Semiconductor
4.2
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
4.3.11
4.3.12
4.3.13
4.3.14
4.3.15
4.3.16
4.3.17
4.3.18
4.3.19
4.3.20
4.3.21
4.3.22
4.3.23
4.3.24
4.3.25
4.3.26
4.3.27
4.3.28
4.3.29
4.3.30
4.3.31
4.3.32
4.3.33
4.3.34
Signal Properties Summary ..............................................................................................33
Detailed Signal Descriptions .............................................................................................39
EXTAL, XTAL — Oscillator Pins.................................................................................39
RESET — External Reset Pin .......................................................................................39
XFC — PLL Loop Filter Pin .........................................................................................39
TDI — Test Data In Pin.................................................................................................40
TDO — Test Data Output Pin........................................................................................40
TCK — Test Clock Pin..................................................................................................40
TMS — Test Mode Pin..................................................................................................40
PA[0:7] / DATA[0:7] — Port A I/O Pins and external Databus ....................................40
PA[8] / DATA[8] / PCS[4] — Port A I/O Pin, External Databus, and DSPI_B ............40
PA[9] / DATA[9] / PCS[3] / NEX1EVTI — Port A I/O Pin, External Databus,
DSPI_B and Nexus Primary ......................................................................................41
PA[10:15] / DATA[10:15] — Port A I/O Pins and external Databus ............................41
PB[0] / SDA / NEX1MCKO — Port B I/O Pin, IIC and Nexus Primary .....................41
PB[1] / SCL / NEX1EVTO — Port B I/O Pin, IIC and Nexus Primary .......................41
PB[2] / SIN_A / NEX1MSEO — Port B I/O Pin, DSPI_A and Nexus Primary...........41
PB[3] / SOUT_A / NEX1RDY — Port B I/O Pin, DSPI_A and Nexus Primary .........42
PB[4] / SCK_A — Port B I/O Pin and DSPI_A............................................................42
PB[5] / PCS[0] / SS[0] — Port B I/O Pin and DSPI_A ................................................42
PB[6:7] / PCS[1:2] — Port B I/O Pin and DSPI_A ......................................................42
PB[8] / PCS[5] / PCSS — Port B I/O Pin and DSPI_A ................................................42
PB[9] / PCS0 / SS[1] / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary ..43
PB[10] / PCS[5] / PCSS — Port B I/O Pin and DSPI_B ..............................................43
PB[11] / PCS[2] / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary ..........43
PB[12] / PCS[1] — Port B I/O Pin and DSPI_B...........................................................43
PB[13] / SCK_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary .........44
PB[14] / SOUT_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary.......44
PB[15] / SIN_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus Primary...........44
PC[0:2] / ADDR[0:2] — Port C I/O Pins and External address bus .............................44
PC[3] / ADDR[3] / NEX2EVTI — Port C I/O Pins, External Address Bus and Nexus
Secondary ..................................................................................................................44
PC[4] / ADDR[4] / NEX2MCKO — Port C I/O Pins, External Address Bus and
Nexus Secondary .......................................................................................................45
PC[5] / ADDR[5] / NEX2EVTO — Port C I/O Pins, External Address Bus and Nexus
Secondary ..................................................................................................................45
PC[6] / ADDR[6] / NEX2MSEO — Port C I/O Pins, External Address Bus and Nexus
Secondary ..................................................................................................................45
PC[7] / ADDR[7] / NEX2RDY — Port C I/O Pins, External Address Bus and Nexus
Secondary ..................................................................................................................45
PC[8:15] / ADDR[8:15] / MDO[0:7] — Port C I/O Pins, External Address Bus and
Nexus Secondary .......................................................................................................46
PD[0] / BWE[0] / MODB — Port D I/O Pin, External Bus Control & Mode
Selection ....................................................................................................................46
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4.3.35
4.3.36
4.3.37
4.3.38
4.3.39
4.3.40
4.3.41
4.3.42
4.3.43
4.3.44
4.3.45
4.3.46
4.3.47
4.3.48
4.3.49
4.3.50
4.3.51
4.3.52
4.3.53
4.3.54
4.3.55
4.3.56
4.3.57
4.3.58
4.3.59
4.3.60
4.3.61
4.3.62
4.3.63
4.3.64
4.3.65
4.3.66
4.3.67
4.3.68
4.3.69
4.3.70
4.3.71
4.3.72
PD[1] / BWE[1] / MODA — Port D I/O Pin, External Bus Control & Mode
Selection ....................................................................................................................46
PD[2] / CLKOUT / XCLKS — Clock Out and Oscillator Selection ............................46
PD[3] / XIRQ / NMI — Port D I/O Pin, High Priority Interrupt and Non-maskable
Interrupt .....................................................................................................................47
PD[4] / IRQ — Port D I/O Pin, and Maskable Interrupt ...............................................47
PD[5:10] / ADDR[16:21] — Port D I/O Pins and External Address Bus.....................47
PD[11] / OE — Port D I/O Pin and External Bus Control ............................................47
PD[12] / Burst — Port D I/O Pin and External Bus Control.........................................47
PD[13] / TA — Port D I/O Pin and External Bus Control ............................................47
PD[15] / CS0 — Port D I/O Pin and External Bus Control...........................................48
PD[15] / R/W — Port D I/O Pin and External Bus Control ..........................................48
PE[0:15] / AN_A[00:15]— Port E I/O Pins and ATD_A..............................................48
PF[0] / EMIOS[0] / NEXPS — Port F I/O Pins, eMIOS Channels and Nexus Port
Selection ....................................................................................................................48
PF[1] / EMIOS[1] / NEXPR — Port F I/O Pins, eMIOS Channels and Nexus Present
Selection ....................................................................................................................48
PF[2] / EMIOS[2] / AUTOACK — Port F I/O Pins, eMIOS Channels and FlexBus
Ack Selection.............................................................................................................49
PF[3] / EMIOS[3] / AUTOACK — Port F I/O Pins, eMIOS Channels and FlexBus
Port Size.....................................................................................................................49
PF[4:7] / EMIOS[4:7] — Port F I/O Pins and eMIOS Channels ..................................49
PF[8] / PCS[5] / PCSS — Port F I/O Pin and DSPI_C .................................................49
PF[9] / PCS[3] — Port F I/O Pin and DSPI_C..............................................................50
PF[10] / PCS[2] — Port F I/O Pin and DSPI_C............................................................50
PF[11] / SCK_C — Port F I/O Pin and DSPI_C ...........................................................50
PF[12] / PCS[1] — Port F I/O Pin and DSPI_C............................................................50
PF[13] / SOUT_C — Port F I/O Pin and DSPI_C ........................................................50
PF[14] / PCS[0] / SS[0] — Port F I/O Pin and DSPI_C ...............................................50
PF[15] / SIN_C — Port F I/O Pin and DSPI_C ............................................................51
PG[0] / RXD_B — PORT G I/O Pin and ESCI_B........................................................51
PG[1] / TXD_B — PORT G I/O Pin and ESCI_B ........................................................51
PG[2] / RXD_A / NEX1MDO — PORT G I/O Pin, ESCI_A and Nexus Primary.......51
PG[3] / TXD_A / NEX1MDO — PORT G I/O Pin, ESCI_A and Nexus Primary.......51
PG[4] / TCNTX_A / NEX1MDO[2] — PORT G I/O Pin, FlexCAN_A and Nexus
Primary ......................................................................................................................52
PG[5] / CNRX_A — PORT G I/O Pin and FlexCAN_A..............................................52
PG[6] / CNTX_B — PORT G I/O Pin and FlexCAN_B ..............................................52
PG[7] / CNRX_B — PORT G I/O Pin and FlexCAN_B ..............................................52
PG[8] — PORT G I/O Pin .............................................................................................52
PG[9] — PORT G I/O Pin .............................................................................................53
PG[10] — PORT G I/O Pin ...........................................................................................53
PG[11] — PORT G I/O Pin ...........................................................................................53
PG[12] / PCS[4] — Port G I/O Pin and DSPI_A ..........................................................53
PG[13] / PCS[3] — Port G I/O Pin and DSPI_A ..........................................................53
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4.3.73
4.3.74
4.4
4.4.1
4.4.2
4.4.3
4.4.4
4.4.5
4.4.6
4.4.7
4.4.8
4.4.9
4.4.10
4.4.11
4.4.12
PG[14] / PCS[4] — Port G I/O Pin and DSPI_B ..........................................................53
PG[15] / PCS[3] — Port G I/O Pin and DSPI_B ..........................................................54
Power Supply Pins .............................................................................................................54
VPP — Power For Flash Program and Erase ................................................................54
VDDX1-4,6-11, VSSX1-11 (except VDDX5) — Power and Ground Pins for
I/O Drivers .................................................................................................................54
VDDX5 /VDDAPASS — Power Pin for I/O Drivers and Control Voltage for Internal
Pass Transistors..........................................................................................................54
VDDR/VREGEN — Power Pin for the Internal Voltage Regulator .............................54
VDD15a, VSS15a — Core Power Pins .........................................................................55
VDD15c/VDDF, VSS15c/VSSF — Core and Flash Logic Power Pins........................55
VDD33/VFLASH, VSS33 — Flash and I/O Pre-Driver Power Pins............................55
VDDA, VSSA — Power Supply Pins for ATD and Voltage Regulator Control...........55
VRH, VRL — ATD Reference Voltage Input Pins .......................................................56
REFBYPC — ATD Reference Voltage Bypass Capacitor ............................................56
VDDPLL, VSSPLL — Power Supply Pins for PLL .....................................................56
VSS-TEST — Power Supply Pin ..................................................................................56
Chapter 5
System Clock Description
5.1
5.2
5.2.1
5.2.1.1
5.2.1.2
5.2.1.3
5.2.1.4
5.2.2
5.2.3
5.2.4
5.3
5.4
5.5
Clocks Introduction............................................................................................................59
Clock Generation ...............................................................................................................61
Clock Source Selection..................................................................................................63
ALC 1:1 Mode...........................................................................................................64
ALC PLL Mode.........................................................................................................64
External Clock 1:1 Mode...........................................................................................65
External Clock PLL Mode.........................................................................................66
Self Clock Mode (SCM) ................................................................................................67
Crystal Monitor..............................................................................................................67
Clock Quality Checker...................................................................................................67
Clock Usage .......................................................................................................................67
Clock Gating ......................................................................................................................68
Oscillator............................................................................................................................69
Chapter 6
Resets
6.1
6.2
6.3
6.4
6.5
6.6
Resets Introduction ............................................................................................................71
Power On Reset (POR) ......................................................................................................73
System Reset......................................................................................................................73
Debug Reset .......................................................................................................................73
Software Reset ...................................................................................................................74
Reset Implementation ........................................................................................................74
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6.7
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.8
6.9
Effects of Reset ..................................................................................................................75
Hardware Configuration ................................................................................................75
Register States................................................................................................................75
Peripheral Disabled State...............................................................................................75
I/O pins ..........................................................................................................................76
Memories .......................................................................................................................76
System Configuration at Reset ..........................................................................................76
Resets Differences from MAC71xx...................................................................................77
Chapter 7
Exceptions
7.1
7.2
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.4
Introduction........................................................................................................................79
Exception Handling ...........................................................................................................79
Reset...............................................................................................................................80
Undefined Instruction ....................................................................................................80
Software Interrupt ..........................................................................................................80
Prefetch (Instruction) Abort...........................................................................................80
Data Abort......................................................................................................................81
IRQ.................................................................................................................................81
FIQ .................................................................................................................................81
Interrupts ............................................................................................................................82
Interrupt Clearing...........................................................................................................86
XIRQ and IRQ ...............................................................................................................86
PIT RTI and Timer 4......................................................................................................86
Non-Maskable Interrupt (NMI) .....................................................................................86
Exceptions Differences from the MAC71xx .....................................................................90
Chapter 8
Debug
8.1
8.2
8.3
8.4
8.4.1
8.4.1.1
8.4.1.2
8.4.1.3
8.4.1.4
8.4.2
8.4.3
8.5
8.6
Debug Introduction ............................................................................................................91
Debug Features ..................................................................................................................91
Debug Protocol ..................................................................................................................91
Debug Implementation ......................................................................................................91
JTAG Interface...............................................................................................................91
TCK Routing .............................................................................................................93
TMS Routing .............................................................................................................93
TDI Routing...............................................................................................................93
TDO Routing .............................................................................................................94
Synchronization .............................................................................................................95
Debug Reset...................................................................................................................97
Debug External Pins ..........................................................................................................97
Debug Bus Aborts..............................................................................................................97
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8.7
8.8
8.8.1
8.8.2
8.8.3
8.8.4
8.8.5
8.8.6
8.8.7
8.8.8
Debug Differences from MAC71xx ..................................................................................97
Debug Application Usage ..................................................................................................97
ARM Debug Overview..................................................................................................98
Entering Debug mode ....................................................................................................99
Exiting Debug mode ....................................................................................................100
Nexus Low Power State...............................................................................................100
Debug Shift Register SC4............................................................................................101
Using the JTAG Interface ............................................................................................101
JTAG Pad Control........................................................................................................101
Resetting Debug Logic ................................................................................................102
Chapter 9
Device Memory Map
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.8.1
9.8.2
9.8.3
9.9
9.10
9.11
9.12
9.13
9.14
9.15
9.16
9.16.1
9.16.2
9.16.3
9.16.3.1
9.16.3.2
9.16.3.3
9.16.3.4
9.16.4
9.17
9.18
9.18.1
Memory Map Example ....................................................................................................104
Normal Single Chip Mode ...............................................................................................105
Normal Primary Bootloader Mode ..................................................................................107
Normal Expanded Mode ..................................................................................................108
Secured Single Chip Mode ..............................................................................................109
Secured Primary Bootloader Mode..................................................................................110
Secured Expanded Mode .................................................................................................110
Accessing registers ..........................................................................................................112
32-bit Register Accesses..............................................................................................112
16-bit Register Accesses..............................................................................................112
8-bit register accesses ..................................................................................................113
Peripheral Bus Memory Map...........................................................................................113
SRAM Memory Map .......................................................................................................114
FlexBus Memory Map .....................................................................................................115
Flash Main Array Memory Map ......................................................................................115
Shadow Block Memory Map ...........................................................................................117
Boot Assist Module (BAM) Memory Map......................................................................118
Exception Table Memory Map ........................................................................................118
Memory Map Relocation .................................................................................................119
System Memory Map Combinations ...........................................................................119
Changing Chip Modes .................................................................................................120
Resource Relocation Summary....................................................................................120
FlexBus ....................................................................................................................120
Flash Main Array.....................................................................................................120
Shadow Block..........................................................................................................120
SRAM ......................................................................................................................121
Programming the AAMR register in the MCM...........................................................121
Exception Table ...............................................................................................................122
System Boot Sequence.....................................................................................................123
Programming with a Bootloader..................................................................................123
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9.18.2
“Normal” Boot with a Bootloader ...............................................................................124
Chapter 10
ARM7TDMI-S Core
10.1
10.2
10.3
10.4
10.5
10.6
10.6.1
Introduction......................................................................................................................127
ARM7 Features................................................................................................................127
ARM7 Implementation ....................................................................................................127
ARM7 External Pins ........................................................................................................128
ARM7 Bus Aborts ...........................................................................................................128
ARM7 Application Usage ...............................................................................................128
Register Bank Initialization .........................................................................................128
Chapter 11
A7S Nexus3 Module
11.1
11.1.1
11.1.2
11.1.3
11.1.3.1
11.1.3.2
11.1.3.3
11.1.4
11.2
11.3
11.3.1
11.3.2
11.4
11.4.1
11.4.2
11.4.3
11.5
11.5.1
11.5.2
11.5.3
11.5.4
11.5.5
11.5.6
11.6
11.7
11.8
11.8.1
11.8.2
Introduction......................................................................................................................129
A7S Nexus3 Overview ................................................................................................130
Nexus Feature List .......................................................................................................130
Modes of Operation .....................................................................................................131
Reset ........................................................................................................................131
Normal .....................................................................................................................131
Disabled ...................................................................................................................131
TCODEs supported......................................................................................................131
Nexus Protocol.................................................................................................................135
Nexus Implementation .....................................................................................................135
Nexus Port Replacement..............................................................................................136
TAP Controller Encodings...........................................................................................136
Nexus Integration.............................................................................................................137
Nexus Integration and SoC Security............................................................................138
Nexus Integration and FlexBus Port Sizing.................................................................138
Nexus Integration and Port Control .............................................................................138
Nexus External Pins.........................................................................................................139
MDO - Message Data (Output) ...................................................................................139
MSEO - Message Start/End (Active low output) ........................................................139
EVTI - Event In (Active low input).............................................................................139
EVTO - Event Out (Active low output).......................................................................139
RDY - DMA Ready (Active low output).....................................................................140
MCKO - Message Clock (Output)...............................................................................140
Nexus Bus Aborts ............................................................................................................140
Nexus Differences from MAC71xx.................................................................................140
Nexus Application Usage ................................................................................................140
Nexus Configuration....................................................................................................140
Programming the PCR Register...................................................................................141
MAC7200 Microcontroller Family Reference Manual, Rev. 2
x
Freescale Semiconductor
11.8.3
11.8.4
11.8.5
11.8.6
11.8.7
11.9
11.9.1
11.9.2
11.9.3
11.9.4
11.9.5
11.10
11.10.1
11.10.2
11.10.3
11.10.3.1
11.10.3.2
11.10.3.3
11.10.3.4
11.10.3.5
11.10.3.6
11.10.3.7
11.10.3.8
11.10.3.9
11.10.3.10
11.10.3.11
11.10.3.12
11.10.3.13
11.10.3.14
11.10.3.15
11.10.3.16
11.10.3.17
11.10.3.18
11.10.4
11.10.5
11.11
11.11.1
11.11.1.1
11.11.1.2
11.11.1.3
11.11.2
11.11.2.1
11.11.2.1.1
11.11.2.1.2
11.11.2.1.3
Resetting Nexus ...........................................................................................................141
Enabling Nexus............................................................................................................141
Disabling Nexus...........................................................................................................141
Nexus Development Status (DS) Register...................................................................142
Unintended Activation of Nexus .................................................................................142
External Signal Description .............................................................................................143
Functional Description.................................................................................................143
Pins Implemented ........................................................................................................143
Pin Protocol..................................................................................................................144
Rules for Output Messages ..........................................................................................146
Examples......................................................................................................................146
A7S Nexus3 Programmers Model ...................................................................................148
JTAG ID Register ........................................................................................................148
Nexus3 Register Map...................................................................................................150
A7S Nexus3 Register Definitions................................................................................151
Client Select Control (CSC) ....................................................................................151
Development Control (DC) .....................................................................................151
Development Status (DS) ........................................................................................152
User Base Address (UBA).......................................................................................153
Read/Write Access Control/Status (RWCS)............................................................154
Read/Write Access Data (RWD) .............................................................................155
Read/Write Access Address (RWA) ........................................................................156
Watchpoint Trigger (WT) ........................................................................................156
Data Trace Control (DTC).......................................................................................157
Data Trace Start Address (DTSA1, DTSA2)...........................................................158
Data Trace End Address (DTEA1, DTEA2) ...........................................................159
Breakpoint / Watchpoint Control (BWC1, BWC2) .................................................160
Breakpoint / Watchpoint Control (BWC3-6)...........................................................161
Breakpoint / Watchpoint Address (BWA1-6) ..........................................................161
Breakpoint / Watchpoint Address Mask (BWAM1, BWAM2)................................162
Breakpoint / Watchpoint Data (BWD1, BWD2) .....................................................162
Breakpoint / Watchpoint Data Mask (BWDM1, BWDM2) ....................................162
Port Configuration (PCR) ........................................................................................163
Nexus Register Access via JTAG ................................................................................164
Programming Considerations (RESET).......................................................................166
Functional Description.....................................................................................................166
Ownership Trace..........................................................................................................166
Ownership Trace Messaging (OTM).......................................................................166
OTM Error Messages ..............................................................................................166
OTM Flow ...............................................................................................................167
Program Trace..............................................................................................................167
Branch Trace Messaging (BTM) .............................................................................167
ARM7 Indirect Branch Message Instructions .....................................................168
ARM7 Direct Branch Message Instructions........................................................168
BTM in ARM mode ............................................................................................169
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11.11.2.1.4
11.11.2.2
11.11.2.2.1
11.11.2.2.2
11.11.2.2.3
11.11.2.2.4
11.11.2.2.5
11.11.2.2.6
11.11.2.2.7
11.11.2.3
11.11.2.3.1
11.11.2.3.2
11.11.2.3.3
11.11.2.3.4
11.11.2.3.5
11.11.2.4
11.11.3
11.11.3.1
11.11.3.2
11.11.3.2.1
11.11.3.2.2
11.11.3.2.3
11.11.3.2.4
11.11.3.3
11.11.3.3.1
11.11.3.3.2
11.11.3.3.3
11.11.3.3.4
11.11.3.3.5
11.11.3.4
11.11.4
11.11.4.1
11.11.4.1.1
11.11.4.1.2
11.11.4.1.3
11.11.4.2
11.11.4.3
11.11.4.3.1
11.11.4.4
11.11.4.5
11.11.5
11.11.5.1
11.11.5.2
11.11.5.3
11.11.5.3.1
BTM in Thumb mode ..........................................................................................169
Branch Trace Message Formats (History and Traditional)......................................169
Indirect Branch Messages (History) ....................................................................169
Indirect Branch Messages (Traditional) ..............................................................170
Direct Branch Messages (Traditional).................................................................170
Resource Full Messages ......................................................................................170
Program Correlation Messages............................................................................171
BTM Overflow Error Messages ..........................................................................171
Program Trace Synchronization Messages..........................................................171
BTM Operation........................................................................................................173
Enabling Program Trace ......................................................................................173
Addressing ...........................................................................................................174
Branch/Predicate Instruction History (HIST)......................................................174
Sequential Instruction Count (I-CNT).................................................................175
Program Trace Queueing .....................................................................................175
Program Trace Timing Diagrams (2 MDO / 1 MSEO configuration).....................175
Data Trace....................................................................................................................176
Data Trace Messaging (DTM).................................................................................176
DTM Message Formats ...........................................................................................177
Data Write Messages ...........................................................................................177
Data Read Messages ............................................................................................177
DTM Overflow Error Messages ..........................................................................177
Data Trace Synchronization Messages ................................................................178
DTM Operation .......................................................................................................179
Enabling Data Trace Messaging ..........................................................................179
DTM Queueing....................................................................................................179
Relative Addressing.............................................................................................180
Data Trace Windowing ........................................................................................180
ARM7 Bus Cycle Cases ......................................................................................180
Data Trace Timing Diagrams (8 MDO / 2 MSEO configuration)...........................180
Watchpoint Units .........................................................................................................181
Watchpoint Generation ............................................................................................181
Internal Watchpoint Units 1 and 2 .......................................................................181
Internal Watchpoint Units 3 - 6 ...........................................................................182
ARM7 Watchpoints .............................................................................................182
Processor Breakpoints .............................................................................................182
Watchpoint Messaging (WPM) ...............................................................................182
Watchpoint Message ............................................................................................182
Watchpoint Error Message.......................................................................................183
Watchpoint Timing Diagram (2 MDO / 1 MSEO configuration)............................184
Read/Write Access.......................................................................................................184
Functional Description.............................................................................................184
Read/Write Access to Internal Nexus Registers ......................................................184
Memory Mapped Register Access via JTAG ..........................................................185
Single Write Access.............................................................................................185
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11.11.5.3.2
11.11.5.3.3
11.11.5.3.4
11.11.5.4
11.11.5.4.1
11.11.5.4.2
11.11.5.4.3
11.11.5.5
11.11.6
11.11.6.1
11.12
11.12.1
11.12.2
11.12.3
11.12.4
Block Write Access .............................................................................................186
Single Read Access .............................................................................................187
Block Read Access ..............................................................................................187
Error Handling .........................................................................................................188
AHB Read/Write Error ........................................................................................188
Access Termination .............................................................................................188
Read/Write Access Error Message ......................................................................188
Timing Diagram.......................................................................................................189
System Status...............................................................................................................189
Debug Status Messages ...........................................................................................189
IEEE 1149.1 State Machine and RD/WR Sequences ......................................................190
JTAG State Machine ....................................................................................................190
JTAG Sequence for Accessing Internal Nexus Registers ............................................191
JTAG Sequence for Read Access of Memory-Mapped Resources .............................191
JTAG Sequence for Write Access of Memory-Mapped Resources.............................191
Chapter 12
Enhanced DMA Controller (eDMA) Module
12.1
12.1.1
12.1.2
12.1.3
12.1.4
12.1.5
12.1.6
12.1.6.1
12.1.6.2
12.1.6.3
12.1.6.3.1
12.1.6.3.2
12.1.6.3.3
12.1.6.3.4
12.1.6.3.5
12.1.6.3.6
12.1.6.4
12.1.6.5
12.2
12.2.1
12.2.2
12.2.3
12.2.4
12.2.4.1
12.2.4.1.1
Overview of the MAC7200 Implementation ...................................................................193
eDMA Features............................................................................................................193
eDMA Implementation ................................................................................................194
eDMA External Pins....................................................................................................195
eDMA Bus Aborts .......................................................................................................195
eDMA Differences from MAC71xx............................................................................195
eDMA Application Usage ...........................................................................................195
Enabling the DMA...................................................................................................195
General Operation of the DMA ...............................................................................196
Configuring the DMA..............................................................................................196
Arbitration and System Loading..........................................................................196
Error Signalling ...................................................................................................197
DEBUG Mode Behavior .....................................................................................198
Transfer Control Descriptor (TCD) .....................................................................198
Channel Completion ............................................................................................198
Channel Activation Method.................................................................................198
Using the DMA........................................................................................................199
TCD Memory Initialization .....................................................................................200
The SPP DMA Controller Module (SPP_DMA2)...........................................................200
Overview......................................................................................................................201
Features........................................................................................................................202
External Signal Description .........................................................................................207
Memory Map/Register Definition ...............................................................................207
Register Descriptions...............................................................................................209
DMA Control Register (DMACR) ......................................................................209
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12.2.4.1.2
12.2.4.1.3
12.2.4.1.4
12.2.4.1.5
12.2.4.1.6
12.2.4.1.7
12.2.4.1.8
12.2.4.1.9
12.2.4.1.10
12.2.4.1.11
12.2.4.1.12
12.2.4.1.13
12.2.4.1.14
12.2.4.1.15
12.2.4.1.16
12.2.5
12.2.6
12.2.6.1
12.2.6.2
12.2.6.3
12.2.6.3.1
12.2.6.3.2
12.2.6.4
12.2.6.4.1
12.2.6.4.2
12.2.6.5
12.2.6.5.1
12.2.6.5.2
12.2.6.5.3
12.2.6.6
12.2.6.7
12.2.6.7.1
12.2.6.7.2
12.2.6.8
DMA Error Status (DMAES) ..............................................................................210
DMA Enable Request (DMAERQH, DMAERQL) ............................................212
DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) .....................................214
DMA Set Enable Request (DMASERQ).............................................................215
DMA Clear Enable Request (DMACERQ).........................................................215
DMA Set Enable Error Interrupt (DMASEEI)....................................................216
DMA Clear Enable Error Interrupt (DMACEEI)................................................217
DMA Clear Interrupt Request (DMACINT) .......................................................217
DMA Clear Error (DMACERR) .........................................................................218
DMA Set START Bit (DMASSRT) ....................................................................218
DMA Clear DONE Status (DMACDNE)............................................................219
DMA Interrupt Request (DMAINTH, DMAINTL) ............................................220
DMA Error (DMAERRH, DMAERRL) .............................................................221
DMA Channel n Priority (DCHPRIn), n = 0,..., {15,31,63} ...............................222
Transfer Control Descriptor (TCD) .....................................................................223
DMA Performance.......................................................................................................232
Initialization/Application Information.........................................................................235
DMA Initialization...................................................................................................235
DMA Programming Errors ......................................................................................235
DMA Arbitration Mode Considerations ..................................................................235
Fixed Channel Arbitration ...................................................................................235
Round Robin Channel Arbitration.......................................................................236
DMA Transfer..........................................................................................................236
Single request ......................................................................................................236
Multiple requests .................................................................................................237
TCD Status...............................................................................................................238
Minor loop complete ...........................................................................................238
Active channel TCD reads...................................................................................239
Preemption status.................................................................................................239
Channel Linking ......................................................................................................240
Dynamic Programming............................................................................................240
Dynamic priority changing..................................................................................240
Dynamic channel linking and dynamic scatter/gather.........................................241
Hardware Request Release Timing..........................................................................242
Chapter 13
Miscellaneous Control Module (MCM)
13.1
13.1.1
13.1.2
13.2
13.2.1
13.2.2
Introduction......................................................................................................................243
Overview......................................................................................................................243
Features........................................................................................................................243
Memory Map/Register Definition ...................................................................................243
Memory Map ...............................................................................................................244
Register Descriptions...................................................................................................245
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13.2.2.1
13.2.2.2
13.2.2.3
13.2.2.4
13.2.2.5
13.2.2.6
13.2.2.7
13.2.2.8
13.2.2.9
13.2.2.10
13.2.2.11
13.2.2.12
13.2.2.13
13.2.2.14
13.2.2.14.1
13.2.2.14.2
13.2.2.14.3
13.2.2.14.4
13.2.2.14.5
13.2.2.14.6
13.2.2.15
13.2.2.15.1
13.2.2.15.2
13.2.2.15.3
13.2.2.15.4
13.2.2.15.5
13.2.2.15.6
13.2.2.15.7
13.2.2.15.8
13.2.2.15.9
13.2.2.15.10
13.2.2.15.11
13.2.2.15.12
13.2.2.16
13.2.2.16.1
13.2.2.16.2
13.2.2.16.3
13.2.2.16.4
13.2.2.16.5
13.3
13.3.1
13.3.2
13.3.2.1
13.3.2.2
13.3.2.3
Processor Core Type (PCT) .....................................................................................245
Revision (REV) .......................................................................................................246
AXBS Master Configuration (AMC) ......................................................................246
AXBS Slave Configuration (ASC)..........................................................................247
IPS Module Configuration (IMC) ...........................................................................247
Miscellaneous Reset Status Register (MRSR) ........................................................248
Miscellaneous Wakeup Control Register (MWCR) ................................................249
Miscellaneous Software Watchdog Timer Control Register (MSWTCR) ..............250
Miscellaneous Software Watchdog Timer Service Register (MSWTSR) ...............252
Miscellaneous Interrupt Register (MIR)..................................................................253
AXBS Address Map Register (AAMR) ..................................................................254
Miscellaneous User-Defined Control Register (MUDCR)......................................255
NMI Control Register (NMICR) .............................................................................256
Peripheral Power Management Registers (PPMR)..................................................257
Peripheral Power Management Set Register (PPMRS).......................................257
Peripheral Power Management Clear Register (PPMRC)...................................258
Peripheral Power Management Set Register 1 (PPMRS1)..................................259
Peripheral Power Management Clear Register 1 (PPMRC1)..............................259
Peripheral Power Management Register (PPMR{H,L}).....................................260
Peripheral Power Management Register 1 (PPMR1{H,L})................................261
ECC Registers..........................................................................................................263
ECC Configuration Register (ECR) ....................................................................263
ECC Status Register (ESR) .................................................................................265
ECC Error Generation Register (EEGR).............................................................266
Flash ECC Address Register (FEAR) .................................................................269
Flash ECC Master Number Register (FEMR).....................................................270
Flash ECC Attributes Register (FEAT) ...............................................................271
Flash ECC Data Register (FEDR) .......................................................................272
RAM ECC Address Register (REAR).................................................................272
RAM ECC Syndrome Register (RESR) ..............................................................273
RAM ECC Master Number Register (REMR)....................................................274
RAM ECC Attributes Register (REAT) ..............................................................275
RAM ECC Data Register (REDR) ......................................................................276
Core Data Fault Recovery Registers........................................................................277
Core Fault Address Register (CFADR) ...............................................................277
Core Fault Location/Interrupt Enable Register (CFLOC1) .................................278
Core Fault Location Register (CFLOC) ..............................................................279
Core Fault Attributes Register (CFATR) .............................................................279
Core Fault Data Register (CFDTR).....................................................................280
MCM as Implemented on MAC7200 ..............................................................................281
MCM Introduction.......................................................................................................281
MCM Features .............................................................................................................282
Processor Core Type (PCT) .....................................................................................282
Revision ID (REV) ..................................................................................................283
AXBS Master/Slave Configuration .........................................................................283
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13.3.2.4
13.3.2.5
13.3.2.6
13.3.2.7
13.3.2.8
13.3.2.9
13.3.2.10
13.3.2.11
13.3.3
13.3.4
13.3.5
13.3.6
13.3.6.1
13.3.6.2
13.3.6.3
13.3.6.4
13.3.6.5
13.3.6.6
Misc. Reset Status Register (MRSR).......................................................................283
Misc. Wakeup Control Register (MWCR) ..............................................................283
Software Watchdog Timer (SWT) ...........................................................................283
AXBS Address Map Register (AAMR) ..................................................................284
Misc. User-Defined Control Register (MUDCR)....................................................284
ECC..........................................................................................................................284
Fault Registers .........................................................................................................284
Non-Maskable Interrupt (NMI) ...............................................................................284
MCM External Pins .....................................................................................................284
MCM Bus Aborts.........................................................................................................284
MCM Differences from MAC71xx .............................................................................285
MCM Application Usage.............................................................................................286
Enabling the MCM ..................................................................................................286
ECC..........................................................................................................................286
Flash.........................................................................................................................286
AAMR .....................................................................................................................286
NMI..........................................................................................................................286
REV Register ...........................................................................................................286
Chapter 14
SPP Interrupt Controller Module for ARM (SPP_INTC_ARM)
14.1
14.1.1
14.2
14.3
14.4
14.5
14.6
14.6.1
14.7
14.7.1
14.8
14.8.1
14.8.1.1
14.8.1.2
14.8.1.3
14.8.1.4
14.8.1.5
14.8.1.6
14.8.1.7
14.8.1.8
14.8.1.9
14.8.1.10
Introduction......................................................................................................................287
Overview......................................................................................................................287
INTC Features..................................................................................................................287
INTC External Pins..........................................................................................................288
INTC Bus Aborts .............................................................................................................288
INTC Differences from MAC71xx..................................................................................288
INTC Application Usage .................................................................................................289
Enabling the INTC.......................................................................................................290
The Interrupt Controller Module (INTC) ........................................................................290
Review of ARM Interrupt Architecture.......................................................................291
Memory Map/Register Definition ...................................................................................292
Register Descriptions...................................................................................................294
IPR[63:0] - Interrupt Pending Register (IPRH, IPRL) ............................................294
IMR[63:0] - Interrupt Mask Register (IMRH, IMRL) ............................................296
INTFRC[63:0] - Force Interrupt Register (INTFRCH, INTFRCL) ........................297
Interrupt Configuration (ICONFIG) Register..........................................................299
Set Interrupt Mask (SIMR) Register........................................................................300
Clear Interrupt Mask (CIMR) Register....................................................................301
Current Level Mask (CLMASK) Register ..............................................................302
Saved Level Mask (SLMASK) Register .................................................................303
Interrupt Control Register n (ICRn), n = 0, 1, 2,..., 63 ............................................304
IRQ Interrupt Acknowledge Register (IRQIACK)..................................................304
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14.8.1.11
14.9
14.9.1
14.9.1.1
14.9.1.2
14.9.1.3
14.9.1.4
14.9.2
14.10
14.10.1
14.10.2
14.10.3
FIQ Interrupt Acknowledge Register (FIQIACK) ..................................................305
Functional Description.....................................................................................................306
Interrupt Controller Theory of Operation ....................................................................306
Interrupt Recognition...............................................................................................307
Interrupt Prioritization and Level Masking .............................................................307
Vector Generation during IACK..............................................................................307
Multiple Controller Requirements...........................................................................308
Performance .................................................................................................................309
Initialization/Application Information .............................................................................310
Initialization .................................................................................................................310
Typical Applications ....................................................................................................310
Interrupt Service Routines ...........................................................................................311
Chapter 15
MAC7200 Crossbar Switch (AXBS)
15.1
15.1.1
15.1.2
15.1.3
15.1.4
15.2
15.3
15.4
15.4.1
15.4.2
15.5
15.5.1
15.5.1.1
15.5.1.2
15.5.2
15.6
15.7
15.7.1
15.7.2
15.8
Introduction......................................................................................................................313
Overview......................................................................................................................314
Features........................................................................................................................314
AXBS Integration ........................................................................................................314
Modes of Operation .....................................................................................................315
External Signal Description .............................................................................................315
Memory Map Definition ..................................................................................................315
Register Descriptions .......................................................................................................316
Priority Register..........................................................................................................316
Control Register...........................................................................................................317
Functional Description.....................................................................................................319
Arbitration....................................................................................................................319
Fixed Priority Operation ..........................................................................................319
Round-Robin Priority Operation .............................................................................320
Priority Assignment .....................................................................................................320
Initialization/Application Information .............................................................................320
AXBS Bus Aborts............................................................................................................320
IPI Register Interface ...................................................................................................320
Master/Slave Interface .................................................................................................322
AXBS Differences from MAC71xx ................................................................................322
Chapter 16
AHB to IPI Bridge (AIPS)
16.1
16.1.1
16.1.2
16.2
Introduction......................................................................................................................323
Features........................................................................................................................323
General Operation........................................................................................................324
AIPS Protocol ..................................................................................................................325
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16.2.1
16.3
16.4
16.4.1
16.4.2
16.4.3
16.4.3.1
16.4.3.2
16.4.3.3
16.5
16.5.1
16.5.1.1
16.5.1.2
16.5.2
16.5.3
16.5.4
16.5.5
16.5.6
16.6
16.7
16.7.1
16.7.2
16.8
8/16/32--bit accesses....................................................................................................325
External Signal Description .............................................................................................329
Memory Map/Register Definition ...................................................................................329
Overview......................................................................................................................330
Control Registers .........................................................................................................330
Register Descriptions...................................................................................................331
Master Privilege Registers (MPROT) .....................................................................331
Peripheral Access Control Registers (PACR)..........................................................332
Off-Platform Peripheral Access Control Registers (OPACRs) ...............................333
Functional Description.....................................................................................................333
AIPS Scalability...........................................................................................................333
Peripheral Presence..................................................................................................333
Registers ..................................................................................................................334
Access Protections .......................................................................................................334
Access Support ............................................................................................................334
Read Cycles .................................................................................................................334
Write Cycles.................................................................................................................334
Aborted Cycles ............................................................................................................334
Initialization/Application Information .............................................................................335
AIPS Bus Aborts..............................................................................................................335
IPI Register Interface ...................................................................................................335
IPI Bridge Interface .....................................................................................................335
AIPS Differences from MAC71xx ..................................................................................336
Chapter 17
External Bus Interface (FlexBus)
17.1
17.1.1
17.1.2
17.1.3
17.1.4
17.2
17.2.1
17.2.2
17.2.3
17.2.4
17.2.5
17.2.6
17.2.7
17.2.8
17.3
17.3.1
17.3.1.1
Introduction......................................................................................................................339
Block Diagram.............................................................................................................340
Features........................................................................................................................340
FlexBus Implementation..............................................................................................341
FlexBus Memory Map Relocation...............................................................................341
External Signals ...............................................................................................................341
Chip-Select (CS[2:0]) ..................................................................................................342
Address Bus (ADDR[21:0]) ........................................................................................342
Data Bus (DATA[15:0])...............................................................................................342
Read/Write (R/W)........................................................................................................342
Transfer Burst (TBST).................................................................................................342
Byte Write Enable/Byte Select (BWE[1:0]) ...............................................................342
Output Enable (OE) .....................................................................................................342
Transfer Acknowledge (TA) ........................................................................................343
Chip-Select Operation......................................................................................................343
General Chip-Select Operation....................................................................................343
8-bit and 16-bit Port Sizing......................................................................................343
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17.3.1.2
17.3.2
17.3.2.1
17.3.2.2
17.3.2.3
17.4
17.4.1
17.4.2
17.4.3
17.4.3.1
17.5
17.5.1
17.5.2
17.6
17.7
17.7.1
17.7.2
17.7.3
17.7.4
17.7.5
17.7.6
Global Chip-Select Operation..................................................................................344
Chip-Select Registers...................................................................................................344
Chip-Select Address Registers (CSAR0–CSAR2)..................................................345
Chip-Select Mask Registers (CSMR0–CSMR2).....................................................345
Chip-Select Control Registers (CSCR0–CSCR2) ...................................................347
Functional Description.....................................................................................................349
Data Transfer Operation ..............................................................................................349
Data Byte Alignment and Physical Connections.........................................................349
Bus Cycle Execution....................................................................................................350
Data Transfer Cycle States.......................................................................................350
FlexBus Bus Aborts .........................................................................................................351
IPI Register Interface ...................................................................................................351
FlexBus Interface.........................................................................................................352
FlexBus Differences from MAC71xx..............................................................................352
FlexBus Application Usage .............................................................................................353
Enabling the FlexBus...................................................................................................353
Global Chip Select Mode.............................................................................................353
FlexBus speed ..............................................................................................................354
How to use the external bus in Expanded Secured/Unsecured Mode .........................354
How to Use the External Bus in Single Chip Unsecured Mode ..................................355
Enabling and Disabling CLKOUT ..............................................................................356
Chapter 18
FLASH (H7Fb) and FLASH Controller (PFLASH)
18.1
18.2
18.2.1
18.2.2
18.2.3
18.2.4
18.3
18.3.1
18.3.2
18.4
18.5
18.5.1
18.5.2
18.6
18.7
18.7.1
18.7.2
18.7.3
18.7.4
Introduction......................................................................................................................357
Flash Features ..................................................................................................................358
General Features ..........................................................................................................358
Main Array Features ....................................................................................................358
Shadow Block Features ...............................................................................................358
Flash Modes.................................................................................................................358
Flash Implementation ......................................................................................................358
MAC72x1 Flash...........................................................................................................358
MAC72x2 Flash...........................................................................................................360
Flash External Pins ..........................................................................................................361
PFLASH Bus Aborts .......................................................................................................361
IPI Register Interface ...................................................................................................361
Flash Array Interface ...................................................................................................361
PFLASH Differences MAC72x2 from MAC71xx ..........................................................361
PFLASH Application Usage............................................................................................362
Flash Terminology .......................................................................................................362
Enabling the PFLASH .................................................................................................363
Flash Array Memory Map ...........................................................................................363
Flash Registers.............................................................................................................363
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18.7.4.1
18.7.4.1.1
18.7.4.1.2
18.7.4.1.3
18.7.4.1.4
18.7.4.1.5
18.7.4.2
18.7.4.2.1
18.7.5
18.7.6
18.7.7
18.7.8
18.7.9
18.7.9.1
18.7.9.2
18.7.10
Flash Block User Registers......................................................................................363
PFCR1 - PFLASH Configuration Register 1 ......................................................364
PFAPR - PFLASH Access Protection Register ...................................................366
PFCR2 - PFLASH Configuration Register 2 ......................................................367
PFSACC - PFLASH Supervisor/user ACCess....................................................367
PFDACC - PFLASH Data/instruction ACCess...................................................367
Flash MCM Registers ..............................................................................................368
PFWACC - PFLASH Write ACCess ...................................................................368
Flash Access Protection ...............................................................................................368
Flash Program/Erase Protection and Selection............................................................372
Flash Programming Word Size ....................................................................................374
Read-while-Write (RWW) ...........................................................................................374
Flash Security ..............................................................................................................374
Securing the device..................................................................................................374
Unsecuring the device..............................................................................................375
Flash Timing ................................................................................................................375
Chapter 19 SRAM and SRAM Controller
19.1
19.1.1
19.1.2
19.1.3
19.1.4
19.1.5
19.1.6
19.1.6.1
19.1.6.2
19.2
19.2.1
19.2.2
19.2.2.1
19.2.2.2
19.2.3
19.2.3.1
19.2.3.1.1
19.2.3.2
19.2.3.3
19.2.3.4
19.2.3.4.1
19.2.3.5
19.2.3.5.1
19.2.3.5.2
19.2.3.5.3
19.2.3.6
SRAM ..............................................................................................................................377
SRAM Features............................................................................................................377
SRAM Protocol............................................................................................................377
SRAM External Pins....................................................................................................377
SRAM Bus Aborts .......................................................................................................377
SRAM Differences from MAC71xx............................................................................377
SRAM Application Usage ...........................................................................................378
SRAM Initialization.................................................................................................378
SRAM Address Mirroring .......................................................................................378
Platform RAM Array Controller (PRAM_CTL) .............................................................378
Introduction..................................................................................................................378
PRAM_CTL Interface Description..............................................................................381
Overview..................................................................................................................381
Detailed Signal Descriptions ...................................................................................382
Functional Description.................................................................................................385
Error Correcting Code (ECC)..................................................................................385
Overview .............................................................................................................385
Max Address............................................................................................................387
Read / Write Introduction ........................................................................................387
Reads........................................................................................................................388
Unaligned Reads..................................................................................................388
Writes.......................................................................................................................388
32-bit / 64-bit Writes............................................................................................388
Less than 32-bit Writes ........................................................................................390
Unaligned Writes .................................................................................................391
Late Write Hits.........................................................................................................392
MAC7200 Microcontroller Family Reference Manual, Rev. 2
xx
Freescale Semiconductor
19.2.3.7
19.2.3.7.1
19.2.3.7.2
19.2.4
19.3
19.3.1
19.3.1.1
19.3.1.2
19.3.1.3
19.3.1.4
ECC Events on Reads..............................................................................................394
Single Bit Errors ..................................................................................................394
Mulitiple Bit Errors .............................................................................................394
Initialization/Application Information.........................................................................395
Hamming Algorithm........................................................................................................395
Basic Algorithm...........................................................................................................395
The Hamming Rule..................................................................................................395
Creating A Hamming Codeword .............................................................................395
Hamming Parity Code Table ...................................................................................396
PRAM_CTL Implementation ..................................................................................397
Chapter 20
Boot Assist Module (BAM)
20.1
20.2
20.3
20.4
20.5
20.6
20.7
BAM Introduction............................................................................................................399
BAM Features..................................................................................................................400
BAM Protocol..................................................................................................................400
BAM External Pins ..........................................................................................................401
BAM Bus Aborts .............................................................................................................401
BAM Differences from MAC71xx..................................................................................401
BAM Application Usage .................................................................................................401
Chapter 21
IPI Subsystem (IPSS)
21.1
21.2
21.3
Bus Abort handling ..........................................................................................................403
Peripheral Bus Peripheral Clock Frequencies .................................................................403
IPSS Differences from MAC71xx ...................................................................................403
Chapter 22
Dual-Output Voltage Regulator (VREG_HIP7A)
22.1
22.1.1
22.1.2
22.1.3
22.1.4
22.2
22.2.1
22.2.2
22.2.2.1
22.2.2.2
22.2.2.3
Introduction......................................................................................................................405
Overview......................................................................................................................405
Features........................................................................................................................405
Modes of Operation .....................................................................................................405
Block Diagram.............................................................................................................406
External Signal Description .............................................................................................407
Overview......................................................................................................................407
Detailed Signal Descriptions .......................................................................................408
VDDR - Regulator Power Input ..............................................................................408
VDDA, VSSA - Regulator Reference Supply.........................................................408
VDD15, VSS15 - Regulator Output1 (Core Logic) ................................................408
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22.2.2.4
22.2.2.5
22.2.2.6
22.3
22.4
22.4.1
22.4.2
22.4.2.1
22.4.3
22.4.4
22.4.5
22.4.6
22.4.7
22.4.7.1
22.4.7.2
22.4.7.2.1
22.4.7.2.2
22.5
22.6
22.7
VDD33, VSS33 - Regulator Output1 (3.3V Logic) ................................................409
VDDPLL, VSSPLL - Regulator Output2 (3.3V PLL) ............................................409
VREGEN - Optional Regulator Enable...................................................................409
Memory Map and Register Definition.............................................................................409
Functional Description.....................................................................................................409
General.........................................................................................................................409
REG - Regulator Core..................................................................................................409
Full Performance Mode ...........................................................................................410
POR - Power-On Reset ................................................................................................410
LVR15 - Low Voltage Reset ........................................................................................410
LVR33 - Low Voltage Reset ........................................................................................410
LVRPLL - Low Voltage Reset .....................................................................................410
Resets ...........................................................................................................................410
General.....................................................................................................................410
Description of Reset Operation ...............................................................................411
Power-On Reset (POR)........................................................................................411
Low Voltage Reset (LVR)....................................................................................411
Interrupts ..........................................................................................................................411
VREG Bus Aborts ...........................................................................................................411
VREG Differences from MAC71xx ................................................................................411
Chapter 23
Clock and Reset Generator (CRG)
23.1
23.1.1
23.1.2
23.1.3
23.1.4
23.2
23.2.1
23.2.1.1
23.2.1.2
23.2.1.3
23.2.1.4
23.3
23.3.1
23.3.2
23.3.2.1
23.3.2.2
23.3.2.3
23.3.2.4
23.3.2.5
23.3.2.6
Introduction......................................................................................................................413
CRG Overview ............................................................................................................413
CRG Block Diagram....................................................................................................413
Features........................................................................................................................414
Modes of Operation .....................................................................................................415
External Signal Description .............................................................................................415
Detailed Signal Descriptions .......................................................................................416
VDDPLL, VSSPLL ......................................................................................................416
XFC..........................................................................................................................416
RESET .....................................................................................................................416
CLKOUT/XCLKS...................................................................................................416
Memory Map and Register Definition.............................................................................417
Memory Map ...............................................................................................................417
Register Descriptions...................................................................................................417
CRG Synthesizer Register (SYNR).........................................................................417
CRG Reference Divider Register (REFDV)............................................................418
CRG ARM Flag Register 1 (CTFLG) .....................................................................419
CRG Flags Register 2 (CRGFLG)...........................................................................420
CRG Interrupt Enable Register (CRGINT) .............................................................421
CRG Clock Select Register (CLKSEL)...................................................................421
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23.3.2.7
23.3.2.8
23.3.2.9
23.4
23.4.1
23.4.2
23.4.2.1
23.4.2.1.1
23.4.2.1.2
23.4.2.2
23.4.2.3
23.4.2.4
23.4.2.5
23.4.2.6
23.4.3
23.4.3.1
23.4.3.2
23.4.4
23.4.4.1
23.4.4.2
23.4.5
23.4.5.1
23.4.5.2
23.4.5.3
23.4.5.4
23.4.5.5
23.4.5.6
23.4.6
23.4.6.1
23.4.6.2
23.4.6.3
23.5
23.6
23.7
23.7.1
23.7.2
CRG PLL Control Register (PLLCTL) ...................................................................422
CRG DOZE Control Register (SDMCTL) ..............................................................423
CRG BDM Control Register (BDMCTL) ...............................................................424
Functional Description.....................................................................................................424
General.........................................................................................................................424
Functional Blocks ........................................................................................................424
Phase Locked Loop (PLL).......................................................................................424
PLL Operation .....................................................................................................425
Acquisition and Tracking Modes.........................................................................426
System Clocks Generator ........................................................................................427
Clock Monitor (CM)................................................................................................428
Clock Quality Checker ............................................................................................428
Software Watchdog Timer (SWT) ...........................................................................430
Real Time Interrupt (RTI)........................................................................................430
Operating Modes..........................................................................................................430
Normal Mode...........................................................................................................430
Self Clock Mode ......................................................................................................430
Low Power Options .....................................................................................................431
Run Mode ................................................................................................................431
Doze Mode...............................................................................................................431
Resets ...........................................................................................................................435
General.....................................................................................................................435
Description of Reset Operation ...............................................................................435
JTAG Reset ..............................................................................................................438
Clock Monitor Reset................................................................................................438
Software Watchdog Timer (SWT) Reset .................................................................438
Power On Reset, Low Voltage Reset .......................................................................438
Interrupts......................................................................................................................439
General.....................................................................................................................439
PLL Lock Interrupt ..................................................................................................440
Self Clock Mode Interrupt .......................................................................................440
CRG Bus Aborts ..............................................................................................................440
CRG Differences from MAC71xx...................................................................................440
CRG Application Usage ..................................................................................................441
Enabling the CRG and PLL .........................................................................................441
Crystal Monitor............................................................................................................441
Chapter 24
Oscillator (OSC)
24.1
24.1.1
24.1.2
24.1.3
Introduction......................................................................................................................443
Features........................................................................................................................443
Block diagram..............................................................................................................444
Modes of Operation .....................................................................................................444
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24.2
24.2.1
24.2.2
24.2.3
24.3
24.4
24.4.1
24.4.2
24.4.3
24.5
24.6
24.7
24.8
24.8.1
24.8.2
24.8.3
External Signal Description .............................................................................................444
VDDPLL, VSSPLL ..........................................................................................................445
EXTAL, XTAL ............................................................................................................445
XCLKS (eXternal CLocK Select) ...............................................................................445
Memory Map/Register Definition ...................................................................................446
Functional Description.....................................................................................................446
Gain control .................................................................................................................446
Clock Monitor..............................................................................................................446
Doze Mode Operation..................................................................................................446
Initialization/Application Information .............................................................................447
OSC Bus Aborts...............................................................................................................447
OSC Differences from MAC71xx ...................................................................................447
OSC Application Usage...................................................................................................447
OSC Mode Selection ...................................................................................................447
OSC Mode - ALC Mode (XCLKS = 1).......................................................................447
OSC Mode - External Clock Mode (XCLKS = 0) ......................................................448
Chapter 25
System Service Module (SSM_MAC7202)
25.1
25.1.1
25.1.2
25.1.3
25.2
25.3
25.3.1
25.3.1.1
25.3.1.2
25.3.1.3
25.3.1.4
25.3.1.5
25.4
25.4.1
25.5
25.5.1
25.5.2
25.5.3
25.5.4
25.6
25.7
Introduction......................................................................................................................449
Overview......................................................................................................................449
Features........................................................................................................................449
Modes of Operation .....................................................................................................449
External Signal Description .............................................................................................450
Memory Map/Register Definition ...................................................................................450
Register Descriptions...................................................................................................450
System Status Register ............................................................................................450
System Memory Configuration Register .................................................................452
Debug Status Port Register ......................................................................................453
Error Configuration .................................................................................................455
System Reset Register .............................................................................................456
Functional Description.....................................................................................................457
System Configuration/Status .......................................................................................457
Initialization/Application Information .............................................................................458
Enabling the SSM ........................................................................................................458
Reset.............................................................................................................................458
Using the STATUS register..........................................................................................458
Using the MEMCONFIG register................................................................................459
SSM Bus Aborts ..............................................................................................................459
SSM Differences from MAC71xx ...................................................................................459
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Chapter 26
Periodic Interrupt Timer (PIT_RTI)
26.1
26.1.1
26.1.2
26.2
26.2.1
26.3
26.4
26.5
26.6
26.7
26.7.1
26.7.2
26.7.3
26.8
26.8.1
26.8.2
26.8.2.1
26.8.2.2
26.8.2.3
26.8.2.4
26.8.2.5
26.8.2.6
26.8.2.7
26.9
26.9.1
26.9.1.1
26.9.1.2
26.9.2
26.9.2.1
26.9.2.2
26.10
26.10.1
Introduction......................................................................................................................461
Overview......................................................................................................................461
Block Diagram.............................................................................................................461
PIT Features .....................................................................................................................462
Modes of Operation .....................................................................................................463
PIT Implementation .........................................................................................................463
PIT External Pins .............................................................................................................463
PIT Bus Aborts ................................................................................................................463
PIT Differences from MAC71xx .....................................................................................464
PIT Application Usage.....................................................................................................464
Enabling the PIT ..........................................................................................................464
SYSTRIG Order ..........................................................................................................464
Interrupts......................................................................................................................464
Memory Map and Register Description...........................................................................464
Memory Map ...............................................................................................................465
Register Descriptions...................................................................................................466
PIT RTI / Timer Load Value Register (TLVAL)......................................................466
PIT Current RTI / Timer Values (TVAL0–10).........................................................468
Interrupt Flags Register (PITFLG) ..........................................................................470
PIT Interrupt Enable Register (PITINTEN) ............................................................471
PIT Interrupt/DMA Select Registers (PITINTSEL)................................................472
PIT Timer Enable Register (PITEN) .......................................................................473
PIT Control Register (PITCTRL)............................................................................474
Functional Description.....................................................................................................476
General.........................................................................................................................476
Timer / RTI ..............................................................................................................476
Debug Mode ............................................................................................................477
Interrupts......................................................................................................................477
Real Time Interrupt..................................................................................................477
Timer Interrupts .......................................................................................................477
Initialization and Application Information ......................................................................478
Example Configuration................................................................................................478
Chapter 27
Enhanced Direct Memory Access (DMA Channel MUX)
27.1
27.1.1
27.1.2
27.2
27.3
Introduction......................................................................................................................481
Features........................................................................................................................482
Modes of Operation .....................................................................................................482
External Signal Description .............................................................................................482
Memory Map and Register Definition.............................................................................483
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Freescale Semiconductor
xxv
27.3.1
27.3.1.1
27.4
27.4.1
27.4.2
27.4.3
27.5
27.6
27.7
27.7.1
27.7.2
27.7.3
27.7.4
27.7.5
27.7.5.1
27.7.5.2
27.7.6
27.7.6.1
Register Descriptions...................................................................................................483
Channel Configuration Registers.............................................................................483
Functional Description.....................................................................................................486
DMA Channels 0-7......................................................................................................486
DMA Channels 8-15....................................................................................................488
"Always Enabled" DMA Sources................................................................................489
DMA_CH_MUX Bus Aborts ..........................................................................................490
DMA_CH_MUX Differences from MAC71xx...............................................................490
Initialization/Application Information .............................................................................492
Reset.............................................................................................................................492
Enabling the DMA_CH_MUX....................................................................................492
Simple Setup from AG ................................................................................................492
Using the “Always Enabled” Feature to Periodically Drive GPIO Pins .....................493
Enabling and Configuring Sources ..............................................................................494
Enabling a Source with Periodic Triggering............................................................494
Enabling a Source without Periodic Triggering ......................................................495
Disabling a Source .......................................................................................................496
Switching the Source of a DMA Channel ...............................................................496
Chapter 28
FlexCAN2
28.1
28.1.1
28.1.2
28.1.3
28.1.3.1
28.1.3.2
28.1.3.3
28.1.3.4
28.1.3.5
28.1.4
28.1.5
28.1.6
28.1.7
28.1.8
28.1.8.1
28.1.8.2
28.2
28.2.1
28.2.2
28.2.3
28.2.4
28.2.4.1
FlexCAN2 Implementation on the MAC7200.................................................................499
Introduction..................................................................................................................499
Features of FlexCAN2 on MAC7200..........................................................................499
CAN Protocol ..............................................................................................................500
Terminology.............................................................................................................500
Data Frame...............................................................................................................500
Remove Frame.........................................................................................................501
Error Frame..............................................................................................................502
Overload Frame .......................................................................................................503
CAN Implementation...................................................................................................503
CAN External Pins.......................................................................................................503
FlexCAN Bus Aborts...................................................................................................503
CAN Differences from MAC71xx ..............................................................................504
CAN Application Usage ..............................................................................................504
Enabling the CAN....................................................................................................504
Message Buffer Initialization...................................................................................505
The Generic FlexCAN2 Module......................................................................................505
Block Diagram.............................................................................................................505
Overview......................................................................................................................506
Features........................................................................................................................507
Modes of Operation .....................................................................................................508
Normal Mode (User or Supervisor):........................................................................508
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28.2.4.2
28.2.4.3
28.2.4.4
28.2.4.5
28.2.4.6
28.2.4.7
28.2.5
28.2.5.1
28.2.5.2
28.2.6
28.2.6.1
28.2.6.2
28.2.6.3
28.2.6.3.1
28.2.6.3.2
28.2.6.3.3
28.2.6.3.4
28.2.6.3.5
28.2.6.3.6
28.2.6.3.7
28.2.6.3.8
28.2.6.3.9
28.2.6.3.10
28.2.6.3.11
28.2.7
28.2.7.1
28.2.7.2
28.2.7.3
28.2.7.4
28.2.7.5
28.2.7.6
28.2.7.6.1
28.2.7.6.2
28.2.7.7
28.2.7.7.1
28.2.7.7.2
28.2.7.7.3
28.2.7.7.4
28.2.7.7.5
28.2.7.8
28.2.7.8.1
28.2.7.8.2
28.2.7.8.3
28.2.7.8.4
28.2.7.9
Freeze Mode: ...........................................................................................................508
Listen-Only Mode:...................................................................................................508
Loop-Back Mode:....................................................................................................508
Module Disable Mode: ............................................................................................508
Doze Mode: .............................................................................................................509
Stop Mode:...............................................................................................................509
External Signal Descriptions .......................................................................................509
CAN Rx ...................................................................................................................509
CAN Tx ...................................................................................................................509
Memory Map and Register Definition.........................................................................509
Memory Map ...........................................................................................................510
Message Buffer Structure ........................................................................................511
Register Descriptions...............................................................................................514
Module Configuration Register (MCR) ..............................................................514
Control Register (CTRL).....................................................................................517
Free Running Timer (TIMER).............................................................................520
Rx Global Mask (RXGMASK) ...........................................................................521
Rx 14 Mask (RX14MASK).................................................................................522
Rx 15 Mask (RX15MASK).................................................................................522
Error Counter Register (ECR) .............................................................................522
Error and Status Register (ESR) ..........................................................................524
Interrupt Masks 1 Register (IMASK1)................................................................526
Interrupt Flags 1 Register (IFLAG1)...................................................................527
Rx Individual Mask Registers (RXIMR0–RXIMR63) .......................................527
Functional Description.................................................................................................528
Overview..................................................................................................................528
Transmit Process......................................................................................................529
Arbitration Process ..................................................................................................529
Receive Process .......................................................................................................530
Matching Process.....................................................................................................531
Data Coherence........................................................................................................532
Message Buffer Deactivation ..............................................................................532
Message Buffer Lock Mechanism .......................................................................533
CAN Protocol Related Features...............................................................................534
Remote Frames ....................................................................................................534
Overload Frames..................................................................................................534
Time Stamp..........................................................................................................534
Protocol Timing ...................................................................................................534
Arbitration and Matching Timing........................................................................537
Modes of Operation Details.....................................................................................538
Freeze Mode ........................................................................................................538
Module Disable Mode .........................................................................................538
Doze Mode ..........................................................................................................539
Stop Mode............................................................................................................540
Interrupts..................................................................................................................541
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xxvii
28.2.7.10
28.2.8
28.2.8.1
28.2.8.2
Bus Interface............................................................................................................541
Initialization/Application Information.........................................................................542
FlexCAN Initialization Sequence ............................................................................542
FlexCAN Addressing...............................................................................................543
Chapter 29
Inter-Integrated Circuit Bus Controller Module (I2C_DMA)
29.1
29.1.1
29.1.2
29.1.3
29.1.4
29.2
29.3
29.4
29.4.1
29.5
29.5.1
29.5.2
29.5.2.1
29.5.2.2
29.5.2.3
29.5.2.4
29.5.2.5
29.5.2.6
29.6
29.6.1
29.6.2
29.6.2.1
29.6.2.2
29.6.2.3
29.6.2.4
29.6.2.5
29.6.2.6
29.6.2.7
29.6.2.8
29.6.2.9
29.6.3
29.6.3.1
29.6.3.2
29.7
29.7.1
29.7.1.1
Introduction......................................................................................................................545
Block Diagram.............................................................................................................545
DMA Interface.............................................................................................................546
Features........................................................................................................................547
Modes of Operation .....................................................................................................548
I2C Module Implementation ............................................................................................548
External Signal Description .............................................................................................548
I2C Module Differences from MAC71xx ........................................................................548
Enabling the I2C Module .............................................................................................549
Memory Map/Register Definition ...................................................................................549
Module Memory Map..................................................................................................549
Register Descriptions...................................................................................................550
I2C Address Register ...............................................................................................550
I2C Frequency Divider Register ..............................................................................550
I2C Control Register ................................................................................................557
I2C Status Register...................................................................................................558
I2C Data I/O Register ..............................................................................................559
I2C Interrupt Config Register ..................................................................................560
Functional Description.....................................................................................................560
General.........................................................................................................................560
I-Bus Protocol .............................................................................................................560
START Signal ..........................................................................................................561
Slave Address Transmission....................................................................................562
Data Transfer ...........................................................................................................562
STOP Signal ............................................................................................................562
Repeated START Signal ..........................................................................................563
Arbitration Procedure ..............................................................................................563
Clock Synchronization.............................................................................................563
Handshaking ............................................................................................................564
Clock Stretching ......................................................................................................564
Interrupts......................................................................................................................564
General.....................................................................................................................564
Interrupt Description................................................................................................564
Initialization/Application Information .............................................................................565
I2C Programming Examples ........................................................................................565
Initialization Sequence.............................................................................................565
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29.7.1.2
29.7.1.3
29.7.1.4
29.7.1.5
29.7.1.6
29.7.1.7
29.7.2
29.7.2.1
29.7.2.2
29.7.2.3
Generation of START ..............................................................................................565
Post-Transfer Software Response ............................................................................565
Generation of STOP.................................................................................................566
Generation of Repeated START ..............................................................................567
Slave Mode ..............................................................................................................567
Arbitration Lost .......................................................................................................567
DMA Application Information ....................................................................................569
DMA Mode, Master Transmit .................................................................................569
DMA Mode, Master RX ..........................................................................................570
Exiting DMA Mode, System Requirement Considerations ....................................571
Chapter 30
Deserial Serial Peripheral Interface (DSPI)
30.1
30.2
30.3
30.4
30.5
30.6
30.7
30.8
30.8.1
30.8.2
30.9
30.9.1
30.9.2
30.9.3
30.9.3.1
30.9.4
30.9.4.1
30.9.4.2
30.9.4.3
30.9.4.4
30.9.4.5
30.10
30.10.1
30.10.2
30.10.2.1
30.10.2.2
30.10.2.3
30.10.2.4
30.10.2.5
30.10.2.6
Introduction to the DSPI on MAC7200 ...........................................................................575
DSPI Features ..................................................................................................................575
DSPI Protocol ..................................................................................................................575
DSPI Implementation ......................................................................................................576
DSPI External Pins ..........................................................................................................577
DSPI Bus Aborts..............................................................................................................577
DSPI Differences from MAC71xx ..................................................................................577
DSPI Application Usage ..................................................................................................578
Enabling the DSPI .......................................................................................................578
Baud Rate Calculation .................................................................................................578
DSPI Module ...................................................................................................................579
Block Diagram.............................................................................................................579
Overview......................................................................................................................580
DSPI Configuration .....................................................................................................580
SPI Configuration ....................................................................................................580
Modes of Operation .....................................................................................................580
Master Mode............................................................................................................581
Slave Mode ..............................................................................................................581
Module Disable Mode .............................................................................................581
External Stop Mode .................................................................................................581
Debug Mode ............................................................................................................581
External Signal Description .............................................................................................581
Overview......................................................................................................................581
Detailed Signal Description .........................................................................................582
PCS[0]/SS — Peripheral Chip Select/Slave Select .................................................582
PCS[1] - PCS[3] — Peripheral Chip Selects 1 - 3...................................................582
PCS[4]/MTRIG — Peripheral Chip Select 4/Master Trigger .................................582
PCS[5]/PCSS — Peripheral Chip Select 5/Peripheral Chip Select Strobe..............582
PCS[6] - PCS[7] — Peripheral Chip Selects 6- 7....................................................583
SIN — Serial Input ..................................................................................................583
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Freescale Semiconductor
xxix
30.10.2.7
30.10.2.8
30.11
30.11.1
30.11.2
30.11.2.1
30.11.2.2
30.11.2.3
30.11.2.4
30.11.2.5
30.11.2.6
30.11.2.7
30.11.2.8
30.11.2.9
30.12
30.12.1
30.12.1.1
30.12.1.2
30.12.1.3
30.12.1.4
30.12.1.5
30.12.2
30.12.3
30.12.3.1
30.12.3.2
30.12.3.3
30.12.3.4
30.12.3.4.1
30.12.3.4.2
30.12.3.5
30.12.3.5.1
30.12.3.5.2
30.12.4
30.12.4.1
30.12.4.2
30.12.4.3
30.12.4.4
30.12.4.5
30.12.5
30.12.5.1
30.12.5.2
30.12.5.3
30.12.5.4
30.12.5.5
SOUT — Serial Output ...........................................................................................583
SCK — Serial Clock................................................................................................583
Memory Map and Register Definition.............................................................................583
Memory Map ...............................................................................................................583
Register Descriptions...................................................................................................584
DSPI Module Configuration Register (DSPI_MCR) ..............................................584
DSPI Transfer Count Register (DSPI_TCR) ...........................................................586
DSPI Clock and Transfer Attributes Registers 0–7
(DSPI_CTAR0–DSPI_CTAR7)...........................................................................587
DSPI Status Register (DSPI_SR) ............................................................................592
DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER) .............594
DSPI PUSH TX FIFO Register (DSPI_PUSHR)....................................................596
DSPI POP RX FIFO Register (DSPI_POPR) .........................................................597
DSPI Transmit FIFO Registers 0–3 (DSPI_TXFR0–DSPI_TXFR3) .....................598
DSPI Receive FIFO Registers 0–3 (DSPI_RXFR0–DSPI_RXFR3) ......................599
Functional Description.....................................................................................................599
Modes of Operation .....................................................................................................600
Master Mode............................................................................................................601
Slave Mode ..............................................................................................................601
Module Disable Mode .............................................................................................601
External Stop Mode .................................................................................................601
Debug Mode ............................................................................................................601
Start and Stop of DSPI Transfers.................................................................................602
Serial Peripheral Interface (SPI) Configuration...........................................................602
Master Mode............................................................................................................603
Slave Mode ..............................................................................................................603
FIFO Disable Operation ..........................................................................................603
Transmit First In First Out (TX FIFO) Buffering Mechanism ................................604
Filling the TX FIFO.............................................................................................604
Draining the TX FIFO .........................................................................................604
Receive First In First Out (RX FIFO) Buffering Mechanism .................................604
Filling the RX FIFO ............................................................................................605
Draining the RX FIFO.........................................................................................605
DSPI Baud Rate and Clock Delay Generation ............................................................605
Baud Rate Generator................................................................................................606
PCS to SCK Delay (tCSC) ........................................................................................606
After SCK Delay (tASC)...........................................................................................606
Delay after Transfer (tDT) .......................................................................................606
Peripheral Chip Select Strobe Enable (PCSS).........................................................607
Transfer Formats..........................................................................................................608
Classic SPI Transfer Format (CPHA = 0) ...............................................................608
Classic SPI Transfer Format (CPHA = 1) ...............................................................609
Modified Transfer Format (MTFE = 1, CPHA = 0) ................................................610
Modified SPI Transfer Format (MTFE = 1, CPHA = 1) .........................................611
Continuous Selection Format ..................................................................................612
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Freescale Semiconductor
30.12.6
30.12.7
30.12.7.1
30.12.7.2
30.12.7.3
30.12.7.4
30.12.7.5
30.12.7.6
30.12.8
30.12.8.1
30.12.8.2
30.12.8.3
30.13
30.13.1
30.13.2
30.13.3
30.13.4
30.13.5
30.13.5.1
30.13.5.2
Continuous Serial Communications Clock..................................................................614
Interrupts/DMA Requests ............................................................................................615
End of Queue Interrupt Request ..............................................................................615
Transmit FIFO Fill Interrupt or DMA Request .......................................................616
Transfer Complete Interrupt Request ......................................................................616
Transmit FIFO Underflow Interrupt Request ..........................................................616
Receive FIFO Drain Interrupt or DMA Request .....................................................616
Receive FIFO Overflow Interrupt Request..............................................................616
Power Saving Features.................................................................................................616
External Stop Mode .................................................................................................617
Module Disable Mode .............................................................................................617
Signal Gating ...........................................................................................................618
Initialization/Application Information .............................................................................618
How to Change Queues ...............................................................................................618
Baud Rate Settings.......................................................................................................619
Delay Settings ..............................................................................................................619
Oak Family Compatibility with the DSPI ...................................................................620
Calculation of FIFO Pointer Addresses .......................................................................621
Address Calculation for the First-in Entry and Last-in Entry in the TX FIFO........622
Address Calculation for the First-in Entry and Last-in Entry in the RX FIFO .......622
Chapter 31
Enhanced Serial Communications Interface (eSCI)
31.1
31.1.1
31.2
31.2.1
31.2.2
31.3
31.3.1
31.4
31.5
31.5.1
31.5.2
31.6
31.7
31.8
31.8.1
31.9
31.9.1
31.9.2
31.9.2.1
31.9.2.2
Introduction to the eSCI on MAC7200............................................................................625
Block Diagram.............................................................................................................626
eSCI Features ...................................................................................................................627
LIN support..................................................................................................................627
Modes of Operation .....................................................................................................628
eSCI Protocol ...................................................................................................................628
LIN Protocol Summary................................................................................................628
eSCI Implementation .......................................................................................................630
eSCI External Pins ...........................................................................................................630
SCI Transmit Pin (TXD_A, TXD_B)..........................................................................630
SCI Receive Pin (RXD)...............................................................................................630
eSCI Bus Aborts ..............................................................................................................630
eSCI Differences from MAC71xx ...................................................................................630
eSCI Application Usage...................................................................................................631
Enabling the eSCI ........................................................................................................631
Memory Map and Register Definition.............................................................................631
Memory Map ...............................................................................................................631
Register Descriptions...................................................................................................634
SCI Baud Rate Registers .........................................................................................634
SCI Control Register 1.............................................................................................635
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Freescale Semiconductor
xxxi
31.9.2.3
31.9.2.4
31.9.2.5
31.9.2.6
31.9.2.7
31.9.2.8
31.9.2.9
31.9.2.10
31.9.2.11
31.9.2.12
31.9.2.13
31.9.2.14
31.10
31.10.1
31.10.2
31.10.3
31.10.4
31.10.4.1
31.10.4.2
31.10.4.3
31.10.4.4
31.10.4.5
31.10.4.6
31.10.5
31.10.5.1
31.10.5.2
31.10.5.3
31.10.5.4
31.10.5.5
31.10.5.5.1
31.10.5.5.2
31.10.5.6
31.10.5.6.1
31.10.5.6.2
31.10.6
31.10.7
31.10.8
31.10.8.1
31.10.8.2
31.10.8.3
31.10.9
31.10.9.1
31.10.9.2
31.10.9.3
31.10.9.4
SCI Control Register 2.............................................................................................637
SCI Control Register 3.............................................................................................638
SCI Control Register 4.............................................................................................639
SCI Data Registers...................................................................................................639
SCI Status Register 1 ...............................................................................................640
SCI Status Register 2 ...............................................................................................642
LIN Status Register 1...............................................................................................642
LIN Status Register 2...............................................................................................643
LIN Control Registers..............................................................................................644
LIN TX Register ......................................................................................................646
LIN RX Register......................................................................................................648
LIN CRC Polynomial Register................................................................................649
Functional Description.....................................................................................................649
General.........................................................................................................................649
Data Format .................................................................................................................650
Baud Rate Generation..................................................................................................651
Transmitter...................................................................................................................652
Transmitter Character Length..................................................................................653
Character Transmission ...........................................................................................653
Break Characters......................................................................................................654
Idle Characters .........................................................................................................655
Standard Bit Error Detection ...................................................................................655
Fast Bit Error Detection in LIN mode .....................................................................655
Receiver .......................................................................................................................657
Receiver Character Length ......................................................................................657
Character Reception.................................................................................................657
Data Sampling .........................................................................................................658
Framing Errors.........................................................................................................662
Baud Rate Tolerance................................................................................................662
Slow Data Tolerance............................................................................................663
Fast Data Tolerance ............................................................................................664
Receiver Wakeup .....................................................................................................664
Idle Input Line Wakeup (WAKE = 0)..................................................................665
Address Mark Wakeup (WAKE = 1) ...................................................................665
Single-Wire Operation .................................................................................................665
Loop Operation ............................................................................................................666
Modes of Operation .....................................................................................................666
Run Mode ................................................................................................................666
Doze Mode...............................................................................................................666
Module Disable........................................................................................................667
Interrupt Operation ......................................................................................................667
Interrupt Flags and Masks .......................................................................................667
Interrupt Description................................................................................................668
TDRE Description ...................................................................................................669
TC Description.........................................................................................................669
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31.10.9.5
31.10.9.6
31.10.9.7
31.10.9.8
31.10.9.9
31.10.9.10
31.10.9.11
31.10.9.12
31.10.9.13
31.10.9.14
31.10.9.15
31.10.9.16
31.10.9.17
31.10.9.18
31.10.9.19
31.10.9.20
31.10.10
31.10.11
31.10.11.1
31.10.11.2
31.10.11.3
31.10.11.4
31.10.11.5
31.10.11.6
31.10.11.7
RDRF Description ...................................................................................................669
PF Description .........................................................................................................669
FE Description .........................................................................................................669
NF Description.........................................................................................................669
OR Description ........................................................................................................669
IDLE Description.....................................................................................................669
BERR Description ...................................................................................................669
RXRDY Description................................................................................................670
TXRDY Description................................................................................................670
LWAKE Description ................................................................................................670
STO Description ......................................................................................................670
PBERR Description .................................................................................................670
CERR Description ...................................................................................................670
CKERR Description ................................................................................................670
FRC Description ......................................................................................................670
OVFL Description ...................................................................................................671
Using the eSCI in 9-bit data mode...............................................................................671
Using the LIN hardware ..............................................................................................671
Generating a TX Frame ...........................................................................................672
Generating an RX frame..........................................................................................673
Features of the LIN Hardware .................................................................................674
LIN Error Handling .................................................................................................675
LIN Wakeup.............................................................................................................675
System Wakeup on LIN Bus Activity......................................................................676
LIN Setup.................................................................................................................676
Chapter 32
Modular I/O Subsystem (eMIOS)
32.1
32.2
32.3
32.4
32.5
32.6
32.7
32.8
32.9
32.10
32.10.1
32.10.2
32.10.3
32.10.4
32.11
Introduction......................................................................................................................677
eMIOS Features on MAC72xx ........................................................................................678
eMIOS Protocol ...............................................................................................................678
eMIOS Implementation ...................................................................................................678
eMIOS External Pins .......................................................................................................679
eMIOS Bus Aborts...........................................................................................................679
eMIOS Differences betwee MAC71xx and MAC72x2...................................................679
eMIOS Differences between MAC72x2 and MAC72x1.................................................680
Enabling the eMIOS ........................................................................................................680
The eMIOS Module .........................................................................................................680
Overview......................................................................................................................680
Block Diagram.............................................................................................................680
Features........................................................................................................................682
Modes of Operation .....................................................................................................683
External Signal Description .............................................................................................684
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Freescale Semiconductor
xxxiii
32.11.1
32.11.2
32.11.2.1
32.11.2.2
32.12
32.12.1
32.12.2
32.12.2.1
32.12.2.2
32.12.2.3
32.12.2.4
32.12.2.5
32.12.2.6
32.12.2.7
32.12.2.8
32.12.2.9
32.12.2.10
32.13
32.13.1
32.13.1.1
32.13.1.1.1
32.13.1.1.2
32.13.1.1.3
32.13.1.1.4
32.13.1.1.5
32.13.1.1.6
32.13.1.1.7
32.13.1.1.8
32.13.1.1.9
32.13.1.1.10
32.13.1.1.11
32.13.1.1.12
32.13.1.1.13
32.13.1.1.14
32.13.1.1.15
32.13.1.1.16
32.13.1.1.17
32.13.1.1.18
32.13.1.2
32.13.1.3
32.13.1.4
32.13.2
32.13.2.1
32.13.3
Overview......................................................................................................................684
Detailed Signal Descriptions .......................................................................................684
EMIOSIn - eMIOS Unified Channel Input Signal ..................................................684
EMIOSOn - eMIOS Unified Channel Output Signal ..............................................684
Memory Map/Register Definition ...................................................................................684
Memory Map ...............................................................................................................684
Register Descriptions...................................................................................................685
eMIOS Module Configuration Register (MCR)......................................................685
eMIOS Global FLAG Register (GFLAG) ...............................................................687
eMIOS Output Update Disable (OUDIS)................................................................688
eMIOS Disable Channel (UCDIS) ..........................................................................689
eMIOS A Register (UCAn) .....................................................................................689
eMIOS B Register (UCBn)......................................................................................690
eMIOS Counter Register (UCCNTn) ......................................................................691
eMIOS Control Register (UCCRn) .........................................................................692
eMIOS Status Register (UCSRn) ............................................................................696
eMIOS Alternate A Register (ALTAn)....................................................................698
Functional Description.....................................................................................................699
Unified Channel (UC)..................................................................................................699
UC Modes of Operation...........................................................................................700
General purpose Input/Output mode (GPIO) Mode ............................................701
Single Action Input Capture (SAIC) Mode.........................................................701
Single Action Output Compare (SAOC) Mode...................................................701
Input Pulse Width Measurement (IPWM) Mode.................................................702
Input Period Measurement (IPM) Mode .............................................................704
Double Action Output Compare (DAOC) Mode ................................................705
Pulse/Edge Accumulation (PEA) Mode ..............................................................706
Pulse/Edge Counting (PEC) Mode ......................................................................708
Quadrature Decode (QDEC) Mode .....................................................................709
Windowed Programmable Time Accumulation (WPTA) Mode..........................711
Modulus Counter (MC) Mode .............................................................................711
Modulus Counter Buffered (MCB) Mode ...........................................................712
Pulse Width and Frequency Modulation (OPWFM) Mode.................................715
Pulse Width and Frequency Modulation Buffered (OPWFMB) Mode ...............716
Center Aligned Output Pulse Width Modulation with Dead-Time
(OPWMC) Mode .............................................................................................720
Center Aligned Output PWM Buffered with Dead-Time (OPWMCB) Mode ....723
Output Pulse Width Modulation (OPWM) Mode................................................727
Pulse Width Modulation Buffered (OPWMB) Mode..........................................729
Input Programmable Filter (IPF) .............................................................................732
Clock Prescaler (CP)................................................................................................733
Effect of Freeze on the Unified Channel .................................................................733
IP Bus Interface Unit (BIU).........................................................................................734
Effect of Freeze on the BIU.....................................................................................734
Global Clock Prescaler Submodule (GCP)..................................................................734
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32.13.3.1
32.14
32.14.1
32.14.2
32.14.2.1
32.14.2.2
Effect of Freeze on the GCP ....................................................................................734
Initialization/Application Information .............................................................................734
Considerations .............................................................................................................734
Application Information ..............................................................................................735
Time Base Generation .............................................................................................735
Coherent Accesses ...................................................................................................736
Chapter 33
A/D Converter (ATD)
33.1
33.2
33.3
33.4
33.5
33.6
33.7
33.7.1
33.7.2
33.7.3
33.7.4
33.7.4.1
33.8
33.8.1
33.8.2
33.8.3
33.8.4
33.9
33.9.1
33.9.2
33.9.2.1
33.9.2.2
33.9.2.3
33.9.2.4
33.9.2.5
33.9.2.6
33.9.2.7
33.9.2.8
33.9.2.9
33.9.2.10
33.10
33.10.1
33.10.2
33.10.2.1
Introduction to the ATD on MAC7200............................................................................737
ATD Features ...................................................................................................................737
ATD Implementation .......................................................................................................738
ATD External Pins ...........................................................................................................738
ATD Bus Aborts...............................................................................................................738
ATD Differences from MAC71xx ...................................................................................739
ATD Application Usage...................................................................................................740
Enabling the ATD ........................................................................................................740
Setting up the ATD ......................................................................................................740
Using external triggers.................................................................................................740
Using the system triggers.............................................................................................740
Example — Using System Triggers ........................................................................740
The DMADC1032 Module ..............................................................................................741
Overview......................................................................................................................741
Block Diagram.............................................................................................................742
Features of DMADC1032............................................................................................742
Modes of Operation .....................................................................................................743
Signal Description............................................................................................................743
Overview......................................................................................................................743
Signal Descriptions ......................................................................................................744
VDDA......................................................................................................................744
VSSA .......................................................................................................................744
VRH.........................................................................................................................745
VRL .........................................................................................................................745
REFBYPC................................................................................................................745
ANn..........................................................................................................................745
SYSTRIGn...............................................................................................................745
RX req / RX done ....................................................................................................745
TX reg / TX done.....................................................................................................745
SYSTRIG0/1, Interrupt, IP Bus Clock, System Clock............................................745
Memory Map and Register Definition.............................................................................745
Module Memory Map..................................................................................................745
Register Descriptions...................................................................................................746
ATD Trigger Control Register (ATDTRIGCTL).....................................................746
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
xxxv
33.10.2.2
33.10.2.3
33.10.2.4
33.10.2.5
33.10.2.6
33.10.2.7
33.10.2.8
33.10.2.9
33.10.2.10
33.11
33.11.1
33.11.2
33.11.2.1
33.11.2.2
33.11.2.3
33.11.2.4
33.11.3
33.11.3.1
33.11.3.2
33.11.3.3
33.11.3.4
33.11.3.5
33.11.3.6
33.11.3.7
33.11.3.8
33.11.4
33.11.5
33.11.5.1
33.11.5.2
33.11.5.3
33.11.6
33.11.7
33.12
33.12.1
33.12.2
33.12.2.1
33.12.2.1.1
33.12.2.1.2
33.12.2.1.3
33.12.2.1.4
33.12.2.1.5
33.12.2.2
33.12.2.3
33.12.2.3.1
33.12.2.3.2
ATD External Trigger Channel Register (ATDETRIGCH).....................................748
ATD Prescaler Register (ATDPRE).........................................................................748
ATD Operating Modes Register (ATDMODE) .......................................................750
ATD Calibration Register (ATDCAL).....................................................................751
ATD Predischarge Time Select Register (ATDPTS) ...............................................752
ATD Interrupt Register (ATDINT) ..........................................................................753
ATD Flag Register (ATDFLAG) .............................................................................754
ATD Command Word Register (ATDCW)..............................................................756
ATD Result Register (ATDRR) ...............................................................................761
Functional Description.....................................................................................................762
General.........................................................................................................................762
Analog Conversion Circuit ..........................................................................................762
Analog Input Multiplexer ........................................................................................762
Sample Capacitor.....................................................................................................762
Reference Voltage Generation .................................................................................762
Conversion Circuit...................................................................................................762
Digital Sub-blocks .......................................................................................................763
Mode / Timing Control ............................................................................................763
Clock Prescaler ........................................................................................................763
Bus Interface / Registers..........................................................................................763
Command Word / Result / DMA .............................................................................763
SYSTRIG0, SYSTRIG1 / External Trigger Input ...................................................763
Flags.........................................................................................................................763
Result Adjustment ...................................................................................................764
Conversion Control..................................................................................................764
Low Power / Operating Modes....................................................................................764
Conversion Process......................................................................................................765
Command Queue .....................................................................................................766
Command Processing and DMA Requests..............................................................766
Command / Result Timing.......................................................................................769
Conversion Timing ......................................................................................................770
Conversions Using Predischarge .................................................................................772
Initialization/Application Information .............................................................................774
Initialization .................................................................................................................774
ATD Calibration / Result Adjustment..........................................................................775
Gain error.................................................................................................................776
Gain Error Correction via GCC (Gain Too High) ...............................................776
Gain Error Correction via OCC (Gain Too High) ...............................................776
Gain Error Correction via OCC and GCC (Gain Too High) ...............................777
Gain Error Correction via Warp (Gain Too High)...............................................777
Gain Error Correction via GCC (Gain Too Low)................................................778
Offset Error ..............................................................................................................778
Steps Required For Calibration ...............................................................................779
Sample Special Channel 75% x (VRH - VRL) ...................................................780
Sample Special Channel 25% x (VRH - VRL) ...................................................780
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33.12.2.3.3
33.12.2.3.4
33.12.3
33.12.3.1
33.12.3.2
33.12.3.3
33.12.3.4
33.12.3.5
33.12.3.6
33.12.3.7
33.12.3.8
33.12.3.9
33.12.4
33.12.5
Determine Gain Constant GCC / Determine Offset Constant OCC....................781
Adjustment Example ...........................................................................................782
Conversion Examples ..................................................................................................782
Example 1: A Simple Conversion ...........................................................................783
Example 2: A Simple Conversion Sequence (Convert then Pause) ........................783
Example 3: Interrupted Conversion Sequence ........................................................785
Example 4: Edge-triggered Conversion...................................................................786
Example 5: Level-triggered Conversion..................................................................787
Example 6: Queue Running Idle..............................................................................789
Example 7: Entering Low-power Mode During a Conversion................................789
Example 8: Debug Mode .........................................................................................790
Conversion Mechanism (bits CWCH, CWNF, CWGI, CWSC, CWAR) ................791
Reset.............................................................................................................................792
Interrupts......................................................................................................................792
Chapter 34
Port Integration Module (PIM_MAC7202)
34.1
34.1.1
34.1.2
34.1.3
34.1.3.1
34.1.3.2
34.1.3.3
34.2
34.2.1
34.2.2
34.2.3
34.2.4
34.2.5
34.2.6
34.2.7
34.3
34.4
34.5
34.5.1
34.5.2
34.5.3
34.5.4
34.6
34.6.1
34.6.1.1
34.6.1.2
Introduction......................................................................................................................795
Overview......................................................................................................................795
Features........................................................................................................................798
Modes of Operation .....................................................................................................798
Peripheral Mode (CONFIG::MODE[1:0] ¼ 0 0) ....................................................798
GPIO Output Mode (CONFIG::MODE[1:0] = 0 0, CONFIG::DDR = 1) ..............799
GPIO Input Mode (CONFIG::MODE[1:0] = 0 0, CONFIG::DDR = 0).................799
External Signal Description .............................................................................................799
Port A...........................................................................................................................803
Port B ...........................................................................................................................803
Port C ...........................................................................................................................803
Port D...........................................................................................................................804
Port E ...........................................................................................................................804
Port F............................................................................................................................804
Port G...........................................................................................................................804
PIM Bus Aborts ...............................................................................................................805
PIM Differences from MAC71xx....................................................................................805
PIM Application Usage ...................................................................................................805
Enabling the PIM .........................................................................................................805
Using Single Pins in a Port ..........................................................................................806
Pin versus Port Registers .............................................................................................806
Peripheral Muxing .......................................................................................................806
Memory Map and Register Definition.............................................................................808
Register Descriptions...................................................................................................816
Pin Configuration Register (Port A, B, C, D, F, G) .................................................816
Pin Configuration Register (Port E) ........................................................................818
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
xxxvii
34.6.1.3
34.6.1.4
34.6.1.5
34.6.1.6
34.6.1.7
34.6.1.8
34.6.1.9
34.6.1.10
34.6.1.11
34.6.1.12
34.6.1.13
34.6.1.14
34.6.1.15
34.6.1.16
34.6.1.17
34.7
34.7.1
34.7.2
34.7.3
34.7.3.1
34.7.3.2
34.7.4
34.7.4.1
34.7.4.2
34.7.5
34.7.5.1
34.7.6
34.8
34.8.1
34.8.2
34.8.2.1
34.8.2.2
34.8.2.2.1
34.8.2.2.2
34.8.2.2.3
34.8.2.3
34.8.3
34.8.3.1
34.8.3.2
34.8.3.3
34.8.3.4
34.8.4
Port Wide Interrupt Flag Register............................................................................820
Port Wide Data Register (Port A, B, C, D, F, G) .....................................................820
Port Wide Data Register (Port E) ............................................................................821
Port Wide Input Register (Port A, B, C, D, F, G) ....................................................822
Port Wide Input Register (Port E)............................................................................822
Pin Data Register (Port A, B, C, D, F, G)................................................................823
Pin Data Register (Port E) .......................................................................................824
Global Interrupt Status Register ..............................................................................824
PIM Configuration Register ....................................................................................825
TDI Pin Configuration Register...............................................................................826
TDO Pin Configuration Register .............................................................................827
TMS Pin Configuration Register .............................................................................828
TCK Pin Configuration Register .............................................................................829
RESET Pin Configuration Register .........................................................................829
Double Port Wide Input Registers ...........................................................................830
Functional Description.....................................................................................................831
Reset.............................................................................................................................831
Peripheral Mode...........................................................................................................832
Peripheral Pin Multiplexing.........................................................................................833
Driving Multiple Outputs ........................................................................................834
Input Multiplexing - Priorities .................................................................................834
General Purpose Input mode........................................................................................835
Overview..................................................................................................................835
Interrupts..................................................................................................................837
General Purpose Output mode.....................................................................................838
Overview..................................................................................................................838
PIM Integration Hints ..................................................................................................840
Initialization/Application Information .............................................................................845
Using a Pin in Peripheral Mode...................................................................................845
Using a Pin in GPIO Mode ..........................................................................................846
Initialization.............................................................................................................846
Accessing Data ........................................................................................................847
Driving/Sampling an Entire Port .........................................................................847
Driving/Sampling Individual Pins .......................................................................848
Using a DMA.......................................................................................................849
Using Interrupts .......................................................................................................850
Using the PD2 pad (CLKOUT) ...................................................................................852
Enabling the CLKOUT output.................................................................................852
Disabling the CLKOUT output ...............................................................................853
Using pad PD2 as a General Purpose Input.............................................................853
Using pad PD2 as a General Purpose Output ..........................................................853
Unbonded Pins.............................................................................................................853
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Chapter 35
Test Controller (PTI)
35.1
35.1.1
35.1.2
35.2
35.3
Test Controller Introduction.............................................................................................855
JTAG Test Register (SC4) ...........................................................................................855
JTAG Lockout Recovery .............................................................................................857
Test Controller External Pins ...........................................................................................857
Test Controller Application Usage...................................................................................857
Appendix A
Electrical Characteristics
A.1
A.2
A.3
A.4
A.4.1
A.4.2
A.4.3
A.5
A.5.1
A.6
A.6.1
A.6.2
A.6.3
A.7
A.7.1
A.8
A.9
A.9.1
A.9.2
A.9.3
A.9.4
A.9.5
A.10
A.10.1
A.10.2
A.11
A.11.1
A.11.2
A.12
A.13
A.14
A.14.1
Parameter Classification ..................................................................................................859
Absolute Maximum Ratings ............................................................................................859
ESD Protection and Latch-up Immunity .........................................................................860
Operating Conditions .......................................................................................................861
Input/Output Pins.........................................................................................................862
Oscillator Pins..............................................................................................................863
PLL Pins ......................................................................................................................863
Power Dissipation and Thermal Characteristics ..............................................................863
Thermal Resistance Simulation Details.......................................................................864
Power Supply ...................................................................................................................866
Current Injection ..........................................................................................................866
Power Supply Pins .......................................................................................................866
Supply Current Characteristics ....................................................................................867
Voltage Regulator Characteristics....................................................................................868
Output Loads................................................................................................................869
Oscillator Characteristics .................................................................................................869
PLL Characteristics..........................................................................................................871
PLL Filter Characteristics............................................................................................871
PLL Characteristics......................................................................................................872
Crystal Monitor Time-out ............................................................................................873
Clock Quality Checker.................................................................................................873
Startup..........................................................................................................................873
General Purpose I/O (PIM) Timing .................................................................................874
General Purpose Input (GPI) .......................................................................................874
General Purpose Output (GPO) ...................................................................................874
Nexus Timing Specifications ...........................................................................................875
Nexus Inputs ................................................................................................................875
Nexus Outputs..............................................................................................................875
External Interrupt Inputs (IRQ/XIRQ) ............................................................................876
JTAG Port Timing............................................................................................................876
DSPI Timing ....................................................................................................................877
Master Mode ................................................................................................................877
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A.14.2
A.15
A.15.1
A.15.2
A.16
A.16.1
A.16.2
A.16.3
A.17
A.18
A.18.1
A.18.2
Slave Mode ..................................................................................................................879
External Bus (FlexBus) Timing Specifications ...............................................................881
FlexBus Inputs .............................................................................................................881
FlexBus Outputs ..........................................................................................................882
Analog-to-Digital Converter Characteristics ...................................................................884
Factors Influencing Accuracy......................................................................................885
ATD Accuracy .............................................................................................................885
ATD Timing Specifications .........................................................................................889
I2C Timing Specifications ...............................................................................................890
Flash Characteristics ........................................................................................................891
NVM Timing Specifications........................................................................................892
NVM Reliability ..........................................................................................................892
Appendix B
Mechanical Information
B.1
B.2
B.3
General.............................................................................................................................895
100-pin LQFP Package ....................................................................................................895
144-pin QFP Package ......................................................................................................895
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Figures
Figure
Number
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9-3
9-4
9-5
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11-3
11-4
11-5
Title
Page
Number
Orderable Part Number Example.............................................................................................8
MAC72xx Architecture Overview.........................................................................................13
PAC7211/PAC7212 Pin Assignment, 144 QFP ....................................................................30
PAC7201/PAC7202 Pin Assignment, 144 QFP ....................................................................31
MAC7241/MAC7242 Pin assignments, 100 Pin LQFP package .........................................32
Bidirectional Open Drain Pin.................................................................................................39
PLL Loop Filter Connections ................................................................................................39
MAC72xx Clock Tree............................................................................................................60
CRG Generated Clocks..........................................................................................................62
Timing of CRG Generated Clocks.........................................................................................63
ALC 1:1 Mode Clock Path ....................................................................................................64
ALC PLL Mode Clock Path ..................................................................................................65
External Clock 1:1 Mode Clock Path ....................................................................................66
External Clock PLL Mode Clock Path ..................................................................................67
System Clock Gating .............................................................................................................70
MAC72xx Resets ...................................................................................................................72
JTAG Interface Overview......................................................................................................92
JTAG TCK Routing ...............................................................................................................93
JTAG TMS Routing...............................................................................................................93
JTAG TDI Routing ................................................................................................................94
JTAG TDO Routing...............................................................................................................94
JTAG Synchronization Circuit ..............................................................................................95
JTAG Synchronization Timing (TCK = 1/3 frequency of ipg_clk) ......................................96
JTAG Synchronization Timing (TCK = 1/8 frequency of ipg_clk) ......................................96
Halt Mode Overview..............................................................................................................98
Monitor Mode Overview .......................................................................................................99
MAC72xx Memory Map Overview.....................................................................................103
MAC72x1 Memory Map Example .....................................................................................104
MAC72x2 Memory Map Example ....................................................................................105
Device Programming Sequence ...........................................................................................124
Device “Normal” Boot Sequence ........................................................................................124
A7S Nexus3 Functional Block Diagram..............................................................................129
Single Pin MSEO Transfers.................................................................................................145
Two Pin MSEO Transfers....................................................................................................146
JTAG ID Register ................................................................................................................149
Client Select Control Register (CSC) ..................................................................................151
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Freescale Semiconductor
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11-46
11-47
11-48
11-49
11-50
Development Control Register (DC) ...................................................................................151
Development Status Register (DS) ......................................................................................153
User Base Address Register (UBA).....................................................................................154
Read/Write Access Control Register (RWCS) ....................................................................154
Read/Write Access Data Register (RWD) ...........................................................................156
Read/Write Access Address Register (RWA) .....................................................................156
Watchpoint Trigger Register (WT)......................................................................................156
Data Trace Control Register (DTC).....................................................................................158
Data Trace Start Address Registers (DTSA1, DTSA2).......................................................159
Data Trace End Address Registers (DTEA1, DTEA2) .......................................................159
Breakpoint/Watchpoint Control Registers (BWC1, BWC2) ...............................................160
Breakpoint / Watchpoint Control Registers (BWC3-6).......................................................161
Breakpoint / Watchpoint Address Registers (BWA1-6)......................................................161
Breakpoint / Watchpoint Address Mask Registers (BWAM1, BWAM2)...........................162
Breakpoint / Watchpoint Data Registers (BWD1, BWD2) .................................................162
Breakpoint / Watchpoint Data Mask Registers (BWDM1, BWDM2) ................................163
Port Configuration Register (PCR)......................................................................................163
JTAG DR for Nexus Register Access..................................................................................165
Ownership Trace Message Format ......................................................................................166
Error Message Format..........................................................................................................167
Indirect Branch Message (History) Format .........................................................................169
Indirect Branch Message (Traditional) Format....................................................................170
Direct Branch Message Format ...........................................................................................170
Resource Full Message Format............................................................................................170
Program Correlation Message Format .................................................................................171
Error Message Format..........................................................................................................171
Indirect Branch History w/ Sync. Message Format .............................................................172
Direct/Indirect Branch with Sync. Message Format (traditional)........................................172
Relative Address Generation and Re-creation .....................................................................174
Program Trace – Indirect Branch Message (Traditional) ....................................................175
Program Trace – Indirect Branch Message (History) ..........................................................176
Program Trace – Direct Branch (Traditional) and Error Messages .....................................176
Program Trace – Indirect Branch w/ Sync. Message (Traditional) .....................................176
Data Write Message Format ................................................................................................177
Data Read Message Format .................................................................................................177
Error Message Format..........................................................................................................178
Data Write/Read with Sync. Message Format .....................................................................178
Data Trace – Data Write Message .......................................................................................180
Data Trace – Data Read w/ Sync Message ..........................................................................180
Error Message (Data Trace only encoded) ..........................................................................181
Watchpoint Message Format ...............................................................................................183
Error Message Format..........................................................................................................183
Watchpoint Message & Watchpoint Error Message............................................................184
JTAG Data Register (DR)....................................................................................................185
Error Message Format..........................................................................................................189
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13-14
13-15
13-16
13-17
A7S Nexus3 DMA clock relationships................................................................................189
Debug Status Message Format.............................................................................................189
JTAG State Machine............................................................................................................190
DMA Block Diagram...........................................................................................................201
DMA Control Register (DMACR) ......................................................................................210
DMA Error Status (DMAES) Register ................................................................................211
DMA Enable Request (DMAERQH, DMAERQL) Register ..............................................213
DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) Registers......................................214
DMA Set Enable Request (DMASERQ) Register...............................................................215
DMA Clear Enable Request (DMACERQ) Register...........................................................216
DMA Set Enable Error Interrupt (DMASEEI) Register......................................................216
DMA Clear Enable Error Interrupt (DMACEEI) Register..................................................217
DMA Clear Interrupt Request (DMACINT) Register .........................................................217
DMA Clear Error (DMACERR) Register ...........................................................................218
DMA Set START Bit (DMASSRT) Register......................................................................219
DMA Clear DONE Status (DMACDNE) Register .............................................................219
DMA Interrupt Request (DMAINTH, DMAINTL) Registers ............................................220
DMA Error (DMAERRH, DMAERRL) Registers..............................................................222
DMA Channel n Priority (DCHPRIn) Register ...................................................................223
TCDn Word 0 (TCDn.saddr) Field......................................................................................224
TCDn Word 1 (TCDn.{soff,smod,ssize,dmod,dsize}) Fields .............................................225
TCDn Word 2 (TCDn.nbytes) Field ....................................................................................226
TCDn Word 3 (TCDn.slast) Field .......................................................................................227
TCDn Word 4 (TCDn.daddr) Field .....................................................................................227
TCDn Word 5 (TCDn.{citer,doff}) Fields ..........................................................................228
TCDn Word 6 (TCDn.dlast_sga) Field................................................................................229
TCDn Word 7 (TCDn.{biter,control/status}) Fields ...........................................................230
ipd_req removal ...................................................................................................................242
Processor Core Type (PCT) Register...................................................................................245
Revision (REV) Register .....................................................................................................246
AXBS Master Configuration (AMC) Register ....................................................................246
AXBS Slave Configuration (ASC) Register........................................................................247
IPS Module Configuration (IMC) Register .........................................................................248
Miscellaneous Reset Status (MRSR) Register.....................................................................248
Miscellaneous Wakeup Control (MWCR) Register ............................................................249
Miscellaneous Software Watchdog Timer Control (MSWTCR) Register ..........................251
Miscellaneous Software Watchdog Timer Service (MSWTSR) Register ...........................253
Miscellaneous Interrupt (MIR) Register ..............................................................................253
AXBS Address Map (AAMR) Register ..............................................................................254
Miscellaneous User-Defined Control (MUDCR) Register..................................................255
NMI Control (NMICR) Register .........................................................................................256
Non-Maskable Interrupt Operation Timing .........................................................................257
Peripheral Power Management Set (PPMRS) Register .......................................................258
Peripheral Power Management Clear (PPMRC) Register ...................................................258
Peripheral Power Management Set 1 (PPMRS1) Register ..................................................259
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Freescale Semiconductor
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15-1
16-1
16-2
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16-4
17-1
17-2
17-3
Peripheral Power Management Clear 1 (PPMRC1) Register ..............................................259
Peripheral Power Management Register High (PPMRH) ...................................................260
Peripheral Power Management Register Low (PPMRL).....................................................261
Peripheral Power Management Register 1 High (PPMR1H) ..............................................262
Peripheral Power Management Register 1 Low (PPMR1L)................................................262
ECC Configuration (ECR) Register.....................................................................................264
ECC Status (ESR) Register..................................................................................................265
ECC Error Generation (EEGR) Register .............................................................................267
Flash ECC Address (FEAR) Register..................................................................................270
Flash ECC Master Number (FEMR) Register .....................................................................270
Flash ECC Attributes (FEAT) Register ...............................................................................271
Flash ECC Data (FEDR) Register .......................................................................................272
Platform Flash ECC Data (PFEDR) Register ......................................................................272
RAM ECC Address (REAR) Register.................................................................................273
RAM ECC Syndrome (RESR) Register ..............................................................................273
RAM ECC Master Number (REMR) Register ....................................................................275
RAM ECC Attributes (REAT) Register ..............................................................................275
RAM ECC Data (REDR) Register ......................................................................................277
Core Fault Address (CFADR) Register ...............................................................................278
Core Fault Location 1 (CFLOC1) Register .........................................................................278
Core Fault Location (CFLOC) Register ..............................................................................279
Core Fault Attributes (CFATR) Register.............................................................................279
Core Fault Data (CFDTR) Register .....................................................................................281
INTC Block Diagram...........................................................................................................291
Interrupt Pending (IPRH, IPRL) Registers ..........................................................................295
Interrupt Mask (IMRH, IMRL) Registers............................................................................297
Force Interrupt (INTFRCH, INTFRCL) Registers ..............................................................298
Interrupt Configuration (ICONFIG) Register ......................................................................299
Set Interrupt Mask (SIMR) Register....................................................................................301
Clear Interrupt Mask (CIMR) Register................................................................................301
Current Level Mask (CLMASK) Register...........................................................................302
Saved Level Mask (SLMASK) Register..............................................................................303
Interrupt Control Register n (ICRn).....................................................................................304
IRQ Interrupt Acknowledge Register (IRQIACK)..............................................................305
FIQ Interrupt Acknowledge Register (FIQIACK)...............................................................306
Interrupt Service Routine and Masking (Not To Scale) ......................................................311
Crossbar Switch Bus Block Diagram ..................................................................................313
AIPS Interface Block Diagram ............................................................................................324
AIPS Memory Map..............................................................................................................325
Master Protection Registers (MPROT)................................................................................331
Peripheral Access Control Registers (PACR)......................................................................332
FlexBus Controller Conceptual Diagram
(Non-Muxed Implementation) .........................................................................................340
Chip-Select Address Registers (CSARn).............................................................................345
Chip-Select Mask Registers (CSMRn) ................................................................................346
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24-2
24-3
24-4
24-5
25-1
25-2
25-3
Chip-Select Control Registers (CSCRn)..............................................................................347
Connections for External Memory Port Sizes .....................................................................350
Data Transfer State Transition Diagram ..............................................................................351
MAC72x1 Flash Blocks and Partitions................................................................................359
MAC72x2 Flash Blocks and Partitions................................................................................360
Simplified Platform Block Diagram ....................................................................................379
Block Diagram: PRAM_CTL ..............................................................................................380
Block Diagram: 39-bit ECC Decode ...................................................................................386
64-bit Read Followed by Two 32-bit Reads ........................................................................388
32/64-bit writes with reads...................................................................................................389
Back to Back 32/64-bit Writes.............................................................................................390
Less than 32-bit writes .........................................................................................................391
Late Write Hits.....................................................................................................................393
Multiple-Bit Error on AHB Read Request...........................................................................394
BAM Sequence ....................................................................................................................400
VREG_HIP7A Block Diagram............................................................................................407
Block diagram of CRG ........................................................................................................414
PLL Loop Filter Connections ..............................................................................................416
CRG Synthesizer Register (SYNR) .....................................................................................418
CRG Reference Divider Register (REFDV)........................................................................418
CRG Flag Register 1 (CTFLG)............................................................................................419
CRG Flag Register 2 (CRGFLG) ........................................................................................420
CRG Interrupt Enable Register (CRGINT) .........................................................................421
CRG Clock Select Register (CLKSEL)...............................................................................422
CRG PLL Control Register (PLLCTL) ...............................................................................422
CRG DOZE Control Register (SDMCTL) ..........................................................................423
CRG BDM Control Register (BDMCTL) ...........................................................................424
PLL Functional Diagram .....................................................................................................425
System Clocks Generator.....................................................................................................427
System Clock and Peripheral Bus Clock Relationship ........................................................428
Check Window Example .....................................................................................................429
Sequence for Clock Quality Check......................................................................................429
Doze Mode Entry/Exit Sequence.........................................................................................432
RESET Timing.....................................................................................................................437
RESET Timing controlled by JTAG....................................................................................438
RESET Pin Tied to VDD (by a pull-up resistor) .................................................................439
RESET Pin Held Low Externally ........................................................................................439
OSC_ALC_HIP7A Block Diagram.....................................................................................444
ALC Oscillator Connections (XCLKS=1)...........................................................................445
External Clock Connections (XCLKS=0) ...........................................................................445
ALC Mode Clock Path.........................................................................................................448
External Clock Mode Clock Path ........................................................................................448
System Service Module Block Diagram..............................................................................449
Status (STATUS) Register...................................................................................................451
System Memory Configuration (MEMCONFIG) Register .................................................452
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Freescale Semiconductor
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29-5
29-6
29-7
29-8
29-9
Debug Status Port (DEBUGPORT) Register ......................................................................454
Error Configuration (ERROR) Register ..............................................................................455
System Reset (SYSRESET) Register ..................................................................................457
Block diagram of PIT...........................................................................................................462
PIT RTI Load Value Register (TLVAL0) ...........................................................................467
PIT Timer Load Value Registers (TLVAL1–10) ................................................................468
PIT Current RTI Value (TVAL0) ........................................................................................469
PIT CurrentTimer Values (TVAL1–10) ..............................................................................470
APIT Interrupt Flags Register (PITFLG) ............................................................................471
PIT Interrupt Enable Register (PITINTEN) ........................................................................472
PIT Interrupt/DMA Select Registers (PITINTSEL) ............................................................473
PIT Timer Enable Register (PITEN) ...................................................................................474
PIT Control Registers (PITCTRL).......................................................................................475
Stopping and Starting a Timer .............................................................................................476
Modifying Running Timer Period .......................................................................................476
Dynamically Setting a New Load Value .............................................................................477
DMA Channel Mux .............................................................................................................481
Channel Configuration Registers (CHCONFIGxx).............................................................484
DMA Mux Channel 0-7 Block Diagram .............................................................................487
DMA Mux Channel Triggering: Normal Operation............................................................487
DMA Mux Channel Triggering: Ignored Trigger................................................................488
DMA Mux Channel 8-15 Block Diagram ...........................................................................489
FlexCAN Block Diagram ....................................................................................................506
Message Buffer Structure ....................................................................................................512
Module Configuration Register (MCR)...............................................................................514
Control Register (CTRL) .....................................................................................................518
Free Running Timer (TIMER).............................................................................................521
Rx Global Mask Register (RXGMASK) .............................................................................521
Error Counter Register (ECR) .............................................................................................523
Error and Status Register (ESR) ..........................................................................................524
Interrupt Masks 1 Register (IMASK1) ................................................................................526
Interrupt Flags 1 Register (IFLAG1) ...................................................................................527
Rx Individual Mask Registers (RXIMR0–RXIMR63)........................................................528
CAN Engine Clocking Scheme ...........................................................................................535
Segments within the Bit Time..............................................................................................536
Arbitration, Match and Move Time Windows.....................................................................537
I2C Block Diagram ..............................................................................................................546
I2C Module DMA Interface Block Diagram .......................................................................547
Key to Register Fields..........................................................................................................550
I2C Bus Address Register (IBAD).......................................................................................550
I2C Bus Frequency Divider Register (IBFD).......................................................................550
SDA Hold Time ...................................................................................................................552
SCL Divider and SDA Hold ................................................................................................552
I2C Bus Control Register (IBCR) ........................................................................................557
I2C Bus Status Register(IBSR) ............................................................................................558
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31-10
31-11
31-12
I2C Bus Data I/O Register (IBDR) ......................................................................................559
I2C Bus Interrupt Config Register (IBIC)............................................................................560
I2C Bus Transmission Signals .............................................................................................561
Start and Stop conditions .....................................................................................................561
I2C Bus Clock Synchronization ...........................................................................................563
Flow-Chart of Typical I2C Interrupt Routine ......................................................................568
Flow-Chart of DMA Mode Master Transmit.......................................................................570
Flow-Chart of DMA Mode Master Receive ........................................................................571
DSPI Block Diagram ...........................................................................................................579
DSPI with Queues and DMA...............................................................................................580
DSPI Module Configuration Register (DSPI_MCR) ..........................................................584
DSPI Transfer Count Register (DSPI_TCR) .......................................................................586
DSPI Clock and Transfer Attributes Register 0–7 (DSPI_CTAR0–DSPI_CTAR7) ..........587
DSPI Status Register (DSPI_SR).........................................................................................593
DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER) .........................595
DSPI PUSH TX FIFO Register (DSPI_PUSHR) ................................................................596
DSPI POP RX FIFO Register (DSPI_POPR)......................................................................598
DSPI Transmit FIFO Register 0–3 (DSPI_TXFR0–DSPI_TXFR3) ...................................598
DSPI Receive FIFO Registers 0–3 (DSPI_RXFR0–DSPI_RXFR3....................................599
SPI Serial Protocol Overview ..............................................................................................600
DSPI Start and Stop State Diagram .....................................................................................602
Communications Clock Prescalers and Scalers ...................................................................605
Peripheral Chip Select Strobe Timing .................................................................................607
DSPI Transfer Timing Diagram (MTFE=0, CPHA=0, FMSZ=8) ......................................609
DSPI Transfer Timing Diagram (MTFE=0, CPHA=1, FMSZ=8) ......................................610
DSPI Modified Transfer Format (MTFE=1, CPHA=0, Fsck = Fsys/4) ..............................611
DSPI Modified Transfer Format (MTFE=1, CPHA=1, Fsck = Fsys/4) ..............................612
Example of Non-Continuous Format (CPHA=1, CONT=0) ...............................................613
Example of Continuous Transfer (CPHA=1, CONT=1) ....................................................613
Continuous SCK Timing Diagram (CONT=0)....................................................................614
Continuous SCK Timing Diagram (CONT=1)....................................................................615
Example of a DSPI in an SoC with a Power Management Block .......................................617
TX FIFO Pointers and Counter............................................................................................622
eSCI Block Diagram ............................................................................................................626
SCI Baud Rate Register High (SCIBDH)............................................................................634
SCI Baud Rate Register Low (SCIBDL) .............................................................................635
SCI Control Register 1 (SCICR1)........................................................................................635
SCI Control Register 2 (SCICR2)........................................................................................637
SCI Control Register 3 (SCICR3)........................................................................................638
SCI Control Register 4 (SCICR4)........................................................................................639
SCI Data Register High (SCIDRH) .....................................................................................639
SCI Data Register Low (SCIDRL) ......................................................................................640
SCI Status Register 1 (SCISR1) ..........................................................................................641
SCI Status Register 2 (SCISR2) ..........................................................................................642
LIN Status Register 1 (LINSTAT1) ....................................................................................642
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
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32-6
32-7
32-8
32-9
32-10
32-11
32-12
32-13
32-14
32-15
32-16
LIN Status Register 2 (LINSTAT2) ....................................................................................643
LIN Control Register 1 (LINCTRL1)..................................................................................644
LIN Control Register 2 (LINCTRL2)..................................................................................645
LIN Control Register 3 (LINCTRL3)..................................................................................646
LIN TX Register (LINTX)...................................................................................................647
LIN RX Register (LINRX) ..................................................................................................648
LIN CRC Polynomial Register 1 (LINCRCP1)...................................................................649
LIN CRC Polynomial Register 2 (LINCRCP2)...................................................................649
eSCI Block Diagram ............................................................................................................650
SCI Data Formats.................................................................................................................650
Transmitter Block Diagram .................................................................................................652
Fast Bit Error Detection on a LIN Bus ................................................................................655
Timing Diagram Fast Bit Error Detection ...........................................................................656
eSCI Receiver Block Diagram.............................................................................................657
Receiver Data Sampling ......................................................................................................658
Start Bit Search Example .....................................................................................................660
Start Bit Search Example 2 ..................................................................................................660
Start Bit Search Example 3 ..................................................................................................661
Start Bit Search Example 4 ..................................................................................................661
Start Bit Search Example 5 ..................................................................................................662
Start Bit Search Example 6 ..................................................................................................662
Slow Data.............................................................................................................................663
Fast Data ..............................................................................................................................664
Single-Wire Operation (LOOPS = 1, RSRC = 1) ................................................................666
Loop Operation (LOOPS = 1, RSRC = 0) ...........................................................................666
Typical LIN frame ...............................................................................................................672
DMA transfer of a TX frame ...............................................................................................673
DMA transfer of a RX frame ...............................................................................................674
LIN frame with CRC bytes ..................................................................................................674
eMIOS Block Diagram for MAC72x2 ................................................................................681
eMIOS Block Diagram for MAC72x1 ................................................................................682
eMIOS Module Configuration Register (MCR) .................................................................686
eMIOS Global FLAG Register (GFLAG) ..........................................................................688
eMIOS Output Update Disable Register (OUDIS)..............................................................688
eMIOS Enable Channel Register (UCDIS) .........................................................................689
eMIOS A Register (UCAn) ................................................................................................690
eMIOS B register (UCBn) ...................................................................................................690
eMIOS Counter Register (UCCNTn) ..................................................................................691
eMIOS Control Register (UCCRn) .....................................................................................692
eMIOS Status Register (UCSRn).........................................................................................697
eMIOS Alternate A register (ALTAn).................................................................................699
Unified Channel Block Diagram .........................................................................................700
Single Action Input Capture example..................................................................................701
SAOC example with EDPOL value being transferred to the output flip-flop ....................702
SAOC example toggling the output flip-flop.......................................................................702
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32-52
32-53
32-54
32-55
32-56
32-57
32-58
33-1
33-2
33-3
Input Pulse Width Measurement example ...........................................................................703
B1 and A1 updates at UCAn and UCBn reads ....................................................................703
Input Period Measurement example ....................................................................................704
A1 and B1 updates at UCAn and UCBn reads ....................................................................705
Double Action Output Compare with FLAG set on the second match ...............................706
Double Action Output Compare with FLAG set on both matches ......................................706
Pulse/Edge Accumulation continuous mode example .........................................................707
Pulse/Edge Accumulation single-shot mode example .........................................................708
Pulse/Edge Counting continuous mode example.................................................................709
Pulse/Edge Counting single-shot mode example.................................................................709
Quadrature Decode mode example with count & direction encoder...................................710
Quadrature Decode mode example with phase_a & phase_B encoder ...............................710
Windowed Programmable Time Accumulation example....................................................711
Modulus Counter up mode example ....................................................................................712
Modulus Counter up/down mode example ..........................................................................712
Modulus Counter Buffered (MCB) Up Count mode ...........................................................713
Modulus Counter Buffered (MCB) Up/Down Mode...........................................................714
MCB Mode A1 Register Update in Up Counter Mode .......................................................714
MCB Mode A1 Register Update in Up/Down Counter Mode ............................................715
OPWFM with immediate update .........................................................................................716
OPWFM with next period update ........................................................................................716
OPWFMB A1 and B1 match to Output Register Delay ......................................................717
OPWFMB Mode with A1 = 0 (0% duty cycle) ...................................................................718
OPWFMB A1 and B1 Registers Update and Flags .............................................................719
OPWFMB Mode with Active Output Disable.....................................................................719
OPWFMB Mode from 100% to 0% Duty Cycle .................................................................720
Output PWMC with leading dead time insertion.................................................................722
Output PWMC with trailing dead time insertion.................................................................722
OPWMCB A1 and B1 registers load ...................................................................................723
Output PWMCB with Lead Dead Time Insertion ...............................................................724
Output PWMCB with Trail Dead Time Insertion................................................................725
OPWMCB with 100% Duty Cycle (A1=4 and B1=3) ........................................................727
Output PWM with immediate update ..................................................................................728
Output PWM with next period update .................................................................................729
OPWMB Mode Matches and Flags .....................................................................................730
OPWMB Mode with 0% Duty Cycle ..................................................................................731
OPWMB Mode with Active Output Disable .......................................................................732
OPWMB Mode from 100% to 0% Duty Cycle ...................................................................732
lnput Programmable Filter submodule diagram ..................................................................733
Input Programmable filter example .....................................................................................733
Time base period when running in the fastest pre scaler ratio.............................................735
Time base period when running with a pre scaler ratio greater than 1 ................................736
DMADC1032 Block Diagram .............................................................................................742
ATD Trigger Control Register (ATDTRIGCTL) ................................................................747
ATD External Trigger Channel Register (ATDETRIGCH) ................................................748
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
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33-37
34-1
34-2
34-3
34-4
34-5
34-6
34-7
34-8
34-9
34-10
34-11
ATD Prescaler Register (ATDPRE) ....................................................................................749
ATD Operating Modes Register (ATDMODE) ..................................................................750
32ATD Calibration Register (ATDCAL) ............................................................................751
ATD Predischarge Time Select Register (ATDPTS) ..........................................................753
ATD Interrupt Register (ATDINT) .....................................................................................753
ATD Flag Register (ATDFLAG).........................................................................................754
ATD Command Word Register (ATDCW) .........................................................................756
RRCR for Right Justified Unsigned ....................................................................................758
RRCR for Right Justified Signed.........................................................................................759
RRCR for Left Justified Unsigned.......................................................................................759
RRCR for Left Justified Signed 8/10 Bit.............................................................................759
ATD Result Register (ATDRR)...........................................................................................761
ATD Command Queue / Result Register.............................................................................766
Flow Diagram for Command Processing.............................................................................768
Flow Diagram for Result Saving/Command Fetching.........................................................769
Command vs. Result Timing ...............................................................................................769
Various Conversion Phases..................................................................................................770
Predischarge Circuit.............................................................................................................773
Predischarge Timing ............................................................................................................773
Gain Error (Gain Too High) Compensated via GCC and OCC...........................................776
Gain Error (Gain Too High) Compensated via Warp ..........................................................777
Gain Error (Gain Too Low) Compensated via GCC ...........................................................778
Offset Error Compensated via OCC ....................................................................................779
Conversion Procedure for Example 1 ..................................................................................783
Conversion Procedure for Example 2 ..................................................................................785
Conversion Procedure for Example 3 ..................................................................................786
Conversion Procedure for Example 4 ..................................................................................787
ATD Edge-Based Trigger Example.....................................................................................787
Conversion Procedure for Example 4 ..................................................................................788
ATD Level-Based Minimum Trigger ..................................................................................788
Conversion Procedure for Example 6 ..................................................................................789
Conversion Procedure for Example 7 ..................................................................................790
Conversion Procedure for Example 8 (part 1) .....................................................................790
Conversion Procedure for Example 8 (part 2) .....................................................................791
Port Integration Module Block Diagram .............................................................................797
PIM Peripheral Muxing .......................................................................................................807
Pin Configuration Register (CONFIGxx, Port A, B, C, D, F, G) ........................................817
Pin Configuration Register (CONFIGxx, Port E) ................................................................819
Port Wide Interrupt Flag Register (PORTIFR)....................................................................820
Port Wide Data Register (PORTDATA, Port A, B, C, D, F, G) .........................................820
Port Wide Data Register (PORTDATA Port E) ..................................................................821
Port Wide Input Register (PORTIR, Port A, B, C, D, F, G)................................................822
Port Wide Input Register (PORTIR, Port E) .......................................................................823
Pin Data Register (PINDATAxx, Port A, B, C, D, F, G).....................................................823
Pin Data Register (PINDATAxx, Port E) ............................................................................824
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A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
A-11
A-12
A-13
A-14
A-15
Global Interrupt Status Register (GLBLINT)......................................................................825
PIM Configuration Register (PICONFIG)...........................................................................825
Pin Configuration Register (CONFIG_TDI) .......................................................................826
Pin Configuration Register (CONFIG_TDO)......................................................................827
Pin Configuration Register (CONFIG_TMS)......................................................................828
Pin Configuration Register (CONFIG_TCK)......................................................................829
Pin Configuration Register (CONFIG_RESET)..................................................................830
Pad in Peripheral Mode (including pad PD2) ......................................................................833
Pad in GPI Mode (including pad PD2) ................................................................................836
External Interrupt Timing Requirements .............................................................................838
Pad in GPO Mode (except pad PD2) ...................................................................................839
Pad PD2 in GPO Mode ........................................................................................................840
I/O Pad Control (Overview).................................................................................................841
I/O Pad Control (Detailed View) .........................................................................................842
PIM Peripheral Muxing .......................................................................................................843
I/O Pad Control Cell Architecture (in PIM core).................................................................844
Basic PLL Functional Diagram ...........................................................................................871
General Purpose Input Timing Specifications .....................................................................874
General Purpose Output Timing Specifications ..................................................................875
Nexus Output Timing Specifications...................................................................................876
JTAG Port Timing Specifications........................................................................................877
SPI Master Timing (CPHA = 0) ..........................................................................................878
SPI Master Timing (CPHA = 1) ..........................................................................................879
SPI Slave Timing (CPHA = 0).............................................................................................880
SPI Slave Timing (CPHA = 1).............................................................................................880
External Bus Input Timing Specifications...........................................................................881
Read/Write (Internally Terminated) Bus Timing ................................................................883
Read Bus Cycle Terminated by TA .....................................................................................884
ATD Accuracy Definitions ..................................................................................................888
ATD External Trigger Timing Diagram ..............................................................................890
I2C Input/Output Timings ....................................................................................................891
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Freescale Semiconductor
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Tables
Table
Number
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3-4
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4-2
5-1
5-2
5-3
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7-1
7-2
7-3
8-1
8-2
8-3
9-1
9-2
9-3
9-4
9-5
Title
Page
Number
Conventions ........................................................................................................................ lxvi
Terminology....................................................................................................................... lxvii
Register Diagram Conventions ......................................................................................... lxxiii
Register Field Description Conventions ........................................................................... lxxiv
EXREG Field Descriptions............................................................................................... lxxiv
List of MAC72xx Devices .......................................................................................................7
Typical System Access Summary............................................................................................9
Chip Mode Encodings............................................................................................................10
System Memory Maps ...........................................................................................................14
MCU Mode Selection Signals ...............................................................................................17
MCU Mode Selection ............................................................................................................18
Oscillator Type Selection.......................................................................................................20
Nexus Port Selection..............................................................................................................21
Nexus Hardware Configuration .............................................................................................21
External Bus Configuration ...................................................................................................21
Low Power Modes .................................................................................................................23
Wakeup Sources.....................................................................................................................25
Low Power Mode Entry Summary ........................................................................................26
Low Power Mode Exit Summary ..........................................................................................26
Signal Properties ....................................................................................................................33
MAC72xx Power and Ground Connection Summary ...........................................................56
Clocks Summary....................................................................................................................59
Clock Source Selection ..........................................................................................................63
Module Clock Usage Overview.............................................................................................68
System Reset Sources ............................................................................................................73
ARM Exception Table ...........................................................................................................79
Interrupt Sources ....................................................................................................................82
ARM7 Core Exception ..........................................................................................................86
JTAG Test Logic Selection....................................................................................................92
Debug External Pins ..............................................................................................................97
ARM7TDMI-S Debug State Overview .................................................................................99
Device Memory Map in Normal Single Chip Mode (After Reset) .....................................106
Allowed Memory Maps in Normal Single Chip Mode .......................................................106
Device Memory Map in Normal/Secured Primary Bootloader Mode (After Reset)...........107
Allowed Memory Maps in Normal Primary Bootloader Mode...........................................108
Device Memory Map in Normal Expanded Mode (After Reset) ........................................108
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11-22
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11-24
11-25
11-26
11-27
11-28
Allowed Memory Maps in Normal Expanded Mode ..........................................................109
Device Memory Map in Secured Single Chip Mode (After Reset).....................................110
Allowed Memory Maps in Secured Single Chip Mode.......................................................110
Device Memory Map in Secured Expanded Mode (After Reset)........................................111
Allowed Memory Maps in Secured Expanded Mode..........................................................111
Peripheral Bus Memory Map...............................................................................................113
SRAM Memory Map ...........................................................................................................114
FlexBus Memory Map .........................................................................................................115
MAC72x1 Flash Main Array Memory Map .......................................................................116
MAC72x2 Flash Main Array Memory Map .......................................................................117
Shadow Block Memory Map ...............................................................................................117
Boot Assist Module (BAM) Memory Map..........................................................................118
Exception Table Memory Map ............................................................................................118
Possible Memory Map Configurations ................................................................................119
AXBS Slave Port Definitions ..............................................................................................121
..............................................................................................................................................122
..............................................................................................................................................122
Public TCODEs Supported ..................................................................................................132
Error Code Encoding (TCODE = 8) ....................................................................................134
Watchpoint Source Encoding (TCODE = 15) .....................................................................134
Resource Code Encoding (TCODE = 27)............................................................................135
Event Code Encoding (TCODE = 33) .................................................................................135
Data Trace Size (DSZ) Encodings (TCODE = 5, 6, 13, 14)................................................135
Nexus Port Assignments ......................................................................................................136
JTAG TAP Controller IR Register Encodings.....................................................................136
Nexus LPS Encodings..........................................................................................................137
FlexBus Port Sizing with Nexus ..........................................................................................138
Nexus External Pins .............................................................................................................139
Nexus Configuration............................................................................................................140
JTAG Pins for A7S Nexus3 .................................................................................................143
A7S Nexus3 Auxiliary Pins .................................................................................................144
MSEO Pin(s) Protocol .........................................................................................................145
Indirect Branch Message Example (2 MDO / 1 MSEO) .....................................................147
Indirect Branch Message Example (8 MDO / 2 MSEO) .....................................................147
Direct Branch Message Example (2 MDO / 1 MSEO)........................................................148
Direct Branch Message Example (8 MDO / 2 MSEO)........................................................148
JTAG ID Field Descriptions ................................................................................................149
A7S Nexus3 Register Map...................................................................................................150
Client Select Register Field Description..............................................................................151
DC Field Descriptions..........................................................................................................152
DS Field Descriptions ..........................................................................................................153
RWCS Field Descriptions....................................................................................................155
Read/Write Access Status Bit Encoding..............................................................................155
WT Field Descriptions .........................................................................................................157
DTC Field Description.........................................................................................................158
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12-16
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12-18
12-19
12-20
12-21
12-22
12-23
12-24
12-25
Data Trace – Address Range Options ..................................................................................159
BWC1, BWC2 Field Description ........................................................................................160
BWC3-6 Field Description ..................................................................................................161
BWAM Field Description....................................................................................................162
BWDM Field Description....................................................................................................163
PCR Field Description .........................................................................................................164
ARM7 JTAG Instructions....................................................................................................164
JTAG DR Field Description for Nexus Register Access.....................................................165
Indirect Branch / Branch History Message Instructions ......................................................168
Direct Branch Message Instructions ....................................................................................168
Program Trace Exception Summary....................................................................................173
Data Trace Exception Summary ..........................................................................................179
ARM7 Bus Cycle Cases.......................................................................................................180
Internal Data Watchpoint Configuration Examples.............................................................182
Watchpoint Source Description ...........................................................................................183
JTAG Nexus3 Register Select .............................................................................................184
JTAG Data Register Field Description ................................................................................185
JTAG Sequence for Accessing Internal Nexus Registers....................................................191
JTAG Sequence for Read Access of Memory-Mapped Resources .....................................191
JTAG Sequence for Write Access of Memory-Mapped Resources ....................................191
DMA Channel Sources ........................................................................................................194
eDMA Bus Abort Memory Map..........................................................................................195
DMA Register Summary .....................................................................................................200
DMA 32-bit Memory Map...................................................................................................208
DMACR Field Descriptions ................................................................................................210
DMAES Field Descriptions .................................................................................................211
DMAERQH, DMAERQL field Descriptions ......................................................................213
DMAEEIH, DMAEEIL Field Descriptions.........................................................................215
DMASERQ Field Descriptions............................................................................................215
DMACERQ Field Descriptions ...........................................................................................216
DMASEEI Field Descriptions .............................................................................................216
DMACEEI Field Descriptions .............................................................................................217
DMACINT Field Descriptions ............................................................................................218
DMACERR Field Descriptions ...........................................................................................218
DMASSRT Field Descriptions ............................................................................................219
DMACDNE Field Descriptions ...........................................................................................219
DMAINTH, DMAINTL Field Descriptions........................................................................221
DMAERRH, DMAERRL Field Descriptions......................................................................222
DCHPRIn Field Descriptions ..............................................................................................223
TCDn 32-bit Memory Structure...........................................................................................223
TCDn Word 0 (TCDn.saddr) Field Description ..................................................................224
TCDn Word 1 (TCDn.{smod,ssize,dmod,dsize,soff}) Field Descriptions..........................225
TCDn Word 2 (TCDn.nbytes) Field Description ................................................................226
TCDn Word 3 (TCDn.slast) Field Descriptions ..................................................................227
TCDn Word 4 (TCDn.daddr) Field Descriptions ................................................................228
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13-33
13-34
13-35
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13-37
13-38
13-39
13-40
TCDn Word 5 (TCDn.{doff,citer}) Field Descriptions.......................................................228
TCDn Word 6 (TCDn.dlast_sga) Field Descriptions ..........................................................229
TCDn Word 7 (TCDn.{biter, control/status}) Field Descriptions.......................................230
DMA Peak Transfer Rates [MBytes/sec] ............................................................................232
DMA Peak Request Rate [MReq/sec] .................................................................................234
MCM 32-bit Memory Map ..................................................................................................244
PCT Field Descriptions........................................................................................................245
REV Field Descriptions .......................................................................................................246
AMC Field Descriptions ......................................................................................................246
ASC Field Descriptions .......................................................................................................247
IPS IMC Field Descriptions.................................................................................................248
MRSR Field Descriptions ....................................................................................................248
MWCR Field Descriptions ..................................................................................................250
MSWTCR Field Definitions ................................................................................................252
MIR Field Descriptions........................................................................................................253
AAMR Field Descriptions ...................................................................................................255
MUDCR Field Descriptions ................................................................................................255
NMICR Field Descriptions ..................................................................................................256
Peripheral Power Management Set (PPMRS) Field Descriptions .......................................258
Peripheral Power Management Clear (PPMRC) Field Descriptions ...................................258
Peripheral Power Management Set 1 (PPMRS1) Field Descriptions ..................................259
Peripheral Power Management Clear 1 (PPMRC1) Field Descriptions ..............................260
Peripheral Power Management (PPMRH, PPMRL) Field Description...............................261
Peripheral Power Management (PPMR1H, PPMR1L) Field Description...........................262
ECR Field Descriptions .......................................................................................................264
ESR Field Descriptions........................................................................................................266
EEGR Field Descriptions.....................................................................................................267
FEAR Field Descriptions .....................................................................................................270
PFEMR Field Descriptions ..................................................................................................270
PFEAT Field Descriptions ...................................................................................................271
FEDR Field Descriptions .....................................................................................................272
REAR Field Descriptions ....................................................................................................273
RESR Field Descriptions .....................................................................................................274
RAM Syndrome Mapping for Single-Bit Correctable Errors..............................................274
REMR Field Descriptions....................................................................................................275
REAT Field Descriptions.....................................................................................................276
REDR Field Descriptions ...................................................................................................277
CFADR Field Descriptions..................................................................................................278
Core Fault Location 1 (CFLOC1) Field Descriptions .........................................................278
CFLOC Field Descriptions ..................................................................................................279
CFATR Field Descriptions ..................................................................................................280
CFDTR Field Descriptions ..................................................................................................281
AAMR Register Configurability..........................................................................................282
Processor Core Type (PCT) Values .....................................................................................282
MAC72xx PCT and REV registers......................................................................................283
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MCM Bus Aborts.................................................................................................................284
INTC Signals .......................................................................................................................288
INTC Bus Aborts .................................................................................................................288
INTC MAC71x1 versus MAC72xx Interrupt Source Assignment......................................289
ARM Interrupt Exception Summary....................................................................................292
INTC 32-bit Memory Map...................................................................................................293
Multiple Interrupt Controller IPS Memory Map .................................................................294
Interrupt Pending (IPRH, IPRL) Field Descriptions............................................................296
Interrupt Mask (IMRH, IMRL) Field Descriptions .............................................................297
Force Interrupt (INTFRCH, INTFRCL) Field Descriptions................................................298
Interrupt Configuration (ICONFIG) Field Descriptions......................................................299
Set Interrupt Mask (SIMR) Field Descriptions....................................................................301
Clear Interrupt Mask (CIMR) Field Descriptions................................................................302
Current Level Mask (CLMASK) Field Descriptions...........................................................303
Saved Level Mask (SLMASK) Field Descriptions .............................................................304
Interrupt Control Register n (ICRn) Field Descriptions ......................................................304
IRQ Interrupt Acknowledge Register (IRQIACK) Field Descriptions ...............................305
FIQ Interrupt Acknowledge Register (FIQIACK) Field Descriptions ................................306
Global IACK Steering Algorithm (3 Controllers) ...............................................................309
Crossbar Slave Port Addresses ............................................................................................314
MAC72xx AXBS Master and Slave Ports...........................................................................315
Module Memory Map ..........................................................................................................316
Priority Register Summary ..................................................................................................316
Priority Register Descriptions..............................................................................................317
Control Register Summary ..................................................................................................318
Control Register Descriptions..............................................................................................318
AXBS Bus Aborts................................................................................................................321
AIPS 32-bit byte lanes .........................................................................................................326
AIPS Register Memory Map ...............................................................................................330
MAC7200 Peripheral to Access Control Register Map.......................................................330
MPROT Field Descriptions .................................................................................................332
PACR Field Descriptions.....................................................................................................332
AIPS Bus Aborts..................................................................................................................335
MAC71x1 versus MAC72xx AIPS PACR Assignment......................................................336
External Bus Auto Acknowledge Configuration .................................................................340
External Bus Port Size Configuration..................................................................................340
FlexBus Signal Summary ....................................................................................................341
Chip-Select Registers...........................................................................................................344
CSARn Field Descriptions...................................................................................................345
CSMRn Field Descriptions ..................................................................................................346
CSCRn Field Descriptions...................................................................................................347
Bus Cycle States .................................................................................................................351
FlexBus Bus Aborts .............................................................................................................352
MAC71x1 to MAC72xx External Bus mapping .................................................................352
Global Chip Select Mode Configuration .............................................................................353
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PFLASH Bus Aborts............................................................................................................361
Flash Terminology ...............................................................................................................362
Flash Block IPI User Registers ............................................................................................363
Flash PFCR1 Register Settings............................................................................................365
Flash Controller APC and RWSC Settings..........................................................................366
MCM Block Flash Registers................................................................................................368
Flash Shadow Block Access Protection Types ....................................................................368
Flash Shadow Block Access Protection Address Ranges....................................................369
Flash Shadow Block Access Protection Types ....................................................................369
Flash Main Array Access Protection ...................................................................................370
Flash Program/Erase Blocks - MAC72x2............................................................................372
Flash Program/Erase Blocks - MAC72x1............................................................................373
System Censor Word Definition..........................................................................................374
SRAM Address Mirroring ...................................................................................................378
Signal Width Variables ........................................................................................................381
Signal Properties ..................................................................................................................381
Signal Property Details ........................................................................................................383
pram_cs_b 64 Bit Behavior .................................................................................................384
Parity vs. Syndrome .............................................................................................................386
Unaligned Writes .................................................................................................................391
Late Write Hit Cases ............................................................................................................392
Parity Codes: ECC Bits vs. Data Bits ..................................................................................397
Hamming Parity Delay ........................................................................................................397
Modified Parity Codes: ECC Bits vs. Data Bits ..................................................................398
VREG_HIP7A - Signal Properties.......................................................................................408
VREG_HIP7A - Reset Sources ...........................................................................................410
Signal Properties ..................................................................................................................415
CRG Memory Map ..............................................................................................................417
CTFLG Field Descriptions ..................................................................................................419
CRGFLG Field Descriptions ...............................................................................................420
CRGINT Field Descriptions ................................................................................................421
CLKSEL Field Descriptions ................................................................................................422
PLLCTL Field Descriptions ................................................................................................423
SDMCTL Field Descriptions ...............................................................................................424
BDMCTL Field Descriptions ..............................................................................................424
MCU Configuration During Doze Mode .............................................................................431
Outcome of Clock Loss in Doze Mode................................................................................433
Entering CRG Modes...........................................................................................................435
Reset Summary ....................................................................................................................435
Reset Vector Selection.........................................................................................................436
CRG Interrupt Vectors .........................................................................................................440
CRG Bus Aborts ..................................................................................................................440
Clock Selection Based on XCLKS ......................................................................................446
Oscillator Modes..................................................................................................................447
Module Memory Map ..........................................................................................................450
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28-12
STATUS Allowed Register Accesses..................................................................................451
STATUS Field Descriptions ................................................................................................451
MEMCONFIG Field Descriptions.......................................................................................453
MEMCONFIG Allowed Register Accesses ........................................................................453
DEBUGPORT Field Descriptions .......................................................................................454
Debug Status Port Modes.....................................................................................................454
DEBUGPORT Allowed Register Accesses.........................................................................455
ERROR Field Descriptions..................................................................................................456
ERROR Allowed Register Accesses ...................................................................................456
SYSRESET Field Descriptions............................................................................................457
SYSRESET Allowed Register Accesses .............................................................................457
SSM Bus Aborts ..................................................................................................................459
PIT Timer Usage..................................................................................................................463
PIT Bus Aborts ....................................................................................................................464
PIT Interrupt Sources ...........................................................................................................464
PIT_RTI Memory Map ........................................................................................................465
TLVAL0 Field Descriptions ................................................................................................467
TLVAL1–10 Field Descriptions ..........................................................................................468
TVAL0 Field Descriptions ..................................................................................................469
TVAL1–10 Field Descriptions ............................................................................................470
PITFLG Field Desciptions ...................................................................................................471
PITINTEN Field Descriptions .............................................................................................472
PITINTSEL Field Descriptions ...........................................................................................473
PITEN Field Descriptions....................................................................................................474
PITCTRL Field Descriptions ...............................................................................................475
PIT Interrupt Vectors ...........................................................................................................477
DMA Request Sources.........................................................................................................481
Module Memory Map ..........................................................................................................483
CHCONFIGxx Field Descriptions.......................................................................................484
Channel and Trigger Enabling .............................................................................................484
SOURCE Configuration ......................................................................................................484
DMA Channel Mux Bus Aborts ..........................................................................................490
MAC71xx versus MAC72xx DMA Channel Mux Assignment..........................................490
CAN External Pins...............................................................................................................503
FlexCAN Memory Map .......................................................................................................504
FlexCAN Signals .................................................................................................................509
Module Memory Map ..........................................................................................................510
Message Buffer MB0 Memory Mapping.............................................................................511
Message Buffer Field Descriptions......................................................................................512
Message Buffer Code for Rx buffers ...................................................................................513
Message Buffer Code for Tx buffers ...................................................................................513
MCR Field Descriptions ......................................................................................................515
CTRL Field Descriptions .....................................................................................................518
RXGMASK Field Descriptions ...........................................................................................522
ESR Field Descriptions........................................................................................................524
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IMASK1 Field Descriptions ................................................................................................526
IFLAG1 Field Descriptions .................................................................................................527
RXIMRn Field Descriptions ................................................................................................528
Time Segment Syntax ..........................................................................................................536
CAN Standard Compliant Bit Time Segment Settings........................................................536
Minimum Ratio Between Peripheral Clock Frequency and CAN Bit Rate.........................537
Wake-up from Doze Mode ..................................................................................................539
Wake-up from Stop Mode ...................................................................................................540
Module Memory Map ..........................................................................................................549
IBAD Field Descriptions .....................................................................................................550
IBFD Field Descriptions ......................................................................................................551
I-Bus Multiplier Factor ........................................................................................................551
I-Bus Prescaler Divider Values............................................................................................551
I-Bus Tap and Prescale Values ............................................................................................551
I2C Divider and Hold Values...............................................................................................554
IBCR Field Descriptions......................................................................................................557
IBSR Field Descriptions ......................................................................................................558
IBIC Field Descriptions .......................................................................................................560
Interrupt Summary ...............................................................................................................564
CPOL and CPHA Control Bits ............................................................................................576
DSPI External Pins ..............................................................................................................577
DSPI Bus Aborts..................................................................................................................577
DSPI Maximum Baud Rate Parameters...............................................................................578
DSPI SCK Duty Cycle Calculation .....................................................................................578
Signal Properties ..................................................................................................................581
DSPI Memory Map..............................................................................................................583
DSPI_MCR Field Descriptions............................................................................................584
DSPI_TCR Field Descriptions.............................................................................................587
DSPI_CTARn Field Descriptions........................................................................................588
DSPI SCK Duty Cycle.........................................................................................................590
DSPI Transfer Frame Size ..................................................................................................591
DSPI PCS to SCK Delay Scaler .........................................................................................591
DSPI After SCK Delay Scaler ............................................................................................591
DSPI Delay after Transfer Scaler ......................................................................................592
DSPI Baud Rate Scaler .......................................................................................................592
DSPI_SR Field Descriptions................................................................................................593
DSPI_RSER Field Descriptions ..........................................................................................595
DSPI_PUSHR Field Descriptions........................................................................................597
DSPI_POPR Field Descriptions ..........................................................................................598
DSPI_TXFRn Field Descriptions ........................................................................................599
DSPI_RXFRn Field Descriptions ........................................................................................599
State Transitions for Start and Stop of DSPI Transfers .......................................................602
Baud Rate Computation Example........................................................................................606
PCS to SCK Delay Computation Example..........................................................................606
After SCK Delay Computation Example.............................................................................606
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Delay after Transfer Computation Example ........................................................................607
Peripheral Chip Select Strobe Assert Computation Example..............................................607
Peripheral Chip Select Strobe Negate Computation Example.............................................607
Interrupt and DMA Request Conditions ..............................................................................615
Baud Rate Values.................................................................................................................619
Delay Values........................................................................................................................620
Oak Family QSPI Compatibility with the DSPI ..................................................................621
eSCI External Pins ...............................................................................................................630
eSCI Bus Aborts ..................................................................................................................630
eSCI Memory Map ..............................................................................................................631
eSCI Register Quick Reference ...........................................................................................632
SCI BDH/L Field Descriptions ............................................................................................635
SCICR1 Field Descriptions..................................................................................................635
SCICR2 Field Descriptions..................................................................................................637
SCICR3 Field Descriptions..................................................................................................638
SCICR4 Field Descriptions..................................................................................................639
SCIDRH/L Field Descriptions .............................................................................................640
SCISR1 Field Descriptions ..................................................................................................641
SCISR2 Field Descriptions ..................................................................................................642
LINSTAT1 Field Descriptions ............................................................................................642
LINSTAT2 Field Descriptions ............................................................................................643
LINCTRL1 Field Descriptions ............................................................................................644
LINCTRL2 Field Descriptions ............................................................................................645
LINCTRL3 Field Descriptions ............................................................................................646
LINTX Field Descriptions ...................................................................................................647
LINRX Field Descriptions ...................................................................................................648
LINCRCP1–2 Field Descriptions ........................................................................................649
Example of 8-bit Data Formats............................................................................................651
Example of 9-Bit Data Formats ...........................................................................................651
Baud Rates (Example: Module Clock = 10.2 Mhz).............................................................651
Start Bit Verification............................................................................................................658
Data Bit Recovery................................................................................................................659
Stop Bit Recovery ................................................................................................................659
eSCI Interrupt Flags and Mask Bits.....................................................................................667
eSCI Interrupt Sources .........................................................................................................668
eMIOS External Pins ...........................................................................................................679
eMIOS Bus Aborts...............................................................................................................679
External signals....................................................................................................................684
eMIOS Memory Map...........................................................................................................684
UC Memory Map .................................................................................................................685
MCR Field Descriptions ......................................................................................................686
Global Prescaler Clock Divider ...........................................................................................687
OUDIS Field Descriptions ...................................................................................................688
OUDIS Field Descriptions ...................................................................................................689
UCAn, UCBn and ALTAn values assignment ....................................................................690
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UCCRn Field Descriptions ..................................................................................................692
ODISSL Selection................................................................................................................693
UC Internal Prescaler Clock Divider ...................................................................................693
Input Filter Bits ....................................................................................................................694
BSL Bits...............................................................................................................................695
MODE Bits ..........................................................................................................................696
UCSRn Field Descriptions...................................................................................................697
ATD External Pins ...............................................................................................................738
ATD Bus Aborts ..................................................................................................................739
DMADC1032 Signals..........................................................................................................743
Module Memory Map ..........................................................................................................745
ATDTRIGCTL Field Descriptions ......................................................................................747
Trigger Sensitivity Selection Table .....................................................................................747
ATDETRIGCH Field Descriptions......................................................................................748
ATDPRE Field Descriptions................................................................................................749
Selection Table for System Clock Divider ..........................................................................749
ATDMODE Field Descriptions ...........................................................................................750
ATDCAL Field Descriptions ...............................................................................................752
ATDPTS Field Descriptions ................................................................................................753
ATDINT Field Descriptions ................................................................................................754
ATDFLAG Field Descriptions ............................................................................................755
ATDCW Field Descriptions ................................................................................................756
Conversion Mode Selection Table.......................................................................................757
Numeric Examples for Result Values..................................................................................760
Channel Selection Table ......................................................................................................760
Conversion Start Behavior ...................................................................................................767
Conversion Continue Behavior............................................................................................767
Command Word #1 to Determine Gain and Offset .............................................................780
Bit Description of the Command Word ...............................................................................791
ATD Interrupt Vectors .........................................................................................................793
Port Pin and Peripheral Allocation ......................................................................................795
Expanded Mode Startup Pin Configuration.........................................................................796
PIM Peripheral Mode Configuration ...................................................................................798
PIM GPIO Mode Configuration ..........................................................................................799
PIM GPIO Input Mode Configuration.................................................................................799
Port Pin to Primary Peripheral Function Assignments ........................................................800
JTAG Pin Functions (Peripheral Mode) ..............................................................................803
PIM Bus Aborts ...................................................................................................................805
PIM Registers.......................................................................................................................806
Port Integration Module Memory Map Overview ...............................................................808
Port Integration Module Memory Map................................................................................809
CONFIGxx (Port A, B, C, D, F, G) Field Descriptions .......................................................817
CONFIGxx (Port A, B, C, D, F, G) Allowed Register Accesses.........................................818
CONFIGxx (Port E) Field Descriptions ...............................................................................819
CONFIGxx (Port E) Allowed Register Accesses.................................................................819
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A-3
A-4
PORTIFR Field Descriptions...............................................................................................820
PORTIFR Allowed Register Accesses ................................................................................820
PORTDATA (Port A, B, C, D, F, G) Field Descriptions ....................................................821
PORTDATA (Port A, B, C, D, F, G) Allowed Register Accesses ......................................821
PORTDATA (Port E) Field Descriptions ............................................................................821
PORTDATA (Port E) Allowed Register Accesses..............................................................822
PORTIR (Port A, B, C, D, F, G) Field Descriptions ...........................................................822
PORTIR (Port A, B, C, D, F, G) Allowed Register Accesses .............................................822
PORTIR (Port E) Field Descriptions ...................................................................................823
PORTIR (Port E) Allowed Register Accesses.....................................................................823
PINDATAxx (Port A, B, C, D, F, G) Field Descriptions ....................................................823
PINDATAxx (Port A, B, C, D, F, G) Allowed Register Accesses ......................................824
PINDATAxx (Port E) Field Descriptions ............................................................................824
PINDATAxx (Port E) Allowed Register Accesses ..............................................................824
GLBLINT Field Descriptions ..............................................................................................825
GLBLINT Allowed Register Accesses................................................................................825
PIMCONFIG Field Descriptions .........................................................................................826
PIMCONFIG Allowed Register Accesses...........................................................................826
CONFIG_TDI Field Descriptions........................................................................................826
CONFIG_TDI Allowed Register Accesses .........................................................................827
CONFIG_TDO Field Descriptions ......................................................................................827
CONFIG_TDO Allowed Register Accesses........................................................................828
CONFIG_TMS Field Descriptions ......................................................................................828
CONFIG_TMS Allowed Register Accesses........................................................................828
CONFIG_TCK Field Descriptions ......................................................................................829
CONFIG_TCK Allowed Register Accesses ........................................................................829
CONFIG_RESET Field Descriptions ..................................................................................830
CONFIG_RESET Allowed Register Accesses....................................................................830
Double Port Wide Input Registers (DPORTIR) ..................................................................830
DPORTIR Allowed Register Accesses................................................................................831
PIM Register Behavior in Peripheral Mode.........................................................................832
MODE[1:0] Values ..............................................................................................................834
Peripheral Pins that can be Multiplexed ..............................................................................834
Input Multiplexing Priority ..................................................................................................834
PIM Register Behavior in GPI Mode...................................................................................836
Interrupt Polarity Configuration ..........................................................................................837
Input Glitch Filter Requirements .........................................................................................838
PIM Register Behavior in GPO Mode .................................................................................839
SC4 Test Register Field Definitions ....................................................................................855
SC4 Test Register Field Descriptions ..................................................................................856
Test Controller External Pins...............................................................................................857
Parametric Value Classification...........................................................................................859
Absolute Maximum Ratings ................................................................................................859
ESD and Latch-up Test Conditions .....................................................................................860
ESD and Latch-Up Protection Characteristics.....................................................................861
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A-33
A-34
A-35
A-36
A-37
MAC7200 Family Device Operating Conditions ................................................................861
5V I/O Characteristics..........................................................................................................862
Oscillator Characteristics .....................................................................................................863
Thermal Resistance for 100 lead 14x14 mm LQFP, 0.5 mm Pitch .....................................864
Thermal Resistance for 144 lead 20x20 mm LQFP, 0.5 mm Pitch .....................................865
Power Dissipation 1/8 Simulation Model Packaging Parameters........................................866
Supply Current Characteristics ............................................................................................867
VREG Operating Conditions ...............................................................................................868
VREG Recommended Load Capacitances ..........................................................................869
Oscillator Characteristics .....................................................................................................870
PLL Characteristics..............................................................................................................872
Crystal Monitor Characteristics ...........................................................................................873
Clock Quality Checker Characteristics ................................................................................873
System Reset Characteristics ...............................................................................................873
General Purpose Input Timing Specifications .....................................................................874
General Purpose Output Timing Specifications ..................................................................874
Nexus Input Timing Specifications .....................................................................................875
Nexus Output Timing Specifications...................................................................................876
External Interrupt Characteristics ........................................................................................876
JTAG Port Timing ...............................................................................................................876
SPI Master Mode Timing Characteristics............................................................................877
SPI Slave Mode Timing Characteristics ..............................................................................879
External Bus Input Timing Specifications...........................................................................881
External Bus Output Timing Specifications ........................................................................882
ATD Electrical Characteristics (Operating).........................................................................884
ATD Electrical Characteristics ............................................................................................885
ATD Conversion Performance in 5 V Range ......................................................................885
ATD Timing Specifications .................................................................................................889
ATD External Trigger Timing Specifications .....................................................................889
I2C Input Timing Specifications between SCL and SDA....................................................890
I2C Output Timing Specifications between SCL and SDA .................................................891
NVM Program/Erase Times ................................................................................................892
NVM Module Life ...............................................................................................................892
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Preface
This reference manual provides information about the MAC7200 family of microcontroller devices, which
are made up of standard System-on-a-Chip modules and an ARM7TDMI-S™ processor core.
Document Structure
This document is part of the documentation needed to complete a design using a MAC7200 family device.
A complete set of device manuals also includes the ARM7TDMI-S core manuals:
• ARM Architecture Reference Manual (ARM DDI-0100)
• ARM7TDMI-S (Rev 4) Technical Reference Manual (ARM DDI 0234A)
• MAC7200 Microcontroller Family Hardware Specifications (MAC7200EC)
NOTE
The document MAC7200EC identified above is not currently available.
Preliminary electrical and mechanical specifications for the MAC7200
family can be found in this reference manual in Chapter 4, “Signal
Description”, Appendix A, “Electrical Characteristics” and Appendix B,
“Mechanical Information”.
How To Use This Document
If the reader is new to the MAC7200 family of devices, it is recommended that the following list of
sections be read before bringing up a MAC7200 family device:
• Chapter 1, “Introduction” — Describes the features of the MAC7200 family.
• Chapter 4, “Signal Description” — Describes the functionality of MAC7200 family device pins
• Chapter 5, “System Clock Description” — Describes clock generation and distribution to modules
on MAC7200 family devices.
• Chapter 6, “Resets” — Describes the reset functionality of the MAC7200 family.
• Chapter 7, “Exceptions” — Describes the system and interrupt exceptions of the MAC7200 family.
• Chapter 2, “Modes of Operation” — Describes the operational modes of the MAC7200 family.
• Chapter 9, “Device Memory Map” — Describes the memory map of the MAC7200 family devices
in various operating modes.
If the functionality of a particular peripheral is of interest, refer to the appropriate module description
(12.2, “The SPP DMA Controller Module (SPP_DMA2)” through Chapter 34, “Port Integration Module
(PIM_MAC7202)”).
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Conventions
Conventions
The following table gives conventions for terms used throughout this document.
Table i. Conventions
Terms
Description
logic level one
The voltage level that corresponds to a Boolean true (1) state.
logic level zero
The voltage level that corresponds to a Boolean false (0) state.
ACTIVE_HIGH
Names for signals that are active high are shown in uppercase text without an overbar. Signals
that are active high are referred to as asserted when they are logic 1 and negated when they
are logic 0.
ACTIVE_LOW
A bar over a signal name indicates that the signal is active low. Active-low signals are referred
to as asserted when they are logic 0 and negated when they are logic 1.
asserted
Signal is in the active logic state. In active high logic, the signal is asserted when it changes to
logic level one; in active low logic, the signal is asserted when it changes to logic zero.
negated
Signal is in the inactive logic state. In active high logic, the signal is negated when it changes to
logic level zero; in active low logic, the signal is negated when it changes to logic level one.
set
To establish logic level one on a bit or bits
clear
To establish logic level zero on a bit or bits
0x0000
Hexadecimal numbers
0b0000
Binary numbers
n
Indicates a numeric place holder. In register field contexts, indicates a value that may be written
or read. In register names, indicates any one of a set of multiple, identical registers. For
example, UCCRn indicates a reference to any one of the eMIOS Channel Control Registers,
UCCR0 through UCCR15.
x
In certain contexts, such as bit or signal encoding, this indicates a don’t care. For example, if a
four-bit binary field is represented as 0bx001, the state of the first bit is a don’t care. In other
contexts, such as module or register names, this is a place holder for a letter to designate a
module instantiation. For example, eSCI_x indicates a reference to either eSCI_A or eSCI_B.
b
Bit place holder
Byte
8 bits
Half-word
16 bits
Word
32 bits
Terminology
The following table lists definitions for abbreviations and names used throughout this document
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Terminology
Table ii. Terminology
Terms
Description
Active Message
Buffer
A Message Buffer is said to be “active” if it can participate in the current matching or arbitration
process. An Rx MB with a ‘0000’ code is inactive. Similarly, a Tx MB with a ‘1000’ code is also
inactive. An MB is temporarily deactivated when the CPU writes to the C/S field (see
Section 28.2.7.6.1, “Message Buffer Deactivation).”
ADB
Allowable disconnect boundary
ADC
Analog to Digital converter: A module to convert analog signals into digital (binary) values
AIPS
AMBA™ to IPS interface unit
ALC
Amplitude Limitation Control
ATD
Analog-to-digital (converter). Frequently used synonymously with ADC
ATM
Asynchronous transfer mode
ATMU
Auxiliary Port
Baud Rate
BD
Address translation and mapping unit
Refers to Nexus auxiliary port. Used as auxiliary port to the IEEE 1149.1 JTAG interface.
Rate of data transmission in bits per second.
Buffer descriptor
BDM
Background Debug Module
BIU
Bus Interface Unit, contains all system level customization required to make the H7Fb module
part of an SoC.
Branch Trace
Messaging (BTM)
Breakpoint
Visibility of addresses for taken branches and exceptions, and the number of sequential
instructions executed between each taken branch.
Processor is halted when all previous instructions are retired and just prior to any architectural
state change by the instruction associated with a pre-selected address.
CAN
Controller Area Network, a serial communication protocol.
CFM
Common Flash Module. Acronym used throughout this document to reference the Flash
memory module. The CFM includes the Common Flash bus interface, IP bus interface, Flash
command controller, Flash memory controller, and Flash arrays.
Clock Phase
Determines when the data should be sampled relative to the active edge of SCK
Clock Polarity
Determines the idle state of the SCK signal.
CM
Clock Monitor
coherency / coherent Coherent access is used to indicate an action to guarantee data consistency, preventing data
access
from being accessed simultaneously using different methods in such a way that it is not
completely updated before being used.
Command Write
Sequence
A three-stop command instruction sequence to program, erase, or verify the Flash memory.
CP
Clock Prescaler
CPI
CAN Protocol Interface, a FlexCAN sub-module containing the CAN protocol engine.
CPU
Central Processor Unit
CRC
Cyclic Redundancy Check.
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Terminology
Table ii. Terminology (Continued)
Terms
CRG
Description
Clock and Reset Generator module
CS
Chip Select. In Master Mode, the CS signal is used to select which slave device to talk to.
CSI
Combined Serial Interface. DSPI configuration that alternates DSI and SPI frames.
CSM
Conversion state machine
DAC
Digital to Analog Converter: Converts a binary value into a voltage
DAIC
Double Action Input Capture
DAOC
Double Action Output Compare
Debug Mode
Deserialize
DMA
DMA Mux
This is a system mode intended for debugging operations. When this mode is triggered, a
global Debug Mode Request signal is sent to all modules, so that they can prepare themselves
with debugging capabilities.
To convert data from a serial format to a parallel format.
Direct memory access
Direct Memory Access Multiplexer module
DMADC1032
ATD with DMA interface
Dominant Bit
A dominant bit wins the arbitration on the CAN bus. It is transmitted as ‘0.’
Doze Mode
Drain
DSI
DSI Frame
This is a system low power mode in which the CPU bus is kept alive and a global Doze Mode
request is sent to all peripherals asking them to enter low power mode. Typically, when Doze
Mode is requested, each peripheral can be enabled individually to enter or not low power
mode.
To remove entries from a FIFO by software or hardware.
Deserial Serial Interface. DSPI configuration that serializes and deserializes registers or
purpleline signals to allow for pin reduction.
Collection of serialized or deserialized pin states or register bits transferred over the serial link
DSPI
(Deserialized) Serial Peripheral Interface
ECC
Error Correction Code. Internally used to correct single bit errors, or detect double errors within
a 64 bit double word.
ECLK
E clock
eDMA
Enhanced Direct Memory Access controller module
EmbeddedICE
eMIOS
EOQ
Erase State
eSCI
The ARM7 EmbeddedICE debug module. This module integrated with each ARM7 core
provides all static (core halted) debug functionality. This module is compliant with Class1 of the
IEEE-ISTO 5001 standard.
Enhanced Modular Input/Output Subsystem
End of Queue
Flash array bit state that reads as a “1.”
Enhanced SCI module with LIN hardware and DMA support
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Terminology
Table ii. Terminology (Continued)
Terms
Description
FC
Flash Core, contains all addressable non-volatile storage elements. This includes Low Address
Space, Mid Address Space, High Address Space, and Shadow Space. Also known as Flash
Array.
Field
Fill
Two or more register bits grouped together.
To add entries to a FIFO by software or hardware.
Flash Array
A non-volatile SuperFlash® memory array used to build the Program Flash blocks, which
includes a Flash memory core with built-in high voltage generation and parametric features.
Flash Logical Page
4096 bytes of contiguous Flash memory consisting of two interleaved Flash physical blocks
representing the smallest section of the Flash memory that can be erased.
Flash Logical Sector Section of contiguous Flash memory that can be protected from program, erase, and
unauthorized access.
Flash User Mode
Frame
Flash module operations defined for User/Normal mode.
The data content of a serial transmission. Also referred to as DSPI Data.
FSM
Finite State Machine
GPIO
General purpose Input/Output
H7Fb
HiP7a Low Cost Flash EEPROM Module.
Hard Reset
Reset coming from external pin and/or following power-on. It resets everything.
HAS
High Address Space. If it exists, it contains 128k Byte subdivisions of the H7Fb array.
Host
Refers to the MCU or other bus master module
IEEE-ISTO 5001
IIB
input capture
Consortium & standard for real-time embedded system design. World wide Web
documentation at http://www.nexus5001.org/.
Internal Interface Bus
Sampling of a time base value upon the occurrence of an input signal transition.
IPI
Internal Peripheral Interface - a Freescale peripheral slave bus
IPF
Input Programmable Filter
IPM
Input Period Measurement
IPS
Intelligent Peripheral Subsystem bus interface
JTAG Compliant
Device complying to IEEE 1149.1 JTAG standard
JTAG IR & DR
Sequence
JTAG Instruction Register (IR) scan to load an opcode value for selecting a development
register. The selected development register is then accessed via a JTAG Data Register (DR)
scan.
LAS
Low Address Space. 256KByte in size. Various configurations exist for Low Address Space.
May also be 128KByte in size if total memory size is 128KByte (i.e. No MAS or HAS).
LC
Loop Control
LIN
Local Interconnect Network – A protocol for low-cost automobile networks
LIN FSM
LIN Finite State Machine – The control logic of the LIN hardware
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Terminology
Table ii. Terminology (Continued)
Terms
Description
LSB
Least Significant Bit
LVR
Low Voltage Reset
MAC
Multiply and accumulate
MADD
Multiply-and-Add unit which is responsible for the raw result adjustment
MAS
Mid Address Space. 256KByte in size. If it exists, it may contain 4 x 64KByte subdivisions of
the H7Fb Array, or 2 x 128KByte subdivisions.
match
Match an event that occurs when the value of a match register becomes equal to the value of
the selected time-base.
MC
MCU
Modulus Counter
Microcontroller Unit.
Message Buffer (MB) Internal FlexCAN data structure containing bytes received or to be transmitted to the CAN line,
as well as information about this data.
MI
Memory Interface, contains all state machines and control logic needed for operation of the
H7Fb module.
MSB
Most Significant Bit
MUX
Multiplexer
NSM
New command word state machine
NVM
Non-Volatile Memory.
OpAmp
Operational Amplifier
OPWFM
Output Pulse Width and Frequency Modulation
OPWM
Output Pulse Width Modulation
OPWMC
Center Aligned Output Pulse Width Modulation
OSCCLK
Oscillator clock
Output Compare
The modification of an output signal due to a time base match.
Ownership Trace
Messaging (OTM)
Visibility of process/function that is currently executing.
PCS
Peripheral Chip Select
PEA
Pulse/Edge Accumulation
PEC
Pulse/Edge Counting
PFLASH
Platform Flash Controller
Pipeline
Act of initiating a bus cycle while another bus cycle is in progress. Thus the bus can have
multiple bus cycles pending at one time.
PIT
Periodic Interrupt Timer
PLL
Phase Locked Loop
POR
Power on Reset
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Terminology
Table ii. Terminology (Continued)
Terms
Program State
Public Messages
Description
Flash array bit state that reads as a “0.”
Messages on the auxiliary pins for accomplishing common visibility and controllability
requirements
QDEC
Quadrature Decode
RC
Resistor-Capacitor
Receive or RX FIFO First-In-First-Out buffer for received data
Recessive Bit
Reset Sequence
A recessive bit loses the arbitration on the CAN bus. It is transmitted as ‘1.’
Coming out of reset, the CFM will read the Flash configuration field and load specific registers.
RQB
Interrupt Request Bus
RSD
Redundant Signed Digit: architecture how the ATD does the conversion
RSM
Result saving state machine
RTI
Real Time Interrupt - A timer with an independent clock which can run in system Doze or
Pseudo-Stop mode, and can be used for system wakeup.
RWCB
Read/Write Control Bus
RWW
Read While Write.
SAIC
Single Action Input Capture
SAOC
Single Action Output Compare
SAR
Successive Approximation Register: A method to adjust a reference voltage to an input voltage
SCI
Serial Communications Interface
SCK
Serial Communications Clock
Sclock
SCM
Serialize
Serial clock (FlexCAN). This is the clock obtained by dividing the clock feeding the CAN engine
(either oscillator or bus clock) by a prescaler factor. The Sclock period defines the time
quantum for CAN protocol timing.
Self Clock Mode
To convert data from a parallel format to a serial format.
Slave
A bus slave is a device that responds to a bus transaction, but never initiates a cycle on the bus.
SMB
Serial Message Buffer, an internal buffer not accessible by the end user.
SoC
System-on-a-chip.
Soft Reset
Global reset typically used by peripherals to re-initialize some of its registers, but not all of
them.
SPI
Serial Peripheral Interface
SS
Slave Select. Signal from the SPI master to the SPI slave indicating which SPI slave device the
Master want to communicate with.
Stop Mode
This is a system low power mode in which all MCU clocks are stopped for maximum power
savings. Typically, when Stop Mode is requested, each module will put itself in a known state
and then send a Stop Acknowledge signal to inform the CPU that it can stop the clocks.
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Terminology
Table ii. Terminology (Continued)
Terms
SWT
SYSCLK
Time Quantum
Transaction
Description
Software Watchdog Timer
System clock (fSYS) is the clock used by the core CPU (peripherals operate at fSYS ÷ 2)
This is equal to the Sclock period. It is the minimum time period used to compose the CAN
protocol bit timing.
A bus transaction consists of an address transfer (address phase) and one or more data
transfer(s) (data phase).
Transfer Code
(TCODE)
Message header that identifies the number and/or size of packets to be transferred, and how
to interpret each of the packets.
Transfer Format
The combination of SCK polarity, SCK phase, data MSB/LSB first, and associated CS signal
timing during a serial transmission
Transmit or TX FIFO First-In-First-Out buffer for transmit data
TUE
Total Unadjusted Error: difference between the expected (ideal) conversion result and the
result delivered by the ATD
UCn
Unified channel n, submodule that performs timed input or output functions supported by the
eMIOS
VCO
Voltage Controlled Oscillator
VREG
Watchpoint
WPTA
Voltage regulator
A Data or Instruction Breakpoint which does not cause the processor to halt. Instead a pin is
used to signal that the condition occurred. A Watchpoint Message is also generated.
Windowed Programmable Time Accumulation
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Register Descriptions
Register Descriptions
Each peripheral module chapter (12.2, “The SPP DMA Controller Module (SPP_DMA2)” through
Chapter 34, “Port Integration Module (PIM_MAC7202)”) contains a register description subsection that
details the location and definition of the user-accessible control and status bits and fields for the peripheral.
All register descriptions in this manual use bit 31, 15 or 7 (depending on the register size) to represent the
most significant bit and bit 0 to represent the least significant bit. Refer to Section 9.8, “Accessing
registers” for details on how registers may be accessed.
Each register description subsection includes a register diagram figure showing bit field mnemonic names
and locations followed by a table containing the full name for each bit field, a short description of
operational characteristics and exact bit value definitions. The figure and tables below show an example
of the format used for register figures, field descriptions and the conventions used to specify bit fields.
Row Label
Column Content
xx
Bit number, specifies the location of the bit or field within the register.
R
Behavior for read accesses. If named, the description table below the register diagram specifies the
definition. If zero, the bit will always read as zero. If shaded, the read value is undefined and the bit
position is reserved and must be ignored for future compatibility.
W
Behavior for write accesses. If named, the description table below the register diagram specifies the
definition. If shaded, the bit position is reserved and must be written as zero for future compatibility.
Reset
Reg Addr
Bit state immediately after a reset operation. Zero or one indicates how the bit state is affected by
reset, an emdash indicates that the bit state is not affected by reset.
Specifies the address of the most significant byte of the register (for a 16- or 32-bit register). Base is
the module address as specified in Chapter 9, “Device Memory Map’, Table 9-4 on page 9-108. Offset
is a hexadecimal number in the format 0x0000, or a formula used to calculate the offset, that is added
to Base to calculate the address of the register.
Table iii. Register Diagram Conventions
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Register Descriptions
Column Label
Row Content
Bits
Bit number, specifies the exact location of the bit field within the register. Always listed from the most
significant bit in the register to the least significant. For bit fields, the most significant and least
significant bit numbers are shown.
Name
Mnemonic name of the bit or field. For bit fields, the mnemonic is followed by bracketed numbers
specifying the size of the field.
Description
Full name of the bit or field. Includes a short definition of operational characteristics. Often contains
cross-references to detailed functional descriptions of module behaviors that are affected by a control
field or that are reflected in a status field. Followed by paragraphs listing definitions for each possible
value of the bit or field. For more complex definitions, or where bits or fields interact with other bits or
fields in various modes, tables are often embedded within the field description cell for more detailed
information.
0 single-bit value definitions
1 single-bit value definitions
0..0 first in a list of multi-bit field value definitions
.
.
.
1..1 last in a list of multi-bit-field value definitions
Table iv. Register Field Description Conventions
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
4
3
2
1
0
RO
0
R
W
Reg Addr
Base + Offset
15
14
13
12
11
10
9
8
7
6
0
0
0
0
0
0
0
0
0
0
R
FIELD
W
Reset
—
—
—
Reg Addr
—
—
—
—
—
—
—
0
0
RWBIT
Reset
0
WO
0
0
—
Base + Offset
Figure i. Example Register (EXREG)
Table v. EXREG Field Descriptions
Bits
Name
15–6
—
5–4
Description
Reserved; always reads as zero, must be written as zero.
FIELD[1:0] Bit field. This is a two-bit read/write field.
00 Behavior when field is written as 0b00, or status indicated when read as 0b00
01 Behavior when field is written as 0b01, or status indicated when read as 0b01
10 Behavior when field is written as 0b10, or status indicated when read as 0b10
11 Behavior when field is written as 0b11, or status indicated when read as 0b11
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Register Descriptions
Table v. EXREG Field Descriptions (Continued)
Bits
Name
Description
3
RWBIT
Read/write bit. This is a writable control bit that is used to specify certain behavior
of the module. Reading the bit position will return the last value written.
0 Behavior when bit is cleared
1 Behavior when bit is set
2
RO
Read-only. Normally used for status bits that reflect operating characteristics at
the time of the read access. Writes are ignored, but for future compatibility zero
should always be written.
0 Status definition if bit is clear
1 Status definition if bit is set
1
WO
Write-only bit. Normally used for control bits that trigger an event when written as
one, but always read as zero.
0 Writing zero has no effect
1 Writing one triggers event
0
—
Undefined bit. Normally indicates bits that are used only for factory testing and
must not be modified by customer code, and whose read contents are
indeterminate. Writing non-zero values may cause erratic device behavior.
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Register Descriptions
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Revision History
Content Changes by Document Version
Version No.
Release Date
Description of Changes
Page Numbers
Rev. 0
Nov-06
First customer release of Preliminary version.
All
Rev. 1
Mar-07
First public release of Preliminary version.
All
Rev. 2
Apr-07
Table A-5 MAC7200 Family Device Operating Condition.
C2 Digital Logic Supply Voltage VDD15, changed min limit from 1.35 to 1.45
861
Table A-12 Vreg operating conditions.
G2 Output Voltage Core (1.5 V) changed min from 1.35 to 1.45
868
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Content Changes by Document Version
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Chapter 1
Introduction
1.1
Overview
Designed for automotive applications, MAC72xx devices are members of a family of 32-bit Flash-based
microcontrollers. The MAC7200 family’s pin compatibility enables users to choose between different
memory and peripheral options for scalable designs. All MAC72xx devices are composed of a 32-bit
central processing unit (ARM7TDMI-S), up to 512K bytes of embedded Flash memory, as well as
additional memory blocks (4 x 16K bytes) to support software emulation of EEPROM and (32K bytes)
Bootloader code. The devices also have up to 32K bytes of System RAM and are implemented with an
eDMA (enhanced Direct Memory Access) controller to enable transfers between memories and standard
on-chip peripherals.
The peripheral set includes up to two asynchronous serial communications interfaces (eSCI), up to three
serial peripheral interfaces (DSPI), one I2C™ bus, a configurable 16-bit Timer (eMIOS) enabling
functions such as dual action Capture/Compare and output Pulse Width Modulation, up to sixteen 12-bit
analog-to-digital (ATD) converter channels, and two CAN 2.0 A/B software compatible modules
(FlexCAN). In addition, a large number of General Purpose Input Output (I/O) pins are also offered. All
of these I/O pins are bidirectional, and are available with interrupt capability. The internal data paths
between the DMA, memory, core and the peripherals are all 32-bits wide, further improving performance
for 32-bit applications.
The inclusion of a Phase Locked Loop (PLL) circuit allows power consumption and performance to be
adjusted to suit operational requirements.
The MAC72xx device members are offered in 100-pin LQFP or 144-pin LQFP. The devices can be
operated over a temperature range of -40°C to 150°C junction temperature.
NOTE
The 144LQFP packages are not currently qualified; any future qualification
will be based upon customer demand and will be subject to specified
leadtimes. This package option is supported for limited samples only, and
does not include burn-in testing.
1.2
•
Features
32-bit ARM7 TDMI-S RISC Core
— Up to 70MHz operating frequency
— Efficient code density through 16-bit instructions.
— Alternate general purpose registers.
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Features
•
•
•
— Byte (8-bit), Halfword (16-bit), Word (32-bit) data types supported.
— Cores and Memory connected using high performance AMBA AHB bus.
— Integrated E-ICE module for debug
Memory size
— 320k Bytes (MAC72x2) or 512k Bytes (MAC72x1) of wide accessed
Program Flash EEPROM.
– 4 Flash page buffers all 128-bits wide and individually configurable as either Instruction or
Data buffers.
– Page buffers can be configured to enable fetch ahead and either least recently used or
counter based buffer replacement schemes.
– Program & erase operations controlled by state machine.
– Internally generated program and erase voltages.
– ECC enabled array with 2-bit error detection, 1-bit error correction providing transparent
operation.
– 64-bit minimum write size.
– Flash configuration suitable for EEPROM emulation.
– Read or Program/Erase access on flash partition basis.
– Flash BIU support for access protection for User/Supervisor mode and Instruction/Data
accesses.
– Protection violation flag.
– Flash Lockout recovery mechanism though JTAG interface.
– 100K W/E endurance.
– 20 year data retention.
— 20k Byte (MAC72x2) or 32k Bytes (MAC72x1) RAM
– Single cycle accesses to RAM for Byte, Halfword and Word reads and writes.
– ECC enabled array with 2-bit error detection, 1-bit error correction.
Interrupt Controller
— 64 vectored interrupt sources.
— Interrupt sources available from internal peripherals, eDMA controller, software watchdog
timer and external sources.
— Supports 16 interrupt levels (0-15) with 64 priorities per level (1-64), to allow maximum
flexibility in configuring the system. Every interrupt source can be programmed to any
interrupt level. Priorities within a level are hard-coded in the MCU.
— Multiple level interrupt nesting.
— Hardware support for first nesting level.
— Normal and Fast interrupts supported with software programmability of sources for both Fast
and Normal Interrupts
Enhanced Direct Memory Access Controller (eDMA)
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Features
•
•
— DMA transfers possible between system memories, SPIs, SCIs, I2C, ATD, eMIOS and General
Purpose I/Os
— Programmable DMA Channel Mux allows assignment of any DMA source to any of the 16
available DMA channels.
— All DMA transfers use dual address format.
— Programmable Transfer Control Descriptor stored in local DMA memory.
— Programmable Source and Destination address with configurable offset.
— Independent 32-bit Minor and 16-bit Major loop counters for “nested” transfers.
— Different final Source and Destination addresses allow circular Queue operation.
— Programmable priority levels for each channel.
— Bandwidth control for each channel.
— Programmable transfer sizes through Major and Minor loop counters.
— Independently Programmable read/write sizes.
— Periodic triggering of up to 8 channels.
— Round Robin channel prioritization
— Scatter-Gather functionality
— Inner Loop channel pre-emption
— Channel to Channel linking
— Software or Hardware start
Analog-to-Digital Converter
— Up to 16 analog input channels.
— 12-bit resolution 9-bit accuracy.
— 2μS minimum conversion time.
— Internal sample and hold circuitry.
— Pre-measurement discharge of internal Sample and Hold circuit possible for all channels.
— Programmable input sample time for various source impedances.
— Queued conversion sequences supported by DMA controller.
— Analog inputs configurable as external sample triggers.
— On-chip timer triggers for sampling.
Two 1M bit per second, CAN 2.0 A/B software compatible modules (FlexCAN)
— Full implementation of the CAN 2.0 protocol specification.
— Programmable bit rate up to 1Mbps.
— 32 flexible Mail Boxes of 0-8 bytes data length on all modules.
— All Mail Boxes configurable for either Rx/Tx.
— Unused Mail Boxes space can be used as general purpose RAM.
— Supports standard or extended messages.
— “Time Stamp”, based on a 16-bit free-running counter.
— Maskable interrupts.
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3
Features
•
•
— Programmable I/O modes.
— External transceiver assumed.
Enhanced Modular I/O Subsystem features (eMIOS)
— 8 unified channels (MAC72x2) / 16 unified channels (MAC72x1), with every channel
able to provide all timer functions and modes.
— All channels can be enabled for eDMA service.
— Channels can be individually disabled to assist with power saving.
— Two or three 16-bit counter buses (A and B, or A, B, and C) for sharing time base around the
module.
— One global prescaler and an individual prescaler available for each channel.
— Modulus counter mode on all channels.
— Single action input capture or output compare modes on all channels.
— Input pulse width and period measurement modes on all channels.
— Double action output compare mode on all channels.
— Output pulse width and frequency modulation modes on all channels.
— Output pulse width modulation modes on all channels.
— Center aligned output pulse width modulation with dead time insertion modes on all channels.
— Pulse or edge accumulation and counting modes on all channels.
— Windowed programmable time accumulation mode on all channels.
— Quadrature decode modes on all channels.
— General purpose I/O available on unused eMIOS pins.
— Center-aligned PWM with dead-time insertion
Three Serial Peripheral Interface features (DSPI)
— Full Duplex, Synchronous Transfers.
— Master or Slave Operation.
— Programmable Master Bit Rates.
— Programmable Clock Polarity and Phase.
— End-of-Transmission Interrupt Flag.
— Programmable transfer Baud rate.
— Programmable data frames from 4-bits to 16-bits.
— Up to 6 chip select lines enable 64 external devices to be selected using external multiplexing
from a single DSPI.
— 8 Clock and Transfer Attributes registers.
— Chip Select Strobe available as alternate function on one of the Chip Select pins for
de-glitching.
— Two dedicated DMA request lines on each peripheral for receive and transmit data.
— FIFO for buffering up to 4 transfers on the transmit and receive side.
— Queueing operation possible through use of the DMA controllers channels.
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Features
•
•
•
•
— General purpose I/O functionality on pins when not used for SPI
Two Asynchronous Enhanced Serial Communications Interface features (eSCI)
— Standard Non return-to-Zero (NRZ) Mark/Space Format.
— Full-Duplex Operation.
— Software Selectable Word Length (8-bit or 9-bit words).
— 10/11 or 13/14 bit Break Character possible.
— 13-Bit Programmable Baud-Rate Modulus Counter.
— Separately Enabled Transmitter and Receiver.
— Separate receiver and transmitter CPU interrupt requests.
— Programmable transmitter output polarity.
— Two Receiver wake-up methods.
— Interrupt-driven operation with eight flags.
— Receiver framing error detection.
— Hardware Parity Checking.
— 1/16 bit time noise reduction.
— LIN Master mode state machine
– Supports generation of LIN message header.
– Detection and flagging of LIN errors.
— Two DMA request lines on each peripheral for receive and transmit data.
Inter IC Bus module features (IIC)
— Compatibility with I2C Bus standard.
— Two wire bi-directional serial bus for on board communications.
— Multimaster operation.
— Software-programmable for one of 256 different serial clock frequencies.
— Software-selectable acknowledge bit.
— Interrupt-driven byte-by-byte data transfer.
— Arbitration-lost interrupt with automatic mode switching from master to slave.
— Calling address identification interrupt.
— Start and stop signal generation/detection.
— Repeated START signal generation.
— Acknowledge bit generation/detection
— Bus-busy detection.
— Two DMA request lines to receive and transmit data
Oscillator
— Low power Amplitude Level Control (ALC) Oscillator.
— Selectable oscillator mode at powerup or after a loss of clock
Clock generation
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Freescale Semiconductor
5
Features
•
•
•
•
— Clock generation and Reset control performed in CRG.
— Phase-locked loop clock frequency multiplier.
— Self clocking mode available in absence of external clock.
— Software Watchdog Timer (SWT) watchdog.
Periodic Interrupt Timer (PIT) Module
— Independent timeout period for each timer.
— Four 32-bit general purpose timers, configurable to generate DMA trigger pulses.
— Four dedicated 32-bit timers to generate DMA trigger pulses.
— Two 32-bit timers that can be configured to generate ATD trigger pulses.
— One 24-bit real-time interrupt (RTI) timer.
— RTI operates from oscillator output clock.
Miscellaneous Control Module (MCM)
— Software watchdog timer with programmable system reset or interrupt response.
— Watchdog with optional Windowed mode.
— Access address information for faulted memory accesses.
— NMI configuration
System Services Module (SSM)
— System configuration and status.
– Memory sizes and status
– Security status
– Device mode
– eDMA status
– Debug Port.
– Nexus Status.
– System Reset.
General Purpose Input/Output
— Select between GPIO, interrupt or peripheral functionality on a pin-by-pin basis
— Register interface for both port wide and pin data reads and writes
— 6 independent 16-bit ports (Port A, B, C, D, F, G), with each pin having the following features:
– Peripheral or GPIO Mode selection, with up to 3 peripherals per pin
– Input/Output selection
– 5V output drive with three selectable slew rates (Disabled, Slow, Fast)
– 5V digital inputs
– Selectable pull-up or pull-down
– Selectable open drain for wired-or connections
– Selectable interrupt capability (with glitch filtering and interrupt mask)
— Control of ATD digital inputs (Port E)
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Features
•
•
•
– Selectable pull-up or pull-down
— Control of the TCK, TMS, TDI and TDO pads
– Input/Output selection
– 5V output drive with three selectable slew rates (Disabled, Slow, Fast) (TDO only)
– 5V digital inputs
– Selectable pull-up or pull-down (TCK, TMS and TDI only)
Internal Voltage Regulators.
— On-chip Voltage Regulators generate all necessary internal supply voltages from 5V only input
voltage, including Flash, Oscillator, PLL and core supply voltage.
— Bypass mode allows off-chip supply of all on-chip voltages.
— Power On Reset (POR) and Low Voltage Reset (LVR) detection with independent flags for full
reset source reporting.
144-Pin LQFP, 100-Pin LQFP
— I/O lines with 5V input and drive capability.
— Programmable pull-up pull-down or no-pull on all port pins.
— Programmable slew rate on all bidirectional port pins.
— 5V ATD converter inputs.
— 1.5V logic supply.
Development support
— Real Time Instruction Trace Support via Nexus Class 3.
— Alternate Nexus port pin position selectable at Reset
— ARM Embedded ICE debug support on all devices.
— JTAG Test Access Port (TAP) Interface.
— Debug mode access to CPU registers.
— Real Time memory access.
— Hardware Breakpoints.
Table 1-1. List of MAC72xx Devices
Flash
RAM
Package
Device
FlexCan
ESCI
DSPI
IIC
ATD1
eMIOS
Nexus3
I/O2
320k
20k
144LQFP
7212
2
2
3
1
1/8
8
Yes
102
144LQFP
7202
2
2
3
1
1/16
8
Yes
102
100LQFP
7242
2
2
3
1
1/15
8
Yes
66
144LQFP
7211
2
2
3
1
1/8
16
Yes
102
144LQFP
7201
2
2
3
1
1/16
16
Yes
102
100LQFP
7241
2
2
3
1
1/15
16
Yes
66
512k
32k
1. ATD column shows: number of modules/total number of ATD channels.
2. I/O column shows: sum of ports able to act as digital input or output.
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
7
Features
•
144 Pin Packages:
— PAC7211/PAC7212
– Port A = 16, B = 16, C = 16, D = 14, E = 8, F = 16, G = 16.
– 101 inputs provide interrupt capability (Ports, XIRQ/NMI).
— PAC7201/PAC7202
– Port A = 16, B = 16, C = 16, D = 12, E = 16, F = 16, G = 10.
– 101 inputs provide interrupt capability (Ports, XIRQ/NMI).
NOTE
The 144LQFP packages are not currently qualified; any future qualification
will be based upon customer demand and will be subject to specified
leadtimes. This package option is supported for limited samples only, and
does not include burn-in testing.
•
100 Pin Packages:
— MAC7242/MAC7241
– Port A = 3, B = 16, C = 0, D = 8, E = 8, F = 16, G = 15.
– 66 inputs provide interrupt capability (Ports, XIRQ/NMI).
P AC 7 2 0 2 C PV 70
MC Status
Core Code
Core Number
Generation / Family
Package Option
Device Number
Temperature Range
Package Identifier
Speed (MHz)
Temperature Option
C = - 40ºC to 85ºC
V = - 40ºC to 105ºC
M = - 40ºC to 125ºC
Package Identifier
FU = 100 QFP
PV = 144 LQFP
Figure 1-1. Orderable Part Number Example
1.2.1
Performance Summary
Max Processor/System Bus Speed: 70MHz (T=14.3ns)
Max Peripheral Bus Speed: 35MHz (T=28.6ns) (1/2 Max Processor Speed)
Context Switching: Assumed to be about 25 cycles for all ISRs
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Modes of Operation
Table 1-2. Typical System Access Summary
Port
Typical
(cycles)
Purpose
Comments
ARM7 Core
Flash
(Port M0=>S0)1
RD: 1.2
(per instr.)
WR: N/A
Instruction Fetch
SRAM2
(Port M0=>S3)1
RD: 1
WR: 1
Operand
Read/Write
External Bus
(Port M0=>S1)1
RD: 2
WR: 2
Operand
Read/Write
Peripheral Bus Periphs
(Port M0=>S2)1
RD: 3
WR: 4
Peripheral
Config
DMA
Flash
(Port M1=>S0)1
RD: 3
WR: 4
Program Flash
SRAM2
(Port M1=>S3)1
RD: 1
WR: 1
Periph to/from
SRAM
External Bus
(Port M1=>S1)1
RD: 2
WR: 2
Periph to/from Ext.
Memory
Peripheral Bus Periphs
(Port M1=>S2)1
RD: 3
WR: 4
Periph to/from
SRAM
1. Port notations refer to Crossbar ports, and are explained in Chapter 15, “MAC7200
Crossbar Switch (AXBS)”.
2. Assumes 0 programmed wait-states.
1.3
Modes of Operation
This section describes the various functional modes of the MAC72xx devices. A functional mode is
selected by asserting the MODA and MODB pins (PD1 and PD0, respectively) while the RESET pin is
asserted. Because there is no way to determine when these values are latched inside the device, the
MODA/MODB pins must be asserted the entire time that the RESET pin is asserted. External (weak)
pull-ups and/or pull-downs may be used for this purpose. Table 1-3 shows the values of the
MODA/MODB pins for each chip mode. Note that these encodings are only valid when the TEST pin is
negated (tied low).
Once a chip mode has been set, it may only be changed by any of the following:
• Securing the flash, and resetting the device. In this case the mode changes from “XXX Unsecured
Mode” to “XXX Secured Mode”.
• Unsecuring the flash, and resetting the device. In this case the mode changes from “XXX Secured
Mode” to “XXX Unsecured Mode”.
• Changing the MODA/MODB pins and resetting the device. In this case the mode changes from
“XXX Secured/Unsecured Mode” to “YYY Secured/Unsecured Mode”.
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9
Modes of Operation
Note that resetting the device is mandatory in all three cases.
Table 1-3. Chip Mode Encodings
1.3.1
•
•
•
•
1.3.2
•
•
•
•
1.3.3
•
•
•
•
MODA
(PD1)
MODB
(PD0)
Flash
Secured ?
Chip Mode
0
0
Yes
Single Chip Secured Mode
0
1
Yes
Expanded Chip Secured Mode
1
0
Yes
PBL Secured Mode
1
1
Yes
Reserved
0
0
No
Single Chip Unsecured Mode
0
1
No
Expanded Chip Unsecured Mode
1
0
No
PBL Unsecured Mode
1
1
No
Reserved
Single Chip mode (Unsecured)
EICE/Nexus/JTAG active
— Enable TCK, TDI, TDO and DBGEN
FlexBus available at $2000 0000
Boot from Flash main array at $0000 0000
— Shadow Block available at $00f0 0000
JTAG Lockout Recovery is available
Single Chip mode (Secured)
No EICE/Nexus/JTAG
— Disable DBGEN and Nexus clock(s)
No FlexBus
Boot from Flash main array at $0000 0000
— Shadow Block available at $00f0 0000
JTAG Lockout Recovery is available
PBL Chip mode (Secured)
Same as Single Chip mode, except boot from the Shadow Block
No EICE/Nexus/JTAG
— Disable DBGEN and Nexus clock(s)
No FlexBus
Relocate Shadow Block to $0000 0000
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Modes of Operation
•
•
1.3.4
•
•
•
•
•
•
1.3.5
•
•
•
•
1.3.6
•
•
•
•
Relocate Flash main array to $2000 0000
— Shadow Block available at $20f0 0000
JTAG Lockout Recovery is available
PBL Chip mode (Unsecured)
Same as Single Chip mode, except boot from the Shadow Block
EICE/Nexus/JTAG active
— Enable TCK, TDI, TDO and DBGEN
No FlexBus
Relocate Shadow Block to $0000 0000
Relocate Flash main array to $2000 0000
— Shadow Block available at $20f0 0000
JTAG Lockout Recovery is available
Expanded Chip mode (Secured)
EICE/Nexus/JTAG active
— Enable TCK, TDI, TDO and DBGEN
Disable Flash Main Array and Shadow Block access
Relocate FlexBus to $0000 0000
Boot from FlexBus
Expanded Chip mode (Unsecured)
EICE/Nexus/JTAG active
— Enable TCK, TDI, TDO and DBGEN
Relocate Flash to $2000 0000
— Shadow Block available at $20f0 0000
Relocate FlexBus to $0000 0000
Boot from FlexBus
See Chapter 9, “Device Memory Map” for more detailed information on how each chip mode affects
relocation of system resources.
1.3.7
Low Power Modes
The microcontroller features only a single low power mode:
• DOZE Mode. In this mode, individual peripherals may be shut down to allow a completely
customizable power consumption profile tailored to the requirements of the application.
MAC7200 Microcontroller Family Reference Manual, Rev. 2
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11
Modes of Operation
In addition to the above mode, each peripheral may be individually disabled in order to minimize power
consumption for those peripherals not used in a particular application.
See Chapter 3, “Low Power Modes” for more detailed information on low power modes.
1.3.8
Debug Mode
In addition to the functional chip modes and low power modes described above, the MAC72xx supports a
Debug mode. By placing the system in Debug mode, the following actions occur:
• The ARM7 core is placed into Halt Mode or Monitor Mode, depending on the state of the DCR[4]
bit.
• The Real Time Interrupt (RTI) clock is shut off
• The Software Watchdog Timer (SWT) clock is shut off
• All peripheral level debug features are enabled
— DMA2
— FlexCAN2
— DSPI
— eMIOS
— ATD
— MCM (Software Watchdog Timer)
More information on system debug features can be found in Chapter 8, “Debug”.
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Block Diagram
1.4
Block Diagram
32
BUS
H7Fb
NATIVE
ARM7
Registers
32
32
AHB2
EICE
PFLASH
320K/512K
Main Array
with ECC
32K
Shadow
with ECC
64
Nexus3p
S0
S3
M0
FlexBus
32
S1
S1
S5
32
32
20K/32K
SRAM with
ECC
PRAM
AXBS
M1
S7
32
32
DMA2
32
INTC
32
MCM
32
BAM
AIPS
32
OSC
32
32
VREG
PIM (GPIO)
CRG/PLL
32
32
SPI_B
32
32
eMIOS
8/16-Channel
SPI_A
32
Gasket
CAN_A
32
CAN_B
32
32
SPI_C
ATD
(12b,16ch)
32
PIT
(32-bit)
DMA Mux
SSM
32
32
32
IIC
32
SCI_A
32
SCI_B
32
32
Full speed System Bus
Full speed Peripheral Bus
Half speed Peripheral Bus
Figure 1-2. MAC72xx Architecture Overview
MAC7200 Microcontroller Family Reference Manual, Rev. 2
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13
System Memory Map
NOTES:
Arrow directions represent bus mastership, not R/W capability. Unless otherwise noted, all buses are R/W
2
Each bus includes a number (8,16 or 32), which represents the width of the data bus
3
The heavy dotted black line represents the boundary of the SPP Platform
4
Modules with a
represent modules with DMA interfaces. All other IPI modules have no DMA connection.
1
1.5
System Memory Map
Please also refer to Chapter 2, “Modes of Operation” and Chapter 9, “Device Memory Map”.
NOTE
Some system resources may be dynamically relocated after reset. refer to
Section 9.16, “Memory Map Relocation for more information on this topic.
Table 1-4. System Memory Maps
Single
Chip
Unsecured
Single
Chip
Secured
$0000 0000
Flash
Main
Array
Flash
Main
Array
$00F0 0000
Shadow
Block
Shadow
Block
$2000 0000
FlexBus
$20F0 0000
$4000 0000
Expanded
Unsecured
Expanded
Secured
PBL
Unsecured
PBL
Secured
Lockout
Recovery
FlexBus
FlexBus
Shadow
Block
Shadow
Block
BAM
Flash
Main
Array
Flash
Main
Array
Flash
Main
Array
Flash
Main
Array
Shadow
Block
Shadow
Block
Shadow
Block
Shadow
Block
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
BAM
BAM
BAM
BAM
BAM
BAM
BAM
Peripheral
Bus
Peripheral
Bus
Peripheral
Bus
Peripheral
Bus
Peripheral
Bus
Peripheral
Bus
Peripheral
Bus
$6000 0000
$8000 0000
$A000 0000
$C000 0000
$E000 0000
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Chapter 2
Modes of Operation
2.1
Introduction
Devices in the MAC7200 family can operate in several different modes, depending on the particular
application and stage of development. In general, there are six different modes available on the MAC7200
family, which are determined by the MODA and MODB pins as well as the security state of the on-chip
Flash memory. The selection of a particular mode affects the following device characteristics:
• The memory map for the device. A detailed description of the memory map in each chip mode can
be found in Chapter 9, “Device Memory Map”
• Which debug features are enabled or disabled
• Which security features are enabled or disabled
2.2
MCU Hardware Configuration Summary
On the MAC72xx, there are 7 pins which are used to determine the configuration of the device at reset, as
follows:
•
•
•
•
MCU Mode (MODA, MODB)
Oscillator Type (XCLKS)
Nexus Port (NEXPORTSEL, NEXPRESENT)
External Bus Port Size and Auto Acknowledge (for those devices with an external bus)
(PORTSIZE, AUTOACK)
Note that all of the hardware configuration is done during Reset with the TEST pin held low. As such, the
values of the pins are latched on the rising edge of the active low device Reset signal RESET, and must be
kept stable while RESET is low. External (weak) pull-ups and/or pull-downs may be used for this purpose.
2.3
Security
When the Flash is secured (Please refer to Section 18.7.9, “Flash Security” for details), the MCU is
considered in a “Secured” state. The purpose of this state is to prevent the application code or data stored
in the Flash Main Array and Shadow Block from being read by outside sources.
The device will make available a security feature preventing the unauthorized read and write of the
memory contents. This feature allows:
• Protection of the contents of Flash main array,
• Protection of the contents of Shadow Block,
• Operation in Single Chip mode,
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
15
Security
•
•
•
Operation from external memory with internal Flash main array and Shadow Block disabled,
Disabling of EICE and Nexus access in secured Single Chip and Primary Bootloader modes,
JTAG Test Registers (See Section 35.1.1, “JTAG Test Register (SC4)) are accessible on a secured
device.
Which features are enabled or disabled is determined by the chip mode and security state in effect. Please
refer to Section 2.4.1, “Normal Single Chip Mode to Section 2.4.6, “Secured Expanded Mode for
complete details.
Note that the security state of the Flash is applied to both the Main Array and to the Shadow Block. It is
not possible to unsecure just one or the other.
The user must be reminded that part of the security must lie with the user’s code. An extreme example
would be user’s code that dumps the contents of the internal program. This code would defeat the purpose
of security. At the same time the user may also wish to put a back door in the user’s program. An example
of this is the case in which a user downloads a key through the FlexCAN, allowing access to a
programming routine that updates parameters stored in the Flash.
2.3.1
2.3.1.1
Operation of the Secured Microcontroller
Single Chip Secured Mode
In this mode, the MCU will function similarly to a device in Normal (Unsecured) Single Chip Mode.
However the FlexBus interface will be disabled, and access to the device via the Debug port will be
blocked, thus preventing access to the contents of the memory.
2.3.1.2
Executing from External Memory
The user may wish to execute from external space with a secured microcontroller. This is accomplished
by resetting directly into expanded mode. With the MCU in secure mode, access to the Flash main array
and Shadow Block will be disabled.
2.3.2
Securing the Microcontroller
Once the user has written the contents of the Flash main array and Shadow Block (if desired), the part can
be secured by programming the security bits located in the Shadow Block. These non-volatile bits will
keep the part secured through resetting the part and through powering down the part. When security is
enabled both the Flash main array and Shadow Block memories are secured (i.e.-it is not possible to
configure security independently for these two memories).
For further information on the security of the Flash, consult Section 18.7.9, “Flash Security”.
2.3.3
Unsecuring the Microcontroller
There are two methods to unsecure the MCU:
• Software unsecure
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MCU Mode Selection
•
JTAG Lockout Recovery
2.3.3.1
Software Unsecure
Since the security state of the device is determined solely by a user programmable location in the Shadow
Block, any application may choose to implement a software unsecure method, through any interface.
There are no built-in features, such as a backdoor access key, on the MAC72xx.
2.3.3.2
JTAG Lockout Recovery
If a software unsecure of the device is not possible, an alternative method exists for unsecuring the device.
In this method, called Lockout Recovery, the Flash main array and Shadow Block are first erased before
the device is unsecured. This procedure can be performed with a JTAG instruction over the JTAG interface
of the device. The recommended procedure is as follows:
1. Assert the RESET to the device
2. While the RESET is asserted, set the “Start Flash Lockout Recovery” bit (bit 9) in JTAG Test
Register SC4
3. Release the RESET
4. The JTAG Lockout Recovery procedure will run automatically, erasing both the Flash main array
and the Shadow Block, followed by a re-programming of the security bits to an unsecured state.
5. Sample the JTAG Test Register SC4 until the “Flash Lockout Recovery is complete” bit (bit 8) is
set
6. If the “Flash Security Request” bit (bit 19) is cleared, the device is now unsecured
7. Reset the device again in order to leave JTAG Lockout Recovery mode. There is no need to clear
the “Start Flash Lockout Recovery” or “Flash Lockout Recovery is complete” bits, as they are
self-clearing.
Note that performing Lockout Recovery erases both the Flash main array and the Shadow Block.
2.4
MCU Mode Selection
The chip operating mode out of Reset is determined by the states of the MODA and MODB pins (Port
D[1:0]) at Reset and the security status of the Program Flash.
Table 2-1. MCU Mode Selection Signals
Signal
Function
MODA/MODB
(PD1/PD0)
These two pins are latched at reset to determine the chip mode (See
Table 2-2).
MAC7200 Microcontroller Family Reference Manual, Rev. 2
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17
MCU Mode Selection
Table 2-2. MCU Mode Selection
MODA
(PD1)
MODB
(PD0)
Flash
Secured ?
Chip Mode
0
0
No
Normal Single Chip Mode
0
1
No
Normal Expanded Mode
1
0
No
Normal Primary Bootloader Mode
1
1
No
Reserved for future use
0
0
Yes
Secured Single Chip Mode
0
1
Yes
Secured Expanded Mode
1
0
Yes
Secured Primary Bootloader Mode
1
1
Yes
Reserved for future use
Once the MCU Mode has been set, it may only be changed by any of the following:
• Securing the flash, and resetting the device. In this case the mode changes from “Normal XX
Mode” to “Secured XXX Mode”.
• Unsecuring the flash, and resetting the device. In this case the mode changes from “Secured XXX
Mode” to “Normal XXX Mode”.
• Changing the MODA/MODB pins and resetting the device. In this case the mode changes from
“Normal XXX Mode” to “Normal YYY Mode” or from “Secured XXX Mode” to “Secured YYY
Mode”.
Note that resetting the device is mandatory in all three cases.
2.4.1
Normal Single Chip Mode
In Normal Single Chip Mode, the system boots from the Flash main array. The system may be configured
to enable the external bus.
• EICE/Nexus/JTAG active
— Enable TCK, TDI, TDO and DBGEN
• FlexBus available at $2000 0000
• Boot from Flash main array at $0000 0000
— Shadow Block available at $00f0 0000
• JTAG Lockout Recovery is available
2.4.2
Secured Single Chip Mode
In Secured Single Chip Mode, the system boots from the Flash main array. The external bus interface is
unavailable.
• No EICE/Nexus/JTAG
— Disable DBGEN and Nexus clock(s)
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MCU Mode Selection
•
•
•
2.4.3
No FlexBus
Boot from Flash main array at $0000 0000
— Shadow Block available at $00f0 0000
JTAG Lockout Recovery is available
Normal Primary Bootloader Mode
In Normal PBL Mode, the memory map of the system is modified to move the location of the Shadow
Block from its default Reset location to starting at location $0000 0000. This remapping enables the device
to boot from the Shadow Block.
• Same as Single Chip mode, except boot from the Shadow Block
• EICE/Nexus/JTAG active
— Enable TCK, TDI, TDO and DBGEN
• No FlexBus
• Relocate Shadow Block to $0000 0000
• Relocate Flash main array to $2000 0000
— Shadow Block available at $20f0 0000
• JTAG Lockout Recovery is available
2.4.4
Secured Primary Bootloader Mode
In Secured PBL Mode, the memory map of the system is modified to move the location of the Shadow
Block from its default Reset location to starting at location $0000 0000. This remapping enables the device
to boot from the Shadow Block.
• Same as Single Chip mode, except boot from the Shadow Block
• No EICE/Nexus/JTAG
— Disable DBGEN and Nexus clock(s)
• No FlexBus
• Relocate Shadow Block to $0000 0000
• Relocate Flash main array to $2000 0000
— Shadow Block available at $20f0 0000
• JTAG Lockout Recovery is available
2.4.5
Normal Expanded Mode
In Normal Expanded Mode, the MCU boots from an external source by accessing external memory and
hardware across the external Address and Data bus. In this mode the Flash main array and Shadow Block
are accessable.
• EICE/Nexus/JTAG active
— Enable TCK, TDI, TDO and DBGEN
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
19
Oscillator Type Selection
•
Relocate Flash to $2000 0000
— Shadow Block available at $20f0 0000
Relocate FlexBus to $0000 0000
Boot from FlexBus
•
•
2.4.6
Secured Expanded Mode
In Secured Expanded Mode, the MCU boots from an external source by accessing external memory and
hardware across the external Address and Data bus. In this mode the Flash main array and Shadow Block
are unavailable. Neither the Flash main array or the Shadow Block can be accessed, except for the accesses
necessary to unsecure the device.
• EICE/Nexus/JTAG active
— Enable TCK, TDI, TDO and DBGEN
• Disable Flash Main Array and Shadow Block access
• Relocate FlexBus to $0000 0000
• Boot from FlexBus
See Chapter 9, “Device Memory Map” for more detailed information on how each chip mode affects
relocation of system resources.
2.5
Oscillator Type Selection
At Reset the type of Oscillator can be selected using the XCLKS pin.
Table 2-3. Oscillator Type Selection
Pin
Reset State Definition
XCLKS
(PD2)
This bit determines the mode of the oscillator as follows:
0 External Clock Mode
1 ALC Mode
Please refer to Section 24.8.1, “OSC Mode Selection” for more details on the various oscillator modes.
The oscillator mode (XCLKS) is latched only during a power-on reset and during a reset while a loss of
clock has occurred. It is not latched during a normal system reset. Please refer to Chapter 24, “Oscillator
(OSC)” for more information on configuring and using the oscillator.
2.6
Nexus Port Selection
If use of the Nexus Port is required for debugging, it may be connected to either the Nexus Primary Port
or the Nexus Secondary Port. The hardware configuration pins associated with the Nexus are:
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External Bus Configuration
Table 2-4. Nexus Port Selection
Pin
Reset State Definition
NEXPORTSEL This bit determines whether the Nexus, if present, resides on the Primary or Secondary Port.
(PF0)
NEXPRESENT This bit determines whether an external debug system is physically connected to the MAC72xx. Internally, it
(PF1)
is used with NEXUSPORTSEL to place the Nexus Primary or Secondary Port pads into the correct
configuration.
The Nexus may be enabled or disabled using the settings described in Table 2-5.
Table 2-5. Nexus Hardware Configuration
NEXPORTSEL
NEXPRESENT
Effect
0
0
Nexus is not present.
0
1
Nexus is present on the Primary Port.
1
0
Nexus is not present.
1
1
Nexus is present on the Secondary Port.
The Nexus Port may be changed only by resetting the device. Please refer to Chapter 8, “Debug” for more
information on configuring and using Nexus.
2.7
External Bus Configuration
If the device and MCU Mode support an external bus, then it may be configured via the PF2 and PF3 pins.
Table 2-6. External Bus Configuration
Pin
Reset State Definition
AUTOACK
(PF2)
This bit enables the Auto Acknowledge feature for the Global
Chip Select on the External Bus. Internally, this latched value is tied to fb_rst_cfg[2].
PORTSIZE
(PF3)
This bit determines the port size of the External Bus as follows:
0 8-bit
1 16-bit
Internally this latched value is driven onto fb_rst_cfg[1], while fb_rst_cfg[0] is tied to 1. This precludes the
use of a 32-bit Port size, which is not supported on the MAC72xx. The full encoding for fb_rst_cfg[1:0] is:
00 32-bit
01 8-bit
1x 16-bit
Please refer to Chapter 17, “External Bus Interface (FlexBus)” for more information on configuring and
using the External Bus.
2.8
Low Power Modes
The microcontroller features only a single low power mode:
• DOZE Mode. In this mode, individual peripherals may be shut down to allow a completely
customizable power consumption profile tailored to the requirements of the application.
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21
Debug Mode
In addition to the above mode, each peripheral may be individually disabled in order to minimize power
consumption for those peripherals not used in a particular application.
Please consult the relevant chapter for information on the module behavior in Doze Mode. An important
source of information about the clocks in the system is Chapter 23, “Clock and Reset Generator (CRG)”.
See Chapter 3, “Low Power Modes” for more detailed information on low power modes.
2.8.1
Doze
In Doze mode the device can be configured to selectively halt the operation of individual peripherals. In
this mode it is possible to maintain operation of the DMA. For further power consumption savings, the
Real Time Interrupt and Watchdog can be disabled. This mode is entered by writing to the DOZE register
in the CRG. Wake up from this mode can be via a reset, an RTI (if enabled), an SWT event (if enabled), a
Self clock mode interrupt, a peripheral interrupt, an external interrupt, or the core clearing the DOZE
register.
2.8.2
Run
Although this is not a low power mode, it is possible to enable power savings when operating in Run mode
by disabling specific peripherals which are not required in the application. This is done with the MDIS
register bit in the particular peripheral.
2.9
Debug Mode
In addition to the functional chip modes and low power modes described above, the MAC72xx supports a
Debug mode. By placing the system in Debug mode, the following actions occur:
• The ARM7 core is placed into Halt Mode or Monitor Mode, depending on the state of the DCR[4]
bit.
• The Real Time Interrupt (RTI) clock is shut off
• The Software Watchdog Timer (SWT) clock is shut off
• All peripheral level debug features are enabled
— DMA2
— FlexCAN2
— DSPI
— eMIOS
— ATD
— MCM (Software Watchdog Timer)
More information on system debug features can be found in Chapter 8, “Debug”.
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Chapter 3
Low Power Modes
3.1
Low Power Modes Introduction
The MAC72xx provides three low power modes to enable the minimum run current for every application.
The following low power modes are supported (in order of decreasing power consumption).
Table 3-1. Low Power Modes
Mode
Description
Run Mode
This is the “normal” operating mode of the MAC72xx, in which all clocks are running, and all peripherals
are powered up.
Doze Mode
In this system level mode, the clocks to each peripheral may be disabled in order to reduce power
consumption. This mode is intended for dynamic power management.
Disabled Mode
3.2
In this mode, the peripheral is completely disabled, typically because it is not used for the particular
application being executed. This mode is intended for static power management.
Run Mode
This is the “normal” operating mode of the MAC72xx, in which all clocks are running, and all peripherals
are powered up.
Entering Run mode
• Reset
• Exiting all other current Low Power Modes
In this mode, the following components may be individually controlled:
• Turn off the RTI by writing 0 to the RTI counter register
• Turn off the SWT by writing 0 to the SWT counter register
• Put any peripheral into Disable mode by setting its MDIS bit. Note that after a reset, all peripherals
that support a Disable mode are put into this mode by default.
Exiting Run mode
• Run mode is exited by entering any other Low Power Mode
3.3
Doze Mode
In this system level mode, the clocks to each peripheral may be disabled in order to reduce power
consumption. This mode is intended for dynamic power management. In Doze mode, each individual
peripheral’s clock is gated by the peripheral itself (See Chapter 5, “System Clock Description” for more
MAC7200 Microcontroller Family Reference Manual, Rev. 2
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23
Disabled Mode
details on this). This is typically done by setting or clearing a DOZE bit in one of the peripheral’s control
registers. Only the core clocks are actually gated in DOZE mode. IPI register clocks are gated only when
no register accesses to the module are detected, thus still allowing access to the module’s DOZE bit. All
protocol clocks are running in DOZE mode in order to enable detection of wakeup events on external
interfaces.
Entering Doze mode
• Core sets the SYSTEM_DOZE bit in the CRG
In this mode, the following components may be individually controlled:
• Turn off the RTI clock by setting RTIDOZE
• Turn off the SWT clock by setting SWTDOZE
• Turn off a peripheral by setting its DOZE bit
Exiting Doze mode
Any of the following events can be used to wake the system from DOZE mode:
• External Reset
• Crystal Monitor Reset
• SWT Reset
• Self Clock Mode Interrupt
• Real Time Interrupt (RTI)
• Any Wakeup event in the system
• Core writes $00 to the CRG DOZE register
• Core clears the DOZE bit in the individual peripheral (optional feature)
3.4
Disabled Mode
In this mode, the peripheral is completely disabled, typically because it is not used for the particular
application being executed. This mode is intended for static power management.
• Controlled via the MDIS bit in each peripheral
• Software is responsible for setting the appropriate MODE bits in the Port Integration Module
(PIM), in order to drive the correct control signals to the pad(s).
• Core enables peripheral by clearing its MDIS bit.
• Note that the peripheral does not finish any current transfers before shutting down.
Entering Disabled mode
• The reset state of all peripherals is disabled (MDIS=1)
• Software configures the appropriate pin(s) in the PIM, including setting the correct MODE bits.
• Core sets the MDIS bit in the peripheral
Exiting Disabled mode
• The reset state of all peripherals is disabled (MDIS=1)
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System Wakeup
•
3.5
Core clears the MDIS bit in the peripheral
System Wakeup
Because the interrupt controller has a combinatorial bypass signal, that is active even during low power
modes, all interrupt sources in the system will serve as wakeup signals, with a flexible priority masking
scheme (i.e.-only interrupts above a certain priority will wake the system).
This gives us the following sources to wake up the system:
Table 3-2. Wakeup Sources
Interrupt
Where to
enable
Pending Status
in INTC ?
Where to
clear
Peripheral
INTC
MCM (MWCR reg)
Yes
Peripheral
INTC
The general flow to setup a wakeup is as follows:
1. Set the ENBWCR bit in the MWCR register in the MCM
2. Set the PRILVL[3:0] bits in the MWCR register in the MCM
3. Clear any pending interrupts in the peripheral(s) that will be used to generate wakeup interrupts
4. Set the appropriate level in the ICR register in the interrupt controller corresponding to the interrupt
source(s) that will be used for wakeup
5. Write the IMRL and/or IMRH registers in the interrupt controller to enable all interrupts that will
be used for wakeup
6. Setup the interrupt(s) in the peripheral(s) that will be used to generate wakeup interrupts.
Generally, this involves setting an interrupt enable and clearing an interrupt mask
Once the system has woken up, the general flow to identify the source of the wakeup is as follows:
1. Read the IPRH and IPRL registers in the interrupt controller to determine which (if any) interrupt
wakeup sources are pending
2. Once the wakeup sources have been identified, clear all sources
3.6
•
•
Low Power Mode Differences from MAC71xx
STOP mode is not supported
Wakeup from DOZE is only on interrupts now
— Wakeup from VREG API is removed
— Wakeup from PIM Keypad Wake-Up (KWU) is removed. Wakeup from an external source can
still be done using the normal interrupt functionality of the PIM.
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25
Low Power Mode Summary
3.7
Low Power Mode Summary
Table 3-3. Low Power Mode Entry Summary
Event
RUN
External Reset
X
DOZE
Write DOZE register
X
Set DOZE bit
(on a Peripheral-by-Peripheral basis)
X
Core enters HALT state
DEBUG
X
NOTE
In most cases, entering RUN mode is equivalent to exiting a Low Power
Mode, so this is described in Table 3-4.
Table 3-4. Low Power Mode Exit Summary
Event
RUN
DOZE
DEBUG
Enter DOZE Mode
X
--
X
Enter DEBUG Mode
X
Core enters HALT state
X
--
Core exits HALT state
3.8
X
External Reset
X
Crystal Monitor Reset
X
SWT Reset
X
SWT Interrupt
X
SCM Interrupt
X
Real Time Interrupt (RTI)
X
Any Enabled, Unmasked Interrupt in the
Interrupt Controller
X
$00 written to DOZE reg
X
DOZE bit cleared
(on a Peripheral-by-Peripheral basis)
X
X
Special Notes on Entering and Exiting Power Modes
When entering DOZE mode on the FlexCAN, I2C or SCI, care should be taken to insure that the
corresponding pin-side bus is stopped in a recessive state.
Because the ARM7 core has no DOZE (or similar) instruction, this functionality will be enabled via a
combination of software and hardware (Graceful Stop module). However, there are some “caveats” that
must be paid attention to:
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Special Notes on Entering and Exiting Power Modes
•
•
Disabling of interrupts between checking of task list (in a multi-tasking environment), and the
execution of the DOZE sequence. This is the responsibility of the software.
Disabling of interrupts during the DOZE sequence. This is the responsibility of the software.
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Special Notes on Entering and Exiting Power Modes
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Chapter 4
Signal Description
This section describes signals that connect off-chip. It includes pinout diagrams, a table of signal
properties, and detailed discussion of the signals.
4.1
Device Pinout
The MAC7200 family is available in 144-pin Quad Flat Package (LQFP), and 100-pin QFP options. The
family of devices offer pin-compatible packaged devices to assist with system development and
accommodate expansion of the application.
The MAC72xx device is offered in the following options:
• 144-pin LQFP package with 8 ATD channels.
• 144-pin LQFP package with 16 ATD channels.
• 100-pin LQFP package with 15 ATD channels.
Most pins perform two or more functions, which is described in more detail in Section 4.2, “Signal
Properties Summary”. Figure 4-1, Figure 4-2, Figure 4-3 show the package pin assignments for the
various packages.
NOTE
The 144LQFP packages are not currently qualified; any future qualification
will be based upon customer demand and will be subject to specified
leadtimes. This package option is supported for limited samples only, and
does not include burn-in testing.
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29
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PG[3]/MDO1/TXD_A
PG[2]/MDO0/RXD_A
PG[1]/TXD_B
PG[0]/RXD_B
PA[0]
PA[1]
PA[2]
PA[3]
PA[4]
PA[5]
PA[6]
TMS
TCK
TDO
TDI
VddX10
VssX10
VDD15a
VSS15a
VSS33a
VDD33
PD[6]
PD[5]
PC[15]/MDO7’
VddX4
VssX4
PD[10]
PD[9]
PG[15]/PCS3_B
PG[14]/PCS4_B
PE[7]/AN07
PE[6]/AN06
VSSA
VRL
VRH
VDDA
Device Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
MAC7212
PAC7212
144 LQFP
144LQFP
REFBYPC
PE[5]/AN05
PE[4]/AN04
PE[3]/AN03
PE[2]/AN02
PE[1]/AN01
PE[0]/AN00
PG[11]
PG[10]
PG[9]
PG[8]
PA[9]/EVTIn
VddX5
VssX5
PA[7]
PA[8]
PA[10]
PA[11]
PA[12]
PC[14]/MDO6’
PC[13]/MDO5’
PC[12]/MDO4’
PD[15]
PD[14]
PD[13]
PD[3]/NMI/XIRQn
PD[2]/CLKOUT/XCLKSn
PB[12]/PCS1_B
VddX3
VssX3
PD[4]/IRQn
PB[15]/MDO7/SIN_B
PB[11]/MDO4/PCS2_B
PB[14]/MDO6/SOUT_B
PB[10]/PCS5_B/PCSS_B
PB[13]/MDO5/SCK_B
eMIOS05/PF[5]
eMIOS04/PF[4]
eMIOS03/PF[3]
eMIOS02/PF[2]
eMIOS01/PF[1]
eMIOS00/PF[0]
MDO0’/PC[8]
MDO1’/PC[9]
MDO2’/PC[10]
MDO3’/PC[11]
RESETn
VssX2
VddX2
PCS4_A/PG[12]
PCS3_A/PG[13]
VDD15c
VSS15c
VPP
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
VssX8
VddX8
PA[15]
PA[14]
PA[13]
VddX9
PD[11]
PD[12]
MODB/PD[0]
MODA/PD[1]
MDO3/PCS0_B/SS_B/PB[9]
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
MDO2/CNTX_A/PG[4]
CNRX_A/PG[5]
CNTX_B/PG[6]
CNRX_B/PG[7]
PC[0]
PC[1]
PC[2]
EVTIn’/PC[3]
VssX7
VddX7
MCKO/SDA/PB[0]
EVTOn/SCL/PB[1]
MSEOn/SIN_A/PB[2]
PCS0_A/SS_A/PB[5]
RDYn/SOUT_A/PB[3]
PCS1_A/PB[6]
SCK_A/PB[4]
PCS2_A/PB[7]
VssX1
VddX1
PCS5_A/PCSS_A/PB[8]
SIN_C/PF[15]
PCS0_C/SS_C/PF[14]
SOUT_C/PF[13]
PCS1_C/PF[12]
MCKO’/PC[4]
EVTOn’/PC[5]
MSEOn’/PC[6]
RDYn’/PC[7]
VssX6
SCK_C/PF[11]
PCS2_C/PF[10]
eMIOS07/PF[7]
PCS3_C/PF[9]
eMIOS06/PF[6]
PCS5_C/PCSS_C/PF[8]
Secondary Mux function provides DSPI_B Chip Select 3 on pin PA[9]
Secondary Mux function provides DSPI_B Chip Select 4 on pin PA[8]
Figure 4-1. PAC7211/PAC7212 Pin Assignment, 144 QFP
NOTE
The 144LQFP packages are not currently qualified; any future qualification
will be based upon customer demand and will be subject to specified
leadtimes. This package option is supported for limited samples only, and
does not include burn-in testing.
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144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PG[3]/MDO1/TXD_A
PG[2]/MDO0/RXD_A
PG[1]/TXD_B
PG[0]/RXD_B
PA[0]
PA[1]
PA[2]
PA[3]
PA[4]
PA[5]
PA[6]
TMS
TCK
TDO
TDI
VddX10
VssX10
VDD15a
VSS15a
VSS33a
VDD33
PD[6]
PD[5]
PC[15]/MDO7’
VddX4
VssX4
PE[11]/AN11
PE[10]/AN10
PE[9]/AN09
PE[8]/AN08
PE[7]/AN07
PE[6]/AN06
VSSA
VRL
VRH
VDDA
Device Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PAC7202
MAC7202
144
LQFP
144LQFP
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
REFBYPC
PE[5]/AN05
PE[4]/AN04
PE[3]/AN03
PE[2]/AN02
PE[1]/AN01
PE[0]/AN00
PE[15]/AN15
PE[14]/AN14
PE[13]/AN13
PE[12]/AN12
PA[9]/EVTIn
VddX5
VssX5
PA[7]
PA[8]
PA[10]
PA[11]
PA[12]
PC[14]/MDO6’
PC[13]/MDO5’
PC[12]/MDO4’
PD[15]
PD[14]
PD[13]
PD[3]/NMI/XIRQn
PD[2]/CLKOUT/XCLKSn
PB[12]/PCS1_B
VddX3
VssX3
PD[4]/IRQn
PB[15]/MDO7/SIN_B
PB[11]/MDO4/PCS2_B
PB[14]/MDO6/SOUT_B
PB[10]/PCS5_B/PCSS_B
PB[13]/MDO5/SCK_B
eMIOS05/PF[5]
eMIOS04/PF[4]
eMIOS03/PF[3]
eMIOS02/PF[2]
eMIOS01/PF[1]
eMIOS00/PF[0]
MDO0’/PC[8]
MDO1’/PC[9]
MDO2’/PC[10]
MDO3’/PC[11]
RESETn
VssX2
VddX2
PCS4_A/PG[12]
PCS3_A/PG[13]
VDD15c
VSS15c
VPP
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
VssX8
VddX8
PA[15]
PA[14]
PA[13]
VddX9
PD[11]
PD[12]
MODB/PD[0]
MODA/PD[1]
MDO3/PCS0_B/SS_B/PB[9]
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
MDO2/CNTX_A/PG[4]
CNRX_A/PG[5]
CNTX_B/PG[6]
CNRX_B/PG[7]
PC[0]
PC[1]
PC[2]
EVTIn’/PC[3]
VssX7
VddX7
MCKO/SDA/PB[0]
EVTOn/SCL/PB[1]
MSEOn/SIN_A/PB[2]
PCS0_A/SS_A/PB[5]
RDYn/SOUT_A/PB[3]
PCS1_A/PB[6]
SCK_A/PB[4]
PCS2_A/PB[7]
VssX1
VddX1
PCS5_A/PCSS_A/PB[8]
SIN_C/PF[15]
PCS0_C/SS_C/PF[14]
SOUT_C/PF[13]
PCS1_C/PF[12]
MCKO’/PC[4]
EVTOn’/PC[5]
MSEOn’/PC[6]
RDYn’/PC[7]
VssX6
SCK_C/PF[11]
PCS2_C/PF[10]
eMIOS07/PF[7]
PCS3_C/PF[9]
eMIOS06/PF[6]
PCS5_C/PCSS_C/PF[8]
Secondary Mux function provides DSPI_B Chip Select 3 on pin PA[9]
Secondary Mux function provides DSPI_B Chip Select 4 on pin PA[8]
Figure 4-2. PAC7201/PAC7202 Pin Assignment, 144 QFP
NOTE
The 144LQFP packages are not currently qualified; any future qualification
will be based upon customer demand and will be subject to specified
leadtimes. This package option is supported for limited samples only, and
does not include burn-in testing.
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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MAC7242
MAC7242
100
LQFP
100LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
REFBYPC
PE[5]/AN05
PE[4]/AN04
PE[3]/AN03
PE[2]/AN02
PE[1]/AN01
PE[0]/AN00
PE[14]/AN14
PE[13]/AN13
PE[12]/AN12
PA[9]/EVTIn
VddX5
VssX5
PA[8]
PD[3]/NMI/XIRQn
PD[2]/CLKOUT/XCLKSn
PB[12]/PCS1_B
VddX3
VssX3
PB[15]/MDO7/SIN_B
PB[11]/MDO4/PCS2_B
PB[14]/MDO6/SOUT_B
PB[10]/PCS5_B/PCSS_B
PB[13]/MDO5/SCK_B
PB[9]/MDO3/PCS0_B/SS_B
eMIOS05/PF[5]
eMIOS04/PF[4]
eMIOS03/PF[3]
eMIOS02/PF[2]
eMIOS01/PF[1]
eMIOS00/PF[0]
RESETn
VssX2
VddX2
PCS4_A/PG[12]
PCS3_A/PG[13]
VDD15c
VSS15c
VPP
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
PA[15]
PD[11]
MODB/PD[0]
MODA/PD[1]
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
MDO2/CNTX_A/PG[4]
CNRX_A/PG[5]
CNTX_B/PG[6]
CNRX_B/PG[7]
MCKO/SDA/PB[0]
EVTOn/SCL/PB[1]
MSEOn/SIN_A/PB[2]
PCS0_A/SS_A/PB[5]
RDYn/SOUT_A/PB[3]
PCS1_A/PB[6]
SCK_A/PB[4]
PCS2_A/PB[7]
VssX1
VddX1
PCS5_A/PCSS_A/PB[8]
SIN_C/PF[15]
PCS0_C/SS_C/PF[14]
SOUT_C/PF[13]
PCS1_C/PF[12]
SCK_C/PF[11]
PCS2_C/PF[10]
eMIOS07/PF[7]
PCS3_C/PF[9]
eMIOS06/PF[6]
PCS5_C/PCSS_C/PF[8]
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PG[3]/MDO1/TXD_A
PG[2]/MDO0/RXD_A
PG[1]/TXD_B
PG[0]/RXD_B
TMS
TCK
TDO
TDI
VDD15a
VSS15a
VSS33a
VDD33
PD[6]
VddX4
VssX4
PE[11]/AN11
PE[10]/AN10
PE[9]/AN09
PE[8]/AN08
PE[7]/AN07
PE[6]/AN06
VSSA
VRL
VRH
VDDA
Device Pinout
Secondary Mux function provides DSPI_B Chip Select 3 on pin PA[9]
Secondary Mux function provides DSPI_B Chip Select 4 on pin PA[8]
Figure 4-3. MAC7241/MAC7242 Pin assignments, 100 Pin LQFP package
MAC7200 Microcontroller Family Reference Manual, Rev. 2
32
Freescale Semiconductor
Signal Properties Summary
4.2
Signal Properties Summary
Table 4-1 summarizes the pin functionality. on the MAC72xx devices.
Table 4-1. Signal Properties
Pin Name Pin Name Pin Name Pin Name Pin Name Power
Func. 1
Func. 2
Func. 3
Func. 4
Func. 5
Supply
Internal Pull
Resistor
Description
Ctrl
Reset
State
EXTAL
—
—
—
—
VDDPLL
NA
NA
Oscillator pins
XTAL
—
—
—
—
VDDPLL
NA
NA
XFC
—
—
—
—
VDDPLL
NA
NA
RESET
—
—
—
—
VDDx
Pulldown
TEST1
—
—
—
—
NA
—
—
Test Input
TCK
—
—
—
—
VDDx
PIM
Pulldown
JTAG TCK
TMS
—
—
—
—
VDDx
PIM
Pull-up
JTAG TMS
TDI
—
—
—
—
VDDx
PIM
Pull-up
JTAG TDI
TDO
—
—
—
—
VDDx
—
—
JTAG TDO
PA02
DATA[0]
SCITXD_A
None
—
VDDx
PIM
Disabled Port A0, External Data bus, eSCI_A serial
transmit data
PA12
DATA[1]
SCIRXD_A
None
—
VDDx
PIM
Disabled Port A1, External Data bus, eSCI_A serial
receive data
PA22
DATA[2]
None
None
—
VDDx
PIM
Disabled Port A2, External Data bus
PA32
DATA[3]
None
None
—
VDDx
PIM
Disabled Port A3, External Data bus
PA42
DATA[4]
None
None
—
VDDx
PIM
Disabled Port A4, External Data bus
PA52
DATA[5]
None
None
—
VDDx
PIM
Disabled Port A5, External Data bus
PA62
DATA[6]
None
None
—
VDDx
PIM
Disabled Port A6, External Data bus
PA72
DATA[7]
None
None
—
VDDx
PIM
Disabled Port A7, External Data bus
PA82
None
PCS4_B
None
—
VDDx
PIM
Disabled Port A8, DSPI_B chip select
PA92
None
PCS3_B
None
EVTI3
VDDx
PIM
Disabled Port A9, DSPI_B chip select, Nexus Event In
PA102
None
PCS3_B
None
—
VDDx
PIM
Disabled Port A10, DSPI_B chip select
PA112
None
None
None
—
VDDx
PIM
Disabled Port A11
PA122
None
None
None
—
VDDx
PIM
Disabled Port A12
PA132
None
None
None
—
VDDx
PIM
Disabled Port A13
PA142
None
None
None
—
VDDx
PIM
Disabled Port A14
PA152
None
None
None
—
VDDx
PIM
Disabled Port A15
PLL Loop Filter
Disabled External Reset
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
33
Signal Properties Summary
Table 4-1. Signal Properties
Pin Name Pin Name Pin Name Pin Name Pin Name Power
Func. 1
Func. 2
Func. 3
Func. 4
Func. 5
Supply
Internal Pull
Resistor
Description
Ctrl
Reset
State
PB0
SDA
PCS0_A
SS_A
None
MCKO3
VDDx
PIM
Disabled Port B0, IIC serial data, DSPI_A chip
select/slave select, Nexus Clock Out
PB1
SCL
PCS1_A
None
EVTO3
VDDx
PIM
Disabled Port B1, IIC serial data, DSPI_A chip select,
Nexus Event Out
PB2
MISO_A
None
None
MSEO3
VDDx
PIM
Disabled Port B2, DSPI_A serial data, Nexus Message
Start/End Out
PB3
MOSI_A
SCL
None
RDY3
VDDx
PIM
Disabled Port B3, DSPI_A serial data, IIC serial data
PB4
SCK_A
MOSI_A
None
—
VDDx
PIM
Disabled Port B4, DSPI_A serial clock, DSPI_A serial
data
PB5
PCS0_A
SS_A
SDA
None
—
VDDx
PIM
Disabled Port B5, DSPI_A chip select/slave select, IIC
serial data
PB6
PCS1_A
MISO_A
None
—
VDDx
PIM
Disabled Port B6, DSPI_A chip select, DSPI_A serial
data
PB7
PCS2_A
SCK_A
None
—
VDDx
PIM
Disabled Port B7, DSPI_A chip select, DSPI_A serial
clock
PB8
PCS5_A
PCS0_A
SS_A
PCS2_A
—
VDDx
PIM
Disabled Port B8, DSPI_A chip select, DSPI_A chip
select/slave select, DSPI_A chip select
PB9
PCS0_B
SS_B
None
CNTXD_A
MDO33
VDDx
PIM
Disabled Port B9, DSPI_B chip select/slave select,
CAN_A serial transmit data, Nexus Message
Data Out
PB10
PCS5_B
PCSS_B
PCS2_B
CNTXD_B
—
VDDx
PIM
Disabled Port B10, DSPI_B chip select, DSPI_B chip
select, CAN_B serial transmit data
PB11
PCS2_B
SCK_B
SDA
MDO43
VDDx
PIM
Disabled Port B11, DSPI_B chip select, DSPI_B serial
clock, IIC serial data, Nexus Message Data
Out
PB12
PCS1_B
MISO_B
None
—
VDDx
PIM
Disabled Port B12, DSPI_B chip select, DSPI_B serial
data
PB13
SCK_B
PCS5_B
PCSS_B
CNRXD_A
MDO53
VDDx
PIM
Disabled Port B13, DSPI_B serial clock, DSPI_B chip
select, CAN_A serial receive data, Nexus
Message Data Out
PB14
MOSI_B
PCS1_B
CNRXD_B
MDO63
VDDx
PIM
Disabled Port B14, DSPI_B serial data, DSPI_B chip
select, CAN_B serial receive data, Nexus
Message Data Out
PB15
MISO_B
MOSI_B
SCL
MDO73
VDDx
PIM
Disabled Port B15, DSPI_B serial data, DSPI_B serial
data, IIC serial data, Nexus Message Data
Out
PC02
ADDR[0]
CNTXD_A
None
—
VDDx
PIM
Disabled Port C0, External Address bus, CAN_A serial
transmit data
MAC7200 Microcontroller Family Reference Manual, Rev. 2
34
Freescale Semiconductor
Signal Properties Summary
Table 4-1. Signal Properties
Pin Name Pin Name Pin Name Pin Name Pin Name Power
Func. 1
Func. 2
Func. 3
Func. 4
Func. 5
Supply
Internal Pull
Resistor
Description
Ctrl
Reset
State
PC12
ADDR[1]
CNRXD_A
None
—
VDDx
PIM
Disabled Port C1, External Address bus, CAN_A serial
receive data
PC22
ADDR[2]
CNTXD_B
None
—
VDDx
PIM
Disabled Port C2, External Address bus, CAN_B serial
transmit data
PC32
ADDR[3]
CNRXD_B
None
EVTI4
VDDx
PIM
Disabled Port C3, External Address bus, CAN_B serial
receive data, Nexus Event In
PC42
ADDR[4]
EMIOS[6]
None
MCKO4
VDDx
PIM
Disabled Port C4, External Address bus, eMIOS
Channel, Nexus Message Clock Out
PC52
ADDR[5]
EMIOS[7]
None
EVTO4
VDDx
PIM
Disabled Port C5, External Address bus, eMIOS
Channel, Nexus Event Out
PC62
ADDR[6]
None
None
MSEO4
VDDx
PIM
Disabled Port C6, External Address bus, Nexus
Message Start/End Out
PC72
ADDR[7]
None
None
RDY4
VDDx
PIM
Disabled Port C7, External Address bus, Nexus Ready
PC82
ADDR[8]
EMIOS[0]
None
MDO04
VDDx
PIM
Disabled Port C8, External Address bus, eMIOS
Channel, Nexus Message Data Out
PC92
ADDR[9]
None
None
MDO14
VDDx
PIM
Disabled Port C9, External Address bus, Nexus
Message Data Out
PC102
ADDR[10]
None
None
MDO24
VDDx
PIM
Disabled Port C10, External Address bus,
PC112
ADDR[11]
None
None
MDO34
VDDx
PIM
Disabled Port C11, External Address bus, Nexus
Message Data Out
PC122
ADDR[12]
None
None
MDO44
VDDx
PIM
Disabled Port C12, External Address bus, Nexus
Message Data Out
PC132
ADDR[13]
None
None
MDO54
VDDx
PIM
Disabled Port C13, External Address bus, Nexus
Message Data Out
PC142
ADDR[14]
None
None
MDO64
VDDx
PIM
Disabled Port C14, External Address bus, Nexus
Message Data Out
PC152
ADDR[15]
None
None
MDO74
VDDx
PIM
Disabled Port C15, External Address bus, Nexus
Message Data Out
PD02
BS0
PCS4_B
None
MODB
VDDx
PIM
Disabled Port D0, External Bus Byte Select, DSPI_B
chip select, Chip Mode select
PD12
BS1
PCS3_B
None
MODA
VDDx
PIM
Disabled Port D1, External Bus Byte Select, DSPI_B
chip select, Chip Mode select
PD22
CLKOUT
None
None
XCLKS5
VDDx
PIM
Disabled Port D2, External Bus Clock, Oscillator mode
select
PD3
XIRQ
None
None
NMI
VDDx
PIM
Disabled Port D3, External interrupt, Non-Maskable
Interrupt
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
35
Signal Properties Summary
Table 4-1. Signal Properties
Pin Name Pin Name Pin Name Pin Name Pin Name Power
Func. 1
Func. 2
Func. 3
Func. 4
Func. 5
Supply
Internal Pull
Resistor
Description
Ctrl
Reset
State
PD4
IRQ
BURST
None
—
VDDx
PIM
Disabled Port D4, External Interrupt, External Bus
Burst
PD52
ADDR[16]
None
None
—
VDDx
PIM
Disabled Port D5, External Address bus
PD62
ADDR[17]
None
None
—
VDDx
PIM
Disabled Port D6, External Address bus
PD72
ADDR[20]
None
None
—
VDDx
PIM
Disabled Port D7, External Address bus
PD82
ADDR[21]
TA
None
—
VDDx
PIM
Disabled Port D8, External Address bus, External Bus
Transfer Acknowledge
PD92
ADDR[18]
None
None
—
VDDx
PIM
Disabled Port D9, External Address bus
PD102
ADDR[19]
TA
None
—
VDDx
PIM
Disabled Port D10, External Address bus, External Bus
Transfer Acknowledge
PD112
OE
None
None
—
VDDx
PIM
Disabled Port D11, External Bus Output Enable
PD122
BURST
CS2
None
—
VDDx
PIM
Disabled Port D12, External Bus Burst, External Bus
Chip Select
PD132
TA
CS1
None
—
VDDx
PIM
Disabled Port D13, External Bus Transfer
Acknowledge, External Bus Chip Select
PD142
CS0
None
None
—
VDDx
PIM
Disabled Port D14, External Bus Chip Select
PD152
RW
None
None
—
VDDx
PIM
Disabled Port D15, External Bus Read/Write
PE06
AN_00
None
None
—
VDDA
PIM
Disabled Port E0, ATD Channel
PE16
AN_01
None
None
—
VDDA
PIM
Disabled Port E1, ATD Channel
PE26
AN_02
None
None
—
VDDA
PIM
Disabled Port E2, ATD Channel
PE36
AN_03
None
None
—
VDDA
PIM
Disabled Port E3, ATD Channel
PE46
AN_04
None
None
—
VDDA
PIM
Disabled Port E4, ATD Channel
PE56
AN_05
None
None
—
VDDA
PIM
Disabled Port E5, ATD Channel
PE66
AN_06
None
None
—
VDDA
PIM
Disabled Port E6, ATD Channel
PE76
AN_07
None
None
—
VDDA
PIM
Disabled Port E7, ATD Channel
PE86
AN_08
None
None
—
VDDA
PIM
Disabled Port E8, ATD Channel
PE96
AN_09
None
None
—
VDDA
PIM
Disabled Port E9, ATD Channel
PE106
AN_10
None
None
—
VDDA
PIM
Disabled Port E10, ATD Channel
PE116
AN_11
None
None
—
VDDA
PIM
Disabled Port E11, ATD Channel
PE126
AN_12
None
None
—
VDDA
PIM
Disabled Port E12, ATD Channel
PE136
AN_13
None
None
—
VDDA
PIM
Disabled Port E13, ATD Channel
PE146
AN_14
None
None
—
VDDA
PIM
Disabled Port E14, ATD Channel
MAC7200 Microcontroller Family Reference Manual, Rev. 2
36
Freescale Semiconductor
Signal Properties Summary
Table 4-1. Signal Properties
Pin Name Pin Name Pin Name Pin Name Pin Name Power
Func. 1
Func. 2
Func. 3
Func. 4
Func. 5
Supply
Internal Pull
Resistor
Description
Ctrl
Reset
State
PE156
AN_15
None
None
—
VDDA
PIM
PF0
EMIOS[0]
None
None
—
VDDx
PIM
Port F0, eMIOS Channel, Debug Status Port,
Nexus Port Select
PF1
EMIOS[1]
None
None
—
VDDx
PIM
Port F1, eMIOS Channel, Debug Status Port,
Nexus Present
PF2
EMIOS[2]
None
None
—
VDDx
PIM
Port F2, eMIOS Channel, Debug Status Port,
External Bus Auto Acknowledge
PF3
EMIOS[3]
None
None
—
VDDx
PIM
Port F3, eMIOS Channel, Debug Status Port,
External Bus Port Size
PF4
EMIOS[4]
None
None
—
VDDx
PIM
Disabled Port F4, eMIOS Channel, Debug Status Port
PF5
EMIOS[5]
None
PCS5_C
PCSS_C
—
VDDx
PIM
Disabled Port F5, eMIOS Channel, DSPI_C chip
select, Debug Status Port
PF6
EMIOS[6]
None
PCS2_C
—
VDDx
PIM
Disabled Port F6, eMIOS Channel, DSPI_C chip
select, Debug Status Port
PF7
EMIOS[7]
None
PCS0_C
SS_C
—
VDDx
PIM
Disabled Port F7, eMIOS Channel, DSPI_C chip
select/slave select, Debug Status Port
PF8
PCS5_C
PCSS_C
EMIOS[7]
PCS3_C
—
VDDx
PIM
Disabled Port F8, DSPI_C chip select, eMIOS
Channel, DSPI_C chip select
PF9
PCS3_C
EMIOS[1]
PCS1_C
—
VDDx
PIM
Disabled Port F9, DSPI_C chip select, eMIOS
Channel, DSPI_C chip select
PF10
PCS2_C
EMIOS[3]
SCK_C
—
VDDx
PIM
Disabled Port F10, DSPI_C chip select, eMIOS
Channel, DSPI_C serial clock
PF11
SCK_C
EMIOS[4]
MOSI_C
—
VDDx
PIM
Disabled Port F11, DSPI_C serial clock, eMIOS
Channel, DSPI_C serial data
PF12
PCS1_C
EMIOS[5]
MISO_C
—
VDDx
PIM
Disabled Port F12, DSPI_C chip select, eMIOS
Channel, DSPI_C serial data
PF13
MOSI_C
PCS5_A
PCSS_A
EMIOS[6]
—
VDDx
PIM
Disabled Port F13, DSPI_C serial data, DSPI_A chip
select, eMIOS Channel
PF14
PCS0_C
SS_C
PCS2_A
EMIOS[7]
—
VDDx
PIM
Disabled Port F14, DSPI_C chip select/slave select,
DSPI_A chip select, eMIOS Channel
PF15
MISO_C
PCS1_A
PCS5_A
PCSS_A
—
VDDx
PIM
Disabled Port F15, DSPI_C serial data, DSPI_A chip
select, DSPI_A chip select
Disabled Port E15, ATD Channel
PG0
SCIRXD_B CNRXD_B
None
—
VDDx
PIM
Disabled Port G0, eSCI_B serial receive data, CAN_B
serial receive data
PG1
SCITXD_B
None
—
VDDx
PIM
Disabled Port G1, eSCI_B serial transmit data, CAN_B
serial transmit data
CNTXD_B
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
37
Signal Properties Summary
Table 4-1. Signal Properties
Pin Name Pin Name Pin Name Pin Name Pin Name Power
Func. 1
Func. 2
Func. 3
Func. 4
Func. 5
Supply
Internal Pull
Resistor
Description
Ctrl
Reset
State
PG2
SCIRXD_A CNRXD_A
None
MDO03
VDDx
PIM
Disabled Port G2, eSCI_A serial receive data, CAN_A
serial receive data, Nexus Message Data Out
PG3
SCITXD_A
CNTXD_A
None
MDO13
VDDx
PIM
Disabled Port G3, eSCI_A serial transmit data, CAN_A
serial transmit data, Nexus Message Data
Out
PG4
CNTXD_A
SCITXD_A
None
MDO23
VDDx
PIM
Disabled Port G4, CAN_A serial transmit data, eSCI_A
serial transmit data, Nexus Message Data
Out
PG5
CNRXD_A SCIRXD_A
None
—
VDDx
PIM
Disabled Port G5, CAN_A serial receive data, eSCI_A
serial receive data
PG6
CNTXD_B
SCITXD_B
None
—
VDDx
PIM
Disabled Port G6, CAN_B serial transmit data, eSCI_B
serial transmit data
PG7
CNRXD_B SCIRXD_B
None
—
VDDx
PIM
Disabled Port G7, CAN_B serial transmit data, eSCI_B
serial receive data
PG8
CS1
None
None
—
VDDx
PIM
Disabled Port G8, External Bus Chip Select
PG9
CS2
None
None
—
VDDx
PIM
Disabled Port G9, External Bus Chip Select
PG10
None
None
None
—
VDDx
PIM
Disabled Port G10
PG11
None
None
None
—
VDDx
PIM
Disabled Port G11
PG12
PCS4_A
SCIRXD_A SCIRXD_B
—
VDDx
PIM
Disabled Port G12, DSPI_A chip select, eSCI_A serial
receive data, eSCI_B serial receive data
PG13
PCS3_A
SCITXD_A SCITXD_B
—
VDDx
PIM
Disabled Port G13, DSPI_A chip select, eSCI_A serial
transmit data, eSCI_B serial transmit data
PG14
PCS4_B
None
None
—
VDDx
PIM
Disabled Port G14, DSPI_B chip select
PG15
PCS3_B
None
None
—
VDDx
PIM
Disabled Port G15, DSPI_B chip select
1. This pin must always be tied to VSS in user mode.
2. This pin has Function 2 automatically selected when the chip is booted into External Chip mode.
3. Nexus Primary Port
4. Nexus Secondary Port
5. This functionality is for Hardware Configuration only, and therefore active only during reset.
6. No General Purpose Output (GPO) functionality is available on this pin
MAC7200 Microcontroller Family Reference Manual, Rev. 2
38
Freescale Semiconductor
Detailed Signal Descriptions
4.3
4.3.1
Detailed Signal Descriptions
EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the crystal driver and external clock pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output. When the XCLKS pin is driven low, an
external 3.3V clock signal can be driven in on the EXTAL pin directly. Otherwise, the XCLKS pin must
be driven high until after the RESET pin has been negated.
4.3.2
RESET — External Reset Pin
An open drain, active low bidirectional control signal, it acts as an input to initialize the MCU to a known
start-up state, and an output when an internal MCU function causes a Reset. A pull-down resistor can be
activated on this pin. This allows the device to enter reset when the connection to an external reset source
is lost. This resistor is implemented using active elements, and is approximately equivalent to a 20KOhm
resistor under typical operating conditions.
VDD
Pin
P
N
N
Open Drain
Output Buffer
Input Buffer
Figure 4-4. Bidirectional Open Drain Pin
4.3.3
XFC — PLL Loop Filter Pin
The XFC pin allows the user to specify the external PLL loop filter components to modify the PLLs
response rate and stability. Please refer to Chapter 23, “Clock and Reset Generator (CRG)” for more
details on this pin and for the calculation of the component values.
XFC
R0
CP
MCU
CS
VDDPLL
VDDPLL
Figure 4-5. PLL Loop Filter Connections
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
39
Detailed Signal Descriptions
4.3.4
TDI — Test Data In Pin
The TDI pin is a device input for the JTAG port. This serial pin is sampled in the device on the rising edge
of the TCK pin. During and after a system reset, this pin will be configured as an input with an internal
pull-up active on this signal. This pull-up is implemented using active elements, and is approximately
equivalent to a 20KOhm resistor under typical operating conditions.
4.3.5
TDO — Test Data Output Pin
The TDO pin is a device output for the JTAG port. This pin is a three-state test data output pin that is
actively driven in the shift-IR and shift-DR controller states. The pin state changes on the falling edge of
the TCK pin. During and after a system reset, this pin will be configured as an output with maximum slew
rate enabled.
4.3.6
TCK — Test Clock Pin
The TCK pin is a device input for the JTAG port. This pin provides the test clock input to synchronize the
device’s test logic. TCK is independent of the processor clock, and is used only as the reference clock for
the TMS, TDI and TDO pins. During and after a system reset, this pin will be configured as an input with
an internal pull-down active on this signal. This pull-down is implemented using active elements, and is
approximately equivalent to a 20KOhm resistor under typical operating conditions.
4.3.7
TMS — Test Mode Pin
The TMS pin is a device input for the JTAG port. This pin is used to input the test mode to sequence the
TAP controller’s state machine. The pin is sampled on the rising edge of the TCK pin. During and after a
system reset, this pin will be configured as an input with an internal pull-up active on this signal. This
pull-up is implemented using active elements, and is approximately equivalent to a 20KOhm resistor under
typical operating conditions.
4.3.8
PA[0:7] / DATA[0:7] — Port A I/O Pins and external Databus
PA[0] to PA[7] are configurable general purpose input or output pins. They can be independently
configured to provide either high or reduced output drive, and also to enable or disable either a pull-up or
pull-down resistor on the pin. The pin is multiplexed with the external Data bus lines DATA[0] to
DATA[7]. Each pin can be independently configured to wake the system out of low-power mode (DOZE)
when an external signal is applied using the interrupt functionality.
4.3.9
PA[8] / DATA[8] / PCS[4] — Port A I/O Pin, External Databus, and
DSPI_B
PA[8] is a configurable general purpose input or output pin. It can be independently configured to provide
either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on
the pin. The pin is multiplexed in Primary Peripheral mode with the external Data bus line DATA[8]. In
Secondary Peripheral mode, it can be configured as a chip select pin PCS[4] when in Master mode for the
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Serial Peripheral Interface B (DSPI_B). It can be configured to wake the system out of low-power mode
(DOZE) when an external signal is applied using the interrupt functionality.
4.3.10
PA[9] / DATA[9] / PCS[3] / NEX1EVTI — Port A I/O Pin, External
Databus, DSPI_B and Nexus Primary
PA[9] is a configurable general purpose input or output pin. It can be independently configured to provide
either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on
the pin. The pin is multiplexed in Primary Peripheral mode with the external Data bus line DATA[9]. In
Secondary Peripheral mode, it can be configured as a chip select pin PCS[3] when in Master mode for the
Serial Peripheral Interface B (DSPI_B). It can be configured to wake the system out of low-power mode
(DOZE) when an external signal is applied using the interrupt functionality. When the Nexus Primary Port
is selected and active, this pin is used as the Event In input.
4.3.11
PA[10:15] / DATA[10:15] — Port A I/O Pins and external Databus
PA[10] to PA[15] are configurable general purpose input or output pins. They can be independently
configured to provide either high or reduced output drive, and also to enable or disable either a pull-up or
pull-down resistor on the pin. The pin is multiplexed with the external Data bus lines DATA[10] to
DATA[15]. Each pin can be independently configured to wake the system out of low-power mode (DOZE)
when an external signal is applied using the interrupt functionality.
4.3.12
PB[0] / SDA / NEX1MCKO — Port B I/O Pin, IIC and Nexus Primary
PB[0] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The port pin is multiplexed with the bidirectional IIC serial data pin.
It can be configured to wake the system out of low-power mode (DOZE) when an external signal is applied
using the interrupt functionality. When the Nexus Primary Port is selected and active, this pin is used as
the Nexus Clock output.
4.3.13
PB[1] / SCL / NEX1EVTO — Port B I/O Pin, IIC and Nexus Primary
PB[1] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The port pin is multiplexed with the bidirectional IIC serial clock
pin used to provide the time base for transfers. It can be configured to wake the system out of low-power
mode (DOZE) when an external signal is applied using the interrupt functionality. When the Nexus
Primary Port is selected and active, this pin is used as the Nexus Event Out output.
4.3.14
PB[2] / SIN_A / NEX1MSEO — Port B I/O Pin, DSPI_A and Nexus
Primary
PB[2] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
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Detailed Signal Descriptions
either an open drain or push-pull pad. The pin can be configured as the input pin of the Serial Peripheral
Interface A (DSPI_A). It can be configured to wake the system out of low-power mode (DOZE) when an
external signal is applied using the interrupt functionality. When the Nexus Primary Port is selected and
active, this pin is used as the Nexus Message Start/End output.
4.3.15
PB[3] / SOUT_A / NEX1RDY — Port B I/O Pin, DSPI_A and Nexus
Primary
PB[3] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as the output pin of the Serial Peripheral
Interface A (DSPI_A). It can be configured to wake the system out of low-power mode (DOZE) when an
external signal is applied using the interrupt functionality. When the Nexus Primary Port is selected and
active, this pin is used as the Nexus Ready output.
4.3.16
PB[4] / SCK_A — Port B I/O Pin and DSPI_A
PB[4] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as serial clock pin SCK of the Serial
Peripheral Interface A (DSPI_A). It can be configured to wake the system out of low-power mode (DOZE)
when an external signal is applied using the interrupt functionality.
4.3.17
PB[5] / PCS[0] / SS[0] — Port B I/O Pin and DSPI_A
PB[5] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as chip select pin PCS[0] when in Master
mode, or as slave select pin SS when in Slave mode for the Serial Peripheral Interface A (DSPI_A). It can
be configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality.
4.3.18
PB[6:7] / PCS[1:2] — Port B I/O Pin and DSPI_A
PB[6] - PB[7] are configurable general purpose input or output pins. They can be configured to provide
either high or reduced output drives, to enable or disable either a pull-up or pull-down resistor on the pins
or to provide either open drain or push-pull pads. The pins can be configured as chip select pin PCS[1:2]
when in Master mode for the Serial Peripheral Interface A (DSPI_A). Each pin can be independently
configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality.
4.3.19
PB[8] / PCS[5] / PCSS — Port B I/O Pin and DSPI_A
PB[8] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
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Detailed Signal Descriptions
either an open drain or push-pull pad. The pin can be configured as chip select pin PCS[5] when in Master
mode for the Serial Peripheral Interface A (DSPI_A), or as a Peripheral Chip Select Strobe to qualify the
other Chip Select signals to eliminate any decoding glitches. Each pin can be independently configured to
wake the system out of low-power mode (DOZE) when an external signal is applied using the interrupt
functionality.
4.3.20
PB[9] / PCS0 / SS[1] / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus
Primary
PB[9] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as chip select pin PCS[0] when in Master
mode, or as slave select pin SS when in Slave mode for the Serial Peripheral Interface B (DSPI_B). After
Reset the pin is able to be used as the General purpose input or output PB9, or as a DSPI_B control line.
This pin can be configured to wake the system out of low-power mode (DOZE) when an external signal
is applied using the interrupt functionality. When the Nexus Primary Port is selected and active, this pin is
used as a Message Data Out output.
4.3.21
PB[10] / PCS[5] / PCSS — Port B I/O Pin and DSPI_B
PB[10] is a configurable general purpose input or output pin. It can be configured to provide either high
or reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as chip select pin PCS[5] when in Master
mode for the Serial Peripheral Interface B (DSPI_B), or as a Peripheral Chip Select Strobe to qualify the
other Chip Select signals to eliminate any decoding glitches. It can be configured to wake the system out
of low-power mode (DOZE) when an external signal is applied using the interrupt functionality.
4.3.22
PB[11] / PCS[2] / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus
Primary
PB[11] is a configurable general purpose input or output pin. It can be configured to provide either high
or reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as a chip select pin PCS[2] when in Master
mode for the Serial Peripheral Interface B (DSPI_B). It can be configured to wake the system out of
low-power mode (DOZE) when an external signal is applied using the interrupt functionality. When the
Nexus Primary Port is selected and active, this pin is used as a Message Data Out output.
4.3.23
PB[12] / PCS[1] — Port B I/O Pin and DSPI_B
PB[12] is a configurable general purpose input or output pin. It can be configured to provide either high
or reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide
either an open drain or push-pull pad. The pins can be configured as a chip select pin PCS[1] when in
Master mode for the Serial Peripheral Interface B (DSPI_B). It can be configured to wake the system out
of low-power mode (DOZE) when an external signal is applied using the interrupt functionality.
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4.3.24
PB[13] / SCK_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus
Primary
PB[13] is a configurable general purpose input or output pin. It can be configured to provide either high
or reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as serial clock pin SCK of the Serial
Peripheral Interface B (DSPI_B). It can be configured to wake the system out of low-power mode (DOZE)
when an external signal is applied using the interrupt functionality. When the Nexus Primary Port is
selected and active, this pin is used as a Message Data Out output.
4.3.25
PB[14] / SOUT_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus
Primary
PB[14] is a configurable general purpose input or output pin. It can be configured to provide either high
or reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as the output pin of the Serial Peripheral
Interface B (DSPI_B). It can be configured to wake the system out of low-power mode (DOZE) when an
external signal is applied using the interrupt functionality. When the Nexus Primary Port is selected and
active, this pin is used as a Message Data Out output.
4.3.26
PB[15] / SIN_B / NEX1MDO — Port B I/O Pin, DSPI_B and Nexus
Primary
PB[15] is a configurable general purpose input or output pin. It can be configured to provide either high
or reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as the input pin of the Serial Peripheral
Interface B (DSPI_B). It can be configured to wake the system out of low-power mode (DOZE) when an
external signal is applied using the interrupt functionality. When the Nexus Primary Port is selected and
active, this pin is used as a Message Data Out output.
4.3.27
PC[0:2] / ADDR[0:2] — Port C I/O Pins and External address bus
PC[0] to PC[2] are configurable general purpose input or output pins. The pins can be independently
configured to provide either high or reduced output drive, and also to enable or disable either a pull-up or
pull-down resistor on the pin. The pin is multiplexed with the external address bus lines Address 0 to
Address 2. Each pin can be independently configured to wake the system out of low-power mode (DOZE)
when an external signal is applied using the interrupt functionality.
4.3.28
PC[3] / ADDR[3] / NEX2EVTI — Port C I/O Pins, External Address Bus
and Nexus Secondary
PC[3] is a configurable general purpose input or output pin. It can be independently configured to provide
either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on
the pin. The pin is multiplexed with the external address bus line Address 3. Each pin can be independently
configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
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the interrupt functionality. When the Nexus Secondary Port is selected and active, this pin is used as an
Event In input.
4.3.29
PC[4] / ADDR[4] / NEX2MCKO — Port C I/O Pins, External Address
Bus and Nexus Secondary
PC[4] is a configurable general purpose input or output pin. It can be independently configured to provide
either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on
the pin. The pin is multiplexed with the external address bus line Address 3. Each pin can be independently
configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality. When the Nexus Secondary Port is selected and active, this pin is used as a
Message Clock output.
4.3.30
PC[5] / ADDR[5] / NEX2EVTO — Port C I/O Pins, External Address
Bus and Nexus Secondary
PC[5] is a configurable general purpose input or output pin. It can be independently configured to provide
either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on
the pin. The pin is multiplexed with the external address bus line Address 3. Each pin can be independently
configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality. When the Nexus Secondary Port is selected and active, this pin is used as a
Event Out output.
4.3.31
PC[6] / ADDR[6] / NEX2MSEO — Port C I/O Pins, External Address
Bus and Nexus Secondary
PC[6] is a configurable general purpose input or output pin. It can be independently configured to provide
either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on
the pin. The pin is multiplexed with the external address bus line Address 3. Each pin can be independently
configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality. When the Nexus Secondary Port is selected and active, this pin is used as a
Message Start/End output.
4.3.32
PC[7] / ADDR[7] / NEX2RDY — Port C I/O Pins, External Address Bus
and Nexus Secondary
PC[7] is a configurable general purpose input or output pin. It can be independently configured to provide
either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on
the pin. The pin is multiplexed with the external address bus line Address 3. Each pin can be independently
configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality. When the Nexus Secondary Port is selected and active, this pin is used as a
Nexus Ready output.
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4.3.33
PC[8:15] / ADDR[8:15] / MDO[0:7] — Port C I/O Pins, External
Address Bus and Nexus Secondary
PC[8] to PC[15] are configurable general purpose input or output pins. The pins can be independently
configured to provide either high or reduced output drive, and also to enable or disable either a pull-up or
pull-down resistor on the pin. The pin is multiplexed with the external address bus lines Address 8 to
Address 15. Each pin can be independently configured to wake the system out of low-power mode (DOZE)
when an external signal is applied using the interrupt functionality. When the Nexus Secondary Port is
selected and active, these pin are used as Message Data Out outputs.
4.3.34
PD[0] / BWE[0] / MODB — Port D I/O Pin, External Bus Control &
Mode Selection
PD[0] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. The state of this pin is latched at the rising edge of RESET to determine the operating mode of the
MCU. After Reset the pin is able to be used as the General purpose input or output PD[0], or as a byte
select/byte write enable line for devices connected to the external bus. It can be configured to wake the
system out of low-power mode (DOZE) when an external signal is applied using the interrupt
functionality.
4.3.35
PD[1] / BWE[1] / MODA — Port D I/O Pin, External Bus Control &
Mode Selection
PD[1] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. The state of this pin is latched at the rising edge of RESET to determine the operating mode of the
MCU. After Reset the pin is able to be used as the General purpose input or output PD[1], or as a byte
select/byte write enable line for devices connected to the external bus. It can be configured to wake the
system out of low-power mode (DOZE) when an external signal is applied using the interrupt
functionality.
4.3.36
PD[2] / CLKOUT / XCLKS — Clock Out and Oscillator Selection
PD[2] is a configurable general purpose input pin (Note that general purpose output functionality is not
available). The pin can be configured to enable or disable either a pull-up or pull-down resistor on the pin.
The state of this pin is latched at the rising edge of RESET. Note that, unlike the rest of the hardware
configuration pins, the XCLKS pin is not latched during every system reset. It is only latched during a
Power On Reset or during a reset after a loss of clock has occurred. After Reset the pin is able to be used
as the General purpose input PD[2], or as a system clock for devices connected to the external bus. It can
be configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality.
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4.3.37
PD[3] / XIRQ / NMI — Port D I/O Pin, High Priority Interrupt and
Non-maskable Interrupt
PD[3] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the high priority interrupt request input that provides a means of applying
asynchronous external interrupt requests. It can be configured to wake the system out of low-power mode
(DOZE) when an external signal is applied using the interrupt functionality. When the system is in NMI
mode, this pin is used exclusively for an external Non-Maskable Interrupt, and may not be used as a GPIO.
4.3.38
PD[4] / IRQ — Port D I/O Pin, and Maskable Interrupt
PD[4] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the low priority interrupt request input that provides a means of applying
asynchronous external interrupt requests. It can be configured to wake the system out of low-power mode
(DOZE) when an external signal is applied using the interrupt functionality.
4.3.39
PD[5:10] / ADDR[16:21] — Port D I/O Pins and External Address Bus
PD[5] to PD[10] are configurable general purpose input or output pins. They can be independently
configured to provide either high or reduced output drives, and also to enable or disable either a pull-up or
pull-down resistor on the pins. The pin is multiplexed with the external address bus lines Address 16 to
Address 21. Each pin can be independently configured to wake the system out of low-power mode (DOZE)
when an external signal is applied using the interrupt functionality.
4.3.40
PD[11] / OE — Port D I/O Pin and External Bus Control
PD[11] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the Output Enable output for devices connected to the external bus. It can be
configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality.
4.3.41
PD[12] / Burst — Port D I/O Pin and External Bus Control
PD[12] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the Burst Attribute output for devices connected to the external bus. It can be
configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality.
4.3.42
PD[13] / TA — Port D I/O Pin and External Bus Control
PD[13] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
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Detailed Signal Descriptions
pin. It is multiplexed with the Transfer Acknowledge input for devices connected to the external bus. It
can be configured to wake the system out of low-power mode (DOZE) when an external signal is applied
using the interrupt functionality.
4.3.43
PD[15] / CS0 — Port D I/O Pin and External Bus Control
PD[15] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the Chip Select 0 output for devices connected to the external bus. It can be
configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality.
4.3.44
PD[15] / R/W — Port D I/O Pin and External Bus Control
PD[15] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the Read/Write output for devices connected to the external bus. It can be
configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality.
4.3.45
PE[0:15] / AN_A[00:15]— Port E I/O Pins and ATD_A
PE[0] to PE[15] are configurable general purpose input pins (Note that general purpose output
functionality is not available). They can be configured to enable or disable either a pull-up or pull-down
resistor on the pins. The pins are multiplexed with the analog inputs AN_A[00:15] for the analog to digital
converter (ATD_A), and may be used either as an Analog Channel or an external ATD trigger. Each pin
can be independently configured to wake the system out of low-power mode (DOZE) when an external
signal is applied using the interrupt functionality.
4.3.46
PF[0] / EMIOS[0] / NEXPS — Port F I/O Pins, eMIOS Channels and
Nexus Port Selection
PF[0] is a configurable general purpose input or output pin. It can be independently configured to provide
either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on
the pin. The pin is multiplexed with the eMIOS channels for the capturing of timed events or the output of
time based signals. At Reset the value of the pin is used to determine the position of the Nexus Port (when
enabled). NEXPS cleared low selects the Primary Nexus Port (PA[0:6]), NEXPS set high selects the
Secondary Nexus Port (PE[0:6]). The pin can be independently configured to wake the system out of
low-power mode (DOZE) when an external signal is applied using the interrupt functionality.
4.3.47
PF[1] / EMIOS[1] / NEXPR — Port F I/O Pins, eMIOS Channels and
Nexus Present Selection
PF[1] is a configurable general purpose input or output pin. It can be independently configured to provide
either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on
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the pin. The pin is multiplexed with the eMIOS channels for the capturing of timed events or the output of
time based signals. At Reset the value of the pin is used to determine if the Nexus Port can be enabled using
the external Debug. The pin can be independently configured to wake the system out of low-power mode
(DOZE) when an external signal is applied using the interrupt functionality.
4.3.48
PF[2] / EMIOS[2] / AUTOACK — Port F I/O Pins, eMIOS Channels and
FlexBus Ack Selection
PF[2] is a configurable general purpose input or output pin. It can be independently configured to provide
either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on
the pin. The pin is multiplexed with the eMIOS channels for the capturing of timed events or the output of
time based signals. At Reset the value of the pin is used to determine whether the AutoAck feature is
enabled for the Global Chip Select of the FlexBus. The pin can be independently configured to wake the
system out of low-power mode (DOZE) when an external signal is applied using the interrupt
functionality.
4.3.49
PF[3] / EMIOS[3] / AUTOACK — Port F I/O Pins, eMIOS Channels and
FlexBus Port Size
PF[3] is a configurable general purpose input or output pin. It can be independently configured to provide
either high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistor on
the pin. The pin is multiplexed with the eMIOS channels for the capturing of timed events or the output of
time based signals. At Reset the value of the pin is used to determine the Port Size for the Global Chip
Select of the FlexBus. The pin can be independently configured to wake the system out of low-power mode
(DOZE) when an external signal is applied using the interrupt functionality.
4.3.50
PF[4:7] / EMIOS[4:7] — Port F I/O Pins and eMIOS Channels
PF[4] to PF[7] are configurable general purpose input or output pins. They can be independently
configured to provide either high or reduced output drives, and also to enable or disable either a pull-up or
pull-down resistor on the pins. The pins are multiplexed with the eMIOS channels for the capturing of
timed events or the output of time based signals. Each pin can be independently configured to wake the
system out of low-power mode (DOZE) when an external signal is applied using the interrupt
functionality.
4.3.51
PF[8] / PCS[5] / PCSS — Port F I/O Pin and DSPI_C
PF[8] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as chip select pin PCS[5] when in Master
mode for the Serial Peripheral Interface C (DSPI_C), or as a Peripheral Chip Select Strobe to qualify the
other Chip Select signals to eliminate any decoding glitches. Each pin can be independently configured to
wake the system out of low-power mode (DOZE) when an external signal is applied using the interrupt
functionality.
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4.3.52
PF[9] / PCS[3] — Port F I/O Pin and DSPI_C
PF[9] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide
either an open drain or push-pull pad. The pins can be configured as a chip select pin PCS[3] when in
Master mode for the Serial Peripheral Interface C (DSPI_C). It can be configured to wake the system out
of low-power mode (DOZE) when an external signal is applied using the interrupt functionality.
4.3.53
PF[10] / PCS[2] — Port F I/O Pin and DSPI_C
PF[10] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide
either an open drain or push-pull pad. The pins can be configured as a chip select pin PCS[2] when in
Master mode for the Serial Peripheral Interface C (DSPI_C). It can be configured to wake the system out
of low-power mode (DOZE) when an external signal is applied using the interrupt functionality.
4.3.54
PF[11] / SCK_C — Port F I/O Pin and DSPI_C
PF[11] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as serial clock pin SCK of the Serial
Peripheral Interface C (DSPI_C). It can be configured to wake the system out of low-power mode (DOZE)
when an external signal is applied using the interrupt functionality.
4.3.55
PF[12] / PCS[1] — Port F I/O Pin and DSPI_C
PF[12] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide
either an open drain or push-pull pad. The pins can be configured as a chip select pin PCS[1] when in
Master mode for the Serial Peripheral Interface C (DSPI_C). It can be configured to wake the system out
of low-power mode (DOZE) when an external signal is applied using the interrupt functionality.
4.3.56
PF[13] / SOUT_C — Port F I/O Pin and DSPI_C
PF[31] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as the output pin of the Serial Peripheral
Interface C (DSPI_C). It can be configured to wake the system out of low-power mode (DOZE) when an
external signal is applied using the interrupt functionality.
4.3.57
PF[14] / PCS[0] / SS[0] — Port F I/O Pin and DSPI_C
PF[14] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as chip select pin PCS[0] when in Master
mode, or as slave select pin SS when in Slave mode for the Serial Peripheral Interface C (DSPI_C). It can
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Detailed Signal Descriptions
be configured to wake the system out of low-power mode (DOZE) when an external signal is applied using
the interrupt functionality.
4.3.58
PF[15] / SIN_C — Port F I/O Pin and DSPI_C
PF[15] is a configurable general purpose input or output pin. It can be configured to provide either high or
reduced output drive, to enable or disable either a pull-up or pull-down resistor on the pin or to provide
either an open drain or push-pull pad. The pin can be configured as the input pin of the Serial Peripheral
Interface C (DSPI_C). It can be configured to wake the system out of low-power mode (DOZE) when an
external signal is applied using the interrupt functionality.
4.3.59
PG[0] / RXD_B — PORT G I/O Pin and ESCI_B
PG[0] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the receive pin for the Enhanced Serial Communications Interface controller B
(ESCI_B). It can be configured to wake the system out of low-power mode (DOZE) when an external
signal is applied using the interrupt functionality.
4.3.60
PG[1] / TXD_B — PORT G I/O Pin and ESCI_B
PG[1] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the transmit pin for the Enhanced Serial Communications Interface controller
B (ESCI_B). It can be configured to wake the system out of low-power mode (DOZE) when an external
signal is applied using the interrupt functionality.
4.3.61
PG[2] / RXD_A / NEX1MDO — PORT G I/O Pin, ESCI_A and Nexus
Primary
PG[2] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the receive pin for the Enhanced Serial Communications Interface controller A
(ESCI_A). It can be configured to wake the system out of low-power mode (DOZE) when an external
signal is applied using the interrupt functionality. When the Nexus Primary Port is selected and active, this
pin is used as a Message Data Out output.
4.3.62
PG[3] / TXD_A / NEX1MDO — PORT G I/O Pin, ESCI_A and Nexus
Primary
PG[3] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the transmit pin for the Enhanced Serial Communications Interface controller
A (ESCI_A). It can be configured to wake the system out of low-power mode (DOZE) when an external
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Detailed Signal Descriptions
signal is applied using the interrupt functionality. When the Nexus Primary Port is selected and active, this
pin is used as a Message Data Out output.
4.3.63
PG[4] / TCNTX_A / NEX1MDO[2] — PORT G I/O Pin, FlexCAN_A and
Nexus Primary
PG[4] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the transmit pin for the CAN controller A (FlexCAN_A). It can be configured
to wake the system out of low-power mode (DOZE) when an external signal is applied using the interrupt
functionality. When the Nexus Primary Port is selected and active, this pin is used as a Message Data Out
output.
4.3.64
PG[5] / CNRX_A — PORT G I/O Pin and FlexCAN_A
PG[5] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the receive pin for the CAN controller A (FlexCAN_A). It can be configured to
wake the system out of low-power mode (DOZE) when an external signal is applied using the interrupt
functionality.
4.3.65
PG[6] / CNTX_B — PORT G I/O Pin and FlexCAN_B
PG[6] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the transmit pin for the CAN controller B (FlexCAN_B). It can be configured
to wake the system out of low-power mode (DOZE) when an external signal is applied using the interrupt
functionality.
4.3.66
PG[7] / CNRX_B — PORT G I/O Pin and FlexCAN_B
PG[7] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It is multiplexed with the receive pin for the CAN controller B (FlexCAN_B). It can be configured to
wake the system out of low-power mode (DOZE) when an external signal is applied using the interrupt
functionality.
4.3.67
PG[8] — PORT G I/O Pin
PG[8] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It can be configured to wake the system out of low-power mode (DOZE) when an external signal is
applied using the interrupt functionality.
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Detailed Signal Descriptions
4.3.68
PG[9] — PORT G I/O Pin
PG[9] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It can be configured to wake the system out of low-power mode (DOZE) when an external signal is
applied using the interrupt functionality.
4.3.69
PG[10] — PORT G I/O Pin
PG[10] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It can be configured to wake the system out of low-power mode (DOZE) when an external signal is
applied using the interrupt functionality.
4.3.70
PG[11] — PORT G I/O Pin
PG[8] is a configurable general purpose input or output pin. The pin can be configured to provide either
high or reduced output drive, and also to enable or disable either a pull-up or pull-down resistors on the
pin. It can be configured to wake the system out of low-power mode (DOZE) when an external signal is
applied using the interrupt functionality.
4.3.71
PG[12] / PCS[4] — Port G I/O Pin and DSPI_A
PG[12] is a configurable general purpose input or output pin. It can be configured to provide either high
or reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide
either an open drain or push-pull pad. The pins can be configured as a chip select pin PCS[4] when in
Master mode for the Serial Peripheral Interface A (DSPI_A). It can be configured to wake the system out
of low-power mode (DOZE) when an external signal is applied using the interrupt functionality.
4.3.72
PG[13] / PCS[3] — Port G I/O Pin and DSPI_A
PG[13] is a configurable general purpose input or output pin. It can be configured to provide either high
or reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide
either an open drain or push-pull pad. The pins can be configured as a chip select pin PCS[3] when in
Master mode for the Serial Peripheral Interface A (DSPI_A). It can be configured to wake the system out
of low-power mode (DOZE) when an external signal is applied using the interrupt functionality.
4.3.73
PG[14] / PCS[4] — Port G I/O Pin and DSPI_B
PG[14] is a configurable general purpose input or output pin. It can be configured to provide either high
or reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide
either an open drain or push-pull pad. The pins can be configured as a chip select pin PCS[4] when in
Master mode for the Serial Peripheral Interface B (DSPI_B). It can be configured to wake the system out
of low-power mode (DOZE) when an external signal is applied using the interrupt functionality.
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Power Supply Pins
4.3.74
PG[15] / PCS[3] — Port G I/O Pin and DSPI_B
PG[15] is a configurable general purpose input or output pin. It can be configured to provide either high
or reduced output drives, to enable or disable either a pull-up or pull-down resistors on the pin or to provide
either an open drain or push-pull pad. The pins can be configured as a chip select pin PCS[3] when in
Master mode for the Serial Peripheral Interface B (DSPI_B). It can be configured to wake the system out
of low-power mode (DOZE) when an external signal is applied using the interrupt functionality.
4.4
Power Supply Pins
MAC72xx power and ground pins are described below.
NOTE
All VSS pins must be connected together in the application.
4.4.1
VPP — Power For Flash Program and Erase
VPP is the power supply and ground input pins for the program and erase circuitry inside the Flash. If this
pin is grounded or left open, programming and erasing of the Flash will be unavailable, and the system
will have unpredictable behavior in the case where Flash programming or erasing is attempted.
4.4.2
VDDX1-4,6-11, VSSX1-11 (except VDDX5) — Power and Ground Pins
for I/O Drivers
External power and ground for I/O drivers. Because fast signal transitions place high, short-duration
current demands on the power supply, use bypass capacitors with high-frequency characteristics and place
them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are
loaded. If one or more of these pins are left open, the ability of the I/O to drive loads could be
compromised, resulting in slower transition times on outputs.
4.4.3
VDDX5 /VDDAPASS — Power Pin for I/O Drivers and Control Voltage
for Internal Pass Transistors
External power for I/O drivers and control voltage for internal pass transistors. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements
depend on how heavily the MCU pins are loaded. If this pin is left open, the internal voltage regulator may
not be able to control the internal pass transistors, resulting in a completely non-functional device.
4.4.4
VDDR/VREGEN — Power Pin for the Internal Voltage Regulator
This 5.0V supply pin supplies all current for the 1.5V and 3.3V on-chip regulated supplies. This pin will
supply most of the current consumed by the device, except for the I/O, which is supplied by the
VDDx/VSSx pad pairs. If this pin is grounded, the internal voltage regulation is disabled, and all 1.5V and
3.3V supplies must be supplied from external sources through the VDD15x/VSS15x, VDD33/VSS33a and
VDDPLL/VSSPLL pin pairs.
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Power Supply Pins
4.4.5
VDD15a, VSS15a — Core Power Pins
These pins provide the operating voltage and ground for the MCU core logic. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. This 1.5V supply is derived
from the internal voltage regulator when the voltage regulator is enabled. Otherwise, it must be supplied
externally. There is no static load on these pins allowed. The internal voltage regulator is turned off, if
VREGEN is tied to ground. If the VDD15a pin is grounded or left open, the device will be completely
non-functional.
NOTE
No load allowed except for bypass capacitors.
4.4.6
VDD15c/VDDF, VSS15c/VSSF — Core and Flash Logic Power Pins
These pins provide the operating voltage and ground for the MCU and Flash core logic. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. This 1.5V supply is derived
from the internal voltage regulator when the voltage regulator is enabled. Otherwise, it must be supplied
externally. There is no static load on these pins allowed. The internal voltage regulator is turned off, if
VREGEN is tied to ground. If the VDD15c pin is grounded or left open, the MCU will be completely
non-functional.
NOTE
No load allowed except for bypass capacitors.
4.4.7
VDD33/VFLASH, VSS33 — Flash and I/O Pre-Driver Power Pins
These pins provide the operating voltage and ground for the Flash and I/O pre-drivers. Because fast signal
transitions place high, short-duration current demands on the power supply, use bypass capacitors with
high-frequency characteristics and place them as close to the MCU as possible. This 3.3V supply is derived
from the internal voltage regulator when the voltage regulator is enabled. Otherwise, it must be supplied
externally. There is no static load on these pins allowed. The internal voltage regulator is turned off, if
VREGEN is tied to ground. If the VDD33 pin is grounded or left open, the Flash and all I/O outputs will
be completely non-functional.
NOTE
No load allowed except for bypass capacitors.
4.4.8
VDDA, VSSA — Power Supply Pins for ATD and Voltage Regulator
Control
These pins provide the operating voltage and ground for the ATD and the Voltage Regulator control block.
This allows the supply voltage to the ATD to be bypassed independently of the main I/O supply VDDx
and VSSx. If the VDDA pin is grounded or left open, the ATD will be completely non-functional. If the
VDDA pin is grounded or left open, and the internal regulator is not bypassed, then the complete MCU
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Power Supply Pins
will be non-functional. It is critical to the operation of the ATD and the MCU that this supply be kept as
noise-free as possible.
4.4.9
VRH, VRL — ATD Reference Voltage Input Pins
VRH and VRL are the reference voltage input pins for the analog to digital converter.
4.4.10
REFBYPC — ATD Reference Voltage Bypass Capacitor
REFBYPC is used to filter the 3/4 VRH reference voltage. A 100nF external capacitor should be placed
between this pin and the VRL pin.
4.4.11
VDDPLL, VSSPLL — Power Supply Pins for PLL
These pins provide the operating voltage and ground for the Oscillator and the Phased-Locked Loop. This
allows the supply voltage to the Oscillator and PLL to be bypassed independently.This 3.3V voltage is
generated by the internal voltage regulator when the voltage regulator is enabled. Otherwise, it must be
supplied externally.
NOTE
No load allowed except for bypass capacitors.
4.4.12
VSS-TEST — Power Supply Pin
This input only pin is reserved for test. The pin must be tied to VSS in all applications. If this pin is shorted
to a VDD supply the operation of the device will be unpredictable. If the pin is left open, an internal
pulldown will protect the device operation.
Table 4-2. MAC72xx Power and Ground Connection Summary
Pin Number
Mnemonic
Nominal
Voltage
144 QFP
100 QFP
VDD15a
127
92
1.5 V
VSS15a
126
91
0V
Description
Provides operating voltage and ground for the MCU core
logic, including the MCU core, all peripherals, and all
RAMs. This allows the supply voltage to the core to be
bypassed independently. When not bypassed, the core
supply is generated by the internal voltage regulators, and
these pins are used for an external bypass capacitor.
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Power Supply Pins
Table 4-2. MAC72xx Power and Ground Connection Summary
Pin Number
Mnemonic
Nominal
Voltage
Description
144 QFP
100 QFP
VDD15c
52
37
1.5 V
VSS15c
53
38
0V
VDD33
124
89
3.3 V
VSS33
125
90
0V
VDDR
55
40
5.0 V
Supplies external power for all internal voltage regulation.
VDDX1-4,6-11
10,20,49,63,
67,80,120
14,34,
58,87
5.0 V
Supplies external power and ground for the I/O drivers.
VSSX1-11
9,19,30,48,
62,79,95,119
13,33,57,
63,86
0V
VDDX5
96
64
5.0 V
Supplies external power and ground for the I/O drivers, as
well as the control voltage for all internal regulator pass
transistors.
VDDA
109
76
5.0 V
VSSA
112
79
0V
Operating voltage and ground for the analog-to-digital
converters and the reference for the internal voltage
regulator, allows the supply voltage to the A/D to be
bypassed independently.
VRH
110
77
5.0 V
VRL
111
78
0V
VDDPLL
56
41
3.3 V
VSSPLL
58
43
0V
VPP
54
39
5.0V
VSS-TEST
61
46
0V
Provides operating voltage and ground for the MCU core
logic, including the MCU core, all peripherals, and all
RAMs. This allows the supply voltage to the core to be
bypassed independently. When not bypassed, the core
supply is generated by the internal voltage regulators, and
these pins are used for an external bypass capacitor.
Provides operating voltage and ground for the Flash and
I/O pre-drivers. This allows the supply voltage to the Flash
and I/O pre-drivers to be bypassed independently. When
not bypassed, the Flash and I/O pre-driver supply is
generated by the internal voltage regulators, and these pins
are used for an external bypass capacitor.
Supplies external reference voltages for the
analog-to-digital converter.
Provides operating voltage and ground for the
Phased-Locked Loop and Oscillator. This allows the supply
voltage to the PLL and Oscillator to be bypassed
independently. When not bypassed, the PLL and Oscillator
supply is generated by the internal voltage regulators, and
these pins are used for an external bypass capacitor.
Supplies external power for program and erase of the
Flash.
Pin must be tied to Ground on all applications.
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Power Supply Pins
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Chapter 5
System Clock Description
5.1
Clocks Introduction
The Clock and Reset Generator (CRG) provides the internal clock signals for the core and all peripheral
modules. Figure 5-1 shows the clock connections from the CRG to all modules. There are six clocks
available on the MAC72xx:
Table 5-1. Clocks Summary
PLLCLK
This is the clock output of the on-chip PLL. When the PLL is enabled, the System Clock is
driven directly by this clock. When the system is in Self Clock Mode (SCM), this clock drives
the Real Time Interrupt (RTI) and Software Watchdog Timer (SWT).
System Clock
This clock is used throughout the MCU to drive the core, the memories and select
peripherals. It may be driven either by the PLLCLK (when the PLL is enabled) or by the
OSCCLK (when the PLL is bypassed). For a list of which modules are driven by this clock,
please see Table 5-3.
Peripheral Bus Clock
This clock is used throughout the MCU to drive the remainder of the peripherals that are
not driven by the System Clock. It is always running at 1/2 the frequency of the System
Clock. For a list of which modules are driven by this clock, please see Table 5-3.
Oscillator Clock
This clock is driven directly from the output of the on-chip oscillator. Programming the
CTRL register inside the FlexCAN will allow the FlexCAN to use either the Oscillator Clock
or Peripheral Bus Clock.
RTI Clock
This clock is driven by OSCCLK in normal operation, and by PLLCLK when the system is
in Self Clock Mode. It is used to clock the on-chip Real Time Interrupt (RTI) inside the PIT
module.
SWT Clock
This clock is driven by OSCCLK in normal operation, and by PLLCLK when the system is
in Self Clock Mode. It is used to clock the on-chip Software Watchdog Timer (SWT) inside
the MCM module.
NOTE
It is possible to configure the PLL to generate a System Clock frequency
higher than that supported by the design of the device. It is the responsibility
of the user to ensure that the device is operated within its specified limits at
all times.
Please refer to Chapter 23, “Clock and Reset Generator (CRG)” for details on clock generation.
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Clocks Introduction
ARM7 TDMI-S
CORE
eDMA
INT C
Flash
Main Array
Shadow Block
CRG
PLLCLK
PLL
RAM
System Clock
DSPI_A, DSPI_B,
DSPI_C
XTAL
ATD_A
Oscillator
RTI Clock
SWT Clock
OSCCLK
Oscillator clock
EXTAL
Peripheral Bus Clock
eMIOS
ESCI_A, ESCI_B
/2
MUX
CAN_A, CAN_B
IIC
PIT
SWT
Figure 5-1. MAC72xx Clock Tree
The MCU’s clocks can be supplied in a variety of ways, enabling a range of system operating frequencies
to be supported:
• From the on-board Phase Locked Loop (PLL) in normal functional mode
• From the PLL in Self Clock Mode (SCM)
• Directly from the Oscillator
The FlexCAN modules may be configured to have their clock sources derived either from the Peripheral
Bus Clock or directly from the Oscillator Clock. This allows the user to select the CAN clock based on the
required jitter performance. Consult Chapter 28, “FlexCAN2” for more details on the operation and
configuration of the CAN modules.
The Real Time Interrupt (RTI) (in the Periodic Interrupt Timer module) and the Software Watchdog Timer
(SWT) (in the MCM module) can also be configured to run from either the Oscillator Clock or the PLL
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Clock Generation
generated clock (in Self Clock Mode only). This allows these functions to continue to run during low
power operating modes if required. Refer to Chapter 26, “Periodic Interrupt Timer (PIT_RTI)” and
Chapter 13, “Miscellaneous Control Module (MCM)” for more information on these modules.
In order to ensure the presence of the clock, the MCU includes an on-chip hardware Crystal Monitor
connected to the output of the Oscillator, OSCCLK. The Crystal Monitor can be configured to invoke the
PLL self clocking mode or to generate a System Reset to time out as a result of no OSCCLK being present.
In addition to the Crystal Monitor, the MCU also provides a Clock Quality checker which performs a more
accurate check of the clock. The Clock Quality Checker counts a predetermined number of clock edges
within a defined time window to ensure that the clock is running. The checker can be invoked following
specific events such as wake-up or a Crystal Monitor failure.
5.2
Clock Generation
Figure 5-2 and Figure 5-3 shows the clock outputs and gating in the CRG. The effect of the different Low
Power modes on the various clocks is discussed in Chapter 3, “Low Power Modes”.
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Clock Generation
PLLSEL or SCM
PHASE
LOCK
LOOP
PLLCLK
System Clock
1
SYSCLK
0
÷2
SCM
DOZE (RTIDOZE)
EXTAL
1
CLOCK
PHASE
GENERATOR
DEBUG
Peripheral
Bus Clock
RTI Clock
OSCCLK
OSC
0
DOZE (SWTDOZE)
XTAL
DEBUG
SWT Clock
Clock
Monitor
Oscillator
Clock
Unused
Gating
Condition
= Clock Gate
Figure 5-2. CRG Generated Clocks
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Clock Generation
2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2
System Clock
Peripheral Bus Clock
RTI Clock
SWT Clock
Figure 5-3. Timing of CRG Generated Clocks
5.2.1
Clock Source Selection
With two oscillator modes, and the ability to bypass the PLL, there are four main clock selection modes
that the system may be run in:
• Automatic Level Control (ALC) 1:1 Mode - In this mode, the oscillator is enabled, and the PLL is
bypassed.
• Automatic Level Control (ALC) PLL Mode - In this mode, the oscillator is enabled, and the PLL
is enabled.
• External Clock 1:1 Mode - In this mode, the oscillator is bypassed, and the PLL is bypassed.
• External Clock PLL Mode - In this mode, the oscillator is bypassed, and the PLL is enabled.
For information on selecting the oscillator mode, please refer to Section 24.8.1, “OSC Mode Selection”.
The enabling or bypassing of the PLL is done with the PLLSEL bit in the CLKSEL register in the CRG
module.
The oscillator mode is chosen by a combination of the JTAG SC4 register and the XCLKS hardware
configuration pin, as follows:
Table 5-2. Clock Source Selection
XCLKS
PLLSEL
Mode
1
0
ALC 1:1 Mode
1
1
ALC PLL Mode
0
0
External Clock 1:1 Mode
0
1
External Clock PLL Mode
Note that the PLL always comes up disabled (PLLSEL = 0) after a System or Power On Reset, and must
be explicitly enabled by the boot software.
In addition to the above modes, the FlexCAN, SWT and RTI all have some level of configurability with
respect to clock source.
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Clock Generation
5.2.1.1
ALC 1:1 Mode
In this mode, the system clock is fed from the Oscillator, and the PLL is bypassed. Refer to Figure 5-4.
XCLKS = 1
PLLSEL = 0 (PLL is bypassed)
SystemClock = OSCCLOCK
Eqn. 5-1
SystemClock
OSCCLK
PeripheralBusClock = ----------------------------------- = ------------------------2
2
Eqn. 5-2
CRG
OSC
EXTAL
OSCCLK
PLL
XTAL
PLLCLK
PLLSEL
0 1
÷2
Peripheral
Bus Clock
System Clock
Figure 5-4. ALC 1:1 Mode Clock Path
5.2.1.2
ALC PLL Mode
In this mode, the system clock is fed from the Oscillator, and the PLL is enabled. Refer to Figure 5-5.
XCLKS = 1
PLLSEL = 1 (PLL is not bypassed)
SYNR + 1
SystemClock = PLLCLK = 2 × OSCCLK × -----------------------------REFDV + 1
SystemClock
PLLCLK
PeripheralBusClock = ----------------------------------- = -----------------------2
2
Eqn. 5-3
Eqn. 5-4
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Clock Generation
CRG
OSC
EXTAL
OSCCLK
PLL
XTAL
PLLCLK
PLLSEL
0 1
÷2
Peripheral
Bus Clock
System Clock
Figure 5-5. ALC PLL Mode Clock Path
5.2.1.3
External Clock 1:1 Mode
In this mode, the system clock is fed from an external 3.3V clock, and the PLL is bypassed. Refer to
Figure 5-6.
XCLKS = 0
PLLSEL = 0 (PLL is bypassed)
SystemClock = OSCCLOCK
Eqn. 5-5
SystemClock
OSCCLK
PeripheralBusClock = ----------------------------------- = ------------------------2
2
Eqn. 5-6
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Clock Generation
CRG
OSC
EXTAL
OSCCLK
PLL
XTAL
PLLCLK
PLLSEL
0 1
÷2
Peripheral
Bus Clock
System Clock
Figure 5-6. External Clock 1:1 Mode Clock Path
5.2.1.4
External Clock PLL Mode
In this mode, the system clock is fed from an external 3.3V clock, and the PLL is enabled. Refer to
Figure 5-7.
XCLKS = 0
PLLSEL = 1 (PLL is not bypassed)
SYNR + 1
SystemClock = PLLCLK = 2 × OSCCLK × -----------------------------REFDV + 1
SystemClock
PLLCLK
PeripheralBusClock = ----------------------------------- = -----------------------2
2
Eqn. 5-7
Eqn. 5-8
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Clock Usage
CRG
OSC
EXTAL
OSCCLK
PLL
XTAL
PLLCLK
PLLSEL
0 1
÷2
Peripheral
Bus Clock
System Clock
Figure 5-7. External Clock PLL Mode Clock Path
5.2.2
Self Clock Mode (SCM)
If the external clock frequency is not available due to a failure or due to long crystal start-up time, the
System Clock is derived from the VCO in the PLL, running at minimum operating frequency. This mode
of operation is called Self Clock Mode. Self Clock Mode may be entered at any time, upon failing the
Clock Quality Check. Self Clock mode may only be exited by passing a Clock Quality Check after a
system reset. When the system is in Self Clock Mode, the RTI, SWT and Oscillator Clock are all
automatically switched to PLLCLK.
5.2.3
Crystal Monitor
The MAC72xx provides an on-chip Crystal Monitor that detects a loss of Oscillator Clock. Please refer to
Section 23.4.2.3, “Clock Monitor (CM)” for more details. Note that the terms “Crystal Monitor” and
“Clock Monitor” are used interchangeably.
5.2.4
Clock Quality Checker
In addition to the Crystal Monitor, the MCU also provides a Clock Quality checker which performs a more
accurate check of the Oscillator Clock. Please refer to Section 23.4.2.4, “Clock Quality Checker” for more
details.
5.3
Clock Usage
Table 5-3 summarizes the usage of clocks on all MAC72xx modules.
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Clock Gating
Table 5-3. Module Clock Usage Overview
Module/Pin
System Clock
(Fast Clock)
ARM7 Core
X
AXBS
X
FlexBus
X
Peripheral Bus Clock
(Slow Clock)
CLKOUT
Oscillator Clock
X
Nexus
X
SRAM
X
INTC
X
MCM (except SWT)
X
SWT (in MCM)
X1
DMA2
X
AIPS
X
Flash (array interface)
X
Flash (registers)
DMA_CH_MUX
X1
X
X
IIC
X
eSCI_A/B
X
SPI_A/B/C
X
SSM
X
PIT (except RTI)
RTI (in PIT)
X
X1
X2
FlexCAN_A/B
ATD_A
X1
X2
X
eMIOS
X
PIM
X
CRG
X
PTI
X
BAM
X
1. PLLCLK is selected when the device is in Self Clock Mode (SCM).
2. Can be switched between the Peripheral Bus Clock and Oscillator Clock via the CLK_SRC bit in the CTRL register in
the corresponding FlexCAN.
5.4
Clock Gating
On the MAC72xx, there are two levels of clock gating implemented:
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Oscillator
•
•
Global clock gating refers to clock gating inside the CRG module which gates entire clock
domains. Figure 5-2 illustrates the global clock gating on the MAC72xx. More information on this
can be found in the CRG documentation.
Local clock gating is implemented inside the CGL, and gates a particular clock for a particular
module. Please refer to the individual chapters for information on gating conditions.
A low power STOP mode is not supported on the MAC72xx.
Since STOP mode is not implemented on the MAC72xx, the user may only control the granularity of
power consumption in DOZE mode, or via the MDIS bit in each module.This topic is discussed in more
detail in Section Chapter 3, “Low Power Modes”.
Figure 5-8 shows the overview of the clock gating and distribution on the MAC72xx.
5.5
Oscillator
Refer to Chapter 24, “Oscillator (OSC) for details on the Oscillator.
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Oscillator
PIT
Channel 0
RTI Clock
CRG
Channel 1
to
Channel 10
SWT Clock
SWT
System Clock
ARM7
OSCCLK
SPP
Nexus
Nexus enabled
Oscillator Clock
FlexCAN
Peripheral Bus Clock
NOTE: The CRG also gates clocks internally.
Please refer to Figure 5-2 for more details on this.
Single Clock
Peripherals
(Registers)
(Pin Side Logic)
DOZE
Peripheral
(Bus Side Logic)
DEBUG
TCK
Test
Controller
CGL
Figure 5-8. System Clock Gating
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Chapter 6
Resets
6.1
Resets Introduction
On the MAC72xx, there are three classes of resets:
• Power On Reset (POR)
• System Reset
• Debug Reset
Figure 6-1 illustrates the overall reset distribution on the MAC72xx.
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Resets Introduction
Power On Reset
VREG
Flash
Low Voltage Reset
Pad inhibit
Core Logic
RESET Pad
A7S
System Reset
CRG
nRESET
Debug Reset
TAP/EICE
dbg_tapsm[3:0]
Test
Controller
SC4 Register
JTAG Synchronization
SWT Reset
SC4 Debug Reset
Crystal Monitor Reset
Software Reset
DBGnTRST
TCK
TMS
TDI
TDO
nex_rst_b
Nexus
Asserted when TAP state
machine is in the Test-Logic
Reset state
SWT
SSM
Crystal Monitor
Power On Reset
System Reset
Debug Reset
Figure 6-1. MAC72xx Resets
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Power On Reset (POR)
6.2
Power On Reset (POR)
Power On Reset is the reset initiated when the device is being powered up. It is generated by the Voltage
Regulator when the voltage supply of the device is below a certain threshold (called the POR trip point).
The POR is used to reset or control the following:
• Flash internal circuits
• CRG system reset generation logic
• CRG debug reset generation logic
• Pad/Level shifter inhibitors
6.3
System Reset
The System Reset is the main reset in the system that is used to reset the majority of the logic in the system.
It can be caused by any of the following events:
Table 6-1. System Reset Sources
Event
Source
Maskable ?
Power On Reset (POR)
Voltage Regulator
No
Low Voltage Reset (LVR)
Voltage Regulator
No
RESET
External
No
Software Watchdog Timer (SWT)
MCM
Yes (In the MCM)
Crystal Monitor Reset
Crystal Monitor
Yes (In the CRG)
Software Reset
SSM
Yes
Illegal Address
Not implemented
Not implemented
All of the above sources may be detected by software (after the reset) by reading the appropriate register(s)
in the CRG module. Note that the use of the MRSR register in the MCM is deprecated.
6.4
Debug Reset
The Debug Reset is generated from the Power-On Reset (POR) of the system, and is intended to reset the
debug logic, which should not be reset during a general system reset (i.e.-when the user presses a reset
button).
On the MAC72xx, the Debug Reset is initiated by either of the following two conditions:
• a Power-On Reset (POR)
• Setting of bit 5 in the SC4 Test Register (See Section 35.1.1, “JTAG Test Register (SC4)”)
Asserting the debug reset will reset the following logic on the MAC72xx:
• EICE in the ARM7 core, including the TAP state machine
• JTAG synchronization logic in the Test Controller
• SC4 register in the Test Controller
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Software Reset
•
•
•
•
•
•
•
SC5 register in the Test Controller
SC6 register in the Test Controller
SC7 register in the Test Controller
BIST muxing in the Test Controller
Scan testpoints in the Test Controller
The debug reset assertion logic in the Test Controller (i.e.-self clearing reset)
Nexus registers
What is not explicitly reset are the Nexus registers, which are reset solely by taking the ARM7 TAP state
machine into the Test-Logic Reset State ($F). Since the ARM7 core TAP state machine is driven by the
debug reset, and resets into the Test-Logic Reset State, this effectively forces the reset of the Nexus
registers as well.
6.5
Software Reset
A software initiated reset of the system may be performed by performing a series of writes to the Software
Reset register in the SSM module. Please refer to Chapter 25, “System Service Module
(SSM_MAC7202)” for details on this. Performing a software reset in this manner is virtually identical to
resetting the device via the RESET pin.
6.6
Reset Implementation
Figure 6-1 illustrates the resets in the MAC72xx. Some points to note are:
• The Nexus is reset by cycling the TAP controller in the A7 through the Test-Logic Reset state ($F).
This is done inside the Nexus block.
• Since the Debug Reset is asserted during a Power On Reset, and the TAP State Machine is reset to
the Test-Logic Reset state on a Debug Reset, the Nexus logic will automatically be reset on a POR
event without the need to explicitly use the POR signal in the Nexus.
• Bringing up the MAC72xx in debug mode will consist of the following steps:
— Power on the MAC72xx. This will reset the ARM7 core, EICE and Nexus.
— A breakpoint at address $0000 0000 is programmed into the EICE
— The external reset is asserted, resetting the system except for the EICE and Nexus
— The processor boots, and fetches its first instruction from $0000 00000, which hits the
previously hit breakpoint, and the system enters DEBUG mode.
Alternatively, the following series of steps may also be used:
— Power on the MAC72xx, while holding the RESET pin low (asserted). This will reset the EICE
and Nexus, but hold the core in a reset state
— A breakpoint at address $0000 0000 is programmed into the EICE
— The external reset is released, starting the execution of the core
— The processor boots, and fetches its first instruction from $0000 00000, which hits the
previously hit breakpoint, and the system enters DEBUG mode.
• Switching Nexus ports will consist of the following steps:
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Effects of Reset
— Power on the MAC72xx. This will reset the ARM7 core, EICE and Nexus.
— While RESET is asserted, drive the Nexus Present (PF1) and Nexus Port Select (PF0) lines to
enable/disable a particular Nexus Port
— The Nexus is reset by cycling through the Test Reset state in the TAP controller
— Once the Nexus resets, it latches in the EVTI bit from the selected Nexus port.
6.7
6.7.1
Effects of Reset
Hardware Configuration
When a POR or System Reset occurs, the following pins are sampled while the RESET pin is asserted
(low) in order to determine the configuration of the system:
• MODA (PD1)
• MODB (PD0)
• NEXPORTSEL (PF0)
• NEXPRESENT (PF1)
• AUTOACK (PF2)
• PORTSIZE (PF3)
In addition, on a POR or System Reset, the security state of the system is determined from the System
Censor word in the Flash (See Section 18.7.9, “Flash Security”). This means that a currently secured
system may come out of reset as secured, and vice-versa.
The oscillator mode selection is done via the XCLKS hardware configuration pin (PD2), but only during
the following conditions:
• POR, or
• System Reset after a loss of clock has occurred.
6.7.2
Register States
When a POR or System Reset occurs, MCU registers and control bits are changed to known start-up states.
Refer to the respective module chapters for register reset states.
When a Debug Reset occurs, the following registers are reset:
• EICE registers. Please refer to the ARM7 documentation for more information.
• Nexus registers. Please refer to Chapter 11, “A7S Nexus3 Module” for more information.
• TAP State Machine. Please refer to the ARM7 documentation for more information.
6.7.3
Peripheral Disabled State
Following a Power on Reset or a System Reset, the following peripheral modules are disabled, and must
be enabled before they can be used:
• eSCI
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System Configuration at Reset
•
•
•
•
•
Periodic Interrupt Timer (PIT)
eMIOS (MTS)
IIC
FlexCAN
DSPI
Following a Debug Reset, the Nexus is disabled, and must be explicitly enabled. Please refer to
Section 11.1.3, “Modes of Operation” for more information.
6.7.4
I/O pins
Refer to Chapter 34, “Port Integration Module (PIM_MAC7202)” for mode dependent pin configuration
of port A, C and D out of Reset. All other pins are configured as General Purpose Inputs out after a POR
or System Reset. Debug Reset has no effect on the configuration of GPIO pins.
NOTE
All non-bonded out pins should be configured as outputs or pull-ups or
pull-downs enabled after reset in order to avoid current drawn from floating
inputs. Refer to Table 4-1 for affected pins.
6.7.5
Memories
Refer to Chapter 9, “Device Memory Map” for locations of the memories depending on the operating
mode after Reset.
The RAM array is not automatically initialized out of Reset. Because of the ECC functionality built into
the RAM, the array must be initialized using 32-bit writes. After initialization, the array may be accessed
using 8, 16 and 32-bit reads and writes.
6.8
System Configuration at Reset
The reset state of the system will be:
• All pads on Ports A-G are placed into GPI mode, except in Expanded Mode, where all external bus
pins are placed in Primary Peripheral Mode.
— Pin A0 to A15 - DATA0 to DATA15
— Pin C0 to C15 - ADDR0 to ADDR15
— Pin D0 to D2 - BWE0, BWE1, CLKOUT
— Pin D5 to D15 - ADDR16 to ADDR21, BURST, TA, CS0, R/W
• TDI pad is an input with pull-up enabled
• TDO pad is an output with fastest slew rate selected
• TCK pad is an input with pull-down enabled
• TMS pad is an input with pull-up enabled
• RESET initially driven by the CRG, but switched to an input after the initial power-on reset setup
by the CRG. This can be thought of as an open-drain RESET pin.
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Resets Differences from MAC71xx
•
6.9
•
•
•
•
•
All peripherals with a Module Enable bit are disabled.
Resets Differences from MAC71xx
Added a software reset
Consolidated all reset source registers into the CRG
Additional POR time due to Flash POR handshaking
Added an internal weak pull-down on the RESET pad
Overall startup time of the device has changed
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Resets Differences from MAC71xx
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Chapter 7
Exceptions
7.1
Introduction
The ARM7 core on the MAC72xx supports the following exceptions:
Table 7-1. ARM Exception Table
Vector
Address
Exception
Mode on entry
I State
on entry
F State
on entry
Priority
(1=highest)
$0000 0000
Reset
Supervisor
Disabled
Disabled
1
$0000 0004
Undefined Instruction
Undefined
I
F
6
$0000 0008
Software Interrupt (SWI)
Supervisor
Disabled
F
7
$0000 000C
Abort (Prefetch)
Abort
I
F
5
$0000 0010
Abort (Data)
Abort
I
F
2
$0000 0018
Reserved
-
-
-
-
$0000 0018
IRQ
IRQ
Disabled
F
4
$0000 001C
FIQ
FIRQ
Disabled
Disabled
3
The ARM7 core does not support a relocatable exception table. Therefore, relocation of exception vectors
is done by relocating the base address of a particular system resource. This is done primarily through the
programming of the AXBS.
7.2
Exception Handling
This section lists any special features that have been added to the MAC72xx to better support the standard
ARM7 exceptions. It does not list the features of the Interrupt Controller, except where those features have
an impact on exception handling in the system.
Besides the requirements below for each exception type, there is a general requirement that the entire
exception table be relocated. This requirement comes from the Primary Boot Loader concept described in
Section 9.18, “System Boot Sequence”. In summary, the exception table must be relocatable into a
non-FLASH, writable space during the boot process. One way to implement this is to implement an
interrupt controller that returns an address for each exception. However, the MAC72xx interrupt controller
only returns a vector number (or index), which can be used as an address offset/multiplier. This scheme is
of limited use in the Primary/Secondary Boot Loader, where the final exception vector address should be
programmable by the Secondary Boot Loader. Another alternative is to provide relocation of the exception
table via a software configurable bit in the core itself (like the ColdFire architecture). However, the
ARM7TDMI-S does not support this. The final alternative is to fix the exception table at a particular
address (both in the core and in the Primary Boot Loader), and then to re-map particular memories to this
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Exception Handling
fixed address. For purposes of explanation in this document, that address will be assumed to be
$0000_0000.
7.2.1
Reset
Address: $0000 0000
As discussed in Chapter 9, “Device Memory Map”, the physical memory or bus to which this address is
mapped can be re-located both in hardware and in software.
7.2.2
Undefined Instruction
Address: $0000 0004
There are no additional co-processors in the system.
7.2.3
Software Interrupt
Address: $0000 0008
There is no special functionality on the MAC72xx to support SWIs.
7.2.4
Prefetch (Instruction) Abort
Address: $0000 000C
A special set of registers has been added to the MCM to support easier debugging of both Instruction and
Data Aborts. These “core fault” registers will store the last address and transfer modifiers (size, type, etc.)
that caused an Instruction or Data Abort (i.e.-the last address that caused a Transfer Error on the ARM7
native bus). The associated read/write data will not be stored.
On the MAC72xx, there are several sources of aborts that can be generated throughout the bus hierarchy,
including the following:
• AXBS
— Access to an unavailable slave port on the AXBS (S2, S4 and S6 on the MAC72xx). See
Section 15.7.2, “Master/Slave Interface” for more details.
— Writing to an AXBS slave address when the RO bit in the slave’s SGPCR register is set. See
Section 15.7.2, “Master/Slave Interface” for more details.
• FlexBus
— Access to the FlexBus hits no chip-select address ranges
• Flash
— Access to Flash blocked by the WACC/SACC/DACC access protection in the Flash Controller
and MCM
— Flash access produces an ECC error
— Flash access produces a Read-while-Write error
• SRAM
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Exception Handling
•
•
— SRAM access produces an ECC error
— Any SRAM access from $5000 to $7FFF (mirrored on a 32K boundary) — only on MAC72x2.
AIPS (See Section 9.9, “Peripheral Bus Memory Map” for a list of PACR/OPACR registers)
— User mode access to any AIPS slave with the corresponding SP bit set in the PACR/OPACR
register.
— Write to any AIPS slave with the corresponding WP bit set in the PACR/OPACR register.
— Any access from an untrusted master to any AIPS slave with the corresponding TP bit set in
the PACR/OPACR register.
— Any access to an AIPS slave that is not implemented (i.e.-marked as “Reserved” in the
documentation)
Access to a Peripheral Bus peripheral is aborted by the peripheral itself.
— Access to reserved addresses
— Access to locked registers (See AXBS registers for an example)
— Access to Supervisor only register when in User mode
The list is similar for the DMA, although the reporting mechanism is different (i.e.-no fault information is
available, only an error is reported). However, on the DMA, the contents of the TCD may be examined to
determine the cause of an aborted transfer.
Note that Instructions Aborts are only taken when the instruction enters the execution phase of the ARM7
pipeline.
In addition to flagging aborted instruction fetches, this exception is also used to implement the Non
Maskable Interrupt (NMI). Please refer to Section 7.3.4, “Non-Maskable Interrupt (NMI) for more details.
This means that the Instruction Abort ISR should first check to see if an NMI is pending before attempting
to service an aborted instruction fetch.
7.2.5
Data Abort
Address: $0000 0010
See Section 7.2.4, “Prefetch (Instruction) Abort” for details of special features. The Data Abort exception
is not used for the implementation of the NMI, and behaves as normal.
7.2.6
IRQ
Address: $0000 0018
7.2.7
FIQ
Address: $0000 001C
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Interrupts
7.3
Interrupts
The MAC72xx supports up to 64 programmable interrupt sources, with Request $00 having the highest
priority. Table 7-2 lists all 64 interrupts sources. Note that unused interrupt sources are reserved for future
use, and are not available to the user.
Table 7-2. Interrupt Sources
Signal
Interrupt
Requesta
Interrupt
Source
Priority
(1=highest)
ipi_int[0]
$00
DMA
64
ch0 - DMA Channel #0
ipi_int[1]
$01
DMA
63
ch1 - DMA Channel #1
ipi_int[2]
$02
DMA
62
ch2 - DMA Channel #2
ipi_int[3]
$03
DMA
61
ch3 - DMA Channel #3
ipi_int[4]
$04
DMA
60
ch4 - DMA Channel #4
ipi_int[5]
$05
DMA
59
ch5 - DMA Channel #5
ipi_int[6]
$06
DMA
58
ch6 - DMA Channel #6
ipi_int[7]
$07
DMA
57
ch7 - DMA Channel #7
ipi_int[8]
$08
DMA
56
ch8 - DMA Channel #8
ipi_int[9]
$09
DMA
55
ch9 - DMA Channel #9
ipi_int[10]
$0A
DMA
54
ch10 - DMA Channel #10
ipi_int[11]
$0B
DMA
53
ch11 - DMA Channel #11
ipi_int[12]
$0C
DMA
52
ch12 - DMA Channel #12
ipi_int[13]
$0D
DMA
51
ch13 - DMA Channel #13
ipi_int[14]
$0E
DMA
50
ch14 - DMA Channel #14
ipi_int[15]
$0F
DMA
49
ch15 - DMA Channel #15
ipi_int[16]
$10
DMA
48
err - DMA Channel Execution Error
ipi_int[17]
$11
MCM
47
swt - Software Watchdog Timer
ipi_int[18]
$12
CRG
46
lock - PLL locked
scm - Self Clock Mode entered
ipi_int[19]
$13
PIT
45
timer1 - Timer Channel 1
ipi_int[20]
$14
PIT
44
timer2 - Timer Channel 1
ipi_int[21]
$15
PIT
43
timer3 - Timer Channel 1
ipi_int[22]
$16
PIT
42
timer4 - Timer Channel 1
rti - Real Time Interrupt
ipi_int[23]
$17
MCM
41
ECC Error
ipi_int[24]
$18
CAN_A
40
mb0 to mb13 - Message Buffer
mb15 to mb31 - Message Buffer
ipi_int[25]
$19
CAN_A
39
mb14 - Message Buffer
Includes
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Interrupts
Table 7-2. Interrupt Sources
Signal
Interrupt
Requesta
Interrupt
Source
Priority
(1=highest)
ipi_int[26]
$1A
CAN_A
38
busoff - FlexCAN has entered the “Bus Off” state
error - Any of a number of FlexCAN errors
wakein - Asserted when the FlexCAN wakes up
txwarn/rxwarn - Repetitive errors detected
ipi_int[27]
$1B
CAN_B
37
mb0 to mb13 - Message Buffer
mb15 to mb31 - Message Buffer
ipi_int[28]
$1C
CAN_B
36
mb14 - Message Buffer
ipi_int[29]
$1D
CAN_B
35
busoff - FlexCAN has entered the “Bus Off” state
error - Any of a number of FlexCAN errors
wakein - Asserted when the FlexCAN wakes up
txwarn/rxwarn - Repetitive errors detected
ipi_int[30]
$1E
Unused
34
ipi_int[31]
$1F
Unused
33
ipi_int[32]
$20
Unused
32
ipi_int[33]
$21
Unused
31
ipi_int[34]
$22
Unused
30
ipi_int[35]
$23
Unused
29
ipi_int[36]
$24
IIC
28
ibal - Arbitration Lost condition
tcf - Byte Transfer condition
iaas - Address Detect condition
ipi_int[37]
$25
SPI_A
27
eoqf - End of Queue
tfff - TX FIFO Fill
tcf - Transfer Complete
tfuf - TX FIFO Underflow
rfdf - RX FIFO Drain
rfof - RX FIFO Overflow
overrun
ipi_int[38]
$26
SPI_B
26
eoqf - End of Queue
tfff - TX FIFO Fill
tcf - Transfer Complete
tfuf - TX FIFO Underflow
rfdf - RX FIFO Drain
rfof - RX FIFO Overflow
overrun
Includes
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Interrupts
Table 7-2. Interrupt Sources
Signal
Interrupt
Requesta
Interrupt
Source
Priority
(1=highest)
ipi_int[39]
$27
SCI_A
25
TDRE - Byte transferred to the transmit shift register
TC - Transmit complete
RDRF - Received data available in the SCI data register
IDLE - Receiver input has become idle
OR - Overrun condition
NF - Noise has been detected
FE - Frame error
PF - Parity error
BERR - Bit Error (only valid in LIN mode)
RXRDY - LIN hardware has received a data byte
TXRDY - LIN hardware can accept a control or data byte
LWAKE - A Wakeup Character has been received from
a LIN frame
STO - Slave TimeOut
PBERR - Physical Bus Error detected
CERR - CRC Error detected
CKERR - Checksum Error detected
FRC - LIN Frame completed
OVFL - LINRX Register Overflow
ipi_int[40]
$28
SCI_B
24
TDRE - Byte transferred to the transmit shift register
TC - Transmit complete
RDRF - Received data available in the SCI data register
IDLE - Receiver input has become idle
OR - Overrun condition
NF - Noise has been detected
FE - Frame error
PF - Parity error
BERR - Bit Error (only valid in LIN mode)
RXRDY - LIN hardware has received a data byte
TXRDY - LIN hardware can accept a control or data byte
LWAKE - A Wakeup Character has been received from
a LIN frame
STO - Slave TimeOut
PBERR - Physical Bus Error detected
CERR - CRC Error detected
CKERR - Checksum Error detected
FRC - LIN Frame completed
OVFL - LINRX Register Overflow
ipi_int[41]
$29
Unused
23
ipi_int[42]
$2A
Unused
22
ipi_int[43]
$2B
eMIOS
21
ch0 - eMIOS Channel 0
ipi_int[44]
$2C
eMIOS
20
ch0 - eMIOS Channel 1
ipi_int[45]
$2D
eMIOS
19
ch0 - eMIOS Channel 2
ipi_int[46]
$2E
eMIOS
18
ch0 - eMIOS Channel 3
ipi_int[47]
$2F
eMIOS
17
ch0 - eMIOS Channel 4
ipi_int[48]
$30
eMIOS
16
ch0 - eMIOS Channel 5
Includes
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Interrupts
Table 7-2. Interrupt Sources
Signal
Interrupt
Requesta
Interrupt
Source
Priority
(1=highest)
ipi_int[49]
$31
eMIOS
15
ch0 - eMIOS Channel 6
ipi_int[50]
$32
eMIOS
14
ch0 - eMIOS Channel 7
ipi_int[51]
$33
Unused
13
ch0 - eMIOS Channel 8 (not on MAC72x2)
ipi_int[52]
$34
Unused
12
ch0 - eMIOS Channel 9 (not on MAC72x2)
ipi_int[53]
$35
Unused
11
ch0 - eMIOS Channel 10 (not on MAC72x2)
ipi_int[54]
$36
Unused
10
ch0 - eMIOS Channel 11 (not on MAC72x2)
ipi_int[55]
$37
Unused
9
ch0 - eMIOS Channel 12 (not on MAC72x2)
ipi_int[56]
$38
Unused
8
ch0 - eMIOS Channel 13 (not on MAC72x2)
ipi_int[57]
$39
Unused
7
ch0 - eMIOS Channel 14 (not on MAC72x2)
ipi_int[58]
$3A
Unused
6
ch0 - eMIOS Channel 15 (not on MAC72x2)
ipi_int[59]
$3B
ATD_A
5
cqnf - Command Queue Not Full
cqf - Command Queue Full
cqe - Command Queue Empty
crl - Conversion Result Lost
eto - external Trigger Overrun
cp - Conversion Paused
cc - Conversion Complete
ipi_int[60]
$3C
SPI_C
4
eoqf - End of Queue
tfff - TX FIFO Fill
tcf - Transfer Complete
tfuf - TX FIFO Underflow
rfdf - RX FIFO Drain
rfof - RX FIFO Overflow
overrun
ipi_int[61]
$3D
PIM
3
ipi_int_pim[0] - Port A
ipi_int_pim[1] - Port B
ipi_int_pim[2] - Port C
ipi_int_pim[3] - Port D
ipi_int_pim[4] - Port E
ipi_int_pim[5] - Port F
ipi_int_pim[6] - Port G
ipi_int[62]
$3E
IRQ (PD4)
2
irq - IRQ pin asserted
ipi_int[63]
$3F
XIRQ (PD3)
1
xirq - XIRQ pin asserted
Includes
a. The Interrupt ‘Request is not the same as the Interrupt Vector Number as returned by the Interrupt Controller. The
relationship is defined in Equation 7-1.
Vector Number = Interrupt Request + 0x40
Eqn. 7-1
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Interrupts
7.3.1
Interrupt Clearing
By definition, all interrupt flags that can be cleared by accessing an interrupt status bit should be cleared
by writing ‘1’. Clear on read, or clear on write 0 are not allowed on the MAC72xx device. All interrupts
sources have been checked, and meet this requirement. The obvious exception are the external interrupts
XIRQ, IRQ and NMI.
7.3.2
XIRQ and IRQ
Please also see Section 7.3.4, “Non-Maskable Interrupt (NMI)” for details on the NMI, and the behaviour
of the XIRQ interrupt pin when in NMI mode.
7.3.3
PIT RTI and Timer 4
The PIT Timer 4 and RTI interrupts are OR’d together in order to allow maximum flexibility in PIT
interrupt generation. Combined with the fact that the Timer 4 and RTI interrupts can be masked
independently, this enables the following use cases:
• Mask RTI and unmask Timer 4: Timer 4 will generate the interrupt
• Mask Timer 4 and unmask RTI: RTI will generate the interrupt
• Unmask both: Timer 4 or RTI will generate the interrupt
• Mask both: no interrupts generated
7.3.4
Non-Maskable Interrupt (NMI)
The actual implementation of the NMI on the MAC72xx is done almost completely within the MCM
module. The NMI has the following features:
• Write-once enabling of NMI mode in order to improve fault tolerance
• Write-once selectable NMI polarity in order to improve fault tolerance
• NMI Pending status
Because the IRQ and FIRQ interrupts may be masked by software in the ARM7 core, and modification to
the ARM7 core was not deemed acceptable, an alternative method for implementing the NMI was
conceived. The ARM7 core exceptions look like:
Table 7-3. ARM7 Core Exception
Priority
Highest
Exception
Software Maskable ?
1
RESET
No
2
Data Abort
No
3
FIRQ
Yes
4
IRQ
Yes
5
Pre-fetch Abort
No
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Interrupts
Table 7-3. ARM7 Core Exception (Continued)
Priority
Lowest
Exception
Software Maskable ?
6
Undefined Instruction
No
7
SWI
Yes
There are several requirements for the NMI on the MAC72xx:
• NMI is re-entrant
• Minimize NMI latency
• Automatic disabling of IRQ/FIRQ during NMI handling with the possibility of explicit software
re-enable
• NMI has priority in the case of simultaneous NMI/Pre-fetch abort
The Data Abort exception has a higher priority in the core than the Instruction Abort, but since the NMI
must be associated with a bus access, the interrupt latency can be improved by associating it with
instruction fetches, which are far more frequent. This means that a normal Data Abort will have higher
priority than an NMI, which may not be desirable.
To implement a "truer" NMI, the abort could be forced, regardless of the access type (instruction or data).
This would place more burden on the customer, in that they would have to check for NMIs in both the
Instruction and Data Abort exception routines, but this would give us a statistically better latency at least.
However, even with this scheme, there is no guaranteed latency. Due to the nature of the ARM instruction
set (i.e.-almost all instructions can be made conditional), a handshaking scheme should be implemented
that tags every bus access with an NMI-caused abort until the user services the NMI. It may be tricky to
avoid re-entrancy of the Data Abort routine with this scheme.
The sequence of events in the system looks like the following:
1. System resets in non-NMI mode
2. Software puts the SoC put into NMI mode and sets NMI polarity by writing a write-once register
in the MCM. Until this happens the NMI interrupts are disabled, regardless of the value of the
ipi_nmi input.
3. Once NMI mode is entered, the SoC forces proper sensitization of the path from ipp_ind (pad
PD3) to the ipp_nmi input on the platform.
4. When a change from passive to active is seen on ipi_nmi (i.e.-edge sensitive), the MCM performs
the following actions:
— Set the NMI Pending bit in the MCM
— Drive the FIRQ/IRQ inputs to the core negated
— Begin tagging all instruction fetches as aborted
5. When one of the tagged instructions enters the execute phase in the ARM7 pipeline, a Pre-fetch
abort exception is taken (assuming no higher exception occurs at the same time).
6. Upon seeing the instruction fetch to $0000_000C (Pre-fetch abort), the MCM stops tagging the
instructions.
7. The ISR saves off all registers (i.e.-switch context, PC, PSR, etc.)
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Interrupts
8. The ISR reads the NMI pending bit to determine if the exception was due to an NMI or to a real
Pre-fetch abort. This provides the simplest (i.e.-lowest latency) NMI recognition, as well as
providing for the case where a simultaneous NMI and Pre-fetch abort occur. In this case, the NMI
should be serviced first (because the ISR sees a pending NMI). Once the NMI ISR is completed,
the ARM core will try to re-fetch the "offending" instruction, so any "real" Pre-fetch aborts will be
taken again.
9. Once the NMI branch of the ISR is taken, the ISR can set or clear the F and I bits in the CPSR to
determine if a FIRQ/IRQ exception should be allowed during execution of the NMI handler.
Remember, during this time, the FIRQ/IRQ signals to the ARM core are being forced negated by
the MCM
10. Next, the ISR should write ’1’ to the NMI Pending bit. This will cause the MCM to do 2 things:
— Stop forcing the FIRQ/IRQ negated, thereby enabling/disabling the FIRQ/ IRQ based solely on
the F/I bits in the CPSR
— Enable another NMI (i.e.-re-entrant NMI). This is automatic, since the NMI input is edge
sensitive (i.e.-you must negate it by clearing the source before it can be asserted again).
11. Once the NMI input is negated, another active edge of the NMI will trigger a new NMI exception,
if the NMI pending bit was written ‘1’ (i.e.-Step #10). If NMI re-entrancy is not desired, the NMI
pending bit can be written at the end of the exception handler.
Since the Data Abort exception has higher priority than the Pre-fetch abort, the Data Abort exception
handler may be entered while an NMI is pending. Since the Data Abort is not tagged for a pending NMI,
and Data Aborts received are true Data Aborts. Upon entering the Data Abort exception, the first
instruction fetch is tagged by the NMI hardware, and the Pre-fetch Abort exception handler will be called,
thus guaranteeing higher NMI priority with a small latency penalty.
When the device is in NMI mode, pin PD[3] is used exclusively for the NMI. As such, the following
special behavior is in effect:
• The XIRQ interrupt input to the platform is driven low (disabled)
• The port control signals from the PIM are ignored, so that the pad is always configured to be an
input.
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ipi_nmi
AHB
Addr
HW: MCM
HW: ARM7
SW: ISR
Exception
Taken
Initial NMI
$0000000C
Start Tagging
Force IRQ/FIRQ
Stop
negated
Tagging
Set NMI
pending bit
NMI
SW: Application Mode
Enabled
NMI Timeline
Clear NMI
pending bit
Release
IRQ/FIRQ
Switch Read NMI Set/Clear Write ‘1’
Context Pending F/I bits to NMI
register
Pending bit
Re-entrant NMI
$0000000C
NMI
Handler
Interrupts
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Exceptions Differences from the MAC71xx
7.4
•
•
Exceptions Differences from the MAC71xx
NMI functionality added, which uses the Prefetch Abort exception to signal an NMI
Interrupt sources re-mapped. Please refer to Section 14.5, “INTC Differences from MAC71xx”
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Chapter 8
Debug
8.1
Debug Introduction
The MAC7200 family of devices offers debugging with the ARM Core’s EmbeddedICE and a NEXUS 3
interface. EmbeddedICE offers debug features such as setting Breakpoints or Watchpoints, modifying and
reading memory contents. EmbeddedICE uses the standard JTAG serial interface and Test Access Port
(TAP), and is compatible with existing ARM tool chains. The NEXUS interface provides real time
program and data trace capability and also uses the JTAG port, as well as providing an auxiliary port. The
auxiliary port can be provided in two pin positions depending on the device and package. Please refer to
Chapter 11, “A7S Nexus3 Module” for more information on configuring and using the Nexus interface.
For details on the E-ICE interface please refer to Debugging Your System in the ARM7TDMI-S Users
Manual, or ARM Application Note 31’ Using Embedded’.
8.2
•
•
•
8.3
Debug Features
Customer visible SC4 Debug Register with the following functionality:
— JTAG Lockout Recovery
— Device ID
— Debug Reset
— Chip Status
— Core Run Control
Please refer to Section 10.2, “ARM7 Features” for a list of debug related ARM7 features.
Please refer to Section 11.1.2, “Nexus Feature List” for a list of debug related Nexus features.
Debug Protocol
The JTAG interface and TAP state machine follow the IEEE 1149.1-1990 protocol. Note that the
MAC72xx does not support JTAG, but simply uses the JTAG protocol as a standard debug interface.
8.4
8.4.1
Debug Implementation
JTAG Interface
The JTAG interface on the MAC72xx is accessed using the following pins:
• TCK - Input Clock
• TMS - Input Mode Select
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Debug Implementation
•
•
TDI - Serial Data In
TDO - Serial Data Out
Through the JTAG interface, the following may be accessed (See also Table 11-8):
• ARM7 EICE registers
• Nexus registers
• Debug register (SC4)
Although there are several blocks of logic that can be accessed through the JTAG interface, the MAC72xx
contains only a single TAP state machine, located in the ARM7 complex. This TAP State Machine is used
to select the various JTAG-accessible registers in the system. This is illustrated in Figure 8-1.
TCK
ARM7
PTI
tck/tms/tdi/tdo
TMS
TDI
dbg_ir[3:0]
Synchr.
Logic
TAP State
Machine
dbg_tapsm[3:0]
TDO
dbg_scan_n[3:0]
Nexus
Figure 8-1. JTAG Interface Overview
Selection between the different pieces of Test Logic on the MAC72xx is done by decoding the dbg_ir[3:0]
and dbg_scan_n[3:0] signals from the TAP state machine. Table 8-1 shows the decoding for the
MAC72xx. The dbg_tapsm[3:0] signal is the current state of the TAP state machine, and is used by the
PTI and Nexus to determine which JTAG state the TAP is currently in.
Table 8-1. JTAG Test Logic Selection
dbg_ir[3:0]
dbg_scan_n[3:0]
Function
$2 (SCAN_N)
$4
ARM7 Scan Chain 0 Selected
$C (INTEST)
$4
Debug Register SC4 Selected
$8 (NEXUS_ACCESS)
n/a
Nexus Selected
Based on which test logic is selected, the TCK, TMS, TDI and TDO inputs/outputs are routed to the correct
destination. The following figures illustrate this.
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Debug Implementation
8.4.1.1
TCK Routing
The TCK signal from the pad is synchronized, and then drives the TCK inputs of the PTI logic, Nexus logic
and the ARM7. See Section 8.4.2, “Synchronization” for more details on how TCKEN is used to
synchronize TMS and TDI.
PTI
TCK
ipp_ind_tck
Synch.
Logic
dbg_tcken_sync dbg_tcken_platform
To ARM7/Nexus
Figure 8-2. JTAG TCK Routing
8.4.1.2
TMS Routing
The TMS signal from the pad is synchronized, and then drives the TMS inputs of the PTI logic, Nexus
logic and the ARM7. The TMS input of the SoC must be valid on the rising edge of the TCK clock, with
the appropriate setup and hold requirements. If the TMS signal is asserted based on the falling clock edge
of TCK, and the maximum TCK frequency is not exceeded, then the setup and hold requirements for TMS
are guaranteed to be met.
PTI
TMS
ipp_ind_tms
Synch.
Logic
dbg_tms_sync
dbg_tms_platform
To ARM7/Nexus
Figure 8-3. JTAG TMS Routing
8.4.1.3
TDI Routing
The TDI signal from the pad is synchronized, and then muxed in to drive the TDI inputs of the PTI logic,
Nexus logic and the ARM7. The synchronized signal is muxed in order to provide additional security when
the debug is disabled in the system for Flash security. When the debug is disabled, the INTEST instruction
is selected, and the TAP state machine is in the Shift-DR state, the TDI input to the platform is tied low.
The TDI input to the PTI logic (SC4/5/6/7) is always driven by dbg_tdi_sync, thus allowing the writing
and reading of SC4/5/6/7 even when debug is disabled. This is to allow the user to run the JTAG Lockout
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Debug Implementation
Recovery, which can be used to unsecure the device and thereby enable all debug features. The TDI input
of the SoC must be valid on the rising edge of the TCK clock, with the appropriate setup and hold
requirements. If the TDI signal is asserted based on the falling clock edge of TCK, and the maximum TCK
frequency is not exceeded, then the setup and hold requirements for TDI are guaranteed to be met.
PTI
Synch.
Logic
ipp_ind_tdi
TDI
dbg_tdi_sync
0
1
dbg_tdi_platform
To ARM7/Nexus
1’b0
PTI Test Logic
debug disabled
&
INTEST/Shift-DR
Figure 8-4. JTAG TDI Routing
8.4.1.4
TDO Routing
The TDO signal is driven by one of many test logic sources (See Table 8-1). If no test logic source is
selected, the ARM7 will drive the TDO signal low.
ARM7
Nexus
PTI
Nexus TDO
1
0
ARM7 TDO
1
0
1’b0
SC0/1
Selected
Nexus
Selected
dbg_tdo
1
0
TDO
tdosel
nex_tdo
test_tdo
PTI TDO
JTAG Test
Register Selected
Figure 8-5. JTAG TDO Routing
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Debug Implementation
8.4.2
Synchronization
As with any external input, it is necessary to synchronize the TCK, TMS and TDI inputs to the internal
clock of the TAP state machine (ipg_clk). However, in the case of these signals, it is not necessary to
synchronize all three signals, as TMS and TDI are driven externally with respect to TCK. Therefore, the
synchronization can be performed by synchronizing the TCK input, and then generating an enable
(tap_enable) signal from this synchronization logic that is used to strobe the TMS and TDI inputs. The
actual logic is illustrated in Figure 8-6, and the timing is described in Figure 8-7.
dbg_tck_sync
tap_enable
TCK
D Q
CK
sync1
D Q
CK
sync2
D Q
sync3
CK
ipg_clk
TMS
D Q
dbg_tms_sync
CK
TDI
D Q
dbg_tdi_sync
CK
Figure 8-6. JTAG Synchronization Circuit
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Debug Implementation
ipg_clk
TCK
sync1
sync2
sync3
sync3
tap_enable
(sync2 & sync3)
Figure 8-7. JTAG Synchronization Timing (TCK = 1/3 frequency of ipg_clk)
ipg_clk
TCK
TDI
sync1
sync2
sync3
sync3
tap_enable
(sync2 & sync3)
Figure 8-8. JTAG Synchronization Timing (TCK = 1/8 frequency of ipg_clk)
Even though Figure 8-7 illustrates the case where TCK is 1/3 the frequency of the system clock, the actual
maximum operating speed of the TCK input is 1/8 the frequency of the system clock. This is done to
account for differences in insertion delay between TCK, TMS and TDI without having to constrain the
timing of these pins.
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Debug External Pins
8.4.3
Debug Reset
See Section 6.4, “Debug Reset” for a complete description of debug logic resets.
8.5
Debug External Pins
Table 8-2. Debug External Pins
Pin
Description
TCK JTAG Input Clock. This pin provides the test clock input to synchronize the device’s test
logic. TCK is independent of the processor clock, and is used only as the reference clock
for the TMS, TDI and TDO pins. During and after a system reset, this pin will be configured
as an input with an internal pull-down active on this signal. This pull-down is implemented
using active elements, and is approximately equivalent to a 20KOhm resistor under typical
operating conditions.
TMS JTAG Input Mode Select. This pin is used to input the test mode to sequence the TAP
controller’s state machine. The pin is sampled on the rising edge of the TCK pin. During
and after a system reset, this pin will be configured as an input with an internal pull-up
active on this signal. This pull-up is implemented using active elements, and is
approximately equivalent to a 20KOhm resistor under typical operating conditions.
TDI JTAG Serial Data In. This serial pin is sampled in the device on the rising edge of the TCK
pin. During and after a system reset, this pin will be configured as an input with an internal
pull-up active on this signal. This pull-up is implemented using active elements, and is
approximately equivalent to a 20KOhm resistor under typical operating conditions.
TDO JTAG Serial Data Out. This pin is a three-state test data output pin that is actively driven in
the shift-IR and shift-DR controller states. The pin state changes on the falling edge of the
TCK pin. During and after a system reset, this pin will be configured as an output with
maximum slew rate enabled.
8.6
Debug Bus Aborts
There is no bus interface to any of the debug logic.
8.7
Debug Differences from MAC71xx
See Section 11.7, “Nexus Differences from MAC71xx”.
8.8
Debug Application Usage
The Debug Mode of the system is completely determined by the Debug state of the ARM7 core. Therefore,
please refer to the ARM7 documentation for all of the possible ways for the ARM7 core to enter the debug
state.
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Debug Application Usage
8.8.1
ARM Debug Overview
Halt Mode
DCR[4]=0
Breakpoint
DBGBREAK=1
Instruction Fetch
Watchpoint
DBGRQ=1
Operand Fetch
Enter debug state after
instruction fetch, but before instruction
execute, even if the instruction is
conditional, and
the condition is not met.
Enter debug state after
execution of the current instruction.
Debug State
Figure 8-9. Halt Mode Overview
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Debug Application Usage
Monitor Mode
DCR[4]=1
Breakpoint
DBGBREAK=1
Watchpoint
Instruction Fetch
DBGRQ=1
Operand Fetch
Instruction
Abort
Exception
No
Action
Data
Abort
Exception
Figure 8-10. Monitor Mode Overview
Table 8-3. ARM7TDMI-S Debug State Overview
8.8.2
•
Debug State
Monitor Mode
Processor
External bus indicates “internal cycles”
Processor executes normally
Interrupts
Disabled
Enabled
Aborts
Disabled
Enabled. Instruction/Data Abort also
triggered by Breakpoint/Watchpoint,
respectively.
JTAG Interface
Active
Can insert instructions into the ARM
instruction pipeline to examine registers and
system state
Active
Can communicate with a software monitor
executing on the core
Entering Debug mode
The ARM7 core is forced into a debug state
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Debug Application Usage
•
•
•
•
•
•
•
8.8.3
•
•
•
•
•
•
•
8.8.4
The ARM7 core is placed into Halt Mode or Monitor Mode, depending on the state of the DCR[4]
bit.
The ARM7 core asserts the DBGACK output
The CRG asserts the ipg_debug signal
The Real Time Interrupt (RTI) clock rti_osc_ps_clk is shut off by the CRG
The Software Watchdog Timer (SWT) clock swt_osc_ps_clk is shut off by the CRG
Debug Mode is optional for all peripherals except the SWT and RTI
All peripheral level debug features are enabled (Please refer to the individual chapters for a
complete description of functionality in Debug Mode).
— DMA2
— FlexCAN2
— DSPI
— eMIOS
— ATD
— MCM (Software Watchdog Timer)
Exiting Debug mode
The ARM7 core exits the debug state
The ARM7 core exits Halt/Monitor Mode
The ARM7 core negates the DBGACK output
The CRG negates the ipg_debug signal
The Real Time Interrupt (RTI) clock rti_osc_ps_clk is turned on by the CRG
The Software Watchdog Timer (SWT) clock swt_osc_ps_clk is turned on by the CRG
All peripheral level debug features are disabled (Please refer to the individual chapters for a
complete description of functionality in Debug Mode).
— DMA2
— FlexCAN2
— DSPI
— eMIOS
— ATD
— MCM (Software Watchdog Timer)
Nexus Low Power State
Both the Debug and Doze mode states may be determined by reading out the Nexus LPS bits. Please refer
to Table 11-9 for the exact encodings.
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Debug Application Usage
8.8.5
Debug Shift Register SC4
Please refer to Section 35.1.1, “JTAG Test Register (SC4)”.
8.8.6
Using the JTAG Interface
Because the JTAG interface requires internal clocks for synchronization, it is generally not safe to assume
that the interface is available all of the time. In particular, there are several situations where the JTAG
interface may not be available:
• Immediately after a Power On Reset (POR)
• Immediately after a loss of clock condition
In general, under normal operating conditions, the JTAG interface may be used while the RESET is
asserted for a normal system reset. The safest approach is to reset the device, program the debug registers,
and then reset the device again. Since the debug logic is not reset by a normal system reset, this procedure
is guaranteed to work.
In order to meet the IEEE 1149.1-1990 JTAG specification, it is required that the JTAG interface be run at
no faster than 1/8 the system clock frequency. As an example, for an 80MHz system, the maximum TCK
frequency is 10MHz. There may be further limitations introduced by the development system or PCB. If
the debug system does not seem to be functioning correctly, try reducing the JTAG speed and resetting the
system.
8.8.7
JTAG Pad Control
Control of the JTAG related pads is done purely from the PIM registers, as follows:
TCK
•
•
Can configure pull-up or pull-down
Can disable the TDI functionality. In this case, the pad becomes an output (driven low), and the
internal TDI signal is driven low (0).
TMS
•
•
TDI
•
•
Can configure pull-up or pull-down
Can disable the TDI functionality. In this case, the pad becomes an output (driven low), and the
internal TDI signal is driven low (0).
Can configure pull-up or pull-down
Can disable the TDI functionality. In this case, the pad becomes an output (driven low), and the
internal TDI signal is driven low (0).
TDO
• Can configure slew rate
• Can disable the TDO functionality. In this case, the pad becomes an input (All changes on the pad
are ignored by the system).
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Freescale Semiconductor
101
Debug Application Usage
8.8.8
Resetting Debug Logic
Please refer to Section 6.4, “Debug Reset” for a complete description of debug logic resets.
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Freescale Semiconductor
Chapter 9
Device Memory Map
This section describes the memory map of the MAC72xx after reset, in the various possible chip modes.
For more details on selecting chip modes, please refer to Chapter 2, “Modes of Operation”. The memory
map of the device immediately following reset is different based on the mode of operation that has been
selected, but is largely re-mappable following reset. It is possible to re-map the flash main array and
shadow block, the SRAM and the external bus interface using the AAMR register in the MCM module,
but not the ARM7 exception table, which is fixed at $0000 0000 to $0000 001F, Figure 9-1 shows the
device memory map at reset in each of the various device modes.
Normal
Single
Chip
Secured
Single
Chip
$0000 0000
Flash
Main
Array
Flash
Main
Array
$00F0 0000
Shadow
Block
Shadow
Block
$2000 0000
FlexBus
$20F0 0000
Normal
Expanded
Secured
Expanded
Normal
Bootload
Secured
Bootload
Lockout
Recovery
FlexBus
FlexBus
Shadow
Block
Shadow
Block
BAM
Flash
Main
Array
Flash
Main
Array
Flash
Main
Array
Flash
Main
Array
Shadow
Block
Shadow
Block
Shadow
Block
Shadow
Block
$4000 0000
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
SRAM
BAM
BAM
BAM
BAM
BAM
BAM
BAM
Peripheral
Bus
Peripheral
Bus
Peripheral
Bus
Peripheral
Bus
Peripheral
Bus
Peripheral
Bus
Peripheral
Bus
$6000 0000
$8000 0000
$A000 0000
$C000 0000
$E000 0000
Figure 9-1. MAC72xx Memory Map Overview
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
103
Memory Map Example
9.1
Memory Map Example
Figure 9-2. MAC72x1 Memory Map Example
$0000 0000
$0000 0000
$0000 0020
ARM Core Exception
Table
$0000 001F
VECTORS
$0000 0000
$0000 0000
VECTORS
ARM Core Exception
Table
$0000 001F
$0000 0000 External Interface
512K Bytes Flash
EEPROM
$0007 FFFF Mappable
$1FFF FFFF Mappable
$2000 0000
$2000 0000 512K Bytes Flash
$2000 0000
$3FFF FFFF
EEPROM
External Interface
Mappable
$2007 FFFF Mappable
32K Bytes RAM
$4000 0000
$4000 0000
$4000 0000
32K Bytes RAM
$4000 7FFF Mirrored on
$4000 7FFF Mirrored on
32K Boundary
32K Boundary
$6000 0000
$8000 0000
$A000 0000
$C000 0000
$7C00 0000 1.5M Bytes Control
$E000 0000 1.5M Bytes Control
Register space
Register space
$E000 0000
$7C17 FFFF
$FC10 FFFF
$FFFF 0000
NORMAL
SINGLE CHIP
EXPANDED
After reset the map is:
Normal Single Chip Mode
Normal Expanded Chip Mode
$0000 0000 - $0007 FFFF: 512K Flash
$00F0 0000 - $00F0 7FFF: 32K Shadow Block
$2000 0000 - $3FFF FFFF: External Bus
$4000 0000 - $4000 7FFF: 32K RAM
$FC00 0000 - $FC03 FFFF: Register Space
$2000 0000 - $2007 FFFF: 512K Flash
$20F0 0000 - $20F0 7FFF: 32K Shadow Block
$0000 0000 - $1FFF FFFF: External Bus
$4000 0000 - $4000 7FFF: 32K RAM
$FC00 0000 - $FC03 FFFF: Register Space
Flash, External Interface and RAM space can all be remapped in software on 512M byte boundaries
after Reset. The ARM core exception table can not be remapped.
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Freescale Semiconductor
Normal Single Chip Mode
Figure 9-3. MAC72x2 Memory Map Example
$0000 0000
$0000 0000
$0000 0020
ARM Core Exception
Table
$0000 001F
VECTORS
$0000 0000
$0000 0000
VECTORS
ARM Core Exception
Table
$0000 001F
$0000 0000 External Interface
320K Bytes Flash
EEPROM
$0004 FFFF Mappable
$1FFF FFFF Mappable
$2000 0000
$2000 0000 320K Bytes Flash
$2000 0000
$3FFF FFFF
EEPROM
External Interface
Mappable
$2004 FFFF Mappable
20K Bytes RAM
$4000 0000
$4000 0000
$4000 0000
20K Bytes RAM
$4000 4FFF Mirrored on
$4000 4FFF Mirrored on
32K Boundary
32K Boundary
$6000 0000
$8000 0000
$A000 0000
$C000 0000
$7C00 0000 1.5M Bytes Control
$E000 0000 1.5M Bytes Control
Register space
Register space
$E000 0000
$7C17 FFFF
$FC10 FFFF
$FFFF 0000
NORMAL
SINGLE CHIP
EXPANDED
After reset the map is:
Normal Single Chip Mode
Normal Expanded Chip Mode
$0000 0000 - $0004 FFFF: 320K Flash
$00F0 0000 - $00F0 7FFF: 32K Shadow Block
$2000 0000 - $3FFF FFFF: External Bus
$4000 0000 - $4000 4FFF: 20K RAM
$FC00 0000 - $FC03 FFFF: Register Space
$2000 0000 - $2004 FFFF: 320K Flash
$20F0 0000 - $20F0 7FFF: 32K Shadow Block
$0000 0000 - $1FFF FFFF: External Bus
$4000 0000 - $4000 4FFF: 20K RAM
$FC00 0000 - $FC03 FFFF: Register Space
Flash, External Interface and RAM space can all be remapped in software on 512M byte boundaries
after Reset. The ARM core exception table can not be remapped.
9.2
Normal Single Chip Mode
Normal Single Chip Mode is typically used to debug and develop application code, where a software
bootloader is not required. Booting is performed from the Flash main array, and all functionality is
available. In this mode, the following functionality is available:
• Debug functionality (EICE, Nexus and the JTAG interface) is enabled
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
105
Normal Single Chip Mode
•
•
•
•
External Bus Interface is enabled
Flash main array access is enabled
Shadow Block access is enabled
Boot from the Flash main array
Table 9-1 shows the device memory map of the MAC72xx in Normal Single Chip Mode after Reset.
Table 9-1. Device Memory Map in Normal Single Chip Mode (After Reset)1
Address
Size
(Bytes)
Module
$0000 0000 - $0007 FFFF
$0000 0000 - $0004 FFFF
Flash main array2 (MAC72x1)
Flash main array2 (MAC72x2)
$00F0 0000 - $00F0 7FFF
Shadow Block
$0008 0000 - $1FFF FFFF
Reserved
$2000 0000 - $3FFF FFFF
External Bus Interface
$4000 0000 - $4000 7FFF
$4000 0000 - $4000 4FFF
SRAM3
(MAC72x1)
SRAM3 (MAC72x2)
$4000 8000 - $FBFF FFFF
Reserved
$FC00 0000 - $FFFF FFFF
Peripheral Bus modules
512K
320K
32K
~511M
512M
32K
20K
~3008M
64M
1. This reset memory map equates to a reset value of $f0d0 0b98 in the AAMR register in the MCM module.
2. The Exception Vector Table is located at $0000 0000 - $0000 001F in the Flash main array.
3. The SRAM is mirrored across the entire 512MByte address range on a 32K boundary. Please refer to
Section 9.10, “SRAM Memory Map”.
After Reset, the memory map may be re-mapped using the AAMR register in the MCM module. The
allowed combinations are shown in Table 9-2. The Peripheral Bus space is always fixed at $FC00 0000,
and is not re-mappable.
Table 9-2. Allowed Memory Maps in Normal Single Chip Mode
$0000 0000
$2000 0000
$4000 0000
AAMR Register
External Bus
Flash Main Array
SRAM
$f0d0 0b89
Unused
Flash Main Array
SRAM
$f0d0 0b80
SRAM
Flash Main Array
SRAM
$f0d0 0b8b
Flash Main Array
External Bus
SRAM
$f0d0 0b98
External Bus
External Bus
SRAM
$f0d0 0b99
Unused
External Bus
SRAM
$f0d0 0b90
SRAM
External Bus
SRAM
$f0d0 0b9b
Flash Main Array
Unused
SRAM
$f0d0 0b08
External Bus
Unused
SRAM
$f0d0 0b09
Unused
Unused
SRAM
$f0d0 0b00
SRAM
Unused
SRAM
$f0d0 0b0b
Flash Main Array
SRAM
SRAM
$f0d0 0bb8
External Bus
SRAM
SRAM
$f0d0 0bb9
Unused
SRAM
SRAM
$f0d0 0bb0
SRAM
SRAM
SRAM
$f0d0 0bbb
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Freescale Semiconductor
Normal Primary Bootloader Mode
9.3
Normal Primary Bootloader Mode
Normal Primary Bootloader Mode is typically used to debug and develop application code, where a
software bootloader is required. Booting is performed from the Shadow Block, and all functionality,
except the External Bus, is available. In this mode, the following functionality is available:
• Debug functionality (EICE, Nexus and the JTAG interface) is enabled
• External Bus Interface is disabled
• Flash main array access is enabled
• Shadow Block access is enabled
• Boot from the Shadow Block
Table 9-3 shows the device memory map of the system in both Normal and Secured Primary Bootloader
Mode after Reset. The memory map for this mode differs from the memory map in Normal Single Chip
Mode as follows:
• The Shadow Block is mirrored to address $0000 0000. Note that the mirroring (rather than
relocating) of the Shadow Block means that it is available both at address $0000 0000 and at
address $20F0 0000.
• The Flash Main Array is relocated to address $2000 0000
• The External Bus Interface is not available
Table 9-3. Device Memory Map in Normal/Secured Primary Bootloader Mode (After Reset)1
Address
Module
$0000 0000 - $0000 7FFF
Shadow Block2
$0000 8000 - $1FFF FFFF
Reserved
$2000 0000 - $2007 FFFF
$2000 0000 - $2004 FFFF
Flash Main Array (MAC72x1)
Flash Main Array (MAC72x2)
$20F0 0000 - $20F0 7FFF
Shadow Block2
$2008 0000 - $3FFF FFFF
Reserved
$4000 0000 - $4000 7FFF
$4000 0000 - $4000 4FFF
SRAM3 (MAC72x1)
SRAM3 (MAC72x2)
$4000 8000 - $FBFF FFFF
Reserved
$FC00 0000 - $FFFF FFFF
Peripheral Bus modules
Size
(Bytes)
32K
~511M
512K
320K
32K
~511M
32K
20K
~3008M
64M
1. This reset memory map equates to a reset value of $f0d0 0b80 in the AAMR register in the MCM module.
2. The Shadow Block is available at both $0000 0000 and $20F0 0000.
3. The SRAM is mirrored across the entire 512MByte address range on a 32K boundary. Therefore, the first
word in SRAM may be read from or written to using address $4000 0000 or address $4000 8000 or address
$4001 0000, etc.
After Reset, the memory map may be re-mapped using the AAMR register in the MCM module. The
allowed combinations are shown in Table 9-4. The Peripheral Bus space is always fixed at $FC00 0000,
and is not re-mappable.
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
107
Normal Expanded Mode
Table 9-4. Allowed Memory Maps in Normal Primary Bootloader Mode
9.4
$0000 0000
$2000 0000
$4000 0000
AAMR Register
Unused
Flash Main Array
SRAM
$f0d0 0b80
SRAM
Flash Main Array
SRAM
$f0d0 0b8b
Flash Main Array
Unused
SRAM
$f0d0 0b08
Unused
Unused
SRAM
$f0d0 0b00
SRAM
Unused
SRAM
$f0d0 0b0b
Flash Main Array
SRAM
SRAM
$f0d0 0bb8
Unused
SRAM
SRAM
$f0d0 0bb0
SRAM
SRAM
SRAM
$f0d0 0bbb
Normal Expanded Mode
Normal Expanded Mode is typically used to debug and develop application code from an external memory.
Booting is done from the external bus, and all functionality is available. The advantage of debugging code
from an external memory (versus the internal Flash Main Array), is that software breakpoints may be
inserted without the added burden of re-programming the Flash Main Array. In this mode, the following
functionality is available:
• Debug functionality (EICE, Nexus and the JTAG interface) is enabled
• External Bus Interface is enabled
• Flash main array access is enabled
• Shadow Block access is enabled
• Boot from the External Bus
Table 9-5 shows the device memory map of the device in Normal Expanded Mode after Reset. The
memory map for this mode differs from the memory map in Normal Single Chip Mode as follows:
• The External Bus Interface is relocated to address $0000 0000
• The Flash Main Array is relocated to address $2000 0000
Table 9-5. Device Memory Map in Normal Expanded Mode (After Reset)1
Address
Module
Size
(Bytes)
$0000 0000 - $1FFF FFFF
External Bus Interface
512M
$2000 0000 - $2007 FFFF
$2000 0000 - $2004 FFFF
Flash Main Array (MAC72x1)
Flash Main Array (MAC72x2)
512K
320K
$20F0 0000 - $20F0 7FFF
Shadow Block
$2008 0000 - $3FFF FFFF
Reserved
$4000 0000 - $4000 7FFF
$4000 0000 - $4000 4FFF
SRAM2
SRAM2
$4000 8000 - $FBFF FFFF
Reserved
$FC00 0000 - $FFFF FFFF
Peripheral Bus modules
32K
~511M
32K
20K
3008M
64M
1. This reset memory map equates to a reset value of $f0d0 0b89 in the AAMR register in the MCM module.
MAC7200 Microcontroller Family Reference Manual, Rev. 2
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Freescale Semiconductor
Secured Single Chip Mode
2. The SRAM is mirrored across the entire 512MByte address range on a 32K boundary. Therefore, the first
word in SRAM may be read from or written to using address $4000 0000 or address $4000 8000 or address
$4001 0000, etc.
After Reset, the memory map may be re-mapped using the AAMR register in the MCM module. The
allowed combinations are shown in Table 9-6. The Peripheral Bus space is always fixed at $FC00 0000,
and is not re-mappable.
Table 9-6. Allowed Memory Maps in Normal Expanded Mode
9.5
$0000 0000
$2000 0000
$4000 0000
AAMR Register
External Bus
Flash Main Array
SRAM
$f0d0 0b89
Unused
Flash Main Array
SRAM
$f0d0 0b80
SRAM
Flash Main Array
SRAM
$f0d0 0b8b
Flash Main Array
External Bus
SRAM
$f0d0 0b98
External Bus
External Bus
SRAM
$f0d0 0b99
Unused
External Bus
SRAM
$f0d0 0b90
SRAM
External Bus
SRAM
$f0d0 0b9b
Flash Main Array
Unused
SRAM
$f0d0 0b08
External Bus
Unused
SRAM
$f0d0 0b09
Unused
Unused
SRAM
$f0d0 0b00
SRAM
Unused
SRAM
$f0d0 0b0b
Flash Main Array
SRAM
SRAM
$f0d0 0bb8
External Bus
SRAM
SRAM
$f0d0 0bb9
Unused
SRAM
SRAM
$f0d0 0bb0
SRAM
SRAM
SRAM
$f0d0 0bbb
Secured Single Chip Mode
Secured Single Chip Mode is typically used to execute application code in the final application, where a
software bootloader is not required. Booting is done from the Flash Main Array, with limited device
functionality. In this mode, the following functionality is available:
• Debug functionality (EICE, Nexus and the JTAG interface) is disabled
— SC4 chain is still enabled
• External Bus Interface is disabled
• Flash main array access is enabled
• Shadow Block access is enabled
• Boot from the Flash main array
Table 9-7 shows the device memory map of the device in Secured Single Chip Mode after Reset. The
memory map for this mode differs from the memory map in Normal Single Chip Mode as follows:
• The External Bus Interface is not available
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
109
Secured Primary Bootloader Mode
Table 9-7. Device Memory Map in Secured Single Chip Mode (After Reset)1
Address
Size
(Bytes)
Module
$2000 0000 - $2007 FFFF
$2000 0000 - $2004 FFFF
Flash Main Array (MAC72x1)
Flash Main Array (MAC72x2)
$00F0 0000 - $00F0 7FFF
Shadow Block
$0008 0000 - $3FFF FFFF
Reserved
$4000 0000 - $4000 7FFF
$4000 0000 - $4000 4FFF
SRAM2
SRAM2
$4000 8000 - $FBFF FFFF
Reserved
$FC00 0000 - $FFFF FFFF
Peripheral Bus modules
512K
320K
32K
~1023M
32K
20K
3008M
64M
1. This reset memory map equates to a reset value of $f0d0 0b08 in the AAMR register in the MCM module.
2. The SRAM is mirrored across the entire 512MByte address range on a 32K boundary. Therefore, the first
word in SRAM may be read from or written to using address $4000 0000 or address $4000 8000 or address
$4001 0000, etc.
After Reset, the memory map may be re-mapped using the AAMR register in the MCM module. The
allowed combinations are shown in Table 9-8. The Peripheral space is always fixed at $FC00 0000, and is
not re-mappable.
Table 9-8. Allowed Memory Maps in Secured Single Chip Mode
9.6
$0000 0000
$2000 0000
$4000 0000
AAMR Register
Unused
Flash Main Array
SRAM
$f0d0 0b80
SRAM
Flash Main Array
SRAM
$f0d0 0b8b
Flash Main Array
Unused
SRAM
$f0d0 0b08
Unused
Unused
SRAM
$f0d0 0b00
SRAM
Unused
SRAM
$f0d0 0b0b
Flash Main Array
SRAM
SRAM
$f0d0 0bb8
Unused
SRAM
SRAM
$f0d0 0bb0
SRAM
SRAM
SRAM
$f0d0 0bbb
Secured Primary Bootloader Mode
Secured Primary Bootloader Mode is typically used to execute application code in the final application,
where a software bootloader is required. Booting is done from the Shadow Block, with limited device
functionality. Secured Primary Bootloader Mode is identical to Normal Primary Bootloader Mode, except
that debug functionality (EICE, Nexus and the JTAG interface) is disabled and the FlexBus is turned off.
Please refer to Section 9.3, “Normal Primary Bootloader Mode” for the functionality available and the
memory map.
9.7
Secured Expanded Mode
Secured Single Expanded Mode is typically used to execute application code in the final application,
where on-chip Flash is not required. Alternatively, it is also used to unsecure secured devices. Booting is
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Freescale Semiconductor
Secured Expanded Mode
done from the external bus, with limited device functionality. In this mode, the following functionality is
available:
• Debug functionality (EICE, Nexus and the JTAG interface) is enabled
• External Bus Interface is enabled
• Flash main array access is disabled
• Shadow Block access is disabled
• Boot from the External Bus
Table 9-9 shows the device memory map of the device in secured expanded mode after Reset. The memory
map for this mode differs from the memory map in Normal Single Chip Mode as follows:
• The External Bus Interface is relocated to address $0000 0000
• The Flash Main Array is not available
• The Shadow Block is not available
Table 9-9. Device Memory Map in Secured Expanded Mode (After Reset)1
Address
Size
(Bytes)
Module
$0000 0000 - $3FFF FFFF
External Bus Interface
$4000 0000 - $4000 7FFF
$4000 0000 - $4000 4FFF
SRAM2
$4000 8000 - $FBFF FFFF
Reserved
$FC00 0000 - $FFFF FFFF
Peripheral Bus modules
512M
32K
20K
SRAM2
3008M
64M
1. This reset memory map equates to a reset value of $f0d0 0b09 in the AAMR register in the MCM module.
2. The SRAM is mirrored across the entire 512MByte address range on a 32K boundary. Therefore, the first word
in SRAM may be read from or written to using address $4000 0000 or address $4000 8000 or address $4001
0000, etc.
After Reset, the memory map may be re-mapped using the AAMR register in the MCM module. The
allowed combinations are shown in Table 9-10. The Peripheral space is always fixed at $FC00 0000, and
is not re-mappable.
Table 9-10. Allowed Memory Maps in Secured Expanded Mode
$0000 0000
$2000 0000
$4000 0000
AAMR Register
External Bus
External Bus
SRAM
$f0d0 0b99
Unused
External Bus
SRAM
$f0d0 0b90
SRAM
External Bus
SRAM
$f0d0 0b9b
External Bus
Unused
SRAM
$f0d0 0b09
Unused
Unused
SRAM
$f0d0 0b00
SRAM
Unused
SRAM
$f0d0 0b0b
External Bus
SRAM
SRAM
$f0d0 0bb9
Unused
SRAM
SRAM
$f0d0 0bb0
SRAM
SRAM
SRAM
$f0d0 0bbb
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
111
Accessing registers
9.8
Accessing registers
All registers use bit 31 to represent the most significant bit (msb), and bit 0 to represent the least significant
bit (lsb). All memory-mapped registers may be accessed using properly aligned 8-bit, 16-bit or 32-bit
accesses, except where indicated. This means that all addresses may be accessed using 8-bit accesses, all
even addresses may be accessed using 16-bit accesses, and every fourth address may be accessed using
32-bit accesses. On the MAC7200 family, which are big-endian devices, this results in the following
register mapping:
9.8.1
32-bit Register Accesses
A read to the above register will result in the following values:
31
0
$0000 0000
32-bit Register REG
All other accesses (i.e., 16-bit READ from $0000 0001) are not allowed.
9.8.2
8-bit READ from $0000 0000
returns REG[31:24]
8-bit READ from $0000 0001
returns REG[23:16]
8-bit READ from $0000 0002
returns REG[15:8]
8-bit READ from $0000 0003
returns REG[7:0]
16-bit READ from $0000 0000
returns REG[31:16]
16-bit READ from $0000 0002
returns REG[15:0]
32-bit READ from $0000 0000
returns REG[31:0]
16-bit Register Accesses
15
$0000 0000
0
16-bit Register REG
A read to the above register will result in the following values:
8-bit READ from $0000 0000
returns REG[15:8]
8-bit READ from $0000 0001
returns REG[7:0]
16-bit READ from $0000 0000
returns REG[15:0]
32-bit READ from $0000 0000 returns
REG[15:0] + the next 16 bits in the memory map
All other accesses (i.e.-16-bit READ from $0000 0001) are not allowed.
MAC7200 Microcontroller Family Reference Manual, Rev. 2
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Freescale Semiconductor
Peripheral Bus Memory Map
9.8.3
8-bit register accesses
7
$0000 0000
0
8-bit Register REG
A read to the above register will result in the following values:
8-bit READ from $0000 0000
returns REG[7:0]
16-bit READ from $0000 0000
returns REG[7:0] + the next 8 bits in the memory map
32-bit READ from $0000 0000
returns REG[7:0] + the next 24 bits in the memory map
All other accesses (i.e.-16-bit READ from $0000 0001) are not allowed.
It is possible to enable bus aborts on illegal register accesses. Please refer to Chapter 25, “System Service
Module (SSM_MAC7202)” for more information on this.
9.9
Peripheral Bus Memory Map
The Peripheral Bus bridge (AIPS) is located on a slave port of the AXBS crossbar switch with a reset value
of $E000 0000, and is not relocatable. However, the Peripheral Bus modules are located above this
boundary, at $FC00 0000. Table 9-11 shows the address of all Peripheral Bus modules.
Table 9-11. Peripheral Bus Memory Map
Address
Module
Size (Bytes)
(O)PACR
$FC00 0000 - $FC00 3FFF
AMBA to IP Bus Bridge (AIPS) Configuration Registers
16K
PACR0
$FC00 4000 - $FC00 7FFF
ARM Crossbar Switch (AXBS) Configuration Registers
16K
PACR1
16K
PACR2
$FC00 8000 - $FC00 BFFF
External Interface Module (EIM) Configuration Registers
$FC00 C000 - $FC03 FFFF
Reserved
$FC04 0000 - $FC04 3FFF
Miscellaneous Control Module (MCM)
16K
PACR16
$FC04 4000 - $FC04 7FFF
Enhanced Direct Memory Access Controller (eDMAC)
16K
PACR17
16K
PACR18
208K
$FC04 8000 - $FC04 BFFF
Interrupt Controller (INTC)
$FC04 C000 - $FC07 FFFF
Reserved
$FC08 0000 - $FC08 3FFF
System services Module (SSM)
16K
OPACR0
$FC08 4000 - $FC08 7FFF
DMA Channel Multiplexer (DMA_CH_MUX)
16K
OPACR1
212K
$FC08 8000 - $FC08 BFFF
Clock and Reset Generator (CRG)
16K
OPACR2
$FC08 C000 - $FC08 FFFF
Programmable Interval Timer (PIT)
16K
OPACR3
$FC09 0000 - $FC09 3FFF
Reserved
16K
$FC09 4000 - $FC09 7FFF
CAN controller 0 (FlexCAN_A)
16K
OPACR5
OPACR6
$FC09 8000 - $FC09 BFFF
CAN controller 1 (FlexCAN_B)
16K
$FC09 C000 - $FC09 FFFF
Reserved
16K
$FC0A 0000 - $FC0A 3FFF
Reserved
16K
$FC0A 4000 - $FC0A 7FFF
Reserved
16K
$FC0A 8000 - $FC0A BFFF Reserved
16K
$FC0A C000 - $FC0A FFFF Inter-IC bus (IIC)
16K
$FC0B 0000 - $FC0B 3FFF
Reserved
16K
$FC0B 4000 - $FC0B 7FFF
Serial Peripheral Interface 0 (DSPI_A)
16K
OPACR11
OPACR13
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
113
SRAM Memory Map
Table 9-11. Peripheral Bus Memory Map (Continued)
Address
Module
Size (Bytes)
(O)PACR
$FC0B 8000 - $FC0B BFFF Serial Peripheral Interface 1 (DSPI_B)
16K
OPACR14
$FC0B C000 - $FC0B FFFF Serial Peripheral Interface 2 (DSPI_C)
16K
OPACR15
$FC0C 0000 - $FC0C 3FFF Reserved
16K
$FC0C 4000 - $FC0C 7FFF Enhanced Serial Communication Interface 0 (ESCI_A)
16K
OPACR17
$FC0C 8000 - $FC0C BFFF Enhanced Serial Communication Interface 1 (ESCI_B)
16K
OPACR18
$FC0C C000 - $FC0C FFFF Reserved
16K
$FC0D 0000 - $FC0D 3FFF Reserved
16K
$FC0D 4000 - $FC0D 7FFF Reserved
16K
$FC0D 8000 - $FC0D BFFF Reserved
16K
$FC0D C000 - $FC0D FFFF Enhanced Modular I/O Subsystem (eMIOS)
16K
OPACR23
$FC0E 0000 - $FC0E 3FFF
Analog to Digital Converter (ATD_A)
16K
OPACR24
$FC0E 4000 - $FC0E 7FFF
Reserved
16K
$FC0E 8000 - $FC0E BFFF Port Integration Module (PIM)
16K
$FC0E C000 - $FC0E FFFF Reserved
16K
$FC0F 0000 - $FC0F 3FFF
Flash registers
16K
$FC0F 4000 - $FFFF FFFF
Reserved
9.10
OPACR26
OPACR28fs
~63M
SRAM Memory Map
Like the Peripheral Bus modules, the SRAM resides on a slave port of the AXBS, and therefore has a
movable base address on a 512MByte boundary. However, unlike the Peripheral Bus, the SRAM is
“mirrored” in the 512MByte space on a 32KB boundary. This gives us the following memory map for the
SRAM:
Table 9-12. SRAM Memory Map
Address Offset
Function
$0000 0000
SRAM
$0000 7FFF
$0000 8000
SRAM
$0000 FFFF
$0001 0000
SRAM
$0001 7FFF
:
:
:
:
:
:
:
:
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FlexBus Memory Map
Table 9-12. SRAM Memory Map (Continued)
Address Offset
Function
$1FFF 0000
SRAM
$1FFF 7FFF
$1FFF 8000
SRAM
$1FFF FFFF
Because of the odd size of the SRAM (20KB) and the mirroring on a 32KB boundary, there will be a “hole”
in the upper 16KB of each mirrored 32KB where no reads or writes are allowed. Any write or read to this
hole will produce a bus abort. Please refer to Section 19.1.6.2, “SRAM Address Mirroring” for more
details on the mirroring in the SRAM controller.
The default base address for the SRAM is $4000 0000 and is not selectable during reset, but is software
selectable after reset.
9.11
FlexBus Memory Map
Like the Peripheral Bus modules, the FlexBus resides on a slave port of the AXBS, and therefore has a
movable base address on a 512MByte boundary. In addition, the FlexBus has 3 chip-selects, where each
chip select can select from 64KBytes to 512MBytes, and may overlap.
Table 9-13. FlexBus Memory Map
Address Offset
Function
$0000 0000
FlexBus
$1FFF FFFF
The default base address for the FlexBus depends on the chip mode selected (See Figure 9-1) and is
software selectable after reset. Note that in some modes, the Flexbus is not available in the memory map
(for security reasons).
9.12
Flash Main Array Memory Map
The Flash main array is relocatable on any 512 MByte boundary, including $0000 0000 (via the AAMR
register in the MCM). The reset location is $0000 0000 in Single Chip Mode, and $2000 0000 in Expanded
Chip and PBL Mode. The base address is software selectable in any chip mode. Note that in some modes,
the Flash Main Array is not available in the memory map (for security reasons).
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Flash Main Array Memory Map
Table 9-14. MAC72x1 Flash Main Array Memory Map
Function
Partition (Size)
Block (Size)
Address Offset
LAS Block 8 (64K)
$0000 0000
$0000 FFFF
LAS Block 9 (64K)
$0001 0000
$0001 FFFF
LAS Block 0 (16K)
$0002 0000
$0002 3FFF
LAS Block 1 (16K)
$0002 4000
$0002 7FFF
LAS Block 2 (16K)
$0002 8000
$0002 BFFF
LAS Block 3 (16K)
$0002 C000
$0002 FFFF
LAS Block 4 (16K)
$0003 0000
$0003 FFFF
LAS Block 5 (16K)
$0003 4000
$0003 7FFF
LAS Block 6 (16K)
$0003 8000
$0003 BFFF
LAS Block 7 (16K)
$0003 C000
$0003 FFFF
MAS Block 1 (128K)
$0004 0000
$0005 FFFF
MAS Block 0 (128K)
$0006 0000
$0007 FFFF
Partition 2 (128K)
Partition 0 (64K)
LAS
Partition 1 (64K)
MAS
Partition 3 (256K)
HAS
—
Not Mapped on MAC72x1
$0008 0000
$000F FFFF
—
—
Not Mapped
$0010 0000
$00EF FFFF
—
—
Shadow Block (32K)
$00F0 0000
$00F0 7FFF
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Shadow Block Memory Map
Table 9-15. MAC72x2 Flash Main Array Memory Map
Function
LAS
Partition (Size)
Block (Size)
Address Offset
LAS Block 0 (128K)
$0000 0000
$0001 FFFF
LAS Block 1 (128K)
$0002 0000
$0003 FFFF
MAS Block 0 (16K)
$0004 0000
$0004 3FFF
MAS Block 1 (16K)
$0004 4000
$0004 7FFF
MAS Block 2 (16K)
$0004 8000
$0004 BFFF
MAS Block 3 (16K)
$0004 C000
$0004 FFFF
Partition 0 (256K)
Partition 1 (32K)
MAS
Partition 2 (32K)
MAS
—
Not Mapped on MAC72x2
$0005 0000
$0007 FFFF
HAS
—
Not Mapped on MAC72x2
$0008 0000
$000F FFFF
—
—
Not Mapped
$0010 0000
$00EF FFFF
—
—
Shadow Block (32K)
$00F0 0000
$00F0 7FFF
NOTE
Accesses to areas not mapped will produce a Prefetch or Data Abort
exception (depending on the access type).
9.13
Shadow Block Memory Map
The 32K Shadow Block is always available at FLASH_BASE + $00F0 0000 (when the Flash is available
in the memory map). In addition, when resetting into PBL mode, it is mirrored at address $0000 0000.
When the Flash Main Array is not available in the memory map (for security reasons), the Shadow Block
is also unavailable.
Table 9-16. Shadow Block Memory Map1
Address Offset
Function
$0000 0000
Shadow Block (User Area)
$0000 7DDF
$0000 7DE0
System Censor Word
$0000 7DE8
LML Register Shadow
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Boot Assist Module (BAM) Memory Map
Table 9-16. Shadow Block Memory Map1 (Continued)
Address Offset
Function
$0000 7DF0
HBL Register Shadow
$0000 7DF8
SLL Register Shadow
$0000 7E00
PFCR2 (BIU2) Register Shadow
$0000 7E08
PFSACC (BIU3) Register Shadow
$0000 7E10
PFDACC (BIU4) Register Shadow
$0000 7E18
Shadow Block (User Area)
$0000 7FFF
1. This memory map is assuming a 32K Shadow Block. If the size of the Shadow Block
changes, the registers will move accordingly (i.e.-the registers are always placed at the
end of the Shadow Block in order to allow the maximum amount of contiguous user area
possible).
9.14
Boot Assist Module (BAM) Memory Map
The BAM, unlike other resources, is not software relocatable in the system, and is always present at $A000
0000, regardless of chip mode. When JTAG Lockout Recovery is triggered, the BAM is mirrored to
address $0000 0000, and the Lockout Recovery firmware is executed after reset. Although it is generally
not used by the application, it is accessible in software at address $A000 0000.
Table 9-17. Boot Assist Module (BAM) Memory Map
Address Offset
Function
$0000 0000
BAM
$1FFF FFFF
9.15
Exception Table Memory Map
The ARM7 exception vector table is located at $0000 0000 to $0000 001F, and may not be relocated either
at reset or after reset. Please refer to Chapter 7, “Exceptions” for more details on exceptions.
Table 9-18. Exception Table Memory Map
Address Offset
Function
$0000 0000
Reset exception
$0000 0004
Undefined Instruction exception
$0000 0008
Software Interrupt (SWI) exception
$0000 000c
Prefetch Abort exception
$0000 0010
Data Abort exception
$0000 0014
Reserved
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Memory Map Relocation
Table 9-18. Exception Table Memory Map (Continued)
9.16
Address Offset
Function
$0000 0018
IRQ exception
$0000 001c
FIRQ exception
Memory Map Relocation
The MAC72xx is designed to have relocatable memory map resources, for the following reasons:
• The ARM7 exception table is not relocatable. Therefore, in order to execute exception handlers
from different memories, relocation of these memories is necessary.
• Security of the Flash may dictate that certain combinations of resources should not be valid on a
secured device.
• Support for a software bootloader concept
• General system flexibility
As previously discussed, relocation of resources is generally available via the crossbar switch on a 512MB
boundary. In addition, certain resources (SRAM and Shadow Block) may also be mirrored to give an extra
granularity of relocation. The following sections discuss the details of this relocation.
9.16.1
System Memory Map Combinations
Possible combinations that can be configured via software after reset are listed in Table 9-19. Shaded lines
are those combinations that are not allowed in the MCM.
Table 9-19. Possible Memory Map Configurations1
$0000 0000
$2000 0000
$4000 0000
$A000 0000
$E000 0000
Unused
Unused
SRAM
BAM
Peripheral Bus
Unused
FLASH
SRAM
BAM
Peripheral Bus
Unused
FlexBus
SRAM
BAM
Peripheral Bus
Unused
SRAM
SRAM
BAM
Peripheral Bus
FLASH
Unused
SRAM
BAM
Peripheral Bus
FLASH
FLASH
SRAM
BAM
Peripheral Bus
FLASH
FlexBus
SRAM
BAM
Peripheral Bus
FLASH
SRAM
SRAM
BAM
Peripheral Bus
FlexBus
Unused
SRAM
BAM
Peripheral Bus
FlexBus
FLASH
SRAM
BAM
Peripheral Bus
FlexBus
FlexBus
SRAM
BAM
Peripheral Bus
FlexBus
SRAM
SRAM
BAM
Peripheral Bus
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Memory Map Relocation
Table 9-19. Possible Memory Map Configurations1 (Continued)
$0000 0000
$2000 0000
$4000 0000
$A000 0000
$E000 0000
SRAM
Unused
SRAM
BAM
Peripheral Bus
SRAM
FLASH
SRAM
BAM
Peripheral Bus
SRAM
FlexBus
SRAM
BAM
Peripheral Bus
SRAM
SRAM
SRAM
BAM
Peripheral Bus
BAM
FLASH
SRAM
BAM
Peripheral Bus
1. The Shadow Block is not included in the above table, because it is generally not relocatable. In Normal/Secured
Bootloader Modes, the Shadow Block is located at address $0000 0000 at reset, but is not relocatable after reset. In
all other modes, if the Flash is available, then the Shadow Block is also available (at FLASH_BASE + $00F0 0000).
9.16.2
Changing Chip Modes
Since changing the security mode of the Flash requires a system reset afterwards, the chip modes can only
be switched by resetting the device, and re-applying the correct signals to the MODA/MODB pins.
9.16.3
Resource Relocation Summary
Also refer to Chapter 2, “Modes of Operation”.
9.16.3.1
FlexBus
The FlexBus is generally software relocatable (via the AAMR register in the MCM) to the following
addresses:
• $0000 0000
• $2000 0000
9.16.3.2
Flash Main Array
The Flash Main Array is generally software relocatable (via the AAMR register in the MCM) to the
following addresses:
• $0000 0000
• $2000 0000
9.16.3.3
Shadow Block
The relocation of the Shadow Block is done by relocating the Flash main array.
In Normal/Secured Bootloader Mode, where the Shadow Block is relocated to address $0000 0000, once
another resource (like the SRAM) has been relocated to address $0000 0000, the Shadow Block can not
be relocated back to address $0000 0000 without resetting the device. The exact mechanism for this is
described in Section 9.16.4, “Programming the AAMR register in the MCM”.
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Memory Map Relocation
9.16.3.4
SRAM
The SRAM is always software relocatable (via the AAMR register in the MCM) to the following
addresses:
• $0000 0000
• $2000 0000
• $4000 0000
9.16.4
Programming the AAMR register in the MCM
Because the programming of this register is initially slightly counter-intuitive, a short explanation of how
it works is presented.
Each 512Mbyte address range in the MAC72xx’s 4GByte addressable space has a corresponding nibble
(called a “slot” hereafter). When an transfer is seen on a Master Port of the AXBS (crossbar switch), the
upper three address bits are used to determine which AAMR slot will be used to determine the correct
Slave Port to route to. The slots in the AAMR are allocated as follows:
Base Address
$E000 0000
$C000 0000
$A000 0000
$8000 0000
AAMR Bits
31:28
27:24
23:20
19:16
Base Address
$6000 0000
$4000 0000
$2000 0000
$0000 0000
AAMR Bits
15:12
11:8
7:4
3:0
The upper bit of each nibble/slot is the valid bit, 1=valid, 0=invalid. In the case of an invalid address, the
transfer is aborted. The lower 3 bits of each nibble/slot determine the Slave Port number that the transfer
will be routed to. The MAC72xx has the following valid Slave Ports:
Table 9-20. AXBS Slave Port Definitions
Slave Port Resource (AAMR Value)
S0
FLASH ($8)
S1
FlexBus ($9)
S3
SRAM ($b)
S5
BAM ($d)
S7
Peripheral Bus ($f)
NOTE
Bits [31:8] of the AAMR are always fixed at value $f0d00b. If any nibble is
written with an illegal value, then none of the register nibbles will be
updated.
In Normal/Secured Bootloader Mode, when the Shadow Block is located at $0000 0000, the reset value of
the AAMR register will be $88.
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Exception Table
In Normal/Secured Bootloader mode, once AAMR[3] has been set (i.e.-Nibble 0 is marked as valid), the
Shadow Block is no longer available at address $0000 0000. Any write to the AAMR that does not set bit
3 will leave the Shadow Block mirroring at address $0000 0000. As an example, in Normal/Secured
Bootloader mode, the initial AAMR register value is $f000 0b88. If the user writes $f000 0bb0 to the
AAMR register, the following configuration will be set:
Table 9-21.
Before
After
$0000 0000
Shadow Block
$0000 0000
Shadow Block
$2000 0000
Main Flash array
$2000 0000
SRAM
$20F0 0000
Shadow Block
However, if the user writes $f000 0bb8 to the AAMR register, the following configuration will be set:
Table 9-22.
Before
$0000 0000
9.17
After
Shadow Block
$2000 0000
Main Flash array
$20F0 0000
Shadow Block
$0000 0000
Main Flash array
$20F0 0000
Shadow Block
$2000 0000
SRAM
Exception Table
See Section 7.2, “Exception Handling”.
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System Boot Sequence
9.18
System Boot Sequence
9.18.1
Programming with a Bootloader
Programming House
Program the Primary Bootloader code into the Shadow Block via the JTAG port
• Done in Normal/Secured Bootloader Mode with the core in debug mode
• Primary Bootloader code is usually less than 20KB
• Branch to Primary Bootloader loaded into Reset Vector ($0000 0000)
• Flash is unsecured
First Sub-Supplier
Boot the device from the Shadow Block (Normal/Secured Bootloader Mode)
• Primary Bootloader checks for empty Flash Main Array
Flash is not empty
Flash is empty
(No application code)
First Sub-Supplier
Program application code into the Flash Main Array
• Primary Bootloader loads Secondary Boot Loader (SBL) into the SRAM via a
pre-defined peripheral/protocol (Flash is secured, so JTAG is disabled)
• SBL is temporary - Only to program the application code into the Flash array
• Requires that all ISRs reside in SRAM => Primary Bootloader relocates SRAM
to address $0000 0000 (Flash stays at address $2000 0000)
• SBL loads the application code (via a pre-defined peripheral/protocol) into the
Flash Main Array at address $2000 0000
• SBL relocates FLASH to address $0000 0000 and SRAM back to address
$4000 0000
Application
Execute application code at address $0000 0000
• Relocate Flash to address $0000 0000 (Use exception table from the application code)
• Jump to address $0000 0000
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System Boot Sequence
Figure 9-4. Device Programming Sequence
9.18.2
“Normal” Boot with a Bootloader
Reset/Power-On
• Flash determines security state of the MAC72xx
• Mode signals determine Chip Mode
Normal Expanded
• Relocate Flash
• Boot from
FlexBus
Secure Expanded
• Disable Flash
• Boot from
FlexBus
Core Reset
• Instruction fetch from $0000 0000
Application
• Execute application code from
external memory/device
Secure Bootloader
• Disable EICE/
Nexus/JTAG
• Boot from
Shadow Block
Normal Bootloader
• Boot from
Shadow Block
Core Reset
• Instruction fetch from $0000 0000
Primary Bootloader
• Execute Primary Bootloader code from
Shadow Block at address $0000 0000
• Primary Bootloader determines application
code (in Flash main array) is to be executed.
Application
Execute application code at address $0000 0000
• Relocate Flash main array to address $0000 0000 (So that
the exception table from the application code is used)
• Jump to address $0000 0000
Figure 9-5. Device “Normal” Boot Sequence
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System Boot Sequence
Note that in both Programming and “Normal” modes, the system is required to dynamically re-map a
memory into address $0000 0000. Because of the pre-fetch/fetch pipeline in the ARM7 core, this requires
some “overlap” between the code in the original memory and the newly swapped in memory. The easiest
way to do this is to insert NOP opcodes into both sets of code at the right location. The following example
illustrates this, using the switch between the bootloader code in the Shadow Block, and the application
code in the Instruction Flash. Note that the example uses “pseudo assembly code”, rather than actual
ARM7 code.
Address
Original Code
(PBL)
in the Shadow Block
New Code
(App. Code)
in the Flash Main Array
$0000 0000
JMP $0000_0000
NOP
$0000 0004
NOP
NOP
$0000 0008
NOP
NOP
$0000 000C
NOP
App. Code starts here...
At least 3 NOPs should be used in both the “original” and “new” code.
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System Boot Sequence
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Chapter 10
ARM7TDMI-S Core
10.1
Introduction
The MAC7200 family is implemented with a licensed ARM7 CPU. This is a 32-bit RISC core with a three
stage pipeline offering high instruction throughput. The core used across the family is the ARM7TDMI-S
which supports both a 32-bit instruction set and a 16-bit instruction set (THUMB) to assist with code
density. No architectural modifications have been made to this core during implementation, enabling the
MAC7200 family to remain compliant to the ARM ISA V4T and existing tool chains. The core has been
configured to support Big Endian memory systems.
For detailed information about the ARM core please consult the following documents:
• ARM Architecture Reference Manual (Second Edition)
• ARM7TDMI-S (Rev 4) Technical Reference Manual (Issue A)
10.2
•
•
10.3
ARM7 Features
32-bit ARM7 TDMI-S RISC Core
— Up to 70MHz operating frequency
— Efficient code density through 16-bit instructions (THUMB).
— Alternate general purpose registers.
— Byte (8-bit), Halfword (16-bit), Word (32-bit) data types supported.
— Cores and Memory connected using high performance AMBA AHB bus.
— Integrated E-ICE module for debug
Version rev4p3.04
T
Thumb architecture extension
D
Debug extensions
M
Enhanced multiplier (32x8) with 64-bit result support
I
EmbeddedICE Macrocell extension
S
Fully Synthesizable
ARM7 Implementation
The MAC72xx devices use the latest version of the ARM7TDMI-S core available. For the MAC72x2
xM84A masksets and MAC72x1 0M19G maskset, revision rev4p3.04 is used.
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ARM7 External Pins
10.4
ARM7 External Pins
There are no ARM7 signals that drive or are driven from MCU pins.
10.5
ARM7 Bus Aborts
As the ARM7 core is a bus master, it is not capable of generating bus aborts.
10.6
ARM7 Application Usage
Please refer to ARM7 Application Notes from ARM for more information.
10.6.1
Register Bank Initialization
It is necessary to initialize all ARM7 user registers, as they are not initialized by a POR or System Reset.
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Chapter 11
A7S Nexus3 Module
11.1
Introduction
The A7S Nexus3 module provides real-time development capabilities for ARM7™ core based
microcontrollers in compliance with the IEEE-ISTO Nexus 5001. This module provides development
support capabilities for MCUs without requiring address and data pins for internal visibility.
A portion of the pin interface is also compliant with the IEEE 1149.1 JTAG standard. The IEEE-ISTO
5001 standard defines an extensible auxiliary port which, for ARM7, will be used in conjunction with the
JTAG port.
Message
Queues
I/O Logic
Instruction and Data
Snoop
A7S Bus
mdo(N:0)
mseo_b(0)
mseo_b(1)
mcko
evto_b
evti_b
Memory
Control
DMA (Read/Write)
System AHB
rdy_b
Registers
JTAG/ICE
Control/Status
Registers
DMA Registers
Breakpoint /
Watchpoint
Control
tdi
tdo
tms
tck
trst_b
Nexus3 Block
JTAG/ICE Block (within ARM7 core)
Figure 11-1. A7S Nexus3 Functional Block Diagram
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Introduction
11.1.1
A7S Nexus3 Overview
This specification defines the auxiliary pin functions, transfer protocols and standard development features
of a Class 3 device in compliance with the IEEE-ISTO Nexus 5001 standard. The development features
supported are Program Trace, Data Trace, Watchpoint Messaging, Breakpoints, Ownership Trace and
Read/Write Access via the JTAG interface. The A7S Nexus3 module also supports two Class 4 features:
Watchpoint Triggering, and processor overrun control.
11.1.2
Nexus Feature List
The A7S Nexus3 module is compliant with Class 3 of the IEEE-ISTO 5001 standard. The following
features are implemented:
• Program Trace via Branch Trace Messaging (BTM). Branch trace messaging displays program
flow discontinuities (direct and indirect branches, exceptions, etc.), allowing the development tool
to interpolate what transpires between the discontinuities. Thus static code may be traced.
— Program Trace in ARM mode will use Branch/Predicate History Messaging due to the
conditional nature of 32-bit ARM instructions
— Program Trace in Thumb Mode can be programmed to use the Branch History Messaging
method, or use traditional Program Trace – Direct/Indirect Branch Messaging
• Data Trace via Data Write Messaging (DWM) and Data Read Messaging (DRM). This provides
the capability for the development tool to trace reads and/or writes to (selected) internal memory
resources.
• Ownership Trace via Ownership Trace Messaging (OTM). OTM facilitates ownership trace by
providing visibility of which process ID or operating system task is activated. An Ownership Trace
Message is transmitted when a new process/task is activated, allowing the development tool to
trace ownership flow.
• Run-time access to the memory map via the JTAG port. This allows for enhanced download/upload
capabilities.
• Watchpoint Messaging (WPM) via the auxiliary pins.
• Breakpoint on instruction address.
• Watchpoint Trigger enable of Program and/or Data Trace Messaging
• Auxiliary interface for higher data input/output
— Configurable two (2) or eight (8) MDO (Message Data Out) pins
— One (1) or two (2) MSEO (Message Start/End Out) pins
— One (1) RDY (Read/Write Ready) pin
— One (1) EVTO (Watchpoint Event) pin
— One (1) EVTI (Event In) pin
— One (1) MCKO (Message Clock Out) pin
• Registers for Program Trace, Ownership Trace, Watchpoint Trigger, and Read/Write Access.
• Programmable processor stall function to mitigate message queue overrun risk.
• All features controllable and configurable via the JTAG port
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Introduction
11.1.3
Modes of Operation
There are three (3) basic modes of operation for the A7S Nexus3 block.
• Reset
• Normal
• Disabled
11.1.3.1
Reset
The reset configuration is received via the EVTI pin to enable or disable the A7S Nexus3 module. EVTI
is sampled synchronously at the exit from the JTAG Test-Logic-Reset state. Reset configuration
information must be valid on EVTI during the JTAG “Test Logic Reset” state (see 11.12, “IEEE 1149.1
State Machine and RD/WR Sequences”).
The A7S Nexus3 module will disable (drive inactive) the output pins during the JTAG Test-Logic-Reset
state or when a Power-on-Reset (POR) event occurs.
11.1.3.2
Normal
If EVTI is asserted at the exit from JTAG Test-Logic-Reset, the A7S Nexus3 module will be enabled. The
module will be ready to accept control input via the JTAG pins.
The A7S Nexus3 module may also be enabled by loading the NEXUS-ACCESS instruction into the JTAG
Instruction Register. Once the A7S Nexus3 module has been enabled, it will remain enabled until entry
into the JTAG Test-Logic-Reset state.
11.1.3.3
Disabled
If EVTI is negated at the exit from JTAG Test-Logic-Reset, the A7S Nexus3 module will be disabled. No
trace output will be provided, auxiliary port output pins (MDO, MSEO, MCKO) will be disabled (driven
inactive), and Nexus3 registers will not be accessible for reads or writes.
NOTE
If there is no debug/development tool connected to the SoC, the EVTI pin
should be held de-asserted in order to keep the Nexus3 module disabled.
The A7S Nexus3 module may be enabled after the exit from JTAG Test-Logic-Reset state by loading the
NEXUS-ACCESS instruction into the JTAG Instruction Register.
11.1.4
TCODEs supported
The A7S Nexus3 pins allow for flexible transfer operations via Public Messages. A TCODE defines the
transfer format, the number and/or size of the packets to be transferred, and the purpose of each packet.
The IEEE-ISTO 5001 standard defines a set of public messages. The A7S Nexus3 block supports the
public TCODEs seen in Table 11-1.
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Introduction
Table 11-1. Public TCODEs Supported
Message Name
Debug Status
Ownership
Trace
Message
Program Trace –
Direct Branch
Message
Program Trace –
Indirect Branch
Message
Data Trace –
Data Write
Message
Data Trace –
Data Read
Message
Error Message
Program Trace –
Direct Branch
Message w/
Sync
Minimum Maximum
Packet
Packet
Size (bits) Size (bits)
Packet
Name
Packet
Type
Packet Description
6
6
TCODE
fixed
TCODE number = 0
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
8
8
STATUS
fixed
Debug Status Register (DS[31:24])
6
6
TCODE
fixed
TCODE number = 2
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
32
32
PROCESS fixed
Task/Process ID tag
6
6
TCODE
fixed
TCODE number = 3 (see Note below)
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
1
8
I-CNT
variable
# sequential instructions executed since last taken branch
6
6
TCODE
fixed
TCODE number = 4 (see Note below)
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
1
8
I-CNT
variable
# sequential instructions executed since last taken branch
1
32
U-ADDR
variable
unique part of target address for taken branches/exceptions
6
6
TCODE
fixed
TCODE number = 5
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
3
3
DSZ
fixed
data size (Refer to Table 11-6)
1
32
U-ADDR
variable
unique portion of the data write address
1
32
DATA
variable
data write value (see Note)
6
6
TCODE
fixed
TCODE number = 6
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
3
3
DSZ
fixed
data size (Refer to Table 11-6)
1
32
U-ADDR
variable
unique portion of the data read address
1
32
DATA
variable
data read value (see Note)
6
6
TCODE
fixed
TCODE number = 8
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
5
5
ERROR
fixed
error code (Refer to Table 11-2)
6
6
TCODE
fixed
TCODE number = 11 (see Note below)
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
1
8
I-CNT
variable
# sequential instructions executed since last taken branch
1
32
F-ADDR
variable
full target address (leading zero (0) truncated)
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Introduction
Table 11-1. Public TCODEs Supported (Continued)
Message Name
Program Trace –
Indirect Branch
Message w/
Sync
Data Trace –
Data Write
Message
w/ Sync
Data Trace –
Data Read
Message
w/ Sync
Watchpoint
Message
Resource Full
Message
Program Trace –
Indirect Branch
History
Message
Program Trace –
Indirect Branch
History
Message w/
Sync
Minimum Maximum
Packet
Packet
Size (bits) Size (bits)
Packet
Name
Packet
Type
Packet Description
6
6
TCODE
fixed
TCODE number = 12 (see Note below)
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
1
8
I-CNT
variable
# sequential instructions executed since last taken branch
1
32
F-ADDR
variable
full target address (leading zero (0) truncated)
6
6
TCODE
fixed
TCODE number = 13
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
3
3
DSZ
fixed
data size (Refer to Table 11-6)
1
32
F-ADDR
variable
full access address (leading zero (0) truncated)
1
32
DATA
variable
data write value (see Note)
6
6
TCODE
fixed
TCODE number = 14
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
3
3
DSZ
fixed
data size (Refer to Table 11-6)
1
32
F-ADDR
variable
full access address (leading zero (0) truncated)
1
32
DATA
variable
data read value (see Note)
6
6
TCODE
fixed
TCODE number = 15
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
8
8
WPHIT
fixed
watchpoint source(s) (refer to Table 11-3)
6
6
TCODE
fixed
TCODE number = 27
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
4
4
RCODE
fixed
resource code (Refer to Table 11-4)
1
32
HIST
variable
branch / predicate instruction history
6
6
TCODE
fixed
TCODE number = 28 (see Note below)
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
1
8
I-CNT
variable
# sequential instructions executed since last taken branch
1
32
U-ADDR
variable
unique part of target address for taken branches/exceptions
1
32
HIST
variable
branch / predicate instruction history
6
6
TCODE
fixed
TCODE number = 29 (see Note below)
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
1
8
I-CNT
variable
# sequential instructions executed since last taken branch
1
32
F-ADDR
variable
full target address (leading zero (0) truncated)
1
32
HIST
variable
branch / predicate instruction history
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Introduction
Table 11-1. Public TCODEs Supported (Continued)
Message Name
Program Trace –
Program
Correlation
Message
Minimum Maximum
Packet
Packet
Size (bits) Size (bits)
Packet
Name
Packet
Type
Packet Description
6
6
TCODE
fixed
TCODE number = 33
4
4
SRC
fixed
source processor identifier (multiple Nexus configuration)
4
4
ECODE
fixed
event correlated with program flow (Refer to Table 11-5)
1
8
I-CNT
variable
# sequential instructions executed since last taken branch
1
32
HIST
variable
branch / predicate instruction history
NOTE
Due to the conditional nature of 32-bit ARM instructions, when in ARM
mode, Program Trace will be implemented using Branch History/Predicate
Instruction Messages. When in Thumb mode, the user can select between
traditional Program Trace using Direct/Indirect Branch Messages, or
Branch History Messages.
If the Branch History method is selected in Thumb mode, the shaded
TCODES above will not be messaged out.
Table 11-2. Error Code Encoding (TCODE = 8)
Error Code
Description
00000
Ownership Trace overrun
00001
Program Trace overrun
00010
Data Trace overrrun
00011
Read/write access error
00101
Invalid access opcode (Nexus Register unimplemented)
00110
Watchpoint overrun
00111
(Program Trace or Data Trace) & Ownership Trace overrun
01000
(Program Trace or Data Trace or Ownership Trace) & Watchpoint overrun
01001–10111
Reserved
11000
BTM lost due to collision w/ higher priority message
11001–11111
Reserved
Table 11-3. Watchpoint Source Encoding (TCODE = 15)
Watchpoint Code
Description
xxxx xxx1
ARM7 Watchpoint 0
xxxx xx1x
ARM7 Watchpoint 1
xxxx x1xx
Nexus Watchpoint 1
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Nexus Protocol
Table 11-3. Watchpoint Source Encoding (TCODE = 15) (Continued)
Watchpoint Code
Description
xxxx 1xxx
Nexus Watchpoint 2
xxx1 xxxx
Nexus Watchpoint 3
xx1x xxxx
Nexus Watchpoint 4
x1xx xxxx
Nexus Watchpoint 5
1xxx xxxx
Nexus Watchpoint 6
Table 11-4. Resource Code Encoding (TCODE = 27)
Resource Code
Description
0000
Program Trace Instruction Counter Overflow
0001
Branch / Predicate Instruction History Buffer
0010–1111
Reserved for future functionality
Table 11-5. Event Code Encoding (TCODE = 33)
Event Code
Description
0000
Entry into Debug Mode
0001
Entry into Low Power Mode (CPU only)
0010–0011
0100
0101–1111
Reserved for future functionality
Program Trace Disable
Reserved for future functionality
Table 11-6. Data Trace Size (DSZ) Encodings (TCODE = 5, 6, 13, 14)
DTM Size
Encoding
000
8-bit
001
16-bit
010
32-bit
011–111
11.2
Transfer Size
Reserved
Nexus Protocol
For a complete description of the Nexus protocol, please refer to the IEEE Nexus specification.
11.3
Nexus Implementation
Nexus 3 was chosen over Nexus 2 because of the additional requirement for Data Trace capabilities. The
Nexus module, part of a standard supported by Freescale, has the following advantages.
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Nexus Implementation
•
•
•
No cost
Already implemented for the ARM9 core
Supported by Metroworks tools
11.3.1
Nexus Port Replacement
The selection between the Primary and Secondary Nexus ports will be done via an external pin (See
Section 2.2, “MCU Hardware Configuration Summary”) latched at RESET in order to alleviate the need
for the development system to write into a memory-mapped register. The Primary and Secondary ports are
defined as follows:
Table 11-7. Nexus Port Assignments
11.3.2
Nexus Pin
Primary Port
Secondary Port
EVTI
PA9
PC3
MCKO
PB0
PC4
EVTO
PB1
PC5
MSEO
PB2
PC6
RDY
PB3
PC7
MDO[0]
PG2
PC8
MDO[1]
PG3
PC9
MDO[2]
PG4
PC10
MDO[3]
PB9
PC11
MDO[4]
PB11
PC12
MDO[5]
PB13
PC13
MDO[6]
PB14
PC14
MDO[7]
PB15
PC15
TAP Controller Encodings
The following table lists the JTAG TAP controller IR register encodings used on the MAC72xx.
Table 11-8. JTAG TAP Controller IR Register Encodings
IR Encoding
Function
Used By
$0 = 0000
EXTEST
ARM9
$1 = 0001
Unused
$2 = 0010
SCAN_N
ARM7/ARM9
$3 = 0011
SAMPLE/PRELOAD
ARM9
$4 = 0100
RESTART
ARM7/ARM9
$5 = 0101
CLAMP
ARM920T
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Nexus Integration
Table 11-8. JTAG TAP Controller IR Register Encodings (Continued)
IR Encoding
Function
Used By
$6 = 0110
Unused
$7 = 0111
HIGHZ
ARM920T
$8 = 1000
NEXUS_ACCESS
Nexus
$9 = 1001
CLAMPZ
ARM920T
$A = 1010
Unused
$B = 1011
Unused
$C = 1100
INTEST
$D = 1101
Unused
$E = 1110
IDCODE
ARM7/ARM9
$F = 1111
BYPASS
ARM7/ARM9
ARM91
1. The INTEST IR encoding is used to load/unload values into the six configuration registers (“Scan
Chains”) built into the MAC72xx:
Bit
0
1–2
Definition
Not Used
ARM7/EICE
3
Not Used
4
PTI Scan Chain 4
5
PTI Scan Chain 5
6
PTI Scan Chain 6
7
PTI Scan Chain 7
12. The IDCODE returned on the MAC72xx is hard-coded in the ARM7 core and is $4f1f0f0f.
11.4
Nexus Integration
On the MAC72xx, the following Nexus Low Power State (LPS) encodings are used:
Table 11-9. Nexus LPS Encodings
Mode
ext_lps
Normal
ext_lps[2:0] = 3’b000
Stop
ext_lps[0] = 1
Doze
ext_lps[1] = 1
Debug
ext_lps[2] = 1
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Nexus Integration
NOTE
On the MAC72xx, STOP mode is not implemented, and ext_lps[0] will
always read back as a ‘0’.
11.4.1
Nexus Integration and SoC Security
In order to prevent access to internal resources, such as the Flash, when they are secured, all debug features
(i.e.-EICE and Nexus) are disabled when the chip is in a secured mode, denoted by the negation of the
debug_enabled signal. Please refer to Chapter 9, “Device Memory Map” for more details on this. When
debug_enabled is negated, the following actions are taken:
• The DBGEN signal to the ARM7 core is negated.
• All clocks to the Nexus are gated off. See the section “Power Consumption” below for more
details.
11.4.2
Nexus Integration and FlexBus Port Sizing
Because the Nexus Secondary Port is muxed in with the address bus of the external bus, it is impossible
to use the FlexBus when the Nexus is active, and the Secondary Port is selected. It is only possible to use
the Nexus on the Primary Port with an 8-bit external bus.
Table 11-10. FlexBus Port Sizing with Nexus
11.4.3
Nexus Port Select
(PF0)
Nexus Present
(PF1)
Allowed FlexBus Port Sizes
(PF3)
0 (Primary)
1 (Yes)
8-bit (PF3=0)
0 (Primary)
0 (No)
8/16-bit (PF3=0/1)
1 (Secondary)
1 (Yes)
FlexBus not available
1 (Secondary)
0 (No)
8/16-bit (PF3=0/1)
Nexus Integration and Port Control
Unlike other “peripherals” in the system, which require programming of the Port Integration Module
(PIM) in order to give control of the pins to the peripheral, the Nexus will automatically be given control
of the appropriate ports once enabled (by setting of Nexus Present and Nexus Port Select hardware
configuration pins). This is done in order to avoid requiring the development system to write internal
memory-mapped registers. On the MAC71xx family, the number of MSEO pins selected was done via an
input port on the Nexus module (ext_mseo_sel) (0 = 1-pin, 1 = 2-pin). For all MAC71xx devices, this was
tied to 0, denoting a single MSEO pin was available. On the MAC72xx, this selection is done via the MSC
bit in the Port Control Register (PCR) in the Nexus (0 = 1-pin, 1 = 2-pin). On the MAC72xx, a single
MSEO pin is available. Therefore, the software must not set this bit in the PCR register.
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Nexus External Pins
11.5
Nexus External Pins
The external pin interface is flexible. The minimum number of pins necessary is 4 pins for a basic Program
Trace implementation, or a maximum of 13 for a full Program + Data Trace implementation. All pins total
must be made available on either a Primary or Secondary Nexus Port
Table 11-11. Nexus External Pins
Signal
MDO[7:0]
MSEO
Description
8-bit Message Data Out (2 required, 6 optional)
Message Start/End Out
EVTI
Event In
EVTO
Event Out
MCKO
Message Clock Out
RDY
11.5.1
Ready (Output)
MDO - Message Data (Output)
These pins provide the packet data for the trace messages. The Nexus module can be programmed to use
a minimum number of MDO pins (2) or a maximum number of MDO pins (8). Following are the minimum
requirements for the number of MDO pins:
• Program Trace only (Class 2): 2 MDO pins. As a benchmark, the EEMBC suite of automotive
benchmarks was run on a M*CORE Nexus3 module using the 2-pin MDO option (only turning on
Program Trace), at 100MHz without buffer overflow.
• Program and Data Trace (Class 3): 8 MDO pins
11.5.2
MSEO - Message Start/End (Active low output)
These pins indicate to the development tool when each packet within a message begins and ends. The
Nexus module supports two of these pins for higher throughput (bandwidth), but only one is necessary for
IEEE compliance. For a Program and Data Trace only module running @ 80MHz, only 1 MSEO pin is
necessary.
11.5.3
EVTI - Event In (Active low input)
This required pin is multi-faceted. Initially, it is used to enable Nexus (sampled during a Debug Reset). It
is also programmable to create a “synchronization” type message (giving the full address if the tool is lost),
or initiate a debug request to the ARM core.
11.5.4
EVTO - Event Out (Active low output)
This optional pin can be used by the development tool to trigger on certain events. EVTO can be
programmed to assert based on the occurrence of a watchpoint (defined within the ARM CPU), or upon
the entry into Debug Mode.
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Nexus Bus Aborts
11.5.5
RDY - DMA Ready (Active low output)
This pin indicates to the development tool that a DMA access has completed successfully.
11.5.6
MCKO - Message Clock (Output)
This pin provides the clock reference for all Nexus inputs and outputs.
11.6
Nexus Bus Aborts
The Nexus is not capable of producing any bus aborts. Any Nexus bus accesses that generate aborts are
treated as if the accesses were initiated by the ARM7 core.
11.7
•
•
•
•
•
Nexus Differences from MAC71xx
Changed from Nexus2p to Nexus3p (Includes data trace)
Added four “address match only” breakpoints (pending approval)
Added two data watchpoints
Changed from two MDO pins to eight MDO pins
Number of MSEO pins is no longer hard-coded in the design, but now selectable with the MSC bit
in the Nexus PCR register
11.8
11.8.1
Nexus Application Usage
Nexus Configuration
Enabling and selection of the Nexus port is via the value of the Port F0/F1 pins at Reset (See Table 11-12).
On some packages, only one Nexus Port may be available. Once a Nexus Port is enabled and selected, the
Nexus itself must still be enabled. Please refer to the Nexus 3 Block Guide or the Nexus web site
www.ieee-isto.org/Nexus5001 for more information.
Table 11-12. Nexus Configuration
PF0
PF1
Description
0
0
Nexus Ports are disabled
(Ports are used for "normal" functionality)
0
1
Nexus Primary Port is enabled
1
0
Nexus Ports are disabled
(Ports are used for "normal" functionality)
1
1
Nexus Secondary Port is enabled
On the MAC71xx family, the number of MSEO pins selected was done via an input port on the Nexus
module (ext_mseo_sel) (0 = 1-pin, 1 = 2-pin). For all MAC71xx devices, this was tied to 0, denoting a
single MSEO pin was available. On the MAC72xx, this selection is done via the MSC bit in the Port
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Nexus Application Usage
Control Register (PCR) in the Nexus (0 = 1-pin, 1 = 2-pin). On the MAC72xx, a single MSEO pin is
available. Therefore, the software must not set this bit in the PCR register.
11.8.2
Programming the PCR Register
In order to match the hardware implementation of the Nexus3p on the MAC72xx, the following PCR
register bits must always be programmed as indicated:
11.8.3
PCR[31:30]
11
PCR[25]
0
Resetting Nexus
Resetting the Nexus3p is done as described in the Nexus Block Guide, by taking the JTAG TAP State
Machine into the Test-Logic-Reset state. There is no minimum required time that this state has to be held.
Please also refer to Chapter 6, “Resets” for information on resetting Nexus.
11.8.4
Enabling Nexus
In order to enable Nexus, you must perform one of the following methods:
Method #1
1. At reset, drive the PF1 pin high to enable a Nexus port
2. At reset, drive the PF0 pin low or high to select which Nexus port to use
3. Drive the JTAG TAP State Machine into the Test-Logic-Reset state
4. Drive the EVTI pin low (asserted)
5. Drive the JTAG TAP State Machine out of the Test-Logic-Reset state (into the Run-Test/Idle state
for instance)
Method #2
1. At reset, drive the PF1 pin high to enable a Nexus port
2. At reset, drive the PF0 pin low or high to select which Nexus port to use
3. Load the NEXUS_ACCESS instruction into the JTAG TAP State Machine
Once the Nexus module has been enabled, it will remain enabled until entry into the JTAG
Test-Logic-Reset state or a Power On Reset is performed.
11.8.5
Disabling Nexus
In order to disable Nexus, you must perform the following:
1. At reset, drive the PF1 pin low to disable Nexus ports. The value driven on PF0 does not matter in
this case.
2. If a Power On Reset has been performed, and the Nexus was not enabled, then no further action is
necessary.
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Nexus Application Usage
3. Drive the JTAG TAP State Machine into the Test-Logic-Reset state. While the State Machine is in
this state, all Nexus output pins are driven to their off value
4. Drive the EVTI pin high (negated)
5. Drive the JTAG TAP State Machine out of the Test-Logic-Reset state (into the Run-Test/Idle state
for instance)
Note that the Nexus is always in a disabled state after a Power On Reset. Once the Nexus module has been
disabled, it will remain disabled until explicitly enabled.
When the Nexus is disabled the Nexus outputs have the following off values:
EVTO
1
MSEO
1
RDY
1
MCKO
0
MDO[n]
0
In the disabled state, all Nexus3 registers are not accessible for reads or writes. In addition, the EVTI input
is ignored, except when exiting the Test-Logic-Reset state, as described in Section 11.8.3, “Resetting
Nexus.
11.8.6
Nexus Development Status (DS) Register
The DS implementation on the MAC72xx is identical to the MAC71xx, except that the MAC72xx does
not support STOP mode, so the DS[28] bit should always read back 0.
The DS[29] is for DOZE mode and the DS[30] is for Debug mode, which on the MAC72xx is identical to
the ARM7 Debug Mode (DS[31]).
The DS[27:26] bits are tied low (0), and DS[25:24] are unused and read back 0b00. This gives the
following possible combinations for DS[31:24]:
11.8.7
$00
Entering Normal Mode
$20
Entering Doze mode from Normal Mode
$C0
Entering Debug Mode from Normal Mode
$E0
Entering Debug Mode from Doze Mode or Doze Mode
from Debug Mode
Unintended Activation of Nexus
If the Nexus is not intended to be used, the PF1 pin should be driven low at reset. This will disconnect all
Nexus outputs, and force the EVTI input to the Nexus high (disabled). It is still possible to activate the
Nexus through the JTAG interface in this case. However, there will be no impact to the value of the pins
on either Nexus port.
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External Signal Description
If, however, the Nexus port is accidentally enabled (by shorting the PF1 pin to 5V for instance), then either
the Primary or Secondary Nexus port will be active. If the Nexus registers have not been programmed
since the last Power On Reset, then the Nexus will come up disabled, and the Nexus pins will have the
functionality as described in Section 11.8.5, “Disabling Nexus. In order for the Nexus port to change
values, the Nexus must be enabled, as described in Section 11.8.3, “Resetting Nexus.
Note that, if the Nexus is enabled, simply setting the TM field in the Nexus DC register to 000 (No Trace)
will not cause the MDO[7:0] pins to become inactive. With the Nexus protocol, there are various non-trace
messages that may be issued.
In order for the MCKO output to toggle, the PCR[29] bit must be set.
If the software wishes to check the status of the Nexus port during boot (highly recommended), then the
NEXUS field of the STATUS register in the SSM module may be read. Note that STATUS[12] reflects
the latched value of the PF1 pin, and STATUS[11] reflects the latched value of the PF0 pin.
11.9
External Signal Description
This section details information regarding the A7S Nexus3 pins and pin protocol.
11.9.1
Functional Description
The A7S Nexus3 pin interface provides the function of transmitting messages from the messages queues
to the external tools. It is also responsible for handshaking with the message queues.
11.9.2
Pins Implemented
The A7S Nexus3 module implements one (1) EVTI and one (1) or two (2) MSEO. It also implements up
to eight (8) MDO pins, (1) RDY pin, (1) EVTO pin, and one (1) clock output pin (MCKO). The output
pins are synchronized to the Nexus3 output clock (MCKO).
All Nexus3 input functionality is controlled through the JTAG port in compliance with IEEE 1149.1 (see
Section 11.10.4, “Nexus Register Access via JTAG,” for details). The JTAG pins are incorporated as I/O
to the ARM7 processor.
Table 11-13. JTAG Pins for A7S Nexus3
JTAG Pins
Input/
Output
TDO
O
The Test Data Output (TDO) pin is the serial output for test instructions and data. TDO is
three-stateable and is actively driven in the “shift-IR” and “shift-DR” controller states. TDO
changes on the falling edge of TCK.
TDI
I
The Test Data Input (TDI) pin receives serial test instruction and data. TDI is sampled on the
rising edge of TCK and has an internal pull-up resistor.
TMS
I
The Test Mode Select (TMS) input pin is used to sequence the JTAG test controllers’ state
machine. TMS is sampled on the rising edge of TCK and has an internal pull-up resistor.
Description of JTAG Pins (included in ARM7 CPU)
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External Signal Description
Table 11-13. JTAG Pins for A7S Nexus3 (Continued)
JTAG Pins
Input/
Output
TCK
I
The Test Clock (TCK) input pin is used to synchronize the test logic, and control register
access through the JTAG port.
TRST
I
The optional Test Reset (TRST) input pin is used to asynchronously initialize the JTAG
controller. The TRST pin has an internal pull-up resistor.
Description of JTAG Pins (included in ARM7 CPU)
Table 11-14. A7S Nexus3 Auxiliary Pins
Auxiliary Pins
Input/
Output
MCKO
O
Message Clock Out (MCKO) is a Nexus generated output clock to development tools for
timing of MDO & MSEO pin functions. MCKO is programmable through the DC Register.
MDO[N:0]
O
Message Data Out (MDO[N:0]) are output pins used for OTM and BTM. External latching of
MDO shall occur on rising edge of the Nexus3 message clock (MCKO).
MSEO[1:0]
O
Message Start/End Out (MSEO) are output pins which indicate when a message on the
MDO pins has started, when a variable length packet has ended, and when the message
has ended. External latching of MSEO shall occur on rising edge of the Nexus3 clock
(MCKO). One or two pin MSEO functionality is determined at integration time.
RDY
O
Ready (RDY) is an output pin used to indicate to the external tool that the Nexus block is
ready for the next Read/Write Access. If Nexus is enabled, this signal is asserted upon
successful (without error) completion of an AHB transfer (Nexus read or write) & is held
asserted until the JTAG state machine reaches the “Capture_DR” state. Upon exit from
system reset or if Nexus is disabled, RDY remains de-asserted.
EVTO
O
Event Out (EVTO) is an output which, when asserted, indicates one of two events has
occurred based on the EOC bits in the DC Register. EVTO is held asserted for one (1) cycle
of MCKO:
1) one of four watchpoints has occurred & EOC = 2'b00
2) debug mode was entered (DBGACK from ARM7) & EOC = 2'b01
EVTI
I
Event In (EVTI) is an input which, when asserted, will initiate one of two events based on
the EIC bits in the DC Register (if the Nexus module is enabled at reset; see
Section 11.1.3.3, “Disabled”):
1) Program Trace synchronization messages (provided Program Trace is enabled & EIC =
2'b00).
2) Debug request (EDBGRQ) to ARM7 EmbeddedICE module (provided EIC = 2'b01 and
this feature is implemented).
11.9.3
Description of Auxiliary Pins
Pin Protocol
The protocol for the ARM7 processor transmitting messages via the auxiliary pins shall be accomplished
with the MSEO pin(s) function (outlined in Table 11-15).
MSEO is used to signal the end of variable-length packets, and not fixed length packets. MSEO is sampled
on the rising edge of the message clock (MCKO).
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External Signal Description
Table 11-15. MSEO Pin(s) Protocol
MSEO Function
Single MSEO data (serial)
Dual MSEO data
Start of message
1–1–0
11–00
End of message
0–1–1–(more 1’s)
00 (or 01)–11–(more 11’s)
0–1–0
00–01
Message transmission
0’s
00’s
Idle (no message)
1’s
11’s
End of variable length packet
Figure 11-2 illustrates the state diagram for single pin MSEO transfers.
MSEO=1
Idle
MDO: Invalid
MSEO=1
End
Message
MSEO=0
MSEO=0
MDO: Invalid
Start
Message
MSEO=1
MSEO=0
MSEO=1
MSEO=1
End
Packet
Normal
Transfer
MSEO=0
Not Allowed
MSEO=0
Figure 11-2. Single Pin MSEO Transfers
Note that the “End Message” state does not contain valid data on the MDO pins. Also, It is not possible to
have two consecutive “End Packet” messages. This implies the minimum packet size for a variable length
packet is 2x the number of MDO pins. This ensures that a false end of message state is not entered by
emitting two consecutive 1’s on the MSEO pin before the actual end of message.
Figure 11-3 illustrates the state diagram for two pin MSEO transfers.
The two-pin MSEO option is more efficient that the single pin option. Termination of the current message
may immediately be followed by the start of the next message on the consecutive clocks. An extra clock
to end the message is not necessary as with the one MSEO pin option. The two-pin option also allows for
consecutive “End Packet” states. This can be an advantage when small, variable sized packets are
transferred.
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External Signal Description
MSEO=11
MSEO=01
MSEO=10
Idle
MDO: Invalid
MSEO=00
MSEO=11
MSEO=10
End
Message
MSEO=01
MSEO=10
MSEO=11
MSEO=00
MSEO=11
01
O=
E
MS
MS
EO
=1
1
Start
Message
MSEO=00
MSEO=01
End
Packet
Normal
Transfer
MSEO=00
MSEO=01
MSEO=00
Figure 11-3. Two Pin MSEO Transfers
NOTE
The “End Message” state may also indicate the end of a variable-length
packet as well as the end of the message when using the two-pin option.
11.9.4
Rules for Output Messages
ARM7 based Class 3 compliant embedded processors must provide messages via the auxiliary port in a
consistent manner as described below:
• A variable-sized packet within a message must end on a port boundary.
• Whenever a variable-length packet is sized such that it does not end on a port boundary, it is
necessary to extend and zero fill the remaining bits after the highest-order bit so that it can end on
a port boundary.
For example, if the MDO port is 2 bits wide, and the unique portion of an indirect branch address
is 5 bits, then the remaining 1 bit of MDO must be packed with a 0.
• A variable-sized packet may start within a port boundary only when following a fixed length
packet. (If two variable-sized packets end and start on the same clock, it is impossible to know
which bits are from the last packet and which bits are from the next packet.
11.9.5
Examples
The following are examples of Program Trace Messages.
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External Signal Description
Table 11-16 illustrates an example Indirect Branch Message (traditional, Thumb mode) with 2 MDO /
1 MSEO configuration. Table 11-17 illustrates the same example with the 8 MDO / 2 MSEO
configuration.
Note that T0 and S0 are the least significant bits where:
• Tx = TCODE number (fixed)
• Sx = Source processor (fixed)
• Ix = Number of instructions (variable)
• Ax = Unique portion of the address (variable)
Note that during clock 13, the MDO pins are ignored in the single MSEO case.
Table 11-16. Indirect Branch Message Example (2 MDO / 1 MSEO)
Clock
MDO[1:0]
MSEO
State
0
X
X
1
Idle (or end of last message)
1
T1
T0
0
Start Message
2
T3
T2
0
Normal Transfer
3
T5
T4
0
Normal Transfer
4
S1
S0
0
Normal Transfer
5
S3
S2
0
Normal Transfer
6
I1
I0
0
Normal Transfer
7
I3
I2
0
Normal Transfer
8
I5
I4
0
End Packet
9
A1
A0
0
Normal Transfer
10
A3
A2
0
Normal Transfer
11
A5
A4
0
Normal Transfer
12
A7
A6
1
End Packet
13
0
0
1
End Message
14
T1
T0
0
Start Message
Table 11-17. Indirect Branch Message Example (8 MDO / 2 MSEO)
Clock
MDO[7:0]
MSEO[1:0]
State
0
X
X
X
X
X
X
X
X
1
1
Idle (or end of last message)
1
S1
S0
T5
T4
T3
T2
T1
T0
0
0
Start Message
2
I5
I4
I3
I2
I1
I0
S3
S2
0
1
End Packet
3
A7
A6
A5
A4
A3
A2
A1
A0
1
1
End Packet/End Message
4
S1
S0
T5
T4
T3
T2
T1
T0
0
0
Start Message
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Table 11-18 and Table 11-19 illustrate examples of Direct Branch Messages: one with 2 MDO / 1 MSEO,
and one with 8 MDO / 2 MSEO.
Note that T0 and I0 are the least significant bits where:
• Tx = TCODE number (fixed)
• Sx = Source processor (fixed)
• Ix = Number of Instructions (variable)
Table 11-18. Direct Branch Message Example (2 MDO / 1 MSEO)
Clock
MDO[1:0]
MSEO
State
0
X
X
1
Idle (or end of last message)
1
T1
T0
0
Start Message
2
T3
T2
0
Normal Transfer
3
T5
T4
0
Normal Transfer
4
S1
S0
0
Normal Transfer
5
S3
S2
0
Normal Transfer
6
I1
I0
1
End Packet
7
0
0
1
End Message
8
T1
T0
0
Start Message
Table 11-19. Direct Branch Message Example (8 MDO / 2 MSEO)
Clock
MDO[7:0]
MSEO[1:0]
State
0
X
X
X
X
X
X
X
X
1
1
Idle (or end of last message)
1
S1
S0
T5
T4
T3
T2
T1
T0
0
0
Start Message
2
0
0
0
0
I1
I0
S3
S2
1
1
End Packet/End Message
3
S1
S0
T5
T4
T3
T2
T1
T0
0
0
Start Message
11.10 A7S Nexus3 Programmers Model
This section describes the A7S Nexus3 programmers model. Nexus registers are accessed using the JTAG
port in compliance with IEEE 1149.1 (discussed in Section 11.10.4, “Nexus Register Access via JTAG”).
11.10.1 JTAG ID Register
This JTAG ID Register (located within the ARM7 CPU) provides key development attributes to the
development tool concerning the ARM7 processor and the A7S Nexus3 block. This register is fixed for
each ARM7 embedded system.
This register is accessed through the standard JTAG IR/DR paths.
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Offset SoC defined
31
R
28
27
26
25
24
23
22
21
20
19
18
17
16
0
PART NUMBER
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
R
PART NUMBER
W
Reset
29
VERSION
W
Reset
30
Access: User read/write
0
0
0
MANUFACTURER ID #
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Figure 11-4. JTAG ID Register
Table 11-20. JTAG ID Field Descriptions
Field
Description
31–28
VER
Embedded Product Version Number
X
SoC defined
27–12
PNUM
ARM7 Based Part Number
M
SoC defined
11–1
MANID
Manufacturer ID Number
00E Freescale
0
Fixed per IEEE 1149.1 (JTAG)
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11.10.2 Nexus3 Register Map
Table 11-21. A7S Nexus3 Register Map
Nexus
Access
Opcode
Read/
Write
Read
Address
Write
Address
Client Select Control (CSC) (see Note below)
0x1
R
0x02
—
Development Control (DC)
0x2
R/W
0x04
0x05
Development Status (DS)
0x4
R
0x08
—
User Base Address (UBA)
0x6
R/W
0x0C
0x0D
Read/Write Access Control/Status (RWCS)
0x7
R/W
0x0E
0x0F
Read/Write Access Address (RWA)
0x9
R/W
0x12
0x13
Read/Write Access Data (RWD)
0xA
R/W
0x14
0x15
Watchpoint Trigger (WT)
0xB
R/W
0x16
0x17
Data Trace Control (DTC)
0xD
R/W
0x1A
0x1B
Data Trace Start Address1 (DTSA1)
0xE
R/W
0x1C
0x1D
Data Trace Start Address2 (DTSA2)
0xF
R/W
0x1E
0x1F
Data Trace End Address1 (DTEA1)
0x12
R/W
0x24
0x25
Data Trace End Address2 (DTEA2)
0x13
R/W
0x26
0x27
Break/Watchpoint Control 1 (BWC1)
0x16
R/W
0x2C
0x2D
Break/Watchpoint Control 2 (BWC2)
0x17
R/W
0x2E
0x2F
Break/Watchpoint Control 3 (BWC3)
0x18
R/W
0x30
0x31
Break/Watchpoint Control 4 (BWC4)
0x19
R/W
0x32
0x33
Break/Watchpoint Control 5 (BWC5)
0x1A
R/W
0x34
0x35
Break/Watchpoint Control 6 (BWC6)
0x1B
R/W
0x36
0x37
Break/Watchpoint Address 1 (BWA1)
0x1E
R/W
0x3C
0x3D
Break/Watchpoint Address 2 (BWA2)
0x1F
R/W
0x3E
0x3F
Break/Watchpoint Address 3 (BWA3)
0x20
R/W
0x40
0x41
Break/Watchpoint Address 4 (BWA4)
0x21
R/W
0x42
0x43
Break/Watchpoint Address 5 (BWA5)
0x22
R/W
0x44
0x45
Break/Watchpoint Address 6 (BWA6)
0x23
R/W
0x46
0x47
Break/Watchpoint Data 1 (BWD1)
0x26
R/W
0x4C
0x4D
Break/Watchpoint Data 2 (BWD2)
0x27
R/W
0x4E
0x4F
Break/Watchpoint Address Mask 1 (BWAM1)
0x42
R/W
0x84
0x85
Break/Watchpoint Address Mask 2 (BWAM2)
0x43
R/W
0x86
0x87
Break/Watchpoint Data Mask 1 (BWDM1)
0x44
R/W
0x88
0x89
Break/Watchpoint Data Mask 2 (BWDM2)
0x45
R/W
0x8A
0x8B
Port Configuration Register (PCR)
0x7F
R/W
0xFE
0xFF
Nexus Register
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NOTE
In a multi-nexus environment, the CSC and PCR may be implemented in a
separate module at the SoC level. If implemented, the values at the SoC
level will override the settings in the Nexus module.
11.10.3 A7S Nexus3 Register Definitions
Detailed register definitions are as follows:
11.10.3.1 Client Select Control (CSC)
The Client Select Control Register determines which Nexus client is under development.
Offset see Table 11-21
Access: User read/write
7
6
5
4
3
2
1
0
0
0
0
0
R
CSC
W
Reset
0
0
0
0
Figure 11-5. Client Select Control Register (CSC)
Table 11-22. Client Select Register Field Description
Field
7–0
CSC
Description
Client Select Control
0xXX Nexus client (SoC level)
11.10.3.2 Development Control (DC)
The Development Control Register is used to control basic development features of A7S Nexus3.
Offset see Table 11-21
R
Access: User read/write
31
30
29
0
0
0
28
R
26
0
0
0
0
0
0
15
14
13
12
11
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EOC
W
Reset
27
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
PTM
WEN
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
0
0
OVC
W
Reset
0
0
EIC
0
0
TM
0
0
0
0
Figure 11-6. Development Control Register (DC)
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Table 11-23. DC Field Descriptions
Field
Description
31–29
Reserved for future functionality (read as 0)
28–27
EOC
EVTO Control
00 EVTO upon occurrence of Watchpoint
01 EVTO upon entry into Debug Mode (DBGACK)
1X Reserved
26
Reserved for future functionality (read as 0)
25
PTM
Program Trace Method (Thumb mode only)
0 Program Trace in Thumb mode uses Branch History Messages
1 Program Trace in Thumb mode uses traditional Branch Messages
24
WEN
Watchpoint Trace Enable
0 Watchpoint Messaging disabled
1 Watchpoint Messaging enabled
23–8
Reserved for future functionality (read as 0)
7–5
OVC
Overrun Control
000 Generate overrun messages
001 Reserved
010 Reserved
011 Delay processor for trace message overruns (FIFOFULL)
1xx Reserved
4–3
EIC
EVTI Control
00 EVTI for synchronization (Program Trace)
01 EVTI for Debug request (if implemented)
10 EVTI disabled
11 Reserved
2–0
TM
Trace Mode
000 No Trace
1xx Program Trace enabled
x1x Data Trace enabled
xx1 Ownership Trace enabled
11.10.3.3 Development Status (DS)
The Development Status Register is used to report system debug status. When Debug Mode is entered or
exited or an SoC or ARM7 defined Low Power Mode is entered (see Note below), a Debug Status Message
is transmitted with DS[31:24]. The external tool can read this register at any time.
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Offset see Table 11-21
31
R
W
Reset
R
30
DBG
Access: User read/write
29
28
27
LPS
26
LPC
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Figure 11-7. Development Status Register (DS)
Table 11-24. DS Field Descriptions
Field
Description
31
DBG
ARM7 CPU Debug Mode Status
0 CPU not in Debug Mode
1 CPU in Debug Mode (DBGACK asserted)
30–28
LPS
ARM7 System Low Power Mode Status
000 Normal (Run) mode
nnn System Low Power Status (SoC level)
27–26
LPC
ARM7 CPU Low Power Mode Status
00 Normal (Run) mode
01 CPU in powered-down state
1x Reserved
25–0
Reserved for future functionality (read as 0)
NOTE
System low power mode bits (LPS) functionality is determined at the
platform or SoC integration level. Any entry into a system-level low power
mode (LPS != 3'b000) will trigger a Debug Status Message sending the DS
register value to the external tool. These bits are recommended for non-CPU
related power-down modes. It is the tool’s responsibility to decode the
specific type of low power mode based on the encodings for the specific
SoC.
The CPU Low Power Mode bits (LPC) must be tied to the logic which
indicates that the ARM7 processor is in a powered-down state. The CPU
low power state may be independent of the SoC defined low power mode(s)
determined by the LPS bits.
11.10.3.4 User Base Address (UBA)
For ARM7 processors, Ownership Trace Messaging is implemented using the Nexus defined User Base
Address Register. The User Base Address Register defines the memory mapped base address for the
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Ownership Trace Register (OTR). The operating system writes the ID for the current task/process in the
OTR. The UBA is read and written to by the external development tool.
Offset see Table 11-21
31
30
Access: User read/write
29
28
27
R
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R
OWNERSHIP TRACE REGISTER ADDRESS
W
Reset
25
OWNERSHIP TRACE REGISTER ADDRESS
W
Reset
26
0
0
0
0
0
0
0
0
0
0
0
Figure 11-8. User Base Address Register (UBA)
NOTE
It is recommended that the UBA only be modified while system reset is
asserted or in debug mode. Caution should be taken when modifying the
UBA when system reset is negated.
11.10.3.5 Read/Write Access Control/Status (RWCS)
The Read Write Access Control/Status Register provides control for Read/Write Access. Read/Write
access provides DMA-like access to Advanced High-performance Bus (AHB) memory mapped resources
when the processor is halted or during runtime. The RWCS Register also provides Read/Write Access
Status information per Table 11-26.
Offset see Table 11-21
R
W
Reset
Access: User read/write
31
30
29
28
27
26
AC
RW
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
SZ
25
23
MAP
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
ERR
DV
0
0
PR
CNT
W
Reset
24
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-9. Read/Write Access Control Register (RWCS)
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Table 11-25. RWCS Field Descriptions
Field
Description
31
AC
Access Control
0 End access
1 Start access
30
RW
Read/Write Select
0 Read access
1 Write access
29–27
SZ
Word Size
000 8-bit (byte)
001 16-bit (halfword)
010 32-bit (word)
011–111Reserved (default to word)
26–24
MAP
Map Select
000 Primary memory map
001–111Reserved
23–22
PR
Read/Write Access Priority
00 Lowest access priority
01 Reserved (default to lowest priority)
10 Reserved (default to lowest priority)
11 Highest access priority
21–16
Reserved for future functionality
15–2
CNT
Access Control Count
hhhh Number of accesses of word size SZ
1
ERR
Read/Write Access Error (see Table 11-26)
0
DV
Read/Write Access Data Valid (see Table 11-26)
Table 11-26. Read/Write Access Status Bit Encoding
Read Action
Write Action
ERR
DV
Read Access has not completed
Write Access completed without error
0
0
Read Access error has occurred
Write Access error has occurred
1
0
Read Access completed without error
Write Access has not completed
0
1
Not Allowed
Not allowed
1
1
11.10.3.6 Read/Write Access Data (RWD)
The Read/Write Access Data Register provides the data to/from AHB memory mapped locations when
initiating a read or a write access.
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Offset see Table 11-21
31
30
Access: User read/write
29
28
27
26
25
R
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
READ/WRITE DATA
W
Reset
23
READ/WRITE DATA
W
Reset
24
0
0
0
0
0
0
0
0
0
Figure 11-10. Read/Write Access Data Register (RWD)
11.10.3.7 Read/Write Access Address (RWA)
The Read/Write Access Address Register provides the AHB memory mapped address to be accessed when
initiating a read or a write access
Offset see Table 11-21
31
30
Access: User read/write
29
28
27
26
R
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
R
READ/WRITE ADDRESS
W
Reset
24
READ/WRITE ADDRESS
W
Reset
25
0
0
0
0
0
0
0
0
0
0
Figure 11-11. Read/Write Access Address Register (RWA)
11.10.3.8 Watchpoint Trigger (WT)
The Watchpoint Trigger Register allows the four watchpoints to trigger actions. These watchpoints can
control Program Trace and Data Trace. The WT bits can be used to produce an address related “window”
for triggering Trace Messages.
Offset see Table 11-21
31
R
R
29
28
PTS
W
Reset
30
Access: User read/write
27
26
25
PTE
24
23
22
DTS
0
0
21
20
DTE
0
0
0
0
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Figure 11-12. Watchpoint Trigger Register (WT)
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Table 11-27. WT Field Descriptions
Field
Description
31–29
PTS
Program Trace Start Control
000 Trigger disabled
001 Use ARM7 Watchpoint 0
010 Use ARM7 Watchpoint 1
011 Use Nexus Watchpoint 1
100 Use Nexus Watchpoint 2
101 Use Nexus Watchpoint 3
110 Use Nexus Watchpoint 4
111 Use Nexus Watchpoint 5
28–26
PTE
Program Trace End Control
000 Trigger disabled
001 Use ARM7 Watchpoint 0
010 Use ARM7 Watchpoint 1
011 Use Nexus Watchpoint 1
100 Use Nexus Watchpoint 2
101 Use Nexus Watchpoint 3
110 Use Nexus Watchpoint 4
111 Use Nexus Watchpoint 5
25–23
DTS
Data Trace Start Control
000 Trigger disabled
001 Use ARM7 Watchpoint 0
010 Use ARM7 Watchpoint 1
011 Use Nexus Watchpoint 1
100 Use Nexus Watchpoint 2
101 Use Nexus Watchpoint 3
110 Use Nexus Watchpoint 4
111 Use Nexus Watchpoint 5
22–20
DTE
Data Trace End Control
000 Trigger disabled
001 Use ARM7 Watchpoint 0
010 Use ARM7 Watchpoint 1
011 Use Nexus Watchpoint 1
100 Use Nexus Watchpoint 2
101 Use Nexus Watchpoint 3
110 Use Nexus Watchpoint 4
111 Use Nexus Watchpoint 5
19–0
Reserved for future functionality (read as 0)
NOTE
The WT bits will control Program/Data Trace only if the TM bits within the
Development Control Register (DC) have not already been set to enable
Program Trace.
11.10.3.9 Data Trace Control (DTC)
The Data Trace Control Register controls whether DTM Messages are restricted to reads, writes or both
for a user programmable address range. There are two Data Trace channels controlled by the DTC for the
A7S Nexus3 module.
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Offset see Table 11-21
31
R
W
Reset
R
30
RWT1
Access: User read/write
29
28
RWT2
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
0
0
0
0
0
0
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
RC1
RC2
0
0
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-13. Data Trace Control Register (DTC)
Table 11-28. DTC Field Description
Field
Description
31–30
RWT1
Read/Write Trace 1
00 No trace messages generated
x1 Enable data read trace
1x Enable data write trace
29–28
RWT2
Read/Write Trace 2
00 No trace messages generated
x1 Enable data read trace
1x Enable data write trace
27–8
Reserved for future functionality (read as 0)
7
RC1
Range Control 1
0 Condition trace on address within range
1 Condition trace on address outside of range
6
RC2
Range Control 2
0 Condition trace on address within range
1 Condition trace on address outside of range
5–0
Reserved for future functionality
11.10.3.10 Data Trace Start Address (DTSA1, DTSA2)
The Data Trace Start Address Registers define the start addresses for each trace channel.
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Offset see Table 11-21
31
30
Access: User read/write
29
28
27
26
R
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
R
DATA TRACE START ADDRESS
W
Reset
24
DATA TRACE START ADDRESS
W
Reset
25
0
0
0
0
0
0
0
0
0
0
Figure 11-14. Data Trace Start Address Registers (DTSA1, DTSA2)
11.10.3.11 Data Trace End Address (DTEA1, DTEA2)
The Data Trace End Address Registers define the end addresses for each trace channel.
Offset see Table 11-21
31
30
Access: User read/write
29
28
27
26
R
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
R
DATA TRACE END ADDRESS
W
Reset
24
DATA TRACE END ADDRESS
W
Reset
25
0
0
0
0
0
0
0
0
0
0
Figure 11-15. Data Trace End Address Registers (DTEA1, DTEA2)
Table 11-29 below illustrates the range that will be selected for Data Trace for various cases of DTSA
being less than, greater than, or equal to DTEA.
Table 11-29. Data Trace – Address Range Options
Programmed Values
Range Control Bit Value
Range Selected
DTSA ⇐ DTEA
0
DTSA → ← DTEA
DTSA ⇐ DTEA
1
← DTSA DTEA →
DTSA > DTEA
N/A
Invalid Range – no trace
NOTE
For inside range traces, the trace range is inclusive of the DTSA and DTEA.
For outside range traces, the trace range is exclusive of the DTSA and
DTEA addresses.
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11.10.3.12 Breakpoint / Watchpoint Control (BWC1, BWC2)
Breakpoint/Watchpoint Control Registers 1 and 2 control the generation of Nexus Internal Watchpoints 1
and 2.
Offset see Table 11-21
31
R
29
BWE
28
BRW
27
26
25
24
23
22
21
20
19
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
18
17
16
BWO
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
BWT
W
Reset
30
Access: User read/write
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
0
0
0
Figure 11-16. Breakpoint/Watchpoint Control Registers (BWC1, BWC2)
Table 11-30. BWC1, BWC2 Field Description
Field
Description
31–30
BWE
Breakpoint/Watchpoint Enable
00 Internal Nexus Watchpoint Unit disabled
01–10Reserved
11 Internal Nexus Watchpoint enabled
29–28
BRW
Breakpoint/Watchpoint Read/Write Select
00 Watchpoint hit on read accesses
01 Watchpoint hit on write accesses
10 Watchpoint on read or write accesses
11 Reserved
27–19
Reserved for future functionality (read as 0)
18–16
BWO
Breakpoint/Watchpoint Operand
000 No Register Compare (same as BWC1[31:30]2'b00)
001 Compare with BWD1 value only
010 Compare with BWA1 value only
011 Compare with BWA1 and BWD1 values
1xx Reserved
15
BWT
Breakpoint/WatchpointType
0 Watchpoint #1 on instruction accesses
1 Watchpoint #1 on data accesses
14–0
Reserved for future functionality (read as 0)
NOTE
Watchpoint units 1 and 2 do not have breakpoint capability.
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11.10.3.13 Breakpoint / Watchpoint Control (BWC3-6)
Breakpoint/Watchpoint Control registers 3 - 6 control the generation of Nexus Internal Watchpoints 3-6.
Offset see Table 11-21
31
R
BWE
W
Reset
R
30
Access: User read/write
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Figure 11-17. Breakpoint / Watchpoint Control Registers (BWC3-6)
Table 11-31. BWC3-6 Field Description
Field
Description
31–30
BWE
Breakpoint/Watchpoint Enable
00 Internal Nexus Watchpoint Unit disabled
01 Internal Nexus Breakpoint enabled
10 Reserved
11 Internal Nexus Watchpoint enabled
29–19
Reserved for future functionality (read as 0)
18–16
Reserved for future functionality (read as 010)
15–0
Reserved for future functionality (read as 0)
NOTE
Watchpoint units 3 - 6 only perform instruction address comparisons.
11.10.3.14 Breakpoint / Watchpoint Address (BWA1-6)
The Breakpoint / Watchpoint Address registers are compared with ARM bus addresses in order to generate
internal watchpoints.
Offset see Table 11-21
31
30
Access: User read/write
29
28
27
R
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R
BREAKPOINT / WATCHPOINT ADDRESS
W
Reset
25
BREAKPOINT / WATCHPOINT ADDRESS
W
Reset
26
0
0
0
0
0
0
0
0
0
0
0
Figure 11-18. Breakpoint / Watchpoint Address Registers (BWA1-6)
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11.10.3.15 Breakpoint / Watchpoint Address Mask (BWAM1, BWAM2)
The Breakpoint / Watchpoint Address Mask Registers allow the user to mask ARM bus addresses for
internal watchpoint units 1 and 2 on a bit-wise granularity.
Offset see Table 11-21
31
30
Access: User read/write
29
28
27
R
24
23
22
21
20
19
18
17
16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
1
1
1
1
1
R
BREAKPOINT / WATCHPOINT ADDRESS MASK
W
Reset
25
BREAKPOINT / WATCHPOINT ADDRESS MASK
W
Reset
26
1
1
1
1
1
1
1
1
1
1
1
Figure 11-19. Breakpoint / Watchpoint Address Mask Registers (BWAM1, BWAM2)
Table 11-32. BWAM Field Description
Field
31–0
Description
Breakpoint / Watchpoint Address Mask Enable
0 Corresponding BWA bit is masked when generating internal watchpoints
1 Corresponding BWA bit is not masked when generating internal watchpoints
11.10.3.16 Breakpoint / Watchpoint Data (BWD1, BWD2)
The Breakpoint / Watchpoint Data Registers are compared with ARM bus values for internal watchpoint
units 1 and 2.
Offset see Table 11-21
31
30
Access: User read/write
29
28
27
R
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
R
BREAKPOINT / WATCHPOINT DATA
W
Reset
25
BREAKPOINT / WATCHPOINT DATA
W
Reset
26
0
0
0
0
0
0
0
0
0
0
0
Figure 11-20. Breakpoint / Watchpoint Data Registers (BWD1, BWD2)
11.10.3.17 Breakpoint / Watchpoint Data Mask (BWDM1, BWDM2)
The Breakpoint / Watchpoint Data Mask Registers allow the user to mask ARM bus data values on a
byte-wise granularity for internal watchpoint units 1 and 2.
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Offset see Table 11-21
R
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
R
BWDME
W
Reset
1
1
1
1
Figure 11-21. Breakpoint / Watchpoint Data Mask Registers (BWDM1, BWDM2)
Table 11-33. BWDM Field Description
Field
31–4
Description
Reserved for future functionality (read as 0)
3–0
Breakpoint / Watchpoint Data Mask Enable
BWDME 0xxx mask data byte (31:24)
xxx0 mask data byte (7:0)
11.10.3.18 Port Configuration (PCR)
The Port Configuration Register controls the basic port functions including clock control and auxiliary
output port width.
NOTE
If the PCR register exists in a separate arbiter module at the SoC level in a
multi-Nexus environment, then the settings at the SoC level override the
settings in the A7S Nexus3 module.
Offset see Table 11-21
30
R
OPC
W
Reset
R
29
28
MCK_EN
31
Access: User read/write
27
26
MCK_DIV
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MSC
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Figure 11-22. Port Configuration Register (PCR)
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Table 11-34. PCR Field Description
Field
31–30
OPC
Description
Output Port Mode Control
00 Reduced Port Mode (2 bits)
01 Reduced Port Mode (2 bits)
10 Reduced Port Mode (2 bits)
11 Full Port Mode (8 bits)
29
Nexus Message Clock Enable
MCK_EN 1 Nexus Message Clock (MCKO) is enabled
0 Nexus Message Clock (MCKO) is disabled
28–26 Nexus Message Clock Divide Ratio
MCK_DIV 000
MCKO is 1x the processor clock freq.
001
MCKO is 1/2x the processor clock freq.
010
Reserved
011
MCKO is 1/4x the processor clock freq.
100–110 Reserved
111
MCKO is 1/8x the processor clock freq.
25
MSC
MSEO Pin Control
0 Select 1 MSEO pin
1 Select 2 MSEO pins
24–0
Reserved for future functionality (read as 0)
NOTE
The PCR must only be modified during system reset, or while the Nexus is
otherwise idle or disabled to insure correct output port and output clock
functionality
11.10.4 Nexus Register Access via JTAG
Access to Nexus register resources is enabled by loading a single instruction (“NEXUS-ACCESS”) into the
JTAG Instruction Register (IR). For the A7S Nexus3 block, the JTAG IR value is programmable at the
platform or SoC integration level. It can be programmed to any of the non-ARM7 implemented IR values.
Table below shows the current ARM7 IR values (as defined by ARM).
Table 11-35. ARM7 JTAG Instructions
IR[3:0]
Usable for NEXUS-ACCESS?
JTAG Instruction
0x0
NO
EXTEST (ARM720T)
0x1
YES
not publicly implemented
0x2
NO
SCAN_N (ARM7TDMI-S)
0x3
NO
SAMPLE/PRELOAD (ARM720T)
0x4
NO
RESTART (ARM7TDMI-S)
0x5
NO
CLAMP (ARM720T)
0x6
YES
not publicly implemented
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Table 11-35. ARM7 JTAG Instructions (Continued)
IR[3:0]
Usable for NEXUS-ACCESS?
JTAG Instruction
0x7
NO
HIGHZ (ARM720T)
0x8
YES
recommended for NEXUS-ACCESS
0x9
NO
CLAMPZ (ARM720T)
0xA
YES
not publicly implemented
0xB
YES
not publicly implemented
0xC
NO
INTEST (ARM7TDMI-S)
0xD
YES
not publicly implemented
0xE
NO
IDCODE (ARM7TDMI-S)
0xF
NO
BYPASS (ARM7TDMI-S)
NOTE
It is recommended to use IR[3:0] = 0x8 for “NEXUS-ACCESS”
Once the JTAG “NEXUS-ACCESS” instruction has been loaded, the JTAG port allows tool/target
communications with all Nexus registers according to the map in Table 11-21.
Reading/writing of a Nexus register then requires two (2) passes through the Data-Scan (DR) path of the
JTAG state machine (see 11.12, “IEEE 1149.1 State Machine and RD/WR Sequences”).
1. The first pass through the DR selects the Nexus register to be accessed by providing an index (see
Table 11-21), and the direction (read/write). This is achieved by loading an 8-bit value into the
JTAG Data Register (DR). This register has the following format:
Access: User read/write
7
6
5
4
3
2
1
0
R
NRI
R/W
W
Reset
0
0
0
0
0
0
0
0
Figure 11-23. JTAG DR for Nexus Register Access
Table 11-36. JTAG DR Field Description for Nexus Register Access
Field
Description
7–1
NRI
Nexus Register Index
xx
Selected from values in Table 11-21
0
R/W
Read/Write (R/W)
0 Read
1 Write
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Functional Description
2. The second pass through the DR then shifts the data in or out of the JTAG port, LSB first.
a) During a read access, data is latched from the selected Nexus register when the JTAG state
machine (see 11.12, “IEEE 1149.1 State Machine and RD/WR Sequences”) passes through the
“Capture-DR” state.
b) During a write access, data is latched into the selected Nexus register when the JTAG state
machine (see 11.12, “IEEE 1149.1 State Machine and RD/WR Sequences”) passes through the
“Update-DR” state.
11.10.5 Programming Considerations (RESET)
If Nexus3 register configuration is to occur during system reset (as opposed to debug mode), all Nexus3
configuration should be completed between the exit from JTAG Test-Logic-Reset state and system reset
de-assertion, after the JTAG ID Register has been read by the tool.
11.11 Functional Description
11.11.1 Ownership Trace
Ownership trace provides a macroscopic view, such as task flow reconstruction, when debugging software
written in a high level (or object-oriented) language. It offers the highest level of abstraction for tracking
operating system software execution. This is especially useful when the developer is not interested in
debugging at lower levels.
11.11.1.1 Ownership Trace Messaging (OTM)
Ownership trace information is messaged via the auxiliary port using an Ownership Trace Message
(OTM). The User Base Address Register (UBA), which can be accessed via the JTAG port, contains the
address of the Ownership Trace Register (OTR). The OTR is updated by the operating system software to
provide task/process ID information.
An OTM is generated when new information is updated in the OTR register by the ARM7 processor, the
data is latched within Nexus, and is messaged out via the auxiliary port, allowing development tools to
trace ownership flow.
Ownership trace information is messaged out in the following format:
(32 bits)
(4 bits)
(6 bits)
Task / Process ID Tag
SRC
TCODE (000010)
Fixed length = 42 bits
Figure 11-24. Ownership Trace Message Format
11.11.1.2 OTM Error Messages
An Error Message occurs when a new message cannot be queued due to the message queue being full. The
FIFO will discard incoming messages until it has completely emptied the queue. Once emptied, an Error
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Functional Description
Message will be queued. The error encoding will indicate which type(s) of messages attempted to be
queued while the FIFO was being emptied.
If only an OTM Message attempts to enter the queue while it is being emptied, the Error Message will
incorporate the OTM only error encoding (00000). If both OTM AND either BTM or DTM messages
attempt to enter the queue, the Error Message will incorporate the OTM and Program Trace error encoding
(00111). If a Watchpoint also attempts to be queued while the FIFO is being emptied, then the Error
Message will incorporate error encoding (01000).
NOTE
The OVC bits within the DC Register can be set to delay the CPU by
asserting the FIFOFULL signal in order to alleviate (but not eliminate)
potential overruns.
Error information is messaged out in the following format (see Table 11-2).
(5 bits)
(4 bits)
(6 bits)
ERROR (00000 / 00111 / 01000)
SRC
TCODE (001000)
Fixed length = 15 bits
Figure 11-25. Error Message Format
11.11.1.3 OTM Flow
Ownership Trace Messages are generated when the operating system writes to the memory mapped
Ownership Trace Register.
The following flow describes the OTM process.
1. For the A7S Nexus3 module, the OTR register is a memory mapped register, whose address is
located in the UBA. The UBA is internal to the Nexus module and can be accessed by the
IEEE-ISTO 5001 tool through the JTAG port.
2. Only word writes to the OTR are valid. The data value written into the OTR is registered and
formed into the Ownership Trace Message that is queued to be transmitted.
3. OTR reads do not cause Ownership Trace Messages to be transmitted by the A7S Nexus3 module.
11.11.2 Program Trace
This section details the program trace mechanisms supported by Nexus 3 for the ARM7 processor.
Program trace is implemented via Branch Trace Messaging (BTM) as per the Class 2 IEEE-ISTO 5001
standard definition.
11.11.2.1 Branch Trace Messaging (BTM)
Traditional Branch Trace Messaging (Thumb mode only) facilitates program trace by providing the
following types of information:
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Functional Description
•
•
Messaging for taken direct branches includes how many sequential instructions were executed
since the last taken branch or exception. Direct (or indirect) branches not taken are counted as
sequential instructions.
Messaging for taken indirect branches and exceptions includes how many sequential instructions
were executed since the last taken branch or exception and the unique portion of the branch target
address or exception vector address.
Branch History Messaging (ARM and Thumb modes) facilitates program trace by providing the following
information.
• Messaging for taken indirect branches and exceptions includes how many sequential instructions
were executed since the last predicate instruction, exception, or taken indirect branch, the unique
portion of the branch target address or exception vector address, as well as a branch/predicate
instruction history field. Each bit in the history field represents a direct branch or predicated
instruction where a value of one (1) indicates taken, and a value of zero (0) indicates not taken.
11.11.2.1.1 ARM7 Indirect Branch Message Instructions
The table below shows the types of instructions and events which cause Indirect Branch Messages or
Branch History Messages to be encoded.
Table 11-37. Indirect Branch / Branch History Message Instructions
Source of Indirect Branch Message
Instructions (ARM mode)
Instr. (Thumb mode)
Taken Register / PC Indirect Branch instruction
bx
bx
Sequential instruction w/ PC as destination reg.
any that write to R15 (PC)
any that write to R15 (PC)
Interrupt / exception
swi, undefined instructions
undefined instructions
movs, subs, ldm(3)
N/A
Return from interrupt / exception
NOTE
Instructions with the Program Counter (PC) as the destination register (R15)
that are interrupted may or may not cause a BTM to be queued depending
on which stage of the pipe the instruction has reached when the interrupt
occurs.
11.11.2.1.2 ARM7 Direct Branch Message Instructions
The table below shows the types of instructions that will cause Direct Branch Messages or will toggle a
bit in the instruction history buffer to be messaged out in a Resource Full Message or Branch History
Message.
Table 11-38. Direct Branch Message Instructions
Source of Direct Branch Message Instructions (ARM mode)
Taken Direct Branch instruction
b, bl
Instr. (Thumb mode)
b(1), b(2), bl
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11.11.2.1.3 BTM in ARM mode
Due to the conditional nature of 32-bit ARM instructions, traditional BTM Messaging can accurately track
the number of sequential instructions between branches, but cannot accurately indicate which instructions
were conditionally executed, and which were not.
Branch History Messaging solves this problem by providing a predicated instruction history field in each
Indirect Branch Message. Each bit in the history represents a predicated instruction or direct branch. A
value of one (1) indicates the conditional instruction was executed or the direct branch was taken. A value
of zero (0) indicates the conditional instruction was not executed or the direct branch was not taken.
Branch History Messages solve predicated instruction tracking and save bandwidth since only indirect
branches cause messages to be queued.
11.11.2.1.4 BTM in Thumb mode
Based on the PTM bit in the DC Register (DC[25]), Program Tracing can utilize either Branch History
Messages (DC[25]=1'b0) or traditional Direct/Indirect Branch Messages (DC[25]=1'b1).
Branch History will save bandwidth and keep consistency between methods of Program Trace in ARM
and Thumb modes, yet may lose temporal order between branch events and other types of messages. Since
direct branches are not messaged, but included in the history field of the Indirect Branch History Message,
other types of messages may enter the FIFO between Branch History Messages. The development tool
cannot determine the ordering of events that occurred with respect to direct branches simply by the order
in which messages are sent out.
Traditional BTM messages maintain their temporal ordering because each event that can cause a message
to be queued will enter the FIFO in the order it occurred and will be messaged out maintaining that order.
11.11.2.2 Branch Trace Message Formats (History and Traditional)
The A7S Nexus3 block supports three types of traditional BTM Messages: Direct, Indirect, and
Synchronization Messages. It supports two types of branch history BTM Messages: Indirect Branch
History, and Indirect Branch History with Synchronization Messages. Debug Status Messages, Program
Correlation Messages and Error Messages are also supported.
11.11.2.2.1 Indirect Branch Messages (History)
Indirect branches include all taken branches whose destination is determined at run time, interrupts and
exceptions. If DC[25] is cleared while in Thumb mode, or the ARM7 processor is in full 32-bit ARM
mode, indirect branch information is messaged out in the following format
(1–32 bits)
(1–32 bits)
(1–8 bits)
(4 bits)
(6 bits)
HIST
U-ADDR
I-CNT
SRC
TCODE (011100)
Max length = 82 bits; Min length = 13 bits
Figure 11-26. Indirect Branch Message (History) Format
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11.11.2.2.2 Indirect Branch Messages (Traditional)
If DC[25] is set in Thumb mode, indirect branch information is messaged out in the following format:
(1–32 bits)
(1–8 bits)
(4 bits)
(6 bits)
U-ADDR
I-CNT
SRC
TCODE (000100)
Max length = 50 bits; Min length = 12 bits
Figure 11-27. Indirect Branch Message (Traditional) Format
11.11.2.2.3 Direct Branch Messages (Traditional)
Direct branches (conditional or unconditional) are all taken branches whose destination is fixed in the
instruction opcode. If DC[25] is set while in Thumb mode, direct branch information is messaged out in
the following format:
(1–8 bits)
(4 bits)
(6 bits)
I-CNT
SRC
TCODE (000100)
Max length = 18 bits; Min length = 11 bits
Figure 11-28. Direct Branch Message Format
NOTE
When DC[25] is cleared in Thumb mode or the ARM7 processor is in full
32-bit ARM mode, Direct Branch Messages will not be transmitted. Instead,
each direct branch or predicated instruction will toggle a bit in the history
buffer.
11.11.2.2.4 Resource Full Messages
The Resource Full Message is used in conjunction with the Branch History Messages. The Resource Full
Message is generated when the internal branch/predicate history buffer is full. If synchronization is needed
at the time this message is generated, the synchronization is delayed until the next Branch Trace Message
that is not a Resource Full Message.
The current value of the history buffer is transmitted as part of the Resource Full Message. This
information can be concatenated by the tool with the branch/predicate history information from
subsequent messages to obtain the complete branch history for a message. The history value is reset by
this message, and the I-CNT value is reset as a result of a bit being added to the history buffer.
(1–32 bits)
(4 bits)
(4 bits)
(6 bits)
HIST
RCODE
(0001)
SRC
TCODE (011011)
Max length = 46 bits; Min length = 15 bits
Figure 11-29. Resource Full Message Format
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11.11.2.2.5 Program Correlation Messages
Program Correlation Messages (PCM) are used to correlate events to the program flow that may not be
associated with the instruction stream. In order to maintain accurate instruction tracing information when
entering debug mode, program trace is disabled or entering CPU low power mode a PCM is sent. It
includes the instruction count and branch history. Program Correlation is messaged out in the following
format:
(1–32 bits)
(1–8 bits)
(4 bits)
(4 bits)
(6 bits)
HIST
I-CNT
ECODE
SRC
TCODE (100001)
Max length = 54 bits; Min length = 16 bits
Figure 11-30. Program Correlation Message Format
11.11.2.2.6 BTM Overflow Error Messages
An Error Message occurs when a new message cannot be queued due to the message queue being full. The
FIFO will discard incoming messages until it has completely emptied the queue. Once emptied, an Error
Message will be queued. The error encoding will indicate which type(s) of messages attempted to be
queued while the FIFO was being emptied.
If only a Program Trace Message attempts to enter the queue while it is being emptied, the Error Message
will incorporate the Program Trace only error encoding (00001). If both OTM and Program Trace
Messages attempt to enter the queue, the Error Message will incorporate the OTM and Program Trace error
encoding (00111). If a Watchpoint also attempts to be queued while the FIFO is being emptied, then the
Error Message will incorporate error encoding (01000).
NOTE
The OVC bits within the DC Register can be set to delay the CPU by
asserting the FIFOFULL signal in order to alleviate (but not eliminate)
potential overruns.
Error information is messaged out in the following format:
(5 bits)
(4 bits)
(6 bits)
ERROR (00001 / 00111 / 01000)
SRC
TCODE (001000)
Fixed length = 15 bits
Figure 11-31. Error Message Format
11.11.2.2.7 Program Trace Synchronization Messages
A Program Trace Direct/Indirect Branch with Sync. or Indirect Branch History with Sync. Message is
messaged via the auxiliary port (provided Program Trace is enabled) for the following conditions (see
Table 11-39):
• Initial Program Trace Message upon the first direct (traditional only) or indirect branch after exit
from system reset or whenever program trace is enabled.
• Upon direct (traditional only) or indirect branch after returning from a Low Power state.
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Functional Description
•
•
•
•
•
•
•
Upon direct (traditional only) or indirect branch after returning from Debug Mode.
Upon direct (traditional only) or indirect branch after occurrence of queue overrun (can be caused
by any trace message), provided Program Trace is enabled.
Upon direct (traditional only) or indirect branch after the periodic program trace counter has
expired indicating 255 without-sync Program Trace Messages have occurred since the last
with-sync message occurred.
Upon direct (traditional only) or indirect branch after assertion of the Event In (EVTI) pin if the
EIC bits within the DC Register have enabled this feature.
Upon direct (traditional only) or indirect branch after the sequential instruction counter has expired
indicating 255 instructions have occurred between branches or since the last bit was entered in the
history field.
Upon direct (traditional only) or indirect branch after a BTM Message was lost due to an attempted
access to a secure memory location (for SOCs with security).
Upon direct (traditional only) or indirect branch after a BTM Message was lost due to a collision
with two other higher priority messages entering the FIFO.
If the A7S Nexus3 module is enabled at reset, an EVTI assertion initiates a Program Trace Indirect Branch
History with Sync. Message (if Program Trace is enabled) upon the first indirect branch. The message will
be a history type message because the ARM7 core will be in full 32-bit ARM mode upon exit from reset.
The history field will contain all taken/not taken direct branch and predicated instructions which occur
before the first indirect branch.
The formats for Program Trace Direct/Indirect Branch with Sync. Messages and Indirect Branch History
with Sync. Messages are as follows:
(1–32 bits)
(1–32 bits)
(1–8 bits)
(4 bits)
(6 bits)
HIST
F-ADDR
I-CNT
SRC
TCODE (011101)
Max length = 82 bits; Min length = 13 bits
Figure 11-32. Indirect Branch History w/ Sync. Message Format
(1–32 bits)
(1–8 bits)
(4 bits)
(6 bits)
F-ADDR
I-CNT
SRC
TCODE (001011 or 001100)
Max length = 50 bits; Min length = 12 bits
Figure 11-33. Direct/Indirect Branch with Sync. Message Format (traditional)
Exception conditions that result in Program Trace Synchronization are summarized in Table 11-39.
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Table 11-39. Program Trace Exception Summary
Exception Condition
Exception Handling
System Reset Negation
Upon entry into JTAG Test-Logic-Reset state, queue pointers, counters, state
machines, and registers within the ARM7 Nexus module are reset. Upon the first
branch out of system reset (if Program Trace is enabled), the first Program Trace
Message is a Direct/Indirect Branch w/ Sync. Message.
Program Trace Enabled
The first Program Trace Message (after Program Trace has been enabled) is a
synchronization message.
Exit from Low Power/Debug
Upon exit from a Low Power mode or Debug mode the next direct/indirect branch will
be converted to a Direct/Indirect Branch with Sync. Message.
Queue Overrun
An Error Message occurs when a new message cannot be queued due to the
message queue being full. The FIFO will discard messages until it has completely
emptied the queue. Once emptied, an Error Message will be queued. The error
encoding will indicate which type(s) of messages attempted to be queued while the
FIFO was being emptied. The next BTM message in the queue will be a
Direct/Indirect Branch w/ Sync. Message.
Periodic Program Trace Synchronization A forced synchronization occurs periodically after 255 Program Trace Messages
have been queued. A Direct/Indirect Branch w/ Sync. Message is queued. The
periodic program trace message counter then resets.
If the Nexus module is enabled, an EVTI assertion initiates a Direct/Indirect Branch
w/ Sync. Message upon the next direct/indirect branch (if Program Trace is enabled
and the EIC bits of the DC Register have enabled this feature).
Event In
Sequential Instruction Count Overflow
When the sequential instruction counter reaches its maximum count (up to 255
sequential instructions may be executed), a forced synchronization occurs. The
sequential counter then resets. A Program Trace Direct/Indirect Branch w/
Sync.Message is queued upon execution of the next branch.
Attempted Access to Secure Memory
For SOCs that implement security, any attempted branch to secure memory locations
will temporarily disable Program Trace & cause the corresponding BTM to be lost.
The following direct/indirect branch will queue a Direct/Indirect Branch w/ Sync.
Message. The count value within this message will be inaccurate since the re-enable
of Program Trace is not necessarily aligned on an instruction boundary.
Collision Priority
Messages have the following priority: Error, Ownership Trace, Watchpoint, Debug,
Program Correlation, Branch Trace (BTM), Data Trace. A BTM message which
attempts to enter the queue at the same time as two other higher priority messages
will be lost. An Error Message will be sent indicating the BTM was lost. Instruction
counts are not reset when a BTM is lost so subsequent instructions will be added to
the preempted message’s instruction count until a change of flow or predicated
instruction is reached. If a message is generated as a result of the subsequent
change of flow, then the instruction count in that message will include the instruction
count of the preempted message. Similarly, the history buffer is not reset when a BTM
is lost due to collision. In ARM mode, the branch that caused the preempted message
will receive a history bit since indirect branches may be conditional in ARM mode.
11.11.2.3 BTM Operation
11.11.2.3.1 Enabling Program Trace
Both types of Branch Trace Messaging can be enabled in one of two ways.
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Functional Description
•
•
Setting the TM field of the DC Register to enable Program Trace (DC[2]).
Using the PTS field of the WT Register to enable Program Trace on Watchpoint hits (ARM7
watchpoints are configured within the CPU).
NOTE
Setting DC[25] will select the traditional Branch Trace Messaging format
when in Thumb mode. By default, Branch History format is used
(DC[25]=1'b0). Full 32-bit ARM mode always utilizes the Branch History
Message format.
11.11.2.3.2 Addressing
The ARM7 architecture supports a processor mode switch into Thumb mode with the least significant bit
of the address bus set. The A7S Nexus3 module ignores this bit and always treats it as if it is zero (all
instruction addresses are aligned) for the purpose of program trace messaging.
The relative address feature is compliant with the IEEE-ISTO 5001 standard recommendations, and is
designed to reduce the number of bits transmitted for addresses of Indirect Branch Messages.
The address transmitted is relative to the target address of the instruction which triggered the previous
Indirect Branch (or Sync) Message. It is generated by XORing the new address with the previous address,
and then using only the results up to the most significant ‘1’ in the result. To recreate this address, an XOR
of the (most-significant 0-padded) message address with the previously decoded address gives the current
address.
Previous Address (A1) =0x0003FC01, New Address (A2) = 0x0003F365
Message Generation:
A1 = 0000 0000 0000 0011 1111 1100 0000 0001
A2 = 0000 0000 0000 0011 1111 0011 0110 0101
A1 ⊕ A2 = 0000 0000 0000 0000 0000 1111 0110 0100
Address Message (M1) = 1111 0110 0100
Address Re-creation:
A1 ⊕ M1 = A2
A1 = 0000 0000 0000 0011 1111 1100 0000 0001
M1 = 0000 0000 0000 0000 0000 1111 0110 0100
A2 = 0000 0000 0000 0011 1111 0011 0110 0101
Figure 11-34. Relative Address Generation and Re-creation
11.11.2.3.3 Branch/Predicate Instruction History (HIST)
In full 32-bit ARM mode (and optionally in Thumb mode), BTM messaging will use the Branch History
format. The branch history (HIST) packet in these messages provides a history of direct branch execution
used for reconstructing the program flow. This packet is implemented as a left-shifting shift register. The
register is always pre-loaded with a value of one (1). This bit acts as a stop bit so that the development
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Functional Description
tools can determine which bit is the end of the history information. The pre-loaded bit itself is not part of
the history, but is transmitted with the packet.
A value of one (1) is shifted into the history buffer on a taken direct branch (conditional or unconditional)
and on any instruction whose predicate condition resolved as true. A value of zero (0) is shifted into the
history buffer on any instruction whose predicate condition executed as false as well as on branches not
taken. This will include indirect as well as direct branches not taken.
11.11.2.3.4 Sequential Instruction Count (I-CNT)
The I-CNT packet, is present in all BTM Messages. For traditional Branch Messages (Thumb mode only),
I-CNT represents the number of sequential ARM7 instructions, or non-taken branches in between
Direct/Indirect Branch Messages.
For Branch History Messages in Thumb mode, I-CNT represents the number of ARM7 instructions
executed since the last taken/non-taken direct branch, last taken indirect branch or exception. Not taken
indirect branches are considered sequential instructions and cause the instruction count to increment. For
Branch History Messages in ARM mode, I-CNT also represents the number of ARM7 instructions
executed since the last predicate instruction.
The sequential instruction counter overflows when its value reaches 255. The next BTM Message
following an instruction counter overflow will be converted to a synchronization type message.
NOTE
When an undefined instruction causes an exception, the undefined
instruction itself will be included in the BTM instruction count.
11.11.2.3.5 Program Trace Queueing
A7S Nexus3 implements a programmable depth queue (32 minimum entry recommended) for queuing all
messages. Messages that enter the queue are transmitted via the auxiliary pins in the order in which they
are queued.
11.11.2.4 Program Trace Timing Diagrams (2 MDO / 1 MSEO configuration)
MCKO
MSEO_B
MDO[1:0]
00
01
00
00
00
00
00
00
10
01
01
10
10
00
TCODE = 4
source processor = 0000
# of sequential instructions = 128
relative address = 8'ha5
Figure 11-35. Program Trace – Indirect Branch Message (Traditional)
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MCKO
MSEO_B
MDO[1:0]
00
11
01
00
00
00
01
01
10
10
01
01
10
10
00
TCODE = 28
source processor = 0000
# of sequential instructions = 0
relative address = 8'ha5
branch history = 8'b10100101 (w/ stop)
Figure 11-36. Program Trace – Indirect Branch Message (History)
Direct Branch
Error
MCKO
MSEO_B
MDO[1:0]
11
00
00
00
00
11
DBM:
TCODE = 3
source processor = 0000
# of sequential instructions = 3
00
00
10
00
00
00
01
00
00
Error:
TCODE = 8
source processor = 0000
error code = 1 (queue overrun, BTM only)
Figure 11-37. Program Trace – Direct Branch (Traditional) and Error Messages
MCKO
MSEO_B
MDO[1:0]
00 11 00 00 00 11 10 11 00 11 10 10 11 11 01 11 10 10 10 11 01 11 00
TCODE = 12
source processor = 0000
# of sequential instructions = 3
full target address = 32'hdeadface
Figure 11-38. Program Trace – Indirect Branch w/ Sync. Message (Traditional)
11.11.3 Data Trace
This section deals with the Data Trace mechanism supported by the A7S Nexus3 module. Data Trace is
implemented via Data Write Messaging (DWM) and Data Read Messaging (DRM), as per the IEEE-ISTO
5001 standard.
11.11.3.1 Data Trace Messaging (DTM)
Data Trace Messaging for ARM7 is accomplished by snooping the ARM7 bus, and storing the information
for qualifying accesses (based on enabled features and matching target addresses). The A7S Nexus3
module traces all data access that meet the selected range and attributes.
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NOTE
Data Trace is only performed on the ARM7 bus. DMA accesses to the
Advanced High-performance Bus (AHB) are not traced.
11.11.3.2 DTM Message Formats
The A7S Nexus3 block supports five types of DTM Messages: Data Write, Data Read, Data Write
Synchronization, Data Read Synchronization and Error Messages.
11.11.3.2.1 Data Write Messages
The Data Write Message contains the data write value and the address of the write access, relative to the
previous Data Trace Message. Data Write Message information is messaged out in the following format:
(1–32 bits)
(1–32 bits)
(3 bits)
(4 bits)
(6 bits)
Data Value
Relative Address
Data Size
Src. Proc.
TCODE (000101)
Max length = 77 bits; Min length = 15 bits
Figure 11-39. Data Write Message Format
11.11.3.2.2 Data Read Messages
The Data Read Message contains the data read value and the address of the read access, relative to the
previous Data Trace Message. Data Read Message information is messaged out in the following format:
(1–32 bits)
(1–32 bits)
(3 bits)
(4 bits)
(6 bits)
Data Value
Relative Address
Data Size
Src. Proc.
TCODE (000110)
Max length = 77 bits; Min length = 15 bits
Figure 11-40. Data Read Message Format
11.11.3.2.3 DTM Overflow Error Messages
An Error Message occurs when a new message cannot be queued due to the message queue being full. The
FIFO will discard incoming messages until it has completely emptied the queue. Once emptied, an Error
Message will be queued. The error encoding will indicate which type(s) of messages attempted to be
queued while the FIFO was being emptied.
If only a Data Trace Message attempts to enter the queue while it is being emptied, the Error Message will
incorporate the Data Trace only error encoding (00010). If both OTM and Data Trace Messages attempt
to enter the queue, the Error Message will incorporate the OTM and Data Trace error encoding (00111). If
a Watchpoint also attempts to be queued while the FIFO is being emptied, then the Error Message will
incorporate error encoding (01000).
NOTE
The OVC bits within the DC Register can be set to delay the CPU by
asserting the FIFOFULL signal in order to alleviate (but not eliminate)
potential overruns.
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Error information is messaged out in the following format:
(5 bits)
(4 bits)
(6 bits)
Error Code (00010 / 00111 / 01000)
Src. Proc.
TCODE (001000)
Fixed length = 15 bits
Figure 11-41. Error Message Format
11.11.3.2.4 Data Trace Synchronization Messages
A Data Trace Write/Read with Sync. Message is messaged via the auxiliary port (provided Data Trace is
enabled) for the following conditions (see Table 11-40):
• Initial Data Trace Message upon exit from system reset or whenever Data Trace is enabled will be
a synchronization message.
• Upon returning from a Low Power state, the first Data Trace Message will be a synchronization
message.
• Upon returning from Debug Mode, the first Data Trace Message will be a synchronization
message.
• After occurrence of queue overrun (can be caused by any trace message), the first Data Trace
Message will be a synchronization message.
• After the periodic data trace counter has expired indicating 255 without-sync Data Trace Messages
have occurred since the last with-sync message occurred.
• Upon assertion of the Event In (EVTI) pin, the first Data Trace Message will be a synchronization
message if the EIC bits of the DC Register have enabled this feature.
• Upon Data Trace Write/Read after the previous DTM Message was lost due to an attempted access
to a secure memory location (for SoCs with security).
• Upon Data Trace Write/Read after the previous DTM Message was lost due to a collision entering
the FIFO between the DTM Message and two other higher priority messages.
Data Trace Synchronization Messages provide the full address (without leading zeros) and insure that
development tools fully synchronize with Data Trace regularly. Synchronization messages provide a
reference address for subsequent DTMs, in which only the unique portion of the Data Trace address is
transmitted. The format for Data Trace Write/Read with Sync. Messages is as follows:
(1–32 bits)
(1–32 bits)
(3 bits)
(4 bits)
(6 bits)
Data Value
Full Address
Data Size
Src. Proc.
TCODE (001101 or 001110)
Max length = 77 bits; Min length = 15 bits
Figure 11-42. Data Write/Read with Sync. Message Format
Exception conditions that result in Data Trace Synchronization are summarized in Table 11-40.
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Table 11-40. Data Trace Exception Summary
Exception Condition
Exception Handling
System Reset Negation
At the negation of JTAG reset (TRST), queue pointers, counters, state machines, and
registers within the A7S Nexus3 module are reset. If Data Trace is enabled, the first
Data Trace Message is a Data Write/Read w/ Sync. Message.
Data Trace Enabled
The first Data Trace Message (after Data Trace has been enabled) is a synchronization
message.
Exit from Low Power/Debug
Upon exit from a Low Power mode or Debug mode the next Data Trace Message will be
converted to a Data Write/Read with Sync. Message.
Queue Overrun
An Error Message occurs when a new message cannot be queued due to the message
queue being full. The FIFO will discard messages until it has completely emptied the
queue. Once emptied, an Error Message will be queued. The error encoding will
indicate which type(s) of messages attempted to be queued while the FIFO was being
emptied. The next DTM message in the queue will be a Data Write/Read w/ Sync.
Message.
Periodic Data Trace Synchronization
A forced synchronization occurs periodically after 255 Data Trace Messages have been
queued. A Data Write/Read w/ Sync. Message is queued. The periodic data trace
message counter then resets.
Event In
If the Nexus module is enabled, an EVTI assertion initiates a Data Trace Write/Read w/
Sync. Message upon the next data write/read (if Data Trace is enabled and the EIC bits
of the DC Register have enabled this feature).
Attempted Access to Secure Memory For SOCs that implement security, any attempted read or write to secure memory
locations will temporarily disable Data Trace & cause the corresponding DTM to be lost.
A subsequent read/write will queue a Data Trace Read/Write w/ Sync. Message.
Collision Priority
Messages have the following priority: Error, Ownership Trace, Watchpoint, Debug,
Program Correlation, Branch Trace, Data Trace. A Data Trace message which attempts
to enter the queue at the same time as two other higher priority messages will be lost.
11.11.3.3 DTM Operation
11.11.3.3.1 Enabling Data Trace Messaging
Data Trace Messaging can be enabled in one of two ways.
• Setting the TM field of the DC Register to enable Data Trace (DC[1]).
• Using the DTS field of the WT Register to enable Data Trace on Watchpoint hits (ARM7
watchpoints are configured within the CPU).
11.11.3.3.2 DTM Queueing
A7S Nexus3 implements a programmable depth queue (32 minimum entry recommended) for queuing all
messages. Messages that enter the queue are transmitted via the auxiliary pins in the order in which they
are queued.
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11.11.3.3.3 Relative Addressing
The relative address feature is compliant with the IEEE-ISTO 5001 standard recommendations, and is
designed to reduce the number of bits transmitted for addresses of Data Trace Messages. Refer to
Section 11.11.2.3.2, “Addressing,” for details.
11.11.3.3.4 Data Trace Windowing
Data Write/Read Messages are enabled via the RWT1(2) field in the Data Trace Control Register (DTC)
for each DTM channel. Data Trace windowing is achieved via the address range defined by the DTEA and
DTSA Registers and by the RC1(2) field in the DTC. All ARM7 initiated read/write accesses which fall
inside or outside these address ranges, as programmed, are candidates to be traced.
11.11.3.3.5 ARM7 Bus Cycle Cases
Table 11-41. ARM7 Bus Cycle Cases
Special Case
Action
ARM7 bus cycle aborted
Cycle ignored
ARM7 bus cycle completed without error
Cycle captured & transmitted
AHB bus cycle initiated by Nexus
Cycle ignored
ARM7 bus cycle is an instruction fetch
Cycle ignored
11.11.3.4 Data Trace Timing Diagrams (8 MDO / 2 MSEO configuration)
MCKO
MSEO_B[1:0]
11
MDO[7:0]
00
00
01
00
11
00000101
10101000
00010100
11101111
10111110
TCODE = 5
source processor = 0000
data size = 010 (halfword)
relative address = 8'ha5
write data = 16'hbeef
Figure 11-43. Data Trace – Data Write Message
MCKO
MSEO_B[1:0]
MDO[7:0]
11
00
01
00001110 11000000 01011001 11010001 00101000 00000000
11
01011100
TCODE = 14
source processor = 0000
data size = 000 (byte)
full access address = 32'h01468ace
write data = 8'h5c
Figure 11-44. Data Trace – Data Read w/ Sync Message
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MCKO
MSEO_B[1:0]
11
MDO[7:0]
00
11
xx
00001000
00001000
xxxxxxxx
TCODE = 8
source processor = 0000
error code = 2 (queue overrun, DTM only)
Figure 11-45. Error Message (Data Trace only encoded)
11.11.4 Watchpoint Units
The A7S Nexus3 module includes watchpoint units for watchpoint messaging and processor breakpoints.
Watchpoint messages can be generated by either using the Nexus internal watchpoints or by ARM7
watchpoints. The A7S Nexus3 module supports using the internal and external watchpoint sources for
triggering the start and stop of program and data trace messaging (see Section 11.10.3.8, “Watchpoint
Trigger (WT)”). The occurrence of any watchpoint can be programmed to assert the event out (EVTO) pin.
11.11.4.1 Watchpoint Generation
11.11.4.1.1 Internal Watchpoint Units 1 and 2
Watchpoint units 1 and 2 can be configured to assert based on an address compare, a data compare, or both
address and data compare. Address comparisons may be masked on a bitwise basis with the BWAM
registers. A zero bit programmed in the BWAM registers will result in the corresponding address bit being
ignored during the associated address comparisons.
Data value comparisons can be masked on a byte basis with the BWDM registers. The data value compare
registers (BWD1 and BWD2) are 32 bit registers. A zero bit programmed in the BWDM registers will
result in the corresponding byte being ignored during the associated data value comparison. Only active
byte lanes are compared. Inactive byte lanes are considered mismatching bytes unless they are masked by
the BWDM registers.
The following compare modes are supported:
1. When the BWO field within a BWC register is initialized to an address only compare, a core access
address that matches the associated BWA register will cause an internal watchpoint signal to be
generated.
2. When the BWO field within a BWC register is initialized to a data only compare, a core access data
value that matches on the associated BWD registers will cause an internal watchpoint to be
generated.
3. When the BWO field within a BWC register is initialized to both address and data compare, a core
access that matches both the associated BWA and BWD registers will cause an internal watchpoint
to be generated.
Table 11-42 provides some example configurations for internal watchpoints.
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Functional Description
Table 11-42. Internal Data Watchpoint Configuration Examples
Compare Operation
BWO
BWAM
BWDM
Single address only
010
FFFF FFFF
xxxx
BWA[31:0]
Address range only
010
FFFF FFF0
xxxx
BWA[31:4]
Signal address and word value
011
FFFF FFFF
1111
BWA[31:0] and BWD[31:0]
Word value only
001
xxxx xxxx
1111
BWD[31:0]
Signal address and byte value
011
FFFF FFFF
0001
BWA[31:0] and BWD[7:0]
0010
BWA[31:0] and BWD[15:8]
0100
BWA[31:0] and BWD[23:16]
1000
BWA[31:0] and BWD[31:24]
0011
BWA[31:0] and BWD[15:0]
1100
BWA[31:0] and BWD[31:24]
Single address and halfword value
011
FFFF FFFF
Compare Target
11.11.4.1.2 Internal Watchpoint Units 3 - 6
Watchpoint units 3 - 6 can be enabled to assert on an instruction address compare. The two least significant
bits of the address are automatically masked for word accesses (ARM mode) and the least significant bit
is masked for half word accesses (thumb mode).
11.11.4.1.3 ARM7 Watchpoints
The ARM7 EmbeddedICE module is capable of setting up to two (2) address and/or data watchpoints.
Please refer to the debug chapter of the ARM7TDMI-S (Rev 4) Technical Reference Manual
(ARM DDI 0234A) for details on watchpoint initialization.
11.11.4.2 Processor Breakpoints
The ARM watchpoint units and the Nexus watchpoint units 3 - 6 can be used to assert a processor
breakpoint. If the processor is configured for halt mode, the processor will enter into debug state before
executing the instruction at the specified address.
11.11.4.3 Watchpoint Messaging (WPM)
The A7S Nexus3 module provides watchpoint messaging using the IEEE-ISTO 5001 defined TCODE.
Enabling watchpoint messaging is done by setting the watchpoint enable (WEN) bit in the DC register.
11.11.4.3.1 Watchpoint Message
When watchpoint messaging is enabled, and any of the eight (8) possible watchpoint sources asserts, a
watchpoint message will be sent to the queue to be transmitted. The message indicates which
watchpoint(s) asserted based on the encodings in Table 11-43.
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Functional Description
(8 bits)
(4 bits)
(6 bits)
Watchpoint Source
Src. Proc.
TCODE (001111)
Fixed length = 18 bits
Figure 11-46. Watchpoint Message Format
Table 11-43. Watchpoint Source Description
Watchpoint Source (8-bits)
Watchpoint Description
xxxx xxx1
ARM7 Watchpoint 0
xxxx xx1x
ARM7 Watchpoint 1
xxxx x1xx
Nexus Watchpoint 1
xxxx 1xxx
Nexus Watchpoint 2
xxx1 xxxx
Nexus Watchpoint 3
xx1x xxxx
Nexus Watchpoint 4
x1xx xxxx
Nexus Watchpoint 5
1xxx xxxx
Nexus Watchpoint 6
11.11.4.4 Watchpoint Error Message
An Error Message occurs when a new message cannot be queued due to the message queue being full. The
FIFO will discard messages until it has completely emptied the queue. Once emptied, an Error Message
will be queued. The error encoding will indicate which type(s) of messages attempted to be queued while
the FIFO was being emptied.
If only a Watchpoint Message attempts to enter the queue while it is being emptied, the Error Message will
incorporate the Watchpoint only error encoding (00110). If an OTM and/or Program Trace Message also
attempts to enter the queue while it is being emptied, the Error Message will incorporate error encoding
(01000).
NOTE
The OVC bits within the DC Register can be set to delay the CPU by
asserting the FIFOFULL signal in order to alleviate (but not eliminate)
potential overruns.
Error information is messaged out in the following format (see Table 11-2):
(5 bits)
(4 bits)
(6 bits)
Error Code (00110 / 01000)
Src. Proc.
TCODE (001000)
Fixed length = 15 bits
Figure 11-47. Error Message Format
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Functional Description
11.11.4.5 Watchpoint Timing Diagram (2 MDO / 1 MSEO configuration)
Watchpoint
Error
MCKO
MSEO_B
MDO[1:0]
11
11
00
00
00
10
00
00
00
10
00
00
00
10
01
00
00
Error:
WPM:
TCODE = 15
TCODE = 8
source processor = 0000
source processor = 0000
watchpoint = 0010 (ARM 1) error code = 6 (queue overrun, WPM only)
Figure 11-48. Watchpoint Message & Watchpoint Error Message
11.11.5 Read/Write Access
The Read/Write access feature allows access to internal memory mapped resources via the JTAG port. The
Read/Write mechanism supports single as well as block reads and writes via an AHB system bus.
11.11.5.1 Functional Description
The Nexus3 module includes the capability of accessing resources on the AHB. All accesses are setup and
initiated by the Read/Write Access Control/Status Register (RWCS), as well as the Read/Write Access
Address (RWA) and Read/Write Access Data Registers (RWD).
11.11.5.2 Read/Write Access to Internal Nexus Registers
Access to Nexus register resources is enabled by loading a single instruction (“NEXUS-ACCESS”) into the
JTAG Instruction Register (IR). For the A7S Nexus3 block, the JTAG IR value is programmable at the
platform or SOC integration level. It can be programmed to any of the non-ARM7 implemented IR values
(see Table 11-35).
Table 11-44. JTAG Nexus3 Register Select
JTAG Instruction
JTAG Access Opcode
Read/Write
NEXUS-ACCESS
0xnn (hex) (programmable)
W
Once the JTAG “NEXUS-ACCESS” instruction has been loaded, the JTAG port allows communication
with all Nexus registers according to the map in Table 11-21.
Reading/writing of a Nexus register then requires two (2) passes through the Data-Scan (DR) path of the
JTAG state machine (see 11.12, “IEEE 1149.1 State Machine and RD/WR Sequences”).
1. The first pass through the DR selects the Nexus register to be accessed by providing an index (see
Table 11-21), and the direction (read/write). This is achieved by loading an 8-bit value into the
JTAG Data Register (DR). This register has the following format:
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Functional Description
Access: User read/write
7
6
5
4
3
2
1
0
R
NRI
R/W
W
Reset
0
0
0
0
0
0
0
0
Figure 11-49. JTAG Data Register (DR)
Table 11-45. JTAG Data Register Field Description
Field
Description
7–1
NRI
Nexus Register Index
nn
Selected from values in Table 11-21
0
R/W
R/W – Read Write
0 Read
1 Write
2. The second pass through the DR then shifts the data in or out of the JTAG port, LSB first.
a) During a read access, data is latched from the selected Nexus register when the JTAG state
machine (see 11.12, “IEEE 1149.1 State Machine and RD/WR Sequences”) passes through the
“Capture-DR” state.
b) During a write access, data is latched into the selected Nexus register when the JTAG state
machine (see 11.12, “IEEE 1149.1 State Machine and RD/WR Sequences”) passes through the
“Update-DR” state.
11.11.5.3 Memory Mapped Register Access via JTAG
Using the Read/Write Access Registers (RWCS/RWA/RWD), memory mapped AHB resources can be
accessed through Nexus. The following steps are required to access memory mapped resources:
NOTE
Read/Write Access can only access memory mapped resources when
system reset is negated.
11.11.5.3.1 Single Write Access
1. Initialize the Read/Write Access Address Register (RWA) through the JTAG access method
outlined in Section 11.11.5.2, “Read/Write Access to Internal Nexus Registers,” using the Nexus
Register Index of 0x9 (see Table 11-21). Configure as follows:
— Write Address → 32'hxxxxxxxx (write address)
2. Initialize the Read/Write Access Control/Status Register (RWCS) through the JTAG access
method outlined in Section 11.11.5.2, “Read/Write Access to Internal Nexus Registers,” using the
Nexus Register Index of 0x7 (see Table 11-21). Configure the bits as follows:
— Access Control (AC) → 1'b1 (to indicate start access)
— Map Select (MAP) → 3'b000 (primary memory map)
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Functional Description
—
—
—
—
Access Priority (PR) → 2'b00 (lowest priority)
Read/Write (RW) → 1'b1 (write access)
Word Size (SZ) → 3'b0xx (32-bit, 16-bit, 8-bit)
Access Count (CNT) → 14'h0000 or 14'h0001(single access)
NOTE
Access Count (CNT) of 14'h0000 or 14'h0001 will perform a single access.
3. Initialize the Read/Write Access Data Register (RWD) through the JTAG access method outlined
in Section 11.11.5.2, “Read/Write Access to Internal Nexus Registers,” using the Nexus Register
Index of 0xA (see Table 11-21). Configure as follows:
— Write Data → 32'hxxxxxxxx (write data)
4. The Nexus block will then arbitrate for the AHB and transfer the data value from the RWD Register
to the memory mapped address in the Read/Write Access Address Register (RWA).
When the access has completed without error (ERR=1'b0), the Nexus block asserts the RDY pin
(see Table 11-13 for detail on RDY) and clears the DV bit in the RWCS Register. This indicates
that the device is ready for the next access.
NOTE
Only the RDY pin as well as the DV and ERR bits within the RWCS provide
Read/Write Access status to the external development tool. The
development tool needs to provide at least one clock after entering the
Run-Test-Idle state to ensure that the RDY pin is asserted.
11.11.5.3.2 Block Write Access
1. For a block write access, follow Steps 1, 2, and 3 outlined in Section 11.11.5.3.1, “Single Write
Access,” to initialize the registers, using a value greater than one (14'h0001) for the CNT field in
the RWCS Register.
2. The Nexus block will then arbitrate for the AHB and transfer the first data value from the RWD
Register to the memory mapped address in the Read/Write Access Address Register (RWA).
When the transfer has completed without error (ERR=1'b0), the address from the RWA Register is
incremented to the next word size (specified in the SZ field) and the number from the CNT field is
decremented. The Nexus block will then assert the RDY pin. This indicates that the device is ready
for the next access.
NOTE
The actual RWA value as well as the CNT field within the RWCS are not
changed when executing a block write access. The original values can be
read by the external development tool at any time.
3. Repeat Step 3 in Section 11.11.5.3.1, “Single Write Access,” until the internal CNT value is zero
(0). When this occurs, the DV bit within the RWCS will be cleared to indicate the end of the block
write access.
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Functional Description
11.11.5.3.3 Single Read Access
1. Initialize the Read/Write Access Address Register (RWA) through the JTAG access method
outlined in Section 11.11.5.2, “Read/Write Access to Internal Nexus Registers,” using the Nexus
Register Index of 0x9 (see Table 11-21). Configure as follows:
— Read Address → 32'hxxxxxxxx (read address)
2. Initialize the Read/Write Access Control/Status Register (RWCS) through the JTAG access
method outlined in Section 11.11.5.2, “Read/Write Access to Internal Nexus Registers,” using the
Nexus Register Index of 0x7 (see Table 11-21). Configure the bits as follows:
— Access Control (AC) → 1'b1 (to indicate start access)
— Map Select (MAP) → 3'b000 (primary memory map)
— Access Priority (PR) → 2'b00 (lowest priority)
— Read/Write (RW) → 1'b0 (read access)
— Word Size (SZ) → 3'b0xx (32-bit, 16-bit, 8-bit)
— Access Count (CNT) → 14'h0000 or 14'h0001(single access)
NOTE
Access Count (CNT) of 14'h0000 or 14'h0001 will perform a single access.
3. The Nexus block will then arbitrate for the AHB and the read data will be transferred from the AHB
to the RWD Register.
When the transfer completed without error (ERR=1'b0), the Nexus block asserts the RDY pin (see
Table 11-13 for detail on RDY) and sets the DV bit in the RWCS Register. This indicates that the
device is ready for the next access.
4. The data can then be read from the Read/Write Access Data Register (RWD) through the JTAG
access method outlined in Section 11.11.5.2, “Read/Write Access to Internal Nexus Registers
using the Nexus Register Index of 0xA (see Table 11-21).
NOTE
Only the RDY pin as well as the DV and ERR bits within the RWCS provide
Read/Write Access status to the external development tool. The
development tool needs to provide at least one clock after entering the
Run-Test-Idle state to ensure that the RDY pin is asserted
11.11.5.3.4 Block Read Access
1. For a block read access, follow Steps 1 and 2 outlined in Section 11.11.5.3.3, “Single Read
Access,” to initialize the registers, using a value greater than one (14'h0001) for the CNT field in
the RWCS Register.
2. The Nexus block will then arbitrate for the AHB and the read data will be transferred from the AHB
to the RWD Register.
When the transfer has completed without error (ERR=1'b0), the address from the RWA Register is
incremented to the next word size (specified in the SZ field) and the number from the CNT field is
decremented. The Nexus block will then assert the RDY pin. This indicates that the device is ready
for the next access.
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Functional Description
NOTE
The actual RWA value as well as the CNT field within the RWCS are not
changed when executing a block read access. The original values can be
read by the external development tool at any time.
3. The data can then be read from the Read/Write Access Data Register (RWD) through the JTAG
access method outlined in Section 11.11.5.2, “Read/Write Access to Internal Nexus Registers,”
using the Nexus Register Index of 0xA (see Table 11-21).
4. Repeat Steps 3 and 4 in Section 11.11.5.3.3, “Single Read Access,” until the CNT value is zero (0).
When this occurs, the DV bit within the RWCS is set to indicate the end of the block read access.
11.11.5.4 Error Handling
The A7S Nexus3 module handles various error conditions as follows:
11.11.5.4.1 AHB Read/Write Error
All address and data errors that occur on read/write accesses to the AHB will return a transfer error
encoding on the HRESP[1:0] signals. If HRESP[1:0] = 2'b01:
1. The access is terminated without re-trying (AC bit is cleared)
2. The ERR bit in the RWCS Register is set
3. The Error Message is sent (TCODE = 8) indicating Read/Write Error
11.11.5.4.2 Access Termination
The following cases are defined for sequences of the Read/Write protocol that differ from those described
in the above sections.
1. If the AC bit in the RWCS Register is set to start Read/Write accesses and invalid values are loaded
into the RWD and/or RWA, then an AHB access error may occur. This is handled as described
above.
2. If a block access is in progress (all cycles not completed), and the RWCS Register is written, then
the original block access is terminated at the boundary of the nearest completed access.
a) If the RWCS is written with the AC bit set, the next Read/Write access will begin and the RWD
can be written to/ read from.
b) If the RWCS is written with the AC bit cleared, the Read/Write access is terminated at the
nearest completed access. This method can be used to break (early terminate) block accesses.
11.11.5.4.3 Read/Write Access Error Message
The Read/Write Access Error Message is sent out when an AHB access error (read or write) error has
occurred.
Error information is messaged out in the following format:
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Functional Description
(5 bits)
(4 bits)
(6 bits)
Error Code (00011)
Src. Proc.
TCODE (001000)
Fixed length = 15 bits
Figure 11-50. Error Message Format
11.11.5.5 Timing Diagram
CLK
HCLKEN
HCLK
AHB outputs (from Nexus)
AHB inputs (@ Nexus reg.)
Figure 11-51. A7S Nexus3 DMA clock relationships
The A7S Nexus3 Read/Write access timing meets the timing requirements for the AHB. The Nexus
module uses the processor clock gated with an AHB clock enable for all DMA transfers. This clock will
correspond to the rising edge of the actual AHB clock. The timing diagram in Figure 11-51 above shows
the relationship between the processor clock (CLK), the AHB clock (HCLK) and the AHB clock enable
(HCLKEN) for DMA writes and reads. Using this clocking method for Nexus read/write access eliminates
the need for a separate asynchronous clock input into the A7S Nexus3 module.
11.11.6 System Status
11.11.6.1 Debug Status Messages
Debug Status Messages report low power mode and debug status. Entering/exiting Debug Mode as well
as entering a Low Power Mode will trigger a Debug Status Message. Debug status information is sent out
in the following format:
(8 bits)
(4 bits)
(6 bits)
DS[31:24]
SRC
TCODE (000000)
Fixed length = 18 bits
Figure 11-52. Debug Status Message Format
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IEEE 1149.1 State Machine and RD/WR Sequences
11.12 IEEE 1149.1 State Machine and RD/WR Sequences
11.12.1 JTAG State Machine
TEST LOGIC
RESET
1
0
RUN-TEST/IDLE
1
1
SELECT-DR_SCAN
0
SELECT-IR_SCAN
0
1
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
1
SHIFT-IR
0
1
1
EXIT1-DR
0
PAUSE-DR
0
EXIT2-DR
1
EXIT1-IR
0
1
0
PAUSE-IR
0
1
0
EXIT2-IR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
0
Figure 11-53. JTAG State Machine
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IEEE 1149.1 State Machine and RD/WR Sequences
11.12.2 JTAG Sequence for Accessing Internal Nexus Registers
Table 11-46. JTAG Sequence for Accessing Internal Nexus Registers
Step #
TMS Pin
Description
1
1
IDLE → SELECT-DR_SCAN
2
0
SELECT-DR_SCAN → CAPTURE-DR (Nexus Command Register value loaded in shifter)
3
0
CAPTURE-DR → SHIFT-DR
4
0
(7) TCK clocks issued to shift in direction (rd/wr) bit and first 6 bits of Nexus reg. addr.
5
1
SHIFT-DR → EXIT1-DR (7th bit of Nexus reg. shifted in)
6
1
EXIT1-DR → UPDATE-DR (Nexus shifter is transferred to Nexus Command Register)
7
1
UPDATE-DR → SELECT-DR_SCAN
8
0
SELECT-DR_SCAN → CAPTURE-DR (Register value is transferred to Nexus shifter)
9
0
CAPTURE-DR → SHIFT-DR
10
0
(31) TCK clocks issued to transfer register value to TDO pin while shifting in TDI value
11
1
SHIFT-DR → EXIT1-DR (MSB of value is shifted in/out of shifter)
12
1
EXIT1-DR → UPDATE-DR (if access is write, shifter is transferred to register)
13
0
UPDATE-DR → RUN-TEST/IDLE (transfer complete, Nexus controller to Reg. Select state)
11.12.3 JTAG Sequence for Read Access of Memory-Mapped Resources
Table 11-47. JTAG Sequence for Read Access of Memory-Mapped Resources
Description
Step #
TCLK clocks
1
13
Nexus Command = write to Read/Write Access Address Register (RWA)
2
37
Write RWA (initialize starting read address, data input on TDI)
3
13
Nexus Command = write to Read/Write Control/Status Register (RWCS)
4
37
Write RWCS (initialize read access mode and CNT value, data input on TDI)
5
—
Wait for falling edge of RDY pin
6
13
Nexus Command = read Read/Write Access Data Register (RWD)
7
37
Read RWD (data output on TDO)
8
—
If CNT > 0, go back to Step #6
11.12.4 JTAG Sequence for Write Access of Memory-Mapped Resources
Table 11-48. JTAG Sequence for Write Access of Memory-Mapped Resources
Step #
TCLK clocks
Description
1
13
Nexus Command = write to Read/Write Address Register (RWA)
2
37
Write RWA (initialize starting write address, data input on TDI)
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IEEE 1149.1 State Machine and RD/WR Sequences
Table 11-48. JTAG Sequence for Write Access of Memory-Mapped Resources (Continued)
Step #
TCLK clocks
Description
3
13
Nexus Command = write to Read/Write Access Control/Status Register
4
37
Write RWCS (initialize write access mode and CNT value, data input on TDI)
5
13
Nexus Command = read Read/Write Access Data Register (RWD)
6
37
Write RWD (data output on TDO)
7
—
Wait for falling edge of RDY pin
8
—
If CNT > 0, go back to Step #5
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Chapter 12
Enhanced DMA Controller (eDMA) Module
12.1
Overview of the MAC7200 Implementation
The MAC7200 family of devices implements a Direct Memory Access controller called the Enhanced
Direct Memory Access controller (eDMA). This module is implemented on other Freescale devices such
as those in the PPC5500 family. It enables transfer of data between the memory, peripherals and off-chip
devices with little intervention from the core, thus helping to increase system performance as well as
assisting with the simplification of software development.
12.1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
eDMA Features
DMA transfers possible between system memories, SPIs, SCIs, I2C, ATD, eMIOS and General
Purpose I/Os
Programmable DMA Channel Mux allows assignment of any DMA source to any of the 16
available DMA channels.
All DMA transfers use dual address format.
Programmable Transfer Control Descriptor stored in local DMA memory.
Programmable Source and Destination address with configurable offset.
Independent 32-bit Minor and 16-bit Major loop counters for ’nested’ transfers.
Different final Source and Destination addresses allow circular Queue operation.
Programmable priority levels for each channel.
Bandwidth control for each channel.
Programmable transfer sizes through Major and Minor loop counters.
Independently Programmable read/write sizes.
Periodic triggering of up to 8 channels.
Round Robin channel prioritization
Scatter-Gather functionality
Inner Loop channel pre-emption
Channel to Channel linking
Software or Hardware start
Memory Map: 32-bit byte/half-word/word addressable peripheral
NOTE
The transfer type of all transfers done by the DMA is as follows:
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Overview of the MAC7200 Implementation
•
•
•
•
12.1.2
Supervisor Mode
Data
Non-Cacheable
Bufferable/Non-Bufferable is software programmable in the DMA
eDMA Implementation
The eDMA has been developed to enable it to be instantiated over a range of devices with different feature
requirements. This allows the module to be reused both within families of devices and across wide product
ranges. The implementation of the DMA controller on the MAC7200 family has been targeted towards
cost sensitive applications while still maintaining a high level of functionality.
The MAC7200 family of devices has 16 independently programmable DMA channels available for use on
the MCU. The eDMA enables the definition of transfers from memory to memory, peripherals to/from
memory, and from peripheral to peripheral. The following shows all possible DMA transfer sources.
Table 12-1. DMA Channel Sources
Type
Source/Destination
DMA
Requests
Comments
Memory
System RAM
-
Transfer between on-chip memories
Program Flash
-
Shadow Block
-
ESCI_A, ESCI_B
4
Two requests per ESCI
(one for Tx, one for Rx)
DSPI_A, DSPI_B,
DSPI_C
6
Two requests per DSPI
(one for Tx, one for Rx)
I2C
2
Two requests
(one for Tx, one for Rx)
ATD_A
2
Two requests
(one for Command, one for Result)
eMIOS
8
One request available for each timer channel
External
External Bus
-
External (PIM)
Port A, B, C, D, E, F, G
7
Not all Ports are available on all devices.
Typically used with an “Always Enabled” source
Triggered
Any of the above
Sources/Destinations
8
Each request trigger can be assigned to a PIT
channel or may be left "always enabled"
(i.e.-continuous DMA requests)
Peripherals
As there are greater than 16 possible sources for the DMA controller, a channel mux is used to enable the
user to define which of the sources are used, and on which channels they are assigned. Refer to Chapter 27,
“Enhanced Direct Memory Access (DMA Channel MUX)” for further details.
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12.1.3
eDMA External Pins
There are no eDMA signals that drive or are driven from MCU pins.
12.1.4
eDMA Bus Aborts
The DMA2 supports bus aborts on the Peripheral Bus, enforcing the following memory map:
Table 12-2. eDMA Bus Abort Memory Map
Abort
Allowed
$0000-$0007
$0008-$000d
$000e-$000f
$0010-$0015
$0016-$001f
$0020-$0025
$0026-$0027
$0028-$002d
$002e-$002f
$0030-$00fc
$00fd-$010f
$0110-$0fff
$1000-$11ff
$1200-$3fff
If any part of a read or write falls within an aborted region, the entire transfer is aborted. For example, a
32-bit read or write to address $000c would be aborted.
Supervisor Access: Unused
12.1.5
•
eDMA Differences from MAC71xx
The debug functionality of the DMA is now enabled
12.1.6
eDMA Application Usage
NOTE
The DMA Block Guide is generic, and refers to configurations of the DMA
with up to 64 channels. The DMA on the MAC72xx is 16 channels, and you
must therefore take this into consideration when writing code to access
DMA configuration registers and (particularly) TCDs. READs to
unmapped registers will return zeros, WRITEs will be ignored.
12.1.6.1
Enabling the DMA
It is not necessary to enable the DMA before it can be used. However, the DMA Channel Mux must be
configured before any DMA transfers can occur.
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12.1.6.2
General Operation of the DMA
1. The channel is initialized by software loading the transfer control descriptor into the DMA2’s
programming model, memory-mapped through the IPS space, and implemented as local memory.
2. The channel is activated, either explicitly by software, a peripheral request or a linkage from
another channel.
3. The contents of the transfer control descriptor for the activated channel is read from the local
memory and loaded into the dma2_engine’s registers.
4. The dma2_engine executes the data transfer defined by the inner minor loop, reading from the
source and writing to the destination.
5. At the conclusion of the minor loop’s execution, certain fields of the transfer control descriptor are
restored from the local memory.
The entire process (steps 1-5) is repeated until the outer major loop’s iteration count is exhausted. At that
time, additional processing steps are completed, e.g., the optional assertion of an interrupt request
signaling the transfer’s completion, final adjustments to the source and destination addresses, etc.
12.1.6.3
Configuring the DMA
Configuration of the DMA is divided into four areas:
— Configuring the arbitration and system loading
— Error signalling
— DEBUG mode behavior
— Transfer Control Descriptor (TCD)
— Channel completion
— Choosing a channel activation method for each channel
12.1.6.3.1
Arbitration and System Loading
There are four arbitration schemes available, all of which can be configured by using the DMACR register.
1. Choose a channel priority scheme that fits your application:
— Fixed-priority with Channel 0 preemption. To use this scheme, write EFPRI=1, ECH0P=1.
— Fixed-priority with high priority Channel 0. To use this scheme, write EFPRI=1, ECH0P=0.
— Round-robin with Channel 0 preemption. To use this scheme, write EFPRI=0, ECH0P=1.
— Round-robin with high priority Channel 0. To use this scheme, write EFPRI=0, ECH0P=0.
2. If a fixed-priority scheme is chosen, choose the priority for each channel by writing the DCHPRIn
registers.
3. For each channel, choose the relative priority of the DMA transfers over bus accesses from the
ARM7 core and/or debugger. Write the ‘bwc[1:0]’ field in Word 7 of the channel’s TCD (Transfer
Control Descriptor). This field controls how much bandwidth the DMA consumes for each access
in a minor loop. In this manner, it is possible to specify highest priority (bwc[1:0]=00) to lowest
priority (bwc[1:0]=11)
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12.1.6.3.2
Error Signalling
The DMA module has the capability to report three types of errors, with each error detected and reported
on a channel-by-channel basis:
— Source bus error
— Destination bus error
— Configuration error
You must choose whether to implement error handling in an interrupt driven or polling method. For
interrupt driven error handling, perform the following steps:
1. For each channel desired, set the corresponding bit in the DMAEEIL register. Alternatively,
individual channels may also be configured by writing the corresponding DMASEEI or
DMACEEI registers to respectively set or clear a DMAEEIL bit. To enable interrupt driven error
handling for all channels, simply write $FF to the DMASEEI register.
2. When an interrupt occurs (Interrupt #0), read the DMAERRL register to determine all current
pending errors. Note that a channel may have an error pending even though its corresponding
Enable Error Interrupt (DMAEEIL) register bit was cleared. Also note that multiple channels may
have pending errors at the same time.
3. Detailed information about the last recorded channel error can be obtained by reading the DMAES
register.
4. Once all errors have been detected (i.e.-Step #2), clear the errors by clearing the corresponding bits
in the DMAERRL register. To clear individual bits, you may also write to the DMACERR register.
If you want to clear all pending errors, simple write $FF to the DMACERR register.
To handles error in a polled fashion, following these steps:
1. For each channel desired, clear the corresponding bit in the DMAEEIL register. Alternatively,
individual channels may also be configured by writing the corresponding DMASEEI or
DMACEEI registers to respectively set or clear a DMAEEIL bit.
2. When desired, read the DMAERRL register to determine all current pending errors. Note that
multiple channels may have pending errors at the same time.
3. Detailed information about the last recorded channel error can be obtained by reading the DMAES
register.
4. Once all errors have been detected (i.e.-Step #2), clear the errors by clearing the corresponding bits
in the DMAERRL register. To clear individual bits, you may also write to the DMACERR register.
If you want to clear all pending errors, simple write $FF to the DMACERR register.
NOTE
As evident from the above steps, it would be very difficult to use polling
driven error handling with peripheral paced channel activation (See below).
For this reason, it is recommended to use interrupt driven error handling in
most cases, and especially when not using explicit software activation of
channels.
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12.1.6.3.3
DEBUG Mode Behavior
In any real-time system, the debugging of code affected by real-time external events can often be very
difficult. For this reason, flexibility in the ability to selectively enable/disable certain kinds of events when
the system is in DEBUG mode is provided. In the DMA, the user has the flexibility to configure the
execution of the major loop counter in the current active channel in DEBUG mode. If desired, the EDBG
bit in the DMACR register can be set in order to stop the operation of a channel.
12.1.6.3.4
Transfer Control Descriptor (TCD)
Each channel has a corresponding TCD, which must be configured to specify the source and destination
information, as well as the minor and major loop counter information. Please refer to the DMA2 Block
Guide for detailed information on TCDs.
12.1.6.3.5
Channel Completion
The completion of a channel (i.e.-completion of the major loop counter) can be either interrupt driven or
polling driven, similar to the error signalling. If interrupt driven channel completion is desired, follow
these steps:
1. Enable interrupt on major loop counter completion by setting the ‘int_maj’ bit in Word 7 of the
channel’s TCD.
2. Once the interrupt is received (Interrupt #1-#16), clear the interrupt by clearing the corresponding
bit in the DMAINTL register. Individual bits can be easily cleared by writing to the DMACINT
register. To clear all pending DMA interrupts, simply write $FF to the DMACINT register. Note
that it is unnecessary to read the DMAINTL register before clearing it, as each DMA Channel on
the MAC72xx has a dedicated interrupt. The exact channel that caused the interrupt can be
determined solely by the Interrupt Vector number in the Interrupt Controller.
3. Besides producing an interrupt at the completion of a channel, the DMA is also capable of causing
an interrupt when the major loop counter is half completed. This feature can be activated by setting
the ‘int_half’ bit in Word 7 of the channel’s TCD. Note that in this case it is impossible to determine
whether an interrupt is signalling the completion of a channel or only the halfway completion of a
channel. The Interrupt Service Routine (ISR) that handles DMA channel interrupts must explicitly
keep track of this by itself.
To implement polling driven channel completion, following these steps:
1. Disable interrupt on major loop counter completion by clearing the ‘int_maj’ bit in Word 7 of the
channel’s TCD.
2. Determine the completion of a channel by continuously reading Word 7 of the channel’s TCD.
When the ‘done’ bit is set, the channel has completed.
12.1.6.3.6
Channel Activation Method
Each DMA Channel may be configured to use one of three channel activation methods available:
— Explicit software activation. This method allows the channel to be started explicitly by the
software at any time.
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— Initiation via a channel-to-channel linking mechanism for continuous transfers. This method
allows a channel to be started once another channel has completed.
— Peripheral-paced hardware requests. The method allows the channel activation to be controlled
by the peripheral itself.
Note than in all three methods, one activation per execution of the minor loop is required.
If explicit software activation is chosen for a channel, perform the following series of steps:
1. Configure the channel’s TCD with the correct source and destination information.
2. Write the ‘start’ bit in Word 7 of the channel’s TCD to activate the channel and start transfers.
If channel-to-channel linking is chosen for a channel, perform the following series of steps:
1. Configure the channel’s TCD with the correct source and destination information, ensuring that the
‘start’ bit in Word 7 is cleared.
2. Set the ‘e_link’ bit in Word 7 of the channel’s TCD.
3. Program the ‘linkch[5:0]’ bits in Word 7 of the channel’s TCD.
If peripheral paced hardware activation is chosen for a channel, perform the following series of steps:
1. Ensure that the DMA channel you want to use is disabled by clearing the corresponding bit in the
DMAERL register.
2. Configure the channel’s TCD with the correct source and destination information, ensuring that the
‘start’ bit in Word 7 is cleared.
3. Configure the DMA Channel Mux. For basic operation (no triggering), you can write the
CONFIGn register in the DMA Channel Mux with $80 | <Channel Source>.
4. Set the corresponding DMAERL register bit. If the ’d_req’ bit in the TCD is set, then the bit in the
DMAERL register will be automatically cleared after completion of the major loop. This
guarantees that the channel will not be re-activated after completion without explicit software
intervention.
5. Configure the peripheral to enable DMA transfers. Please refer to the documentation for the
particular peripheral for more details.
12.1.6.4
Using the DMA
Accessing multiple registers
Use the scatter-gather feature of the eDMA to construct more complex sets of transactions in order to (for
example) access peripherals with separate control and data transmit/receive registers. Assuming channel
1 is used, the following sequence illustrates this:
1. Peripheral requests a DMA transfer (also applies to software and triggered requests)
2. TCD1a transfers data to the peripheral’s control register
3. TCD1a executes a scatter-gather operation, and reloads its TCD descriptor with TCD1b
4. TCD1b has the TCD.start bit already set in the descriptor
5. The transfer request is automatically issued once TCD1b is loaded
6. TCD1b transfers data to the peripheral’s data register (as many loops as required)
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7. TCD1b executes a scatter-gather operation, and reloads its TCD descriptor with TCD1a
8. TCD1a has the TCD.start bit cleared in the descriptor
Once the peripheral requests another transfer, the series of steps repeats.
Basically, the TCDs ping-pong between each other, with the throttling of block/frame transfers done by
the peripheral (hardware request) or by software (software request).
Table 12-3. DMA Register Summary
DMA Register
Register “Mirrors”
Purpose
DMACR
--
DMA Control Register
DMAES
--
DMA Error Status
DMAERQH/L
DMASERQ
DMACERQ
DMA Enable Request
DMAEEIH/L
DMASEEI
DMACEEI
DMA Enable Error Interrupt
DMAINTH/L
DMACINT
DMA Interrupt Request
DMAERRH/L
DMACERR
DMA Error
DCHPRIn
--
DMA Channel n Priority
TCDnn
--
Transfer Control Descriptor nn
12.1.6.5
TCD Memory Initialization
As the TCD Memory does not have ECC, there is no requirement to initialize the memory in a specific
manner.
12.2
The SPP DMA Controller Module (SPP_DMA2)
This section provides a more detailed description of the generice SPP DMA Controller Module.
The DMA (Direct Memory Access) is a second-generation platform module capable of performing
complex data transfers with minimal intervention from a host processor via “n” programmable channels.
Intended for use as part of the Standard Product Platform (SPP), the hardware microarchitecture includes
a dma_engine which performs source and destination address calculations, and the actual data movement
operations, along with a local memory containing the transfer control descriptors (TCD) for the channels.
This SRAM-based implementation is utilized to minimize the overall module size.
Figure 12-1 is a block diagram of the DMA module.
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DMA
addr
wdata[31:0]
0
j
j+1
SRAM
Transfer
Control
Descriptor (TCD)
n-1
64
dma_engine
pmodel_charb
hrdata[{63,31}:0]
rdata[31:0]
addr_path
data_path
c
o
n
t
r
o
l
IPS
Bus
hwdata[{63,31}:0]
haddr[31:0]
AMBA
AHB
Bus
ipd_req[n-1:0]
dma_ipi_int[n-1:0]
dma_ipd_done[n-1:0]
Figure 12-1. DMA Block Diagram
12.2.1
Overview
The DMA is a highly-programmable data transfer engine, which has been optimized to minimize the
required intervention from the host processor. It is intended for use in applications where the data size to
be transferred is statically known, and is not defined within the data packet itself. The DMA hardware
supports:
• Single design supporting 16-, 32- and 64-channel implementations, dependent on size of the TCD
memory and design parameters (the MAC72xx family of devices has 16 channels)
• Connections to the AMBA-AHB crossbar switch for bus mastering the data movement, IPS slave
bus for programming the module
— Parameterized support for 32- and 64-bit AMBA-AHB data path widths
• 32-byte transfer control descriptor per channel stored in local memory
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•
32 bytes of data registers, used as temporary storage to support burst transfers
Throughout this document, n is used to reference the channel number. Additionally, data sizes are defined
as byte (8-bit), halfword (16-bit), word (32-bit) and doubleword (64-bit).
12.2.2
Features
The DMA module supports the following features:
• All data movement via dual-address transfers: read from source, write to destination
— Programmable source, destination addresses, transfer size, plus support for enhanced
addressing modes
• Transfer control descriptor organized to support two-deep, nested transfer operations
— An inner data transfer loop defined by a “minor” byte transfer count
— An outer data transfer loop defined by a “major” iteration count
• Channel service request via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
— Independent channel linking at end of minor loop and/or major loop
— Peripheral-paced hardware requests (one per channel)
— For all three methods, one service request per execution of the minor loop is required
• Support for fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
— One interrupt per channel, optionally asserted at completion of major iteration count
— Error terminations are optionally enabled per channel, and logically summed together to form
a small number of error interrupt outputs
• Optional support for scatter/gather DMAprocessing
The structure of the transfer control descriptor is fundamental to the operation of the DMA module. It is
defined below in a ‘C‘ pseudo-code specification:
NOTE
To compile these structures, change any periods ’.’ in the variable name to
underscores ’_’.
typedef union {
struct {
unsigned short citer.linkch:6;
unsigned short citer:9;
} minor_link_enabled;
struct {
unsigned short citer:15;
} minor_link_disabled;
} t_minor_link_citer;
typedef union {
struct {
/*
/*
/*
/*
/*
/*
/*
citer.e_link = 1 */
link channel number, */
current (“major”) iteration count */
channel link at end of the minor loop */
citer.e_link = 0 */
current (“major”) iteration count */
no linking at end of the minor loop */
/* biter.e_link = 1 */
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unsigned short biter.linkch:6;
unsigned short biter:9;
} init_minor_link_enabled;
struct {
unsigned short biter:15;
} init_minor_link_disabled;
} t_minor_link_biter;
typedef struct {
unsigned intsaddr;
unsigned intsmod:5;
unsigned intssize:3;
unsigned intdmod:5;
unsigned intdsize:3;
short
soff;
unsigned intnbytes;
int
slast;
unsigned intdaddr;
unsigned shortciter.e_link:1;
t_minor_link_citerminor_link_citer;
short
doff;
int
dlast_sga;
unsigned shortbiter.e_link:1;
t_minor_link_biterminor_link_biter;
unsigned intbwc:2;
unsigned intmajor.linkch:6;
unsigned intdone:1;
unsigned intactive:1;
unsigned intmajor.e_link:1;
unsigned inte_sg:1;
unsigned intd_req:1;
unsigned intint_half:1;
unsigned intint_maj:1;
unsigned intstart:1;
} tcd
/*
/*
/*
/*
/*
/*
link channel number, */
beginning (“major”) iteration count */
channel link at end of the minor loop */
biter.e_link = 0 */
beginning (“major”) iteration count */
no linking at end of the minor loop */
/* source address */
/* source address modulo */
/* source transfer size */
/* destination address modulo */
/* destination transfer size */
/* signed source address offset */
/* inner (“minor”) byte count */
/* last source address adjustment */
/* destination address */
/* enable channel linking on minor loop */
/* conditional current iteration count */
/* signed destination address offset */
/* last destination address adjustment, or
scatter/gather address (if e_sg = 1) */
/* beginning channel link enable */
/* beginning (“major”) iteration count */
/* bandwidth control */
/* link channel number */
/* channel done */
/* channel executing */
/* enable channel linking on major loop*/
/* enable scatter/gather descriptor */
/* disable ipd_req when done */
/* interrupt on citer = (biter >> 1) */
/* interrupt on major loop completion */
/* explicit channel start */
/* transfer_control_descriptor */
where int refers to a 32-bit variable (unless noted otherwise) and short is a 16-bit variable. The basic
operation of a channel is defined as:
1. The channel is initialized by software loading the transfer control descriptor into the DMA’s
programming model, memory-mapped through the IPS space, and implemented as local memory.
2. The channel requests service; either explicitly by software, a peripheral request or a linkage from
another channel.
Note: The major loop executes one iteration per service request.
3. The contents of the transfer control descriptor for the activated channel is read from the local
memory and loaded into the dma_engine’s registers.
4. The dma_engine executes the data transfer defined by the transfer control descriptor, reading from
the source and writing to the destination. The number of iterations in the minor loop is
automatically calculated by the dma_engine. The number of iterations within the minor loop is a
function of the number of bytes to transfer (nbytes), the source size (ssize) and the destination size
(dsize). The completion of the minor loop is equal to one iteration of the major loop.
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5. At the conclusion of the minor loop’s execution, certain fields of the transfer control descriptor are
written back to the local TCD memory.
The process (steps 2-5) is repeated until the outer major loop’s iteration count is exhausted. At that time,
additional processing steps are completed, e.g., the optional assertion of an interrupt request signaling the
transfer’s completion, final adjustments to the source and destination addresses, etc. A more detailed
description of the channel processing is listed in the pseudo-code below. This simplified example is
intended to represent basic data transfers. Detailed processing associated with the error handling is
omitted.
/* the given DMAchannel is requesting service by the software assertion of the
tcd[channel].start bit, the assertion of an enabled ipd_req from a device, or
the implicit assertion of a channel-to-channel link */
/* begin by reading the transfer control descriptor from the local RAM
into the local dma_engine registers */
dma_engine
= read_from_local_memory [channel];
dma_engine.active = 1;
/* set active flag */
dma_engine.done
= 0;
/* clear done flag */
/* check the transfer control descriptor for consistency */
if (dma_engine.config_error == 0) {
/ * begin execution of the inner “minor” loop transfers */
{
/* convert the source transfer size into a byte count */
switch (dma_engine.ssize) {
case 0:
/* 8-bit transfer */
src_xfr_size = 1;
break;
case 1:
/* 16-bit transfer */
src_xfr_size = 2;
break;
case 2:
/* 32-bit transfer */
src_xfr_size = 4;
break;
case 3:
/* 64-bit transfer */
src_xfr_size = 8;
break;
case 4:
/* 16-byte burst transfer */
src_xfr_size = 16;
break;
case 5:
/* 32-byte burst transfer */
src_xfr_size = 32;
break;
}
/* convert the destination transfer size into a byte count */
switch (dma_engine.dsize) {
case 0:
/* 8-bit transfer */
dest_xfr_size = 1;
break;
case 1:
/* 16-bit transfer */
dest_xfr_size = 2;
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break;
case 2:
dest_xfr_size
break;
case 3:
dest_xfr_size
break;
case 4:
dest_xfr_size
break;
case 5:
dest_xfr_size
break;
}
/* 32-bit transfer */
= 4;
/* 64-bit transfer */
= 8;
/* 16-byte burst transfer */
= 16;
/* 32-byte burst transfer */
= 32;
/*
/*
/*
if
determine the larger of the two transfer sizes, this value reflects */
the number of bytes transferred per read->write sequence. */
number of iterations of the minor loop = nbytes / xfer_size */
(dma_engine.ssize < dma_engine.dsize)
xfr_size = dest_xfer_size;
else
xfr_size = src_xfer_size;
/* process the source address, READ data into the buffer*/
/* read “xfr_size” bytes from the source */
/* if the ssize < dsize, do multiple reads to equal the dsize */
/* if the ssize => dsize, do a single read of source data */
number_of_source_reads = xfer_size / src_xfer_size;
for (number_of_source_reads) {
dma_engine.data = read_from_amba-ahb (dma_engine.saddr, src_xfr_size);
/* generate the next-state source address */
/* sum the current saddr with the signed source offset */
ns_addr = dma_engine.saddr + (int) dma_engine.soff; }
/* if enabled, apply the power-of-2 modulo to the next-state addr */
if (dma_engine.smod != 0)
address_select = (1 << dma_engine.smod) - 1; }
else
address_select = 0xffff_ffff;
dma_engine.saddr = ns_addr
&
address_select
| dma_engine.saddr & ~address_select; }
}
/* process the destination address, WRITE data from buffer */
/* write “xfr_size” bytes to the destination */
/* if the dsize < ssize, do multiple writes to equal the ssize */
/* if the dsize => ssize, do a single write of dest data */
number_of_dest_writes = xfer_size / dest_xfer_size;
for (number_of_dest_writes) {
write_to_amba-ahb (dma_engine.daddr, dest_xfr_size) = dma_engine.data;
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/* generate the next-state destination address */
/* sum the current daddr with the signed destination offset */
ns_addr = dma_engine.daddr + (int) dma_engine.doff;
/* if enabled, apply the power-of-2 modulo to the next-state dest addr */
if (dma_engine.dmod != 0)
address_select = (1 << dma_engine.dmod) - 1;
else
address_select = 0xffff_ffff;
dma_engine.daddr = ns_addr
&
address_select
| dma_engine.daddr & ~address_select;
}
/*
/*
/*
/*
/*
if
check for a higher priority channel to service if: */
1) preemption is enabled */
2) in fixed arbitration mode */
3) a higher priority channel is requesting service */
4) not already servicing a preempting channel */
((DCHPRIn.ecp = 1) & fixed_arbitration_mode
higher_pri_request & ~current_channel_is_preempt)
service_preempt_channel;
/* the bandwidth control field determines when the next read/write occurs */
if (dma_engine.bwc > 1)
stall_dma_engine (1 << dma_engine.bwc);
/* decrement the minor loop byte count */
dma_engine.nbytes = dma_engine.nbytes - xfr_size;
}while (dma_engine.nbytes > 0) /* end of minor inner loop */
dma_engine.citer--;
/* decrement major loop iteration count */
/* if the major loop is not yet exhausted, update certain TCD values in the RAM */
if (dma_engine.citer != 0) {
write_to_local_memory [channel].saddr = dma_engine.saddr;
write_to_local_memory [channel].daddr = dma_engine.daddr;
write_to_local_memory [channel].citer = dma_engine.citer;
/* if minor loop linking is enabled, make the channel link */
if (dma_engine.citer.e_link)
TCD[citer.linkch].start = 1;
/* specified channel service req */
/* check for interrupt assertion if half of the major iterations are done */
if (dma_engine.int_half && (dma_engine.citer == (dma_engine.biter >> 1)))
generate_interrupt (channel);
dma_engine.active = 0;
/* clear the channel busy flag */
}
else { /* major loop is complete, dma_engine.citer == 0 */
/* since the major loop is complete, perform the final address adjustments */
/* sum the current {src,dst} addresses with “last” adjustment */
write_to_local_memory [channel].saddr = dma_engine.saddr + dma_engine.slast;
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write_to_local_memory [channel].daddr = dma_engine.daddr + dma_engine.dlast;
/* restore the major iteration count to the beginning value */
write_to_local_memory [channel].citer = dma_engine.biter;
/* check for interrupt assertion at completion of the major iteration */
if (dma_engine.int_maj)
generate_interrupt (channel);
/* check if the ipd_req is to be disabled at completion of the major iteration */
if (dma_engine.d_req)
DMAERQ [channel] = 0;
/* check for a scatter/gather transfer control descriptor */
if (dma_engine.e_sg) {
/* load new transfer control descriptor from the address defined by dlast_sga */
write_to_local_memory [channel] =
read_from_amba-ahb(dma_engine.dlast_sga,32);
}
if (dma_engine.major.e_link)
TCD[major.linkch].start = 1;
/* specified channel service req */
dma_engine.active = 0;
dma_engine.done = 1;
/* clear the channel busy flag */
/* set the channel done flag */
}
else { /* configuration error detected, abort the channel */
dma_engine.error_status = error_type; /* record the error */
dma_engine.active = 0;
/* clear the channel busy flag */
/* check for interrupt assertion on error */
if (dma_engine.int_err)
generate_interrupt (channel);
}
For more details, consult Section 12.2.4.1, “Register Descriptions.”
12.2.3
External Signal Description
As shown in Figure 12-1, the DMA’s primary platform interfaces are the AMBA-AHB 2.v6 master bus
and the IPS slave bus. The AHB 2.v6 nomenclature refers to the AMBA-AHB 2.0 AHB-Lite protocol,
with AMBA V6 extensions for exclusive access support and extended cache control attributes.
Additionally, the DMA inputs request signals (one per channel) from the peripherals and outputs interrupt
signals (one per channel plus error indicators) to the platform’s interrupt controller. It also interfaces to the
off-platform local memory array. The memory BIST (MBIST) controller is a separate module since test
requirements for the RAM may vary by process technology.
12.2.4
Memory Map/Register Definition
The DMA’s programming model is partitioned into two sections, both mapped into the IPS space: the first
region defines a number of registers providing control functions, while the second region corresponds to
the local transfer control descriptor memory. Reading an unimplemented register bit or memory location
will return the value of zero. Writes to an unimplemented register bit or memory location will be ignored.
Any access to a reserved memory location will result in a bus error.
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The SPP DMA Controller Module (SPP_DMA2)
Many of the control registers have a bit width that matches the number of channels implemented in the
module, i.e., 16-, 32- or 64-bits in size. Registers associated with a 64-channel design are implemented as
two 32-bit registers, and include an “H” and “L” suffixes, signaling the “high” and “low” portions of the
control function. The descriptions in this section define the 64-channel implementation. For 16- or
32-channel designs, the unused bits are not implemented: reads return zeroes, and writes are ignored.
The DMA module does not include any logic which provides access control. Rather, this function is
supported using the standard access control logic provided by the AIPS controller.
Table 12-4 is a 32-bit view of the DMA’s memory map. Areas not applicable to the MAC72xx family,
which has 16 channels, have been grayed out in theis table.
Table 12-4. DMA 32-bit Memory Map
DMA Offset
Register
0x0000
DMA Control Register (DMACR)
0x0004
DMA Error Status (DMAES)
0x0008
DMA Enable Request High (DMAERQH, Channels 63-32)
0x000c
DMA Enable Request Low (DMAERQL, Channels 31-00)
0x0010
DMA Enable Error Interrupt High (DMAEEIH, Channels 63-32)
0x0014
DMA Enable Error Interrupt Low (DMAEEIL, Channels 31-00)
0x0018
DMA Set Enable
Request
(DMASERQ)
DMA Clear Enable
Request
(DMACERQ)
DMA Set Enable
Error Interrupt
(DMASEEI)
DMA Clear Enable
Error Interrupt
(DMACEEI)
0x001c
DMA Clear Interrupt
Request
(DMACINT)
DMA Clear Error
(DMACERR)
DMA Set Start Bit
(DMASSRT)
DMA Clear Done
Status Bit
(DMACDNE)
0x0020
DMA Interrupt Request High (DMAINTH, Channels 63-32)
0x0024
DMA Interrupt Request Low (DMAINTL, Channels 31-00)
0x0028
DMA Error High (DMAERRH, Channels 63-32)
0x002c
DMA Error Low (DMAERRL, Channels 31-00)
0x0030-0x00fc
Reserved
0x0100
DMA Channel 0
Priority (DCHPRI0)
DMA Channel 1
Priority (DCHPRI1)
DMA Channel 2
Priority (DCHPRI2)
DMA Channel 3
Priority (DCHPRI3)
0x0104
DMA Channel 4
Priority (DCHPRI4)
DMA Channel 5
Priority (DCHPRI5)
DMA Channel 6
Priority (DCHPRI6)
DMA Channel 7
Priority (DCHPRI7)
0x0108
DMA Channel 8
Priority (DCHPRI8)
DMA Channel 9
Priority (DCHPRI9)
DMA Channel 10
DMA Channel 11
Priority (DCHPRI10) Priority (DCHPRI11)
0x010c
DMA Channel 12
DMA Channel 13
DMA Channel 14
DMA Channel 15
Priority (DCHPRI12) Priority (DCHPRI13) Priority (DCHPRI14) Priority (DCHPRI15)
0x0110
DMA Channel 16
DMA Channel 17
DMA Channel 18
DMA Channel 19
Priority (DCHPRI16) Priority (DCHPRI17) Priority (DCHPRI18) Priority (DCHPRI19)
0x0114
DMA Channel 20
DMA Channel 21
DMA Channel 22
DMA Channel 23
Priority (DCHPRI20) Priority (DCHPRI21) Priority (DCHPRI22) Priority (DCHPRI23)
0x0118
DMA Channel 24
DMA Channel 25
DMA Channel 26
DMA Channel 27
Priority (DCHPRI24) Priority (DCHPRI25) Priority (DCHPRI26) Priority (DCHPRI27)
0x011c
DMA Channel 28
Priority (DCHPRI28)
0x0120
DMA Channel 32
DMA Channel 33
DMA Channel 34
DMA Channel 35
Priority (DCHPRI32) Priority (DCHPRI33) Priority (DCHPRI34) Priority (DCHPRI35)
DMA Channel 29
DMA Channel 30
DMA Channel 31
Priority (DCHPRI29) Priority (DCHPRI30) Priority (DCHPRI31)
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Table 12-4. DMA 32-bit Memory Map (Continued)
DMA Offset
Register
0x0124
DMA Channel 36
DMA Channel 37
DMA Channel 38
DMA Channel 39
Priority (DCHPRI36) Priority (DCHPRI37) Priority (DCHPRI38) Priority (DCHPRI39)
0x0128
DMA Channel 40
DMA Channel 41
DMA Channel 42
DMA Channel 43
Priority (DCHPRI40) Priority (DCHPRI41) Priority (DCHPRI42) Priority (DCHPRI43)
0x012c
DMA Channel 44
DMA Channel 45
DMA Channel 46
DMA Channel 47
Priority (DCHPRI44) Priority (DCHPRI45) Priority (DCHPRI46) Priority (DCHPRI47)
0x0130
DMA Channel 48
DMA Channel 49
DMA Channel 50
DMA Channel 51
Priority (DCHPRI48) Priority (DCHPRI49) Priority (DCHPRI50) Priority (DCHPRI51)
0x0134
DMA Channel 52
DMA Channel 53
DMA Channel 54
DMA Channel 55
Priority (DCHPRI52) Priority (DCHPRI53) Priority (DCHPRI54) Priority (DCHPRI55)
0x0138
DMA Channel 56
DMA Channel 57
DMA Channel 58
DMA Channel 59
Priority (DCHPRI56) Priority (DCHPRI57) Priority (DCHPRI58) Priority (DCHPRI59)
0x013c
DMA Channel 60
Priority (DCHPRI60)
DMA Channel 61
DMA Channel 62
DMA Channel 63
Priority (DCHPRI61) Priority (DCHPRI62) Priority (DCHPRI63)
0x0200-0x0ffc
Reserved
0x1000-0x11fc
TCD00-TCD15
0x1200-0x13fc
TCD16-TCD31
0x1400-0x15fc
TCD32-TCD47
0x1600-0x17fc
TCD48-TCD63
12.2.4.1
12.2.4.1.1
Register Descriptions
DMA Control Register (DMACR)
The 32-bit DMACR defines the basic operating configuration of the DMA.
The DMA arbitrates channel service requests in groups of 16 channels. The 16 channel configuration has
only one group (0). Group 0 contains channels 15-0.
Arbitration within the group can be configured to use either a fixed priority or a round robin. In fixed
priority arbitration, the highest priority channel requesting service is selected to execute. The priorities are
assigned by the channel priority registers (see section Section 12.2.4.1.15, “DMA Channel n Priority
(DCHPRIn), n = 0,..., {15,31,63}).” In round robin arbitration mode, the channel priorities are ignored and
the channels are cycled through without regard to priority.
See Figure 12-2 and Table 12-5 for the DMACR definition.
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30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
EDBG
R
31
ERCA
Register address: DMA_Offset + 0x0000
W
R
W
EBW
Reset
Reset
= Unimplemented
Figure 12-2. DMA Control Register (DMACR)
Table 12-5. DMACR Field Descriptions
Field
Description
31–3
Reserved, should be cleared.
2
ERCA
Enable Round Robin Channel Arbitration.
0 Fixed priority arbitration is used for channel selection.
1 Round robin arbitration is used for channel selection.
1
EDBG
Enable Debug.
0 The assertion of the ipg_debug input is ignored.
1 The assertion of the ipg_debug input causes the DMA to stall the start of a new channel. Executing channels are
allowed to complete. Channel execution will resume when either the ipg_debug input is negated or the EDBG bit
is cleared.
0
EBW
Enable Buffered Writes.
0 The bufferable write signal (hprot[2]) is not asserted during AMBA AHB writes.
1 The bufferable write signal (hprot[2]) is asserted on all AMBA AHB writes except for the last write sequence.
12.2.4.1.2
DMA Error Status (DMAES)
The DMAES register provides information concerning the last recorded channel error. Channel errors can
be caused by a configuration error (an illegal setting in the transfer control descriptor or an illegal priority
register setting in fixed arbitration mode) or an error termination to a bus master read or write cycle.
A configuration error is caused when the starting source or destination address, source or destination
offsets, minor loop byte count and the transfer size represent an inconsistent state. The addresses and
offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a
multiple of the source and destination transfer sizes. All source reads and destination writes must be
configured to the natural boundary of the programmed transfer size respectively. In fixed arbitration mode,
a configuration error is caused by any two channel priorities being equal. All channel priority levels must
be unique when fixed arbitration mode is enabled. If a scatter/gather operation is enabled upon channel
completion, a configuration error is reported if the scatter/gather address (dlast_sga) is not aligned on a
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32 byte boundary. If minor loop channel linking is enabled upon channel completion, a configuration error
is reported when the link is attempted if the TCD.citer.e_link bit does not equal the TCD.biter.e_link bit.
All configuration error conditions except scatter/gather and minor loop link error are reported as the
channel is activated and assert an error interrupt request, if enabled. A scatter/gather configuration error is
reported when the scatter/gather operation begins at major loop completion when properly enabled. A
minor loop channel link configuration error is reported when the link operation is serviced at minor loop
completion.
If a system bus read or write is terminated with an error, the data transfer is stopped and the appropriate
bus error flag set. In this case, the state of the channel’s transfer control descriptor is updated by the
dma_engine with the current source address, destination address and current iteration count at the point of
the fault. When a system bus error occurs, the channel is terminated after the read or write transaction
which is already pipelined after errant access, has completed. If a bus error occurs on the last read prior to
beginning the write sequence, the write will execute using the data captured during the bus error. If a bus
error occurs on the last write prior to switching to the next read sequence, the read sequence will execute
before the channel is terminated due to the destination bus error.
The occurrence of any type of error causes the dma_engine to immediately stop, and the appropriate
channel bit in the DMA Error register to be asserted. At the same time, the details of the error condition
are loaded into the DMAES register. The major loop complete indicators, setting the transfer control
descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is
detected. See Figure 12-3 and Table 12-6 for the DMAES definition.
Register address: DMA_Offset + 0x0004
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
CPE
SAE
SOE
DAE
DOE
NCE
SGE
SBE
DBE
0
0
0
0
0
0
0
0
0
0
R VLD
W
Reset
R
0
ERRCHN[5:0]
W
Reset
0
0
0
0
0
0
= Unimplemented
Figure 12-3. DMA Error Status (DMAES) Register
Table 12-6. DMAES Field Descriptions
Field
31
VLD
30–15
Description
Logical OR of all DMAERRH and DMAERRL status bits.
0 No DMAERR bits are set.
1 At least one DMAERR bit is set indicating a valid error exists that has not been cleared.
Reserved, should be cleared.
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Table 12-6. DMAES Field Descriptions (Continued)
Field
14
CPE
Description
Channel Priority Error.
0 No channel priority error.
1 The last recorded error was a configuration error in the channel priorities. All channel priorities are not unique.
13–8
Error Channel Number. The channel number of the last recorded error. (excluding CPE errors).
ERRCHN
[5:0]
7
SAE
Source Address Error.
0 No source address configuration error.
1 The last recorded error was a configuration error detected in the TCD.saddr field. TCD.saddr is inconsistent with
TCD.ssize.
6
SOE
Source Offset Error.
0 No source offset configuration error.
1 The last recorded error was a configuration error detected in the TCD.soff field. TCD.soff is inconsistent with
TCD.ssize.
5
DAE
Destination Address Error.
0 No destination address configuration error.
1 The last recorded error was a configuration error detected in the TCD.daddr field. TCD.daddr is inconsistent with
TCD.dsize.
4
DOE
Destination Offset Error.
0 No destination offset configuration error.
1 The last recorded error was a configuration error detected in the TCD.doff field. TCD.doff is inconsistent with
TCD.dsize.
3
NCE
Nbytes/Citer Configuration Error.
0 No nbytes/citer configuration error.
1 The last recorded error was a configuration error detected in the TCD.nbytes or TCD.citer fields. TCD.nbytes is
not a multiple of TCD.ssize and TCD.dsize, or TCD.citer is equal to zero, or TCD.citer.e_link is not equal to
TCD.biter.e_link.
2
SGE
Scatter/Gather Configuration Error.
0 No scatter/gather configuration error.
1 The last recorded error was a configuration error detected in the TCD.dlast_sga field. This field is checked at the
beginning of a scatter/gather operation after major loop completion if TCD.e_sg is enabled. TCD.dlast_sga is not
on a 32 byte boundary.
1
SBE
Source Bus Error.
0 No source bus error.
1 The last recorded error was a bus error on a source read.
0
DBE
Destination Bus Error.
0 No destination bus error.
1 The last recorded error was a bus error on a destination write.
12.2.4.1.3
DMA Enable Request (DMAERQH, DMAERQL)
The DMAERQ{H,L} registers provide a bit map for the implemented channels {16,32,64} to enable the
request signal for each channel. DMAERQH supports channels 63-32, while DMAEQRL covers channels
31-00. The state of any given channel enable is directly affected by writes to this register; it is also affected
by writes to the DMASERQ and DMACERQ registers. The DMA{S,C}ERQ registers are provided so that
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the request enable for a single channel can easily be modified without the need to perform a
read-modify-write sequence to the DMAERQ{H,L} registers.
Both the DMA request input signal and this enable request flag must be asserted before a channel’s
hardware service request is accepted. The state of the DMA enable request flag does not affect a channel
service request made explicitly through software or a linked channel request. See Figure 12-4 and
Table 12-7 for the DMAERQ definition.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
ERQ15
ERQ14
ERQ13
ERQ12
ERQ11
ERQ10
ERQ09
ERQ08
ERQ07
ERQ06
ERQ05
ERQ04
ERQ03
ERQ02
ERQ01
ERQ00
Register address: DMA_Offset + 0x0008 (DMAERQH) + 0x000c (DMAERQL)
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
R
W
Reset
R
W
Reset
R
Figure 12-4. DMA Enable Request (DMAERQH, DMAERQL) Register
Table 12-7. DMAERQH, DMAERQL field Descriptions
Field
31–16
Description
Reserved, should be cleared.
15–0
Enable DMA Request n.
ERQn
0 The DMA request signal for channel n is disabled.
n = 0,... 15 1 The DMA request signal for channel n is enabled.
As a given channel completes the processing of its major iteration count, there is a flag in the transfer
control descriptor that may affect the ending state of the DMAERQ bit for that channel. If the TCD.d_req
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The SPP DMA Controller Module (SPP_DMA2)
bit is set, then the corresponding DMAERQ bit is cleared, disabling the DMA request; else if the d_req bit
is cleared, the state of the DMAERQ bit is unaffected.
12.2.4.1.4
DMA Enable Error Interrupt (DMAEEIH, DMAEEIL)
The DMAEEI{H,L} registers provide a bit map for the implemented channels {16,32,64} to enable the
error interrupt signal for each channel. DMAEEIH supports channels 63-32, while DMAEEIL covers
channels 31-00. The state of any given channel’s error interrupt enable is directly affected by writes to this
register; it is also affected by writes to the DMASEEI and DMACEEI registers. The DMA{S,C}EEI
registers are provided so that the error interrupt enable for a single channel can easily be modified without
the need to perform a read-modify-write sequence to the DMAEEI{H,L} registers.
Both the DMA error indicator and this error interrupt enable flag must be asserted before an error interrupt
request for a given channel is asserted. See Figure 12-5 and Table 12-8 for the DMAEEI definition.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
EEI15
EEI14
EEI13
EEI12
EEI11
EEI10
EEI09
EEI08
EEI07
EEI06
EEI05
EEI04
EEI03
EEI02
EEI01
EEI00
Register address: DMA_Offset + 0x0010 (DMAEEIH), + 0x0014 (DMAEEIL)
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
R
W
Reset
R
W
Reset
R
Figure 12-5. DMA Enable Error Interrupt (DMAEEIH, DMAEEIL) Registers
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Table 12-8. DMAEEIH, DMAEEIL Field Descriptions
Field
Description
31–16
Reserved, should be cleared.
15–0
Enable Error Interrupt n.
EEIn
0 The error signal for channel n does not generate an error interrupt.
n = 0,... 15 1 The assertion of the error signal for channel n generate an error interrupt request.
12.2.4.1.5
DMA Set Enable Request (DMASERQ)
The DMASERQ register provides a simple memory-mapped mechanism to set a given bit in the
DMAERQ{H,L} registers to enable the DMA request for a given channel. The data value on a register
write causes the corresponding bit in the DMAERQ{H,L} register to be set. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global set function, forcing the entire
contents of DMAERQ{H,L} to be asserted. Reads of this register return all zeroes. See Figure 12-6 and
Table 12-9 for the DMASERQ definition.
Register address: DMA_Offset + 0x0018
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
SERQ[6:0]
0
0
0
0
= Unimplemented
Figure 12-6. DMA Set Enable Request (DMASERQ) Register
Table 12-9. DMASERQ Field Descriptions
Field
7
Description
Reserved, should be cleared.
6–0
Set Enable Request.
SERQ[6:0] 0-63
Set the corresponding bit in DMAERQ{H,L}
64-127 Set all bits in DMAERQ{H,L}
12.2.4.1.6
DMA Clear Enable Request (DMACERQ)
The DMACERQ register provides a simple memory-mapped mechanism to clear a given bit in the
DMAERQ{H,L} registers to disable the DMA request for a given channel. The data value on a register
write causes the corresponding bit in the DMAERQ{H,L} register to be cleared. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global clear function, forcing the entire
contents of the DMAERQ{H,L} to be zeroed, disabling all DMA request inputs. Reads of this register
return all zeroes. See Figure 12-7 and Figure 12-10 for the DMACERQ definition.
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The SPP DMA Controller Module (SPP_DMA2)
Register address: DMA_Offset + 0x0019
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
CERQ[6:0]
Reset
0
0
0
0
= Unimplemented
Figure 12-7. DMA Clear Enable Request (DMACERQ) Register
Table 12-10. DMACERQ Field Descriptions
Field
7
Description
Reserved, should be cleared.
6–0
Clear Enable Request
CERQ[6:0] 0-63
Clear corresponding bit in DMAERQ{H,L}
64-127 Clear all bits in DMAERQ{H,L}
12.2.4.1.7
DMA Set Enable Error Interrupt (DMASEEI)
The DMASEEI register provides a simple memory-mapped mechanism to set a given bit in the
DMAEEI{H,L} registers to enable the error interrupt for a given channel. The data value on a register
write causes the corresponding bit in the DMAEEI{H,L} register to be set. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global set function, forcing the entire
contents of DMAEEI{H,L} to be asserted. Reads of this register return all zeroes. See Figure 12-8 and
Table 12-11 for the DMASEEI definition.
Register address: DMA_Offset + 0x001a
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
SEEI[6:0]
0
0
0
0
= Unimplemented
Figure 12-8. DMA Set Enable Error Interrupt (DMASEEI) Register
Table 12-11. DMASEEI Field Descriptions
Field
7
Description
Reserved, should be cleared.
6–0
Set Enable Error Interrupt.
SEEI[6:0] 0-63
Set the corresponding bit in DMAEEI{H,L}
64-127 Set all bits in DMAEEI{H,L}
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12.2.4.1.8
DMA Clear Enable Error Interrupt (DMACEEI)
The DMACEEI register provides a simple memory-mapped mechanism to clear a given bit in the
DMAEEI{H,L} registers to disable the error interrupt for a given channel. The data value on a register
write causes the corresponding bit in the DMAEEI{H,L} register to be cleared. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global clear function, forcing the entire
contents of the DMAEEI{H,L} to be zeroed, disabling all DMA request inputs. Reads of this register
return all zeroes. See Figure 12-7 and Table 12-12 for the DMACEEI definition.
Register address: DMA_Offset + 0x001b
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
CEEI[6:0]
Reset
0
0
0
0
= Unimplemented
Figure 12-9. DMA Clear Enable Error Interrupt (DMACEEI) Register
Table 12-12. DMACEEI Field Descriptions
Field
7
Description
Reserved, should be cleared.
6–0
Clear Enable Error Interrupt.
CEEI[6:0] 0-63
Clear corresponding bit in DMAEEI{H,L}
64-127 Clear all bits in DMAEEI{H,L}
12.2.4.1.9
DMA Clear Interrupt Request (DMACINT)
The DMACINT register provides a simple memory-mapped mechanism to clear a given bit in the
DMAINT{H,L} registers to disable the interrupt request for a given channel. The given value on a register
write causes the corresponding bit in the DMAINT{H,L} register to be cleared. A data value of 64 to 127
(regardless of the number of implemented channels) provides a global clear function, forcing the entire
contents of the DMAINT{H,L} to be zeroed, disabling all DMA interrupt requests. Reads of this register
return all zeroes. See Figure 12-10 and Table 12-13 for the DMACINT definition.
Register address: DMA_Offset + 0x001c
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
CINT[6:0]
0
0
0
0
= Unimplemented
Figure 12-10. DMA Clear Interrupt Request (DMACINT) Register
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The SPP DMA Controller Module (SPP_DMA2)
Table 12-13. DMACINT Field Descriptions
Field
7
Description
Reserved, should be cleared.
6–0
Clear Interrupt Request.
CINT[6:0] 0-63
Clear the corresponding bit in DMAINT{H,L}
64-127 Clear all bits in DMAINT{H,L}
12.2.4.1.10 DMA Clear Error (DMACERR)
The DMACEER register provides a simple memory-mapped mechanism to clear a given bit in the
DMAERR{H,L} registers to disable the error condition flag for a given channel. The given value on a
register write causes the corresponding bit in the DMAERR{H,L} register to be cleared. A data value of
64 to 127 (regardless of the number of implemented channels) provides a global clear function, forcing the
entire contents of the DMAERR{H,L} to be zeroed, clearing all channel error indicators. Reads of this
register return all zeroes. See Figure 12-11 and Table 12-14 for the DMACERR definition.
Register address: DMA_Offset + 0x001d
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
CERR[6:0]
0
0
0
0
= Unimplemented
Figure 12-11. DMA Clear Error (DMACERR) Register
Table 12-14. DMACERR Field Descriptions
Field
7
Description
Reserved, should be cleared.
6–0
Clear Error Indicator.
CERR[6:0] 0-63
Clear corresponding bit in DMAERR{H,L}
64-127 Clear all bits in DMAERR{H,L}
12.2.4.1.11 DMA Set START Bit (DMASSRT)
The DMASSRT register provides a simple memory-mapped mechanism to set the START bit in the TCD
of the given channel. The data value on a register write causes the START bit in the corresponding Transfer
Control Descriptor to be set. A data value of 64 to 127 (regardless of the number of implemented channels)
provides a global set function, forcing all START bits to be set. Reads of this register return all zeroes. See
Table 12-28 for the TCD START bit definition.
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The SPP DMA Controller Module (SPP_DMA2)
Register address: DMA_Offset + 0x001e
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
SSRT[6:0]
Reset
0
0
0
0
= Unimplemented
Figure 12-12. DMA Set START Bit (DMASSRT) Register
Table 12-15. DMASSRT Field Descriptions
Field
7
Descriptions
Reserved, should be cleared.
6–0
Set START Bit (Channel Service Request).
SSRT[6:0] 0-63
Set the corresponding channel’s TCD.start
64-127 Set all TCD.start bits
12.2.4.1.12 DMA Clear DONE Status (DMACDNE)
The DMACDNE register provides a simple memory-mapped mechanism to clear the DONE bit in the
TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding
Transfer Control Descriptor to be cleared. A data value of 64 to 127 (regardless of the number of
implemented channels) provides a global clear function, forcing all DONE bits to be cleared. Reads of this
register return all zeroes. See Table 12-28 for the TCD DONE bit definition.
Register address: DMA_Offset + 0x001f
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
CDNE[6:0]
0
0
0
0
= Unimplemented
Figure 12-13. DMA Clear DONE Status (DMACDNE) Register
Table 12-16. DMACDNE Field Descriptions
Field
7
Description
Reserved, should be cleared.
6–0
Clear DONE Status Bit.
CDNE[6:0] 0-63 Clear the corresponding channel’s DONE bit 64-127 Clear all TCD DONE bits
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The SPP DMA Controller Module (SPP_DMA2)
12.2.4.1.13 DMA Interrupt Request (DMAINTH, DMAINTL)
The DMAINT{H,L} registers provide a bit map for the implemented channels {16,32,64} signaling the
presence of an interrupt request for each channel. DMAINTH supports channels 63-32, while DMAINTL
covers channels 31-00. The dma_engine signals the occurrence of a programmed interrupt upon the
completion of a data transfer as defined in the transfer control descriptor by setting the appropriate bit in
this register. The outputs of this register are directly routed to the platform’s interrupt controller. During
the execution of the interrupt service routine associated with any given channel, it is software’s
responsibility to clear the appropriate bit, negating the interrupt request. Typically, a write to the
DMACINT register in the interrupt service routine is used for this purpose.
The state of any given channel’s interrupt request is directly affected by writes to this register; it is also
affected by writes to the DMACINT register. On writes to the DMAINT, a one in any bit position clears
the corresponding channel’s interrupt request. A zero in any bit position has no affect on the corresponding
channel’s current interrupt status. The DMACINT register is provided so the interrupt request for a single
channel can easily be cleared without the need to perform a read-modify-write sequence to the
DMAINT{H,L} registers. See Figure 12-14 and Table 12-17 for the DMAINT definition.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
INT15
INT14
INT13
INT12
INT11
INT10
INT09
INT08
INT07
INT06
INT05
INT04
INT03
INT02
INT01
INT00
Register address: DMA_Offset + 0x0020 (DMAINTH), +0x0024 (DMAINTL)
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
R
W
Reset
R
W
Reset
R
= Unimplemented
Figure 12-14. DMA Interrupt Request (DMAINTH, DMAINTL) Registers
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The SPP DMA Controller Module (SPP_DMA2)
Table 12-17. DMAINTH, DMAINTL Field Descriptions
Field
31–16
Description
Reserved, should be cleared.
15–0
DMA Interrupt Request n.
INTn,
0 The interrupt request for channel n is cleared.
n = 0,... 15 1 The interrupt request for channel n is active.
12.2.4.1.14 DMA Error (DMAERRH, DMAERRL)
The DMAERR{H,L} registers provide a bit map for the implemented channels {16,32,64} signaling the
presence of an error for each channel. DMAERRH supports channels 63-32, while DMAERRL covers
channels 31-00. The dma_engine signals the occurrence of a error condition by setting the appropriate bit
in this register. The outputs of this register are enabled by the contents of the DMAEEI register, then
logically summed across groups of 16, 32 and 64 channels to form several group error interrupt requests
which is then routed to the platform’s interrupt controller. During the execution of the interrupt service
routine associated with any DMA errors, it is software’s responsibility to clear the appropriate bit, negating
the error interrupt request. Typically, a write to the DMACERR register in the interrupt service routine is
used for this purpose. Recall the normal DMA channel completion indicators, setting the transfer control
descriptor done flag and the possible assertion of an interrupt request, are not affected when an error is
detected.
The contents of this register can also be polled and a non-zero value indicates the presence of a channel
error, regardless of the state of the DMAEEI register. The state of any given channel’s error indicators is
affected by writes to this register; it is also affected by writes to the DMACERR register. On writes to the
DMAERR, a one in any bit position clears the corresponding channel’s error status. A zero in any bit
position has no affect on the corresponding channel’s current error status. The DMACERR register is
provided so the error indicator for a single channel can easily be cleared. See Figure 12-15 and Table 12-18
for the DMAERR definition.
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The SPP DMA Controller Module (SPP_DMA2)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
ERR15
ERR14
ERR13
ERR12
ERR11
ERR10
ERR09
ERR08
ERR07
ERR06
ERR05
ERR04
ERR03
ERR02
ERR01
ERR00
Register address: DMA_Offset + 0x0028 (DMAERRH), +0x002c (DMAERRL)
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
R
W
Reset
R
W
Reset
R
= Unimplemented
Figure 12-15. DMA Error (DMAERRH, DMAERRL) Registers
Table 12-18. DMAERRH, DMAERRL Field Descriptions
Field
31–16
Description
DMA Error n.
0 An error in channel n has not occurred.
1 An error in channel n has occurred.
15–0
DMA Error n.
ERRn,
0 An error in channel n has not occurred.
n = 0,... 15 1 An error in channel n has occurred.
12.2.4.1.15 DMA Channel n Priority (DCHPRIn), n = 0,..., {15,31,63}
When the fixed-priority channel arbitration mode is enabled (DMACR[ERCA] = 0), the contents of these
registers define the unique priorities associated with each channel. The channel priorities are evaluated by
numeric value, i.e., 0 is the lowest priority, 1 is the next higher priority, then 2, 3, etc. Software must
program the channel priorities with unique values, otherwise a configuration error will be reported. The
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The SPP DMA Controller Module (SPP_DMA2)
range of the priority value is limited to the values of 0 through 15. See Figure 12-2 and Table 12-5 for the
DMACR definition.
Channel preemption is enabled on a per channel basis by setting the ECP bit in the DCHPRIn register.
Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of
starting a higher priority channel. Once the preempting channel has completed all of its minor loop data
transfers, the preempted channel is restored and resumes execution. After the restored channel completes
one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting
service, the restored channel will be suspended and the higher priority channel will be serviced. Nested
preemption (attempting to preempt a preempting channel) is not supported. Once a preempting channel
begins execution, it cannot be preempted. Preemption is only available when fixed arbitration is selected
for channel arbitration modes. See Figure 12-16 and Table 12-19 for the DCHPRIn definition.
Register address: DMA_Offset + 0x100 + n
7
R ECP
6
5
4
0
0
0
*
*
3
2
1
0
CHPRI[3:0]
W
Reset
0
*
*
*
*
= Unimplemented,
*
= defaults to channel number (n) after reset
Figure 12-16. DMA Channel n Priority (DCHPRIn) Register
Table 12-19. DCHPRIn Field Descriptions
Field
7
ECP
6-4
3–0
CHPRI[3:0]
Description
Enable Channel Preemption.
0 Channel n cannot be suspended by a higher priority channel’s service request.
1 Channel n can be temporarily suspended by the service request of a higher priority channel.
Reserved, should be cleared.
Channel n Arbitration Priority. Channel priority when fixed-priority arbitration is enabled.
12.2.4.1.16 Transfer Control Descriptor (TCD)
Each channel requires a 32-byte transfer control descriptor for defining the desired data movement
operation. The TCD structure was previously discussed in detail in Section 12.2.2, “Features.” The
channel descriptors are stored in the local memory in sequential order: channel 0, channel 1, ... channel
[n-1]. The definitions of the TCD are presented as eight 32-bit values. Table 12-20 is a 32-bit view of the
basic TCD structure.
Table 12-20. TCDn 32-bit Memory Structure
DMA Offset
TCDn Field
0x1000 + (32 x n) + 0x00
Source Address (saddr)
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The SPP DMA Controller Module (SPP_DMA2)
Table 12-20. TCDn 32-bit Memory Structure
0x1000 + (32 x n) + 0x04
Transfer Attributes
(smod, ssize, dmod, dsize)
Signed Source Address Offset (soff)
0x1000 + (32 x n) + 0x08
Inner “Minor” Byte Count (nbytes)
0x1000 + (32 x n) + 0x0c
Last Source Address Adjustment (slast)
0x1000 + (32 x n) + 0x10
Destination Address (daddr)
0x1000 + (32 x n) + 0x14
Current “Major” Iteration Count (citer)
0x1000 + (32 x n) + 0x18
Signed Destination Address Offset (doff)
Last Destination Address Adjustment/Scatter Gather Address (dlast_sga)
0x1000 + (32 x n) + 0x1c
Beginning “Major” Iteration Count (biter)
Channel Control/Status
(bwc, major.linkch, done, active, major.e_link,
e_sg, d_req, int_half, int_maj, start)
Figure 12-17 and Table 12-21 define word 0 of the TCDn structure, the saddr field.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x00
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
saddr[31:16]
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
saddr[15:00]
W
Reset
—
—
—
—
—
—
—
—
—
= Unimplemented
Figure 12-17. TCDn Word 0 (TCDn.saddr) Field
Table 12-21. TCDn Word 0 (TCDn.saddr) Field Description
Field
Description
31–0
Source address. Memory address pointing to the source data.
saddr[31:0]
Figure 12-18 and Table 12-22 define word 1 of the TCDn structure, the soff and transfer attribute fields.
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The SPP DMA Controller Module (SPP_DMA2)
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x04
31
30
R
29
28
27
26
smod[4:0]
25
24
23
22
ssize[2:0]
21
20
19
18
dmod[4:0]
17
16
dsize[2:0]
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
soff[15:0]
W
Reset
—
—
—
—
—
—
—
—
—
= Unimplemented
Figure 12-18. TCDn Word 1 (TCDn.{soff,smod,ssize,dmod,dsize}) Fields
Table 12-22. TCDn Word 1 (TCDn.{smod,ssize,dmod,dsize,soff}) Field Descriptions
Field
Description
31–27
Source address modulo.
smod[4:0] 0
Source address modulo feature is disabled.
non-0 The value defines a specific address bit which is selected to be either the value after saddr + soff calculation
is performed or the original register value. This feature provides the ability to easily implement a circular data
queue. For data queues requiring power-of-2 “size” bytes, the queue should be based at a 0-modulo-size
address and the smod field set to the appropriate value to freeze the upper address bits. The bit select is
defined as ((1 << smod[4:0]) - 1) where a resulting 1 in a bit location selects the next state address for the
corresponding address bit location and a 0 selects the original register value for the corresponding address
bit location. For this application, the soff is typically set to the transfer size to implement post-increment
addressing with the smod function constraining the addresses to a 0-modulo-size range.
26–24
Source data transfer size.
ssize[2:0] 000 8-bit
001 16-bit
010 32-bit
011 64-bit
100 16-byte (32-bit implementations only)
101 32-byte (if supported by the platform)
110 Reserved
111 Reserved
The attempted specification of a 64-bit source size in a 32-bit AMBA AHB bus implementation produces a
configuration error. Likewise, the attempted specification of a 16-byte source size in a 64-bit AMBA AHB bus
implementation generates a configuration error. The attempted specification of a 32-byte burst on platforms that do
not support such a transfer type will result in a configuration error.
23–19
Destination address modulo. See the smod[5:0] definition.
dmod[4:0]
18–16
Destination data transfer size. See the ssize[2:0] definition.
dsize[2:0]
15–0
Source address signed offse. Sign-extended offset applied to the current source address to form the next-state
soff[15:0] value as each source read is completed.
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The SPP DMA Controller Module (SPP_DMA2)
Figure 12-19 and Table 12-23 define word 2 of the TCDn structure, the nbytes field.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x08
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
nbytes[31:16]
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
nbytes[15:00]
W
Reset
—
—
—
—
—
—
—
—
—
= Unimplemented
Figure 12-19. TCDn Word 2 (TCDn.nbytes) Field
Table 12-23. TCDn Word 2 (TCDn.nbytes) Field Description
Field
Description
31–0
Inner “minor” byte transfer count. Number of bytes to be transferred in each service request of the channel. As a
nbytes[31:0] channel is activated, the contents of the appropriate TCD is loaded into the dma_engine, and the appropriate
reads and writes performed until the complete byte transfer count has been transferred. This is an indivisible
operation and cannot be stalled or halted. Once the minor count is exhausted, the current values of the saddr and
daddr are written back into the local memory, the major iteration count is decremented and restored to the local
memory. If the major iteration count is completed, additional processing is performed. The nbytes value
0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4GB transfer.
Figure 12-20 and Table 12-24 define word 3 of the TCDn structure, the slast field.
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The SPP DMA Controller Module (SPP_DMA2)
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x0c
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
slast[31:16]
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
slast[15:00]
W
Reset
—
—
—
—
—
—
—
—
—
= Unimplemented
Figure 12-20. TCDn Word 3 (TCDn.slast) Field
Table 12-24. TCDn Word 3 (TCDn.slast) Field Descriptions
Field
Description
31–0
Last source address adjustment. Adjustment value added to the source address at the completion of the outer
slast[31:0] major iteration count. This value can be applied to “restore” the source address to the initial value, or adjust the
address to reference the next data structure.
Figure 12-21 and Table 12-25 define word 4 of the TCDn structure, the daddr field.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x10
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
daddr[31:16]
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
daddr[15:00]
W
Reset
—
—
—
—
—
—
—
—
—
= Unimplemented
Figure 12-21. TCDn Word 4 (TCDn.daddr) Field
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The SPP DMA Controller Module (SPP_DMA2)
Table 12-25. TCDn Word 4 (TCDn.daddr) Field Descriptions
Field
Description
31–0
Destination address. Memory address pointing to the destination data.
daddr[31:0]
Figure 12-22 and Table 12-26 define word 5 of the TCDn structure, the citer and doff fields.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x14
31
30
29
R citer.
e_link
W
Reset
28
27
26
25
24
23
22
21
citer[14:9] or
citer.linkch[5:0]
20
19
18
17
16
citer[8:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
doff[15:0]
W
Reset
—
—
—
—
—
—
—
—
—
= Unimplemented
Figure 12-22. TCDn Word 5 (TCDn.{citer,doff}) Fields
Table 12-26. TCDn Word 5 (TCDn.{doff,citer}) Field Descriptions
Field
Description
31
Enable channel-to-channel linking on minor loop complete. As the channel completes the inner minor loop, this flag
citer.e_link enables the linking to another channel, defined by citer.linkch[5:0]. The link target channel initiates a channel
service request via an internal mechanism that sets the TCD.start bit of the specified channel. If channel linking is
disabled, the citer value is extended to 15 bits in place of a link channel number. If the "major" loop is exhausted,
this link mechanism is suppressed in favor of the major.e_link channel linking. This bit must be equal to the
biter.e_link bit otherwise a configuration error will be reported.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
30–25
citer[14:9]
or
citer.linkch
[5:0]
Current “major” iteration count or Link channel number. If (TCD.citer.e_link = 0) then
No channel-to-channel linking (or chaining) is performed after the inner "minor" loop is exhausted. TCD word 5,
bits [30:25] are used to form a 15 bit citer field.
else
After the "minor" loop is exhausted, the dma_engine initiates a channel service request at the channel defined by
citer.linkch[5:0] by setting that channel’s TCD.start bit. The value contained in citer.linkch[5:0] must not exceed the
number of implemented channels.
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Table 12-26. TCDn Word 5 (TCDn.{doff,citer}) Field Descriptions (Continued)
Field
Description
24–16
citer[8:0]
Current “major” iteration count. This 9 or 15-bit count represents the current major loop count for the channel. It is
decremented each time the minor loop is completed and updated in the transfer control descriptor memory. Once
the major iteration count is exhausted, the channel performs a number of operations (e.g., final source and
destination address calculations), optionally generating an interrupt to signal channel completion before reloading
the citer field from the beginning iteration count (biter) field. When the citer field is initially loaded by software, it
must be set to the same value as that contained in the biter field. If the channel is configured to execute a single
service request, the initial values of biter and citer should be 0x0001.
15–0
doff[15:0]
Destination address signed offset. Sign-extended offset applied to the current destination address to form the
next-state value as each destination write is completed.
Figure 12-23 and Table 12-27 define word 6 of the TCDn structure, the dlast_sga field.
Register address: DMA_Offset + 0x1000 + (32 x n) + 0x18
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
dlast_sga[31:16]
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
dlast_sga[15:00]
W
Reset
—
—
—
—
—
—
—
—
—
= Unimplemented
Figure 12-23. TCDn Word 6 (TCDn.dlast_sga) Field
Table 12-27. TCDn Word 6 (TCDn.dlast_sga) Field Descriptions
Field
Description
31–0
Last destination address adjustment or the memory address for the next transfer control descriptor to be loaded
dlast_sga into this channel (scatter/gather). If (TCD.e_sg = 0) then
[31:0]
Adjustment value added to the destination address at the completion of the outer major iteration count. This value
can be applied to “restore” the destination address to the initial value, or adjust the address to reference the next
data structure.
else
This address points to the beginning of a 0-modulo-32 region containing the next transfer control descriptor to be
loaded into this channel. This channel reload is performed as the major iteration count completes. The
scatter/gather address must be 0-modulo-32, else a configuration error is reported.
Figure 12-24 and Table 12-28 define word 7 of the TCDn structure, the biter and control/status fields.
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Register address: DMA_Offset + 0x1000 + (32 x n) + 0x1c
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
biter[15:0]
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
int_maj
Reset
int_half
W
start
—
—
0
R
bwc
major.linkch[5:0]
done active major. e_sg d_req
e_link
W
Reset
—
—
—
—
—
—
—
—
0
0
—
—
—
= Unimplemented
Figure 12-24. TCDn Word 7 (TCDn.{biter,control/status}) Fields
Table 12-28. TCDn Word 7 (TCDn.{biter, control/status}) Field Descriptions
Field
Description
biter.e_link
Enable channel-to-channel linking on minor loop complete. This is the initial value copied into the citer.e_link
field when the major loop is completed. The citer.e_link field controls channel linking during channel execution.
This bit must be equal to the citer.e_link bit otherwise a configuration error will be reported.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
biter[14:9]
Beginning “major” iteration count or Beginning Link channel number. This is the initial value copied into the
or
citer field or citer.linkch field when the major loop is completed. The citer fields controls the interation count
biter.linkch[5:0] and link ing during channel execution.
if (TCD.biter.e_link = 0) then
No channel-to-channel linking (or chaining) is performed after the inner "minor" loop is exhausted. TCD word
5, bits [30:25] are used to form a 15 bit biter field.
else
After the "minor" loop is exhausted, the dma_engine initiates a channel service request at the channel defined
by biter.linkch[5:0] by setting that channel’s TCD.start bit.
The value contained in biter.linkch[5:0] must not exceed the number of implemented channels
biter[8:0]
Beginning “major” iteration count. This is the initial value copied into the citer field or citer.linkch field when the
major loop is completed. The citer fields controls the interation count and link ing during channel execution.
This 9 or 15-bit count represents the beginning major loop count for the channel. As the major iteration count
is exhausted, the contents of the entire 16 bit biter entry is reloaded into the 16 bit citer entry. When the biter
field is initially loaded by software, it must be set to the same value as that contained in the citer field. If the
channel is configured to execute a single service request, the initial values of biter and citer should be 0x0001.
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Table 12-28. TCDn Word 7 (TCDn.{biter, control/status}) Field Descriptions (Continued)
Field
Description
bwc[1:0]
Bandwidth control. This two-bit field provides a mechanism to effectively throttle the amount of bus bandwidth
consumed by the DMA. In general, as the DMA processes the inner minor loop, it continuously generates
read/write, read/write, ... sequences until the minor count is exhausted. This field forces the DMA to stall after
the completion of each read/write access to control the bus request bandwidth seen by the platform’s
cross-bar arbitration switch. To minimize start-up latency, bandwidth control stalls are suppressed for the first
two AHB bus cycles and after the last write of each minor loop. The dynamic priority elevation setting elevates
the priority of the DMA as seen by the cross-bar arbitration switch for the executing channel. Dynamic priority
elevation is suppressed during the first two AHB bus cycles.
00 No dma_engine stalls
01 Dynamic priority elevation
10 dma_engine stalls for 4 cycles after each r/w
11 dma_engine stalls for 8 cycles after each r/w
major.linkch[5: Link channel number. If TCD.major.e_link = 0) then
0]
No channel-to-channel linking (or chaining) is performed after the outer "major" loop counter is exhausted.
else
After the "major" loop counter is exhausted, the dma_engine initiates a channel service request at the channel
defined by major.linkch[5:0] by setting that channel’s TCD.start bit. The value contained in major.linkch[5:0]
must not exceed the number of implemented channels.
done
Channel done. This flag indicates the DMA has completed the outer major loop. It is set by the dma_engine
as the citer count reaches zero; it is cleared by software, or the hardware when the channel is activated. This
bit must be cleared in order to write the major.e_link or e_sg bits.
active
Channel active. This flag signals the channel is currently in execution. It is set when channel service begins,
and is cleared by the dma_engine as the inner minor loop completes or if any error condition is detected.
major.e_link
Enable channel-to-channel linking on major loop complete. As the channel completes the outer major loop,
this flag enables the linking to another channel, defined by major.linkch[5:0]. The link target channel initiates
a channel service request via an internal mechanism that sets the TCD.start bit of the specified channel. To
support the dynamic linking coherency model, this field is forced to zero when written to while the TCD.done
bit is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
e_sg
Enable scatter/gather processing. As the channel completes the outer major loop, this flag enables
scatter/gather processing in the current channel. If enabled, the dma_engine uses dlast_sga as a memory
pointer to a 0-modulo-32 address containing a 32-byte data structure which is loaded as the transfer control
descriptor into the local memory. To support the dynamic scatter/gather coherency model, this field is forced
to zero when written to while the TCD.done bit is set.
0 The current channel’s TCD is “normal” format.
1 The current channel’s TCD specifies a scatter gather format. The dlast_sga field provides a memory pointer
to the next TCD to be loaded into this channel after the outer major loop completes its execution.
d_req
Disable request. If this flag is set, the DMA hardware automatically clears the corresponding DMAERQ bit
when the current major iteration count reaches zero.
0 The channel’s DMAERQ bit is not affected.
1 The channel’s DMAERQ bit is cleared when the outer major loop is complete.
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Table 12-28. TCDn Word 7 (TCDn.{biter, control/status}) Field Descriptions (Continued)
Field
Description
int_half
Enable an interrupt when major counter is half complete. If this flag is set, the channel generates an interrupt
request by setting the appropriate bit in the DMAINT register when the current major iteration count reaches
the halfway point. Specifically, the comparison performed by the dma_engine is (citer == (biter >> 1)). This
halfway point interrupt request is provided to support double-buffered schemes or other types of data
movement where the processor needs an early indication of the transfer’s progress. The halfway complete
interrupt is disabled when biter values are less than two.
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
int_maj
Enable an interrupt when major iteration count completes. If this flag is set, the channel generates an interrupt
request by setting the appropriate bit in the DMAINT register when the current major iteration count reaches
zero.
0 The end-of-major loop interrupt is disabled.
1 The end-of-major loop interrupt is enabled.
start
12.2.5
Channel start. If this flag is set, the channel is requesting service. The DMA hardware automatically clears
this flag after the channel begins execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software initiated service request.
DMA Performance
This section addresses the performance of the DMA module, focusing on two separate metrics. In the
traditional data movement context, performance is best expressed as the peak data transfer rates achieved
using the DMA. In most implementations, this transfer rate is limited by the speed of the source and
destination address spaces. In a second context where device-paced movement of single data values
to/from peripherals is dominant, a measure of the requests which can be serviced in a fixed time is a more
interesting metric. In this environment, the speed of the source and destination address spaces remains
important, but the microarchitecture of the DMA also factors significantly into the resulting metric.
The peak transfer rates for several different source and destination transfers are shown in Figure 12-29.
The following assumptions apply to Figure 12-29 and Figure 12-30:
• Platform SRAM can be accessed with zero wait-states when viewed from the AMBA-AHB data
phase
• All IPS reads require two wait-states, and IPS writes three wait-states, again viewed from the
system bus data phase
• All IPS accesses are 32-bits in size
Table 12-29 presents a peak transfer rate comparison, measured in MBytes per sec.
Table 12-29. DMA Peak Transfer Rates [MBytes/sec]
Platform Speed,
Width
Platform SRAM-toPlatform SRAM
32b IPS-toPlatform SRAM
Platform SRAM-to32b IPS
66.7 MHz, 32b
133.3
66.7
53.3
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where the Platform_SRAM-to-Platform_SRAM transfers occur at the native platform datapath width, i.e.,
either 32- or 64-bits per access. For all transfers involving the IPS bus, 32-bit transfer sizes are used. In all
cases, the transfer rate includes the time to read the source plus the time to write the destination.
The second performance metric is a measure of the number of DMA requests which can be serviced in a
given amount of time. For this metric, it is assumed the peripheral request causes the channel to move a
single IPS-mapped operand to/from the platform SRAM. The same timing assumptions used in the
previous example apply to this calculation. In particular, this metric also reflects the time required to
activate the channel. The DMA design supports the following hardware service request sequence:
• Cycle 1: ipd_req[n] is asserted.
• Cycle 2: The ipd_req[n] is registered locally in the DMA module and qualified. (TCD.start bit
initiated requests start at this point with the registering of the IPS write to TCD word7).
• Cycle 3: Channel arbitration begins.
• Cycle 4: Channel arbitration completes. The transfer control descriptor local memory read is
initiated.
• Cycle 5 - 6: The first two parts of the activated channel’s TCD is read from the local memory. The
memory width to the dma_engine is 64 bits, so the entire descriptor can be accessed in four cycles.
• Cycle 7: The first AMBA-AHB read cycle is initiated, as the third part of the channel’s TCD is read
from the local memory. Depending on the state of the platform’s crossbar switch, arbitration at the
system bus may insert an additional cycle of delay here.
• Cycle 8 - ?: The last part of the TCD is read in. This cycle represents the 1st data phase for the read,
and the address phase for the destination write.
The exact timing from this point is a function of the response times for the channel’s read and write
accesses. In this case of an IPS read and a platform SRAM write, the combined data phase time is
4 cycles. For an SRAM read and IPS write, it is 5 cycles.
• Cycle ?+1: This cycle represents the data phase of the last destination write.
• Cycle ?+2: The dma_engine completes the execution of the inner minor loop and prepares to write
back the required TCDn fields into the local memory. TCD word7 is read and checked for channel
linking or scatter/gather requests.
• Cycle ?+3: The appropriate fields in the first part of the TCDn are written back into the local
memory.
• Cycle ?+4: The fields in the second part of the TCDn are written back into the local memory. This
cycle coincides with the next channel arbitration cycle start.
• Cycle ?+5: The next channel to be activated performs the read of the first part of its TCD from the
local memory. This is equivalent to Cycle 4 for the first channel’s service request.
Assuming zero wait states on the AHB system bus, DMA requests can be processed every 9 cycles.
Assuming an average of the access times associated with IPS-to-SRAM (4 cycles) and SRAM-to-IPS (5
cycles), DMA requests can be processed every 11.5 cycles (4 + (4+5)/2 + 3). This is the time from Cycle
4 to Cycle “?+5”. The resulting peak request rate, as a function of the platform frequency, is shown in
Table 12-30. This metric represents millions of requests per second.
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Table 12-30. DMA Peak Request Rate [MReq/sec]
Platform Speed
Request Rate
(zero wait state)
Request Rate
(with wait states)
66.6 MHz
7.4
5.8
A general formula to compute the peak request rate (with overlapping requests) is:
PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ]
where:
PEAKreq - peak request rate
freq - platform frequency
entry - channel startup (4 cycles)
read_ws - wait states seen during the system bus read data phase
write_ws - wait states seen during the system bus write data phase
exit - channel shutdown (3 cycles)
For example: consider a platform with the following characteristics:
• Platform SRAM can be accessed with one wait-state when viewed from the AMBA-AHB data
phase
• All IPS reads require two wait-states, and IPS writes three wait-states, again viewed from the
system bus data phase
• Platform operates at 150 MHz
For an SRAM to IPS transfer,
150 MHz
PEAKreq = ------------------------------------------------------------------------------------- = 11.5 M req/sec
[ 4 + ( 1 + 1 ) + ( 1 + 3 ) + 3 ]cycles
Eqn. 12-1
For an IPS to SRAM transfer,
150 MHz
PEAKreq = ------------------------------------------------------------------------------------ = 12.5 M req/sec
[ 4 + ( 1 + 2 ) + ( 1 + 1 ) + 3 ]cycles
Eqn. 12-2
Assuming an even distribution of the two transfer types, the average Peak Request Rate would be:
11.5 M req/sec + 12.5 M req/sec
PEAKreq = -------------------------------------------------------------------------------------- = 12.0 M req/sec
2
Eqn. 12-3
The minimum number of cycles to perform a single read/write, zero wait states on the system bus, from a
cold start (where no channel is executing, DMA is idle) are:
• 11 cycles for a software (TCD.start bit) request
• 12 cycles for a hardware (ipd_req signal) request
Two cycles account for the arbitration pipeline and one extra cycle on the hardware request resulting from
the internal registering of the ipd_req signals. For the peak request rate calculations above, the arbitration
and request registering is absorbed in or overlap the previous executing channel.
Note: When channel linking or scatter/gather is enabled, a two cycle delay is imposed on the next channel
selection and startup. This allows the link channel or the scatter/gather channel to be eligible and
considered in the arbitration pool for next channel selection.
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12.2.6
12.2.6.1
Initialization/Application Information
DMA Initialization
A typical initialization of the DMA would be:
1. write the DMACR register if a configuration other than the default is desired,
2. write the channel priority levels into the DCHPRIn registers if a configuration other than the
default is desired,
3. enable error interrupts in the DMAEEI registers if so desired,
4. write the 32 byte TCD for each channel that may request service,
5. enable any hardware service requests via the DMAERQ register,
6. request channel service by either software (setting the TCD.start bit) or by hardware (slave device
asserting its ipd_req signal).
Once any channel requests service, a channel is selected for execution based on the arbitration and priority
levels written into the programmer's model. The dma_engine will read the entire TCD for the selected
channel into its internal address path module. As the TCD is being read, the first transfer is initiated on the
AHB bus unless a configuration error is detected. Transfers from the source (as defined by the source
address, TCD.saddr) to the destination (as defined by the destination address, TCD.daddr) continue until
the specified number of bytes (TCD.nbytes) have been transferred. When the transfer is complete, the
dma_engine's local TCD.saddr, TCD.daddr, and TCD.citer are written back to the main TCD memory and
any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post
processing is executed, i.e. interrupts, major loop channel linking, and scatter/gather operations, if enabled.
12.2.6.2
DMA Programming Errors
The DMA performs various tests on the Transfer Control Descriptor to verify consitency in the descriptor
data. Most programming errors are reported on a per channel basis with the exception of Channel Priority
Error, CPE in the DMAES register respectively.
For all error types other than Channel Priority Errors, the channel number causing the error is recorded in
the DMAES register. If the error source is not removed before the next activation of the problem channel,
the error will be detected and recorded again.
In general, if priority levels are not unique, the highest channel priority that has an active request will be
selected, but the lowest numbered channel with that priority will be selected by arbitration and executed
by the dma_engine. The hardware service request handshake signals, error interrupts and error reporting
will be associated with the selected channel.
12.2.6.3
12.2.6.3.1
DMA Arbitration Mode Considerations
Fixed Channel Arbitration
In this mode, the channel service request from the highest priority channel will be selected to execute.
Preemption is available in this scenario only.
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12.2.6.3.2
Round Robin Channel Arbitration
Channels are serviced starting with the highest channel number and rotating through to the lowest channel
number without regard to channel priority levels.
All channels are treated equally. Priority levels are not used in round robin mode.
12.2.6.4
12.2.6.4.1
DMA Transfer
Single request
To perform a simply transfer of ’n’ bytes of data with one activation, set the major loop to one (TCD.citer
= TCD.biter = 1). The data transfer will begin after the channel service request is acknowledged and the
channel is selected to execute. Once the transfer is complete, the TCD.done bit will be set and an interrupt
will be generated if properly enabled.
For example, the following TCD entry is configured to transfer 16 bytes of data. The DMA is programmed
for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte wide
memory port located at 0x1000. The destination memory has a word wide port located at 0x2000. The
address offsets are programmed in increments to match the size of the transfer; one byte for the source and
four bytes for the destination. The final source and destination addresses are adjusted to return to their
beginning values.
TCD.citer
= TCD.biter = 1
TCD.nbytes
= 16
TCD.saddr
= 0x1000
TCD.soff
=1
TCD.ssize
=0
TCD.slast
= -16
TCD.daddr
= 0x2000
TCD.doff
=4
TCD.dsize
=2
TCD.dlast_sga
= -16
TCD.int_maj
=1
TCD.start
= 1 (TCD.word7 should be written last after all other fields have been initialized)
All other TCD fields = 0
This would generate the following sequence of events:
1. IPS write to the TCD.start bit requests channel service,
2. the channel is selected by arbitration for servicing,
3. dma_engine writes: TCD.done = 0, TCD.start = 0, TCD.active = 1,
4. dma_engine reads: channel TCD data from local memory to internal register file,
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5. the source to destination transfers are executed as follows:
a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003),
b) write_word(0x2000) -> first iteration of the minor loop
c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007),
d) write_word(0x2004) -> second iteration of the minor loop
e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b),
f) write_word(0x2008) -> third iteration of the minor loop
g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f),
h) write_word(0x200c) -> last iteration of the minor loop -> major loop complete
6. dma_engine writes: TCD.saddr = 0x1000, TCD.daddr = 0x2000, TCD.citer = 1 (TCD.biter),
7. dma_engine writes: TCD.active = 0, TCD.done = 1, DMAINT[n] = 1,
8. the channel retires.
The DMAgoes idle or services next channel.
12.2.6.4.2
Multiple requests
The next example is the same as previous with the exception of transferring 32 bytes via two hardware
requests. The only fields that change are the major loop iteration count and the final address offsets. The
DMAis programmed for two iterations of the major loop transferring 16 bytes per iteration. After the
channel’s hardware requests is enabled in the DMAERQ register, channel service requests are initiated by
the slave device.
TCD.citer
TCD.slast
TCD.dlast_sga
= TCD.biter = 2
= -32
= -32
This would generate the following sequence of events:
1. first hardware (ipd_req) request for channel service,
2. the channel is selected by arbitration for servicing,
3. dma_engine writes: TCD.done = 0, TCD.start = 0, TCD.active = 1,
4. dma_engine reads: channel TCD data from local memory to internal register file,
5. the source to destination transfers are executed as follows:
a) read_byte(0x1000), read_byte(0x1001), read_byte(0x1002), read_byte(0x1003),
b) write_word(0x2000) -> first iteration of the minor loop
c) read_byte(0x1004), read_byte(0x1005), read_byte(0x1006), read_byte(0x1007),
d) write_word(0x2004) -> second iteration of the minor loop
e) read_byte(0x1008), read_byte(0x1009), read_byte(0x100a), read_byte(0x100b),
f) write_word(0x2008) -> third iteration of the minor loop
g) read_byte(0x100c), read_byte(0x100d), read_byte(0x100e), read_byte(0x100f),
h) write_word(0x200c) -> last iteration of the minor loop
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6. dma_engine writes: TCD.saddr = 0x1010, TCD.daddr = 0x2010, TCD.citer = 1,
7. dma_engine writes: TCD.active = 0,
8. the channel retires -> one iteration of the major loop
The DMA goes idle or services next channel.
9. second hardware (ipd_req) requests channel service,
10. the channel is selected by arbitration for servicing,
11. dma_engine writes: TCD.done = 0, TCD.start = 0, TCD.active = 1,
12. dma_engine reads: channel TCD data from local memory to internal register file,
13. the source to destination transfers are executed as follows:
a) read_byte(0x1010), read_byte(0x1011), read_byte(0x1012), read_byte(0x1013),
b) write_word(0x2010) -> first iteration of the minor loop
c) read_byte(0x1014), read_byte(0x1015), read_byte(0x1016), read_byte(0x1017),
d) write_word(0x2014) -> second iteration of the minor loop
e) read_byte(0x1018), read_byte(0x1019), read_byte(0x101a), read_byte(0x101b),
f) write_word(0x2018) -> third iteration of the minor loop
g) read_byte(0x101c), read_byte(0x101d), read_byte(0x101e), read_byte(0x101f),
h) write_word(0x201c) -> last iteration of the minor loop -> major loop complete
14. dma_engine writes: TCD.saddr = 0x1000, TCD.daddr = 0x2000, TCD.citer = 2 (TCD.biter),
15. dma_engine writes: TCD.active = 0, TCD.done = 1, DMAINT[n] = 1,
16. the channel retires -> major loop complete
The DMAgoes idle or services the next channel.
12.2.6.5
12.2.6.5.1
TCD Status
Minor loop complete
There are two methods to test for minor loop completion when using software initiated service requests.
The first method is to read the TCD.citer field and test for a change. Another method may be extracted
from the sequence shown below. The second method is to test the TCD.start bit AND the TCD.active bit.
The minor loop complete condition is indicated by both bits reading zero after the TCD.start was written
to a one. Polling the TCD.active bit may be inconclusive because the active status may be missed if the
channel execution is short in duration.
The TCD status bits execute the following sequence for a software activated channel:
1. TCD.start = 1, TCD.active = 0, TCD.done = 0 (channel service request via software)
2. TCD.start = 0, TCD.active = 1, TCD.done = 0 (channel is executing)
3. TCD.start = 0, TCD.active = 0, TCD.done = 0 (channel has completed the minor loop and is idle) or
4. TCD.start = 0, TCD.active = 0, TCD.done = 1 (channel has completed the major loop and is idle)
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The SPP DMA Controller Module (SPP_DMA2)
The best method to test for minor loop completion when using hardware initiated service requests is to
read the TCD.citer field and test for a change. The hardware request and ackowledge handshakes signals
are not visible in the programmer’s model.
The TCD status bits execute the following sequence for a hardware activated channel:
1. ipd_req asserts (channel service request via hardware)
2. TCD.start = 0, TCD.active = 1, TCD.done = 0 (channel is executing)
3. TCD.start = 0, TCD.active = 0, TCD.done = 0 (channel has completed the minor loop and is idle) or
4. TCD.start = 0, TCD.active = 0, TCD.done = 1 (channel has completed the major loop and is idle)
For both activation types, the major loop complete status is explicitly indicated via the TCD.done bit.
The TCD.start bit is cleared automatically when the channel begins execution regardless of how the
channel was activated.
12.2.6.5.2
Active channel TCD reads
The DMA will read back the 'true' TCD.saddr, TCD.daddr, and TCD.nbytes values if read while a channel
is executing. The 'true' values of the saddr, daddr, and nbytes are the values the dma_engine is currently
using in its internal register file and not the values in the TCD local memory for that channel. The
addresses (saddr and daddr) and nbytes (decrements to zero as the transfer progresses) can give an
indication of the progress of the transfer. All other values are read back from the TCD local memory.
12.2.6.5.3
Preemption status
Preemption is only available when fixed arbitration is selected for channel arbitration modes. A
preempt-able situation is one in which a preempt-enabled channel is running and a higher priority request
becomes active. When the dma_engine is not operating in fixed group, fixed channel arbitration mode, the
determination of the relative priority of the actively running and the outstanding requests become
undefined. Channel and/or group priorities are treated as equal (or more exactly, constantly rotating) when
round-robin arbitration mode is selected.
The TCD.active bit for the preempted channel remains asserted throughout the preemption. The preempted
channel is temporarily suspended while the preempting channel executes one iteration of the major loop.
Two TCD.active bits set at the same time in the overall TCD map indicates a higher priority channel is
actively preempting a lower priority channel.
The worst case latency when switching to a preempt channel is the summation of:
• arbitration latency (2 cycles)
• bandwidth control stalls (if enabled)
• the time to execute two read/write sequences (including AHB bus holds; a system dependency
driven by the slave devices or the crossbar)
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The SPP DMA Controller Module (SPP_DMA2)
12.2.6.6
Channel Linking
Channel linking (or chaining) is a mechanism where one channel sets the TCD.start bit of another channel
(or itself) thus initiating a service request for that channel. This operation is automatically performed by
the dma_engine at the conclusion of the major or minor loop when properly enabled.
The minor loop channel linking occurs at the completion of the minor loop (or one iteration of the major
loop). The TCD.citer.e_link field are used to determine whether a minor loop link is requested. When
enabled, the channel link is made after each iteration of the major loop except for the last. When the major
loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be
made. For example, with the initial fields of:
TCD.citer.e_link
=1
TCD.citer.linkch
= 0xC
TCD.citer value
= 0x4
TCD.major.e_link
=1
TCD.major.linkch
= 0x7
will execute as:
1. minor loop done -> set channel 12 TCD.start bit
2. minor loop done -> set channel 12 TCD.start bit
3. minor loop done -> set channel 12 TCD.start bit
4. minor loop done, major loop done -> set channel 7 TCD.start bit
When minor loop linking is enabled (TCD.citer.e_link = 1), the TCD.citer field uses a nine bit vector to
form the current iteration count.
When minor loop linking is disabled (TCD.citer.e_link = 0), the TCD.citer field uses a 15 bit vector to form
the current iteration count. The bits associated with the TCD.citer.linkch field are concatenated onto the
citer value to increase the range of the citer.
Note: the TCD.citer.e_link bit and the TCD.biter.e_link bit must equal or a configuration error will be
reported. The citer and biter vector widths must be equal in order to calculate the major loop, half-way
done interrupt point.
12.2.6.7
Dynamic Programming
This section provides recommended methods to change the programming model during channel execution.
12.2.6.7.1
Dynamic priority changing
The following two options are recommended for dynamically changing channel priority levels:
1. switch to round-robin channel arbitration mode, change the channel priorities, then switch back to
fixed arbitration mode,
2. disable all the channels, then change the channel priorities, then enable the appropriate channels.
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The SPP DMA Controller Module (SPP_DMA2)
12.2.6.7.2
Dynamic channel linking and dynamic scatter/gather
Dynamic channel linking and dynamic scatter/gather is the process of changing the TCD.major.e_link or
TCD.e_sg bits during channel execution. These bits are read from the TCD local memory at the end of
channel execution thus allowing the user to enable either feature during channel execution.
Because the user is allowed to change the configuration during execution, a coherency model is needed.
Consider the scenario where the user attempts to execute a dynamic channel link by enabling the
TCD.major.e_link bit at the same time the dma_engine is retiring the channel. The TCD.major.e_link
would be set in the programmer’s model, but it would be unclear whether the actual link was made before
the channel retired.
The following coherency model is recommended when executing a dynamic channel link or dynamic
scatter/gather request:
1. set the TCD.major.e_link bit,
2. read back the TCD.major.e_link bit,
3. test the TCD.major.e_link request status:
a) if the bit is set, the dynamic link attempt was successful,
b) if the bit is cleared, the attempted dynamic link did not succeed, the channel was already
retiring.
This same coherency model is true for dynamic scatter/gather operations. For both dynamic requests, the
TCD local memory controller forces the TCD.major.e_link and TCD.e_sg bits to zero on any writes to a
channel’s TCD.word7 once that channel’s TCD.done bit is set indicating the major loop is complete.
Note: The user must clear the TCD.done bit before writing the TCD.major.e_link or TCD.e_sg bits. The
TCD.done bit is cleared automatically by the dma_engine once a channel begins execution.
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The SPP DMA Controller Module (SPP_DMA2)
12.2.6.8
Hardware Request Release Timing
This section provides a timing diagram for deasserting the ipd_req hardware request signal. Figure 12-25
shows an encapsulating write (i.e. 2 word reads -> 1 longword write) with grey indicating the release of
the ipd_req hardware request signal.
Figure 12-25. ipd_req removal
hclk
htrans
AHB_AP
rd1
rd2
wr1,2
rd3
rd4
wr3,4
hwrite
hready
ipd_req
ipd_ack
ipd_done
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Chapter 13
Miscellaneous Control Module (MCM)
13.1
Introduction
The Miscellaneous Control Module (MCM), formerly known as the System Control Module (SCM),
provides a myriad of miscellaneous control functions for the device including program-visible information
about configuration and revision levels, a reset status register, a software watchdog timer, wakeup control
for exiting sleep modes, and optional features such as an address map for the device’s crossbar switch,
information on memory errors reported by error-correcting codes and/or generic access error information
for certain processor cores.
13.1.1
Overview
The Miscellaneous Control Module is mapped into the IPS space and supports a number of miscellaneous
control functions for the device.
13.1.2
Features
The MCM includes these features:
• Program-visible information on the device configuration and revision
• Reset status register (MRSR)
• Software watchdog timer (SWT) with programmable system reset or interrupt response which runs
on a separate, asynchronous clock
• Wakeup control for exiting sleep modes
• Optional address map for device’s crossbar switch (AXBS)
• Optional registers for capturing information on memory errors if error-correcting codes (ECC) are
implemented
• Optional registers to specify the generation of single- and double-bit memory data inversions for
test purposes if error-correcting codes are implemented
• Optional access address information for faulted memory accesses for certain processor core
micro-architectures, e.g. ARM7TDMI-S
• Non-Maskable Interrupt with programmable polarity.
13.2
Memory Map/Register Definition
This section details the programming model for the Miscellaneous Control Module. This is a 128-byte
space mapped to the region serviced by an IPS bus controller.
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Memory Map/Register Definition
13.2.1
Memory Map
The Miscellaneous Control Module does not include any logic which provides access control. Rather, this
function is supported using the standard access control logic provided by the IPS controller.
Table 13-1. MCM 32-bit Memory Map
MCM
Offset
Register
0x00
Processor Core Type (PCT)
Revision (REV)
0x04
AXBS Master Configuration
(AMC)
AXBS Slave Configuration
(ASC)
0x08
IPS Module Configuration (IMC)
0x0c
Reserved
Misc Reset Status
(MRSR)
0x10
Reserved
Misc Wakeup Control
(MWCR)
0x14
Misc Software Watchdog Timer Control
(MSWTCR)
Reserved
0x18
Reserved
Misc SWT
Service (MSWTSR)
0x1c
Reserved
Misc Interrupt
(MIR)
0x20
AXBS Address Map Register (AAMR)
0x24
Miscellaneous User-Defined Control Register (MUDCR)
0x28
Reserved
0x28
0x2c
NMI Control (NMICR)
Reserved
PPMRS
PPMRC
PPMRS1
0x30
PPMRC1
PPMRH[63:32]
0x34
PPMRL[31:0]
0x38
PPMR1H[63:32]
0x3c
PPMR1L[31:0]
0x40
Reserved
ECC Configuration
(ECR)
0x44
Reserved
ECC Status
(ESR)
Reserved
0x48
ECC Error Generation (EEGR)
0x4c
Reserved
0x50
Flash ECC Address (FEAR)
Flash ECC Master
(FEMR)
Reserved
0x54
Reserved
0x58
0x5c
Flash ECC Data (FEDR)
0x60
RAM ECC Address (REAR)
0x64
Flash ECC Attributes
(FEAT)
Reserved
RAM ECC Syndrome
(RESR)
RAM ECC Master
(REMR)
0x68
Reserved
0x6c
RAM ECC Data (REDR)
0x40 - 0x6c
Reserved
RAM ECC Attributes
(REAT)
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Memory Map/Register Definition
Table 13-1. MCM 32-bit Memory Map (Continued)
0x70 - 0x7c
Reserved
0x70
Core Fault Address (CFADR)
0x74
Core Fault Location 1
(CFLOC1)
Reserved
Core Fault Location
(CFLOC)
0x78
Reserved
0x7c
Core Fault Data (CFDTR)
13.2.2
Core Fault Attributes
(CFATR)
Register Descriptions
Attempted accesses to reserved addresses result in an error termination, while attempted writes to
read-only registers are ignored and do not terminate with an error. Unless noted otherwise, writes to the
programming model must match the size of the register, e.g., an n-bit register only supports n-bit writes,
etc. Attempted writes of a different size than the register width produce an error termination of the bus
cycle and no change to the targeted register.
13.2.2.1
Processor Core Type (PCT)
The PCT is a 16-bit read-only register specifying the architecture of the processor core in the device. The
state of this register is defined by a module input signal; it can only be read from the IPS programming
model. Any attempted write is ignored.
See Figure 13-1 and Table 13-2 for the Processor Core Type definition.
Register address: MCM Base + 0x00
15
14
R
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PCT[15:0]
W
Reset
PCT[15:0]
Figure 13-1. Processor Core Type (PCT) Register
Table 13-2. PCT Field Descriptions
Field
15–0
PCT[15:0
Description
Processor Core Type. The device supports ARM, ColdFire and PowerPC cores. The following values
identify the specific core complexes:
A700
ARM7
A900
ARM9
A110
ARM11
CF20
V2 ColdFire
CF30
V3 ColdFire
CF40
V4 ColdFire
CF50
V5 ColdFire
E650
Z650 PowerPC
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Memory Map/Register Definition
13.2.2.2
Revision (REV)
The REV is a 16-bit read-only register specifying a revision number. The state of this register is defined
by an input signal; it can only be read from the IPS programming model. Any attempted write is ignored.
See Figure 13-2 and Table 13-3 for the Revision definition.
Register address: MCM Base + 0x02
15
14
13
12
11
10
9
R
8
7
6
5
4
3
2
1
0
REV[15:0]
W
Reset
REV[15:0]
Figure 13-2. Revision (REV) Register
Table 13-3. REV Field Descriptions
Field
Description
15–0
REV[15:0]
Revision. The REV[15:0] field is specified by an input signal to define a software-visible revision number.
13.2.2.3
AXBS Master Configuration (AMC)
The AMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the
device’s AMBA-AHB Crossbar Switch (AXBS). The state of this register is defined by a module input
signal; it can only be read from the IPS programming model. Any attempted write is ignored.
See Figure 13-3 and Table 13-4 for the AXBS Master Configuration definition.
Register address: MCM Base + 0x04
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
AMC[7:0]
0
0
0
0
0
0
0
0
AMC[7:0]
R
7
6
5
4
3
2
1
0
W
Reset
Figure 13-3. AXBS Master Configuration (AMC) Register
Table 13-4. AMC Field Descriptions
Field
15–8
7–0
AMC[7:0]
Description
Reserved, should be cleared.
AXBS Master Configuration.
AMCn = 0 if a bus master connection to AXBS input port “n” is absent
AMCn = 1 if a bus master connection to AXBS input port “n” is present
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13.2.2.4
AXBS Slave Configuration (ASC)
The ASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the
device’s AMBA-AHB Crossbar Switch (AXBS), plus a 1-bit flag defining the datapath width (DP64). The
state of this register is defined by a module input signal; it can only be read from the IPS programming
model. Any attempted write is ignored.
See Figure 13-4 and Table 13-5 for the AXBS Slave Configuration definition.
Register address: MCM Base + 0x06
15
R DP64
14
13
12
11
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
ASC[7:0]
0
0
0
0
0
0
0
ASC[7:0]
2
1
0
W
Reset DP64
Figure 13-4. AXBS Slave Configuration (ASC) Register
Table 13-5. ASC Field Descriptions
Field
Description
15
DP64
64-bit Datapath.
0 The datapath width is 32 bits
1 The datapath width is 64 bits
14–8
Reserved, should be cleared.
7–0
ASC[7:0]
13.2.2.5
AXBS Slave Configuration.
ASCn = 0 if a bus slave connection to AXBS output port “n” is absent
ASCn = 1 if a bus slave connection to AXBS output port “n” is present
IPS Module Configuration (IMC)
The IMC is a 32-bit read-only register identifying the presence/absence of the 32 low-order IPS peripheral
modules connected to the primary IPS bus controller. The state of this register is defined by a module input
signal; it can only be read from the IPS programming model. Any attempted write is ignored.
See Figure 13-5 and Table 13-6 for the IPS Module Configuration definition.
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Memory Map/Register Definition
Register address: MCM Base + 0x08
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
MC[31:16]
W
Reset
MC[031:16]
15
14
13
12
11
10
9
8
R
7
MC[15:0]
W
Reset
MC[15:0]
Figure 13-5. IPS Module Configuration (IMC) Register
Table 13-6. IPS IMC Field Descriptions
Field
Description
31–0
MC[31:0]
13.2.2.6
IPS Module Configuration,
MCn = 0 if an IPS module connection to decoded slot “n” is absent
MCn = 1 if an IPS module connection to decoded slot “n” is present
Miscellaneous Reset Status Register (MRSR)
The MRSR contains a bit for each of the reset sources to the device. An asserted bit indicates the last type
of reset that occurred. Only one bit is set at any time in the MRSR, reflecting the cause of the most recent
reset as signalled by device reset input signals. The MRSR can only be read from the IPS programming
model. Any attempted write is ignored. See Figure 13-6 and Table 13-7 for the Miscellaneous Reset Status
Register definition.
Register address: MCM Base + 0x0f
R
7
6
5
4
3
2
1
0
POR
DIR
SWTR
0
0
0
0
0
*
*
*
0
0
0
0
0
W
Reset
Figure 13-6. Miscellaneous Reset Status (MRSR) Register
Table 13-7. MRSR Field Descriptions
Field
Description
7
POR
Power-On Reset.
1 Last recorded event was caused by a power-on reset (based on a device input signal)
6
DIR
Device Input Reset.
1 Last recorded event was a reset caused by a device input reset.
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Memory Map/Register Definition
Table 13-7. MRSR Field Descriptions (Continued)
Field
Description
5
SWTR
Software Watchdog Timer Reset.
1 Last recorded event was a reset caused by the MCM’s software watchdog timer.
4–0
13.2.2.7
Reserved, should be cleared.
Miscellaneous Wakeup Control Register (MWCR)
Implementation of low-power sleep modes and exit from these modes via an interrupt require
communication between the MCM, the interrupt controller and external logic typically associated with
phase-locked loop clock generation circuitry. The Miscellaneous Wakeup Control Register (MWCR)
provides an 8-bit register controlling entry into these types of low-power modes as well as definition of
the interrupt level needed to exit the mode.
The following sequence of operations is generally needed to enable this functionality. Note that the exact
details are likely to be system-specific.
1. The processor core loads the appropriate data value into the MWCR, setting the ENBWCR bit and
the desired interrupt priority level.
2. At the appropriate time, the processor ceases execution. The exact mechanism varies by processor
core. In some cases, a processor-is-stopped status is signaled to the MCM and external logic. This
assertion, if properly enabled by MWCR[ENBWCR], causes the selected external, low-power
mode, as specified by MWCR[LPMD], to be entered, and the appropriate clock signals disabled.
In most implementations, there are multiple low-power modes, where the exact clocks to be
disabled vary across the different modes.
3. After entering the low-power mode, the interrupt controller enables a special combinational logic
path which evaluates all unmasked interrupt requests. The device remains in this mode until an
event which generates an unmasked interrupt request with a priority level greater than the value
programmed in the MWCR[PRILVL] occurs.
4. Once the appropriately-high interrupt request level arrives, the interrupt controller signals its
presence, and the MCM responds by asserting an “exit_low_power_mode” signal.
5. The external logic senses the assertion of the “exit” signal, and re-enables the appropriate clock
signals.
6. With the processor core clocks enabled, the core handles the pending interrupt request.
See Figure 13-7 and Table 13-8 for the Miscellaneous Wakeup Control Register definition.
Register address: MCM Base + 0x13
7
6
R
5
4
3
2
1
0
0
ENBWCR
LPMD[1:0]
PRILVL[3:0]
W
Reset
0
0
0
0
0
0
0
0
Figure 13-7. Miscellaneous Wakeup Control (MWCR) Register
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Memory Map/Register Definition
Table 13-8. MWCR Field Descriptions
Field
Description
7
ENBWCR
Enable WCR.
0 MWCR is disabled.
1 MWCR is enabled.
6
Reserved, should be cleared.
5–4
LPMD[1:0]
Low Power Mode. Used to select the low-power mode the chip enters once the ColdFire core executes
the STOP instruction. These bits must be written prior to instruction execution for them to take effect. The
LPMD bits are readable and writable in all modes.
0b00 Run
0b01 Doze
0b10 Wait
0b11 Stop
Note: If MWCR[LPMD] is cleared, then the device will stop executing code upon issue of a STOP
instruction. However, no clocks will be disabled.
3–0
PRILVL[3:0]
Interrupt Priority Level. The interrupt priority level is a core-specific definition. It specifies the interrupt
priority level needed to exit the low-power mode. Specifically, an unmasked interrupt request of a priority
level greater than the PRILVL value is required to exit the mode.
Certain interrupt controller implementations include logic associated with this priority level that restricts
the data value contained in this field to a [0, maximum - 1] range. See the specific interrupt controller
module for details.
13.2.2.8
Miscellaneous Software Watchdog Timer Control Register (MSWTCR)
The software watchdog timer (SWT) prevents system lockup if the software becomes trapped in a loop
with no controlled exit or if a bus transaction becomes “hung.” The software watchdog timer can be
enabled or disabled through the MSWTCR[SWE]. By default, it is disabled. The SWT operates in a
separate, asynchronous clock domain and contains clock domain synchronizers as the communication
mechanism between the system clock domain and the software watchdog timer domain. If enabled, the
watchdog timer requires the periodic execution of a software watchdog servicing sequence. If this periodic
servicing action does not occur, the timer expires, resulting in a watchdog timer interrupt or a hardware
reset, as programmed in the MSWTCR[SWRI].
There are three user-defined responses to a time-out:
1. The MSWTCR[SWRI] can specify the assertion of a watchdog timer interrupt.
2. The MSWTCR[SWRI] can specify the immediate assertion of a system reset.
3. The MSWTCR[SWRI] can specify a sequence of responses. Upon the first time-out, a watchdog
timer interrupt is asserted. If this time-out condition is not serviced before a second time-out
occurs, the watchdog timer asserts the system reset signal in response to the second time-out. This
configuration supports a more graceful response to watchdog time-outs: first attempting an
interrupt to notify the system, and if that fails, generating a system reset.
In addition to these three basic modes of operation, the watchdog timer also supports a “windowed” mode
of operation. In this mode, the time-out period is divided into 4 equal segments and the actual servicing of
the watchdog timer must occur during the last segment, i.e., during the last 25% of the time-out period. If
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Memory Map/Register Definition
the watchdog timer is serviced anytime in the first 75% of the time-out period, an immediate system reset
occurs.
Throughout Section 13.2.2.8, “Miscellaneous Software Watchdog Timer Control Register (MSWTCR),
there are numerous references to the generation of a system reset. MCM’s behavior during this process is
detailed below. When the watchdog timer expires and MSWTCR[SWRI] is programmed for a reset (either
as the initial or secondary response), the MCM generates a watchdog timer reset output signal which is
driven off the device where it is typically combined with other reset signals and driven throughout the
system. The combined reset input signal is driven back to the device and MCM, where MRSR[SWTR] can
be set and the appropriate action taken by the core and device logic.
The watchdog timer logic also sends an interrupt request to the device’s interrupt controller.
To prevent the watchdog timer from interrupting or resetting, the MSWTSR must be serviced by
performing the following sequence:
• Write 0x55 to the MSWTSR.
• Write 0xAA to the MSWTSR.
Both writes must occur in this order before the time-out, but any number of instructions can be executed
between the two writes. This definition allows interrupts and exceptions to occur, if necessary, between
the two writes. The timer value is constantly compared with the time-out period specified by
MSWTCR[SWT]. Any write to the MSWTCR resets the watchdog timer. In addition, there is a read-only
control flag included in the MSWTCR to prevent accidental updates to this control register from changing
the desired system configuration.
If the second write occurs at the exact same cycle as the time-out condition is reached, the clear takes
precedence and the time-out response suppressed.
The MSWTCR controls the software watchdog timer, time-out periods, and time-out response. The
register can be read or written at any time. At system reset, the software watchdog timer is disabled. See
Figure 13-8 and Table 13-9 for the Miscellaneous Software Watchdog Timer Control Register definition.
R
W
Reset
14
13
12
11
10
9
8
7
0
0
0
0
0
SWRWH
15
SWCIN16
Register address: MCM Base + 0x16
SWE
0
0
0
RO
0
0
0
0
0
0
6
5
4
3
SWRI[1:0]
0
0
2
1
0
0
0
SWT[4:0]
0
0
0
Figure 13-8. Miscellaneous Software Watchdog Timer Control (MSWTCR) Register
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Memory Map/Register Definition
Table 13-9. MSWTCR Field Definitions
Field
Description
15
RO
Read-Only.
0 MSWTCR can be read or written.
1 MSWTCR can only be read. A system reset is required before this register can again be written. The
setting of this bit is intended to prevent accidental writes of the MSWTCR from changing the defined
system watchdog configuration.
14–10
Reserved, should be cleared.
9
SWCIN16
Force SWT CarryIn16. This control bit is intended for use only when testing the operation of the SWT.
When asserted, it forces the actual timer to increment by 65537 (216 + 1) each cycle rather than simply
by 1. It allows testing of the large SWT time-out values without actually incrementing through the entire
dynamic range.
8
SWRWH
Software Watchdog Run While Halted.
0 SWT stops counting if the processor core is halted.
1 SWT continues to count even while the processor core is halted.
7
SWE
Software Watchdog Enable
0 SWT is disabled.
1 SWT is enabled.
6–5
SWRI[1:0]
Software Watchdog Reset/Interrupt.
00 If a time-out occurs, the SWT generates an interrupt to the processor core. The programming of the
interrupt level for the SWT is system-specific. Typically, the highest priority interrupt level is used to
signal the SWT.
01 The first time-out generates an interrupt to the processor, and if not serviced, then a second time-out
generates a system reset and sets the MRSR[SWTR] flag.
10 If a time-out occurs, the SWT generates a system reset. MRSR[SWTR] is set.
11 The SWT functions in a “window” mode of operation. For this mode, the servicing of the MSWSR must
occur during the last 25% of the time-out period. Any writes to the MSWSR during the first 75% of the
time-out period generate an immediate system reset. Likewise, if the MSWSR is not serviced during
the last 25% of the time-out period, then a system reset is generated. For any type of reset response,
the MRSR[SWTR] flag is set.
As noted previously, the generation of a system reset actually causes the MCM module to assert an
output signal which is driven out of the device where it is combined with other reset signals and then
driven throughout the system.
4–0
SWT[4:0]
Software Watchdog Time-Out Period. This field selects the time-out period for the SWT. At reset, this field
is cleared selecting the minimum time-out period, but the SWT is disabled since MSWTCR[SWE] = 0.
In general, the value in this field defines the bit position within the 32-bit counter that specifies the time-out
period. Thus, if SWT[4:0] = n, then the time-out period is 2n system clock cycles. Since it is not practical
to operate the software watchdog timer with very short time-out periods, data values of [0-7] are forced
to a value of 8, defining a minimum time-out period of 256 system clock cycles. The logic which forces the
minimum value to 8 does not affect the contents of this field in the register.
For SWT[4:0] = n, then time-out period = 2n system clock cycles, n = 8,9,..., 31.
13.2.2.9
Miscellaneous Software Watchdog Timer Service Register (MSWTSR)
The software service sequence must be performed using the MSWTSR as a data register to prevent a SWT
time-out. The service sequence requires two writes to this data register: first a write of 0x55 followed by
a write of 0xAA. Both writes must be performed in this order prior to the SWT time-out, but any number
of instructions or accesses to the SWSR may occur between the two writes. If the SWT has already timed
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Memory Map/Register Definition
out, writing to this register has no effect in negating the SWT interrupt or reset. Figure 13-9 illustrates the
MSWTSR.
Register address: MCM Base + 0x1b
7
6
5
4
3
2
1
0
—
—
—
—
R
SWSR[7:0]
W
Reset
—
—
—
—
Figure 13-9. Miscellaneous Software Watchdog Timer Service (MSWTSR) Register
If the software watchdog timer is enabled (MSWTCR[SWE] = 1), then any write of a data value other
than 0x55 or 0xAA generates an immediate system reset, regardless of the value in the MSWTCR[SWRI]
field.
13.2.2.10 Miscellaneous Interrupt Register (MIR)
All interrupt requests associated with MCM are collected in the MIR register. This includes the software
watchdog timer interrupt and the processor core system bus fault interrupt.
During the appropriate interrupt service routine handling these requests, the interrupt source contained in
the MCMIR must be explicitly cleared. See Figure 13-10 and Table 13-10.
Register address: MCM Base + 0x1f
R
7
6
5
4
3
2
0
0
0
0
0
0
1
0
CFEI
SWTIC
0
0
W
Reset
0
0
0
0
0
0
Figure 13-10. Miscellaneous Interrupt (MIR) Register
Table 13-10. MIR Field Descriptions
Field
7–2
Description
Reserved, should be cleeared.
1
CFEI
Code Fault Error Interrupt Flag.
0 An enabled processor core system bus fault has not occurred..
1 An enabled processor core system bus fault has occurred. The faulting address, attributes (and
possibly write data) are captured in the CFADR, CFATR, and CFDTR registers. The error interrupt is
only enabled if CFLOC[ECFEI] is set. The interrupt request is negated by writing a 1 to this bit. Writing
a 0 has no effect..
0
SWTIC
Software Watchdog Interrupt Flag.
0 An SWT interrupt has not occurred.
1 An SWT interrupt has occurred. The interrupt request is negated by writing a 1 to this bit. Writing a 0
has no effect.
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Memory Map/Register Definition
13.2.2.11 AXBS Address Map Register (AAMR)
For certain designs, the static decoding of the upper bits of the AMBA-AHB address bus to steer requests
to the appropriate crossbar switch slave may not be sufficient. For those designs, the AAMR provides an
optional register which implements additional capability for AXBS request steering. This register provides
a program-visible address steering mechanism by supporting the mapping of any 512 MByte address space
to any of the AXBS slave connections.
The AAMR is divided into eight 4-bit fields providing an enable bit and a 3-bit slave number. Thus, the
upper 3 bits of the AMBA-AHB address (HADDR[31:29]) are used to index into the AAMR to select a
corresponding 3-bit vector which defines the targeted AXBS slave.
The AAMR is initially loaded at reset with a 32-bit value provided as an input. For subsequent writes to
the AAMR, the hardware invokes the following synchronization mechanism:
1. The 32-bit IPS write to the AAMR loads the pending address map operand into a temporary
register.
2. The pending AAMR write causes the MCM to assert a control signal which forces the AXBS into
a “halted” state.
3. The IPS write cycle is terminated normally.
4. Once the AXBS module indicates it has stalled all bus master transactions and entered the halted
state, then MCM loads the pending address map operand into the AAMR, effectively enabling the
new mapping.
5. MCM then releases the halt request signal to the AXBS, allowing it to resume operation with the
just-loaded address map.
The device is guaranteed to function properly after changing the value of the AAMR if the write to the
register is followed by a sufficient number of NOP instructions necessary to flush out the depth of the
processor pipeline.
The AAMR can only be written in its entirety, i.e., only 32-bit writes are supported. Any attempted write
of a smaller data size (e.g., 8- or 16-bit value) generates an error response. See Figure 13-11 and
Table 13-11 for the AXBS Address Map Register definition.
Register address: MCM Offset + 0x20
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
EA7
A7Slave
EA6
A6Slave
EA5
A5Slave
EA4
A4Slave
W
Reset
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
EA3
A3Slave
EA2
A2Slave
EA1
A1Slave
EA0
A0Slave
W
Reset
0
0
0
0
1
0
1
1
aamr_init[7:0]
Figure 13-11. AXBS Address Map (AAMR) Register
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Memory Map/Register Definition
where aamr_init[7:0] is the value at reset controlled by the reset mode. The MCM only allows the
following values to be written to the AAMR[31:0] 0xF000_00{00, 08, 09, 0B, 80, 90, B0, 89, 8B, 98, 9B,
B8, B9, 99, and BB}. If the flash is not valid, 0x8 cannot be written to either of the two least-significant
nibbles of the AAMR. Likewise, if the EIM is not valid, 0x9 cannot be written to AAMR[7:4] or
AAMR[3:0]. The register will not update if an attempt is made to write an illegal value to the AAMR
register.
Table 13-11. AAMR Field Descriptions
Field
Description
EAn
Enable Address Region n.
0 The 512 MByte address region associated with HADDR[31:29] = n is disabled, and not mapped to an
AXBS slave. Accesses to this memory region terminate with an error response.
1 The 512 MByte address region associated with HADDR[31:29] = n is enabled, and mapped to the
AXBS slave defined by AnSlave.
AnSlave
Address n Slave Number.
1 AnSlave defines the AXBS slave mapped to the memory region defined by HADDR[31:29] = n
13.2.2.12 Miscellaneous User-Defined Control Register (MUDCR)
The MUDCR provides a program-visible register for user-defined control functions. It typically is used as
configuration control for miscellaneous SoC-level modules. The contents of this register is simply output
from MCM to other modules where the user-defined control functions are implemented. See Figure 13-12
and Table 13-12 for the Miscellaneous User-Defined Control Register definition.
Register address: MCM Base + 0x24
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
MUDCR[31:16]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
R
MUDCR[15:0]
W
Reset
0
0
0
0
0
0
0
0
0
Figure 13-12. Miscellaneous User-Defined Control (MUDCR) Register
Table 13-12. MUDCR Field Descriptions
Field
31–0
MUDCR
Description
User-Defined control Register.
0 The control associated with this MUDCR bit is disabled.
1 The control associated with this MUDCR bit is enabled.
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Memory Map/Register Definition
13.2.2.13 NMI Control Register (NMICR)
The NMICR is an 8-bit register controlling the operation of a non-maskable interrupt. This functionality
is specifically provided to compensate for processor cores which do not directly support this type of
interrupt request. This logic operates by forcing error terminations (or aborts) on instruction fetches once
a properly-enabled NMI request is asserted. The resulting exception processing of the prefetch abort then
provides the required NMI service routine. The NMI input signal is treated as an edge-sensitive event, and
the request must be negated before a subsequent NMI is recognized. The required sequence of operations
is detailed below:
1. The NMICR is written to enable the non-maskable request and specify the polarity of the input
signal. The NMICR is a write-once register and any subsequent writes to this register are ignored.
2. Once an enabled NMI request is detected, the MCM logic begins forcing error terminations on all
instruction prefetches from the processor. At the same time, both FIQ and IRQ interrupt requests
are disabled by this logic.
3. The error tagging of instruction prefetches continues until the processor recognizes the prefetch
abort exception and accesses the exception vector at address 0x0000_000c.
4. Once the prefetch abort exception handler begins execution, the state of the NMICR[NMI_PEND]
flag is checked by the handler. If NMI_PEND = 1, then the prefetch abort was generated by a
pending NMI request, and execution continues in the appropriate NMI service routine.
5. Eventually, the source of the NMI request is negated. The service routine must properly adjust the
value of the CPSR to enable/disable FIQ and IRQ interrupts as required. The MCM logic disables
both the FIQ and IRQ inputs to the processor core while a properly-enabled NMI request is
asserted.
See Table 13-13 and Table 13-13 for the NMI Control Register definition.
Register address: MCM Base + 0x2b
7
R NMI_PEND
6
5
4
3
2
0
0
0
0
0
1
0
NMI_POL
NMI_ENB
0
0
W
Reset
—
—
—
—
—
0
Figure 13-13. NMI Control (NMICR) Register
Table 13-13. NMICR Field Descriptions
Field
7
NMI_PEND
6–2
Description
Non-Maskable Interrupt Pending.
0 Non-Maskable Interrupt is not pending
1 Non-Maskable Interrupt is pendin
Reserved, should be cleared.
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Memory Map/Register Definition
Table 13-13. NMICR Field Descriptions (Continued)
Field
Description
1
NMI_POL
Non-Maskable Interrupt Polarity.
0 Non-Maskable Interrupt is active low
1 Non-Maskable Interrupt is active high
0
NMI_ENB
Non-Maskable Interrupt Enable.
0 Non-Maskable Interrupt is disabled
1 Non-Maskable Interrupt is enabled
clk
nmicr[nmi_enb]
nmicr[nmi_pol]
nmi_b
nmicr[nmi_pend]
fiq_b
irq_b
cpu_addr[*]
op1 if1 if2 if3 0xc
cpu_operand
cpu_data[*]
vec
cpu_abort
nmi_fsm[*]
idle
active_nmi
wf_nmi_negate
idle
Figure 13-14. Non-Maskable Interrupt Operation Timing
13.2.2.14 Peripheral Power Management Registers (PPMR)
The Miscellaneous Control Module implements two 64-bit IPS peripheral power management control
registers along with 4 additional registers for easy manipulation of these configuration registers.
13.2.2.14.1 Peripheral Power Management Set Register (PPMRS)
The PPMRS register provides a simple memory-mapped mechanism to set a given bit in the PPMR{H,L}
registers to disable the clock for a given IPS module without the need to perform a read-modify-write on
the PPMR. The data value on a register write causes the corresponding bit in the PPMR{H,L} register to
be set. A data value of 64 to 127 provides a global set function, forcing the entire contents of the
PPMR{H,L} to be set, disabling all IPS module clocks. Reads of this register return all zeroes. See
Figure 13-15 and Figure 13-14 for the PPMRS definition.
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Memory Map/Register Definition
Register address: MCM Base + 0x2c
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
PPMRS[6:0]
—
0
0
0
0
Figure 13-15. Peripheral Power Management Set (PPMRS) Register
Table 13-14. Peripheral Power Management Set (PPMRS) Field Descriptions
Field
Description
7
Reserved, should be cleared.
6–0
PPMRS[6:0]
Set Module Clock Disable.
0-63
Set corresponding bit in PPMR{H,L}, disabling the module clock.
64-127 Set all bits in PPMR{H,L}, disabling all the module clocks.
13.2.2.14.2 Peripheral Power Management Clear Register (PPMRC)
The PPMRC register provides a simple memory-mapped mechanism to clear a given bit in the
PPMR{H,L} registers to enable the clock for a given IPS module without the need to perform a
read-modify-write on the PPMR. The data value on a register write causes the corresponding bit in the
PPMR{H,L} register to be cleared. A data value of 64 to 127 provides a global clear function, forcing the
entire contents of the PPMR{H,L} to be zeroed, enabling all IPS module clocks. In the event on
simultaneous writes of the PPMRS and PPMRC, the write to the PPMRC takes priority. Reads of this
register return all zeroes. See Figure 13-16 and Figure 13-15 for the PPMRC definition.
Register address: MCM Base + 0x2d
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
PPMRC[6:0]
—
0
0
0
0
0
Figure 13-16. Peripheral Power Management Clear (PPMRC) Register
Table 13-15. Peripheral Power Management Clear (PPMRC) Field Descriptions
Field
7
6–0
PPMRC[6:0]
Description
Reserved, should be cleared.
Clear Module Clock Disable.
0-63
Clear corresponding bit in PPMR{H,L}, enabling the module clock.
64-127 Clear all bits in PPMR{H,L}, enabling all the module clocks.
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Memory Map/Register Definition
13.2.2.14.3 Peripheral Power Management Set Register 1 (PPMRS1)
The PPMRS1 register provides a simple memory-mapped mechanism to set a given bit in the
PPMR1{H,L} registers to disable the clock for a given IPS module without the need to perform a
read-modify-write on the PPMR1. The data value on a register write causes the corresponding bit in the
PPMR1{H,L} register to be set. A data value of 64 to 127 provides a global set function, forcing the entire
contents of the PPMR1{H,L} to be set, disabling all IPS module clocks. Reads of this register return all
zeroes. See Figure 13-17 and Figure 13-16 for the PPMRS1 definition.
Register address: MCM Base + 0x2e
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
PPMRS1[6:0]
Reset
—
0
0
0
0
0
Figure 13-17. Peripheral Power Management Set 1 (PPMRS1) Register
Table 13-16. Peripheral Power Management Set 1 (PPMRS1) Field Descriptions
Field
7
Description
Reserved, should be cleared.
6–0
Set Module Clock Disable.
PPMRS1[6:0] 0-63
Set corresponding bit in PPMR1{H,L}, disabling the module clock.
64-127 Set all bits in PPMR1{H,L}, disabling all the module clocks.
13.2.2.14.4 Peripheral Power Management Clear Register 1 (PPMRC1)
The PPMRC1 register provides a simple memory-mapped mechanism to clear a given bit in the
PPMR1{H,L} registers to enable the clock for a given IPS module without the need to perform a
read-modify-write on the PPMR1. The data value on a register write causes the corresponding bit in the
PPMR1{H,L} register to be cleared. A data value of 64 to 127 provides a global clear function, forcing the
entire contents of the PPMR1{H,L} to be zeroed, enabling all IPS module clocks. In the event on
simultaneous writes to the PPMRS1 and PPMRC1, the write to the PPMRC1 takes priority. Reads of this
register return all zeroes. See Figure 13-18 and Figure 13-17 for the PPMRC1 definition.
Register address: MCM Base + 0x2f
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
W
Reset
PPMRC1[6:0]
—
0
0
0
0
0
Figure 13-18. Peripheral Power Management Clear 1 (PPMRC1) Register
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
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Memory Map/Register Definition
Table 13-17. Peripheral Power Management Clear 1 (PPMRC1) Field Descriptions
Field
Description
7
Reserved, should be cleared.
6–0
Clear Module Clock Disable.
PPMRC1[6:0] 0-63
Clear corresponding bit in PPMR1{H,L}, enabling the module clock.
64-127 Clear all bits in PPMR1{H,L}, enabling all the module clocks.
13.2.2.14.5 Peripheral Power Management Register (PPMR{H,L})
The PPMR{H,L} registers provide a bit map for controlling the generation of the module clocks for each
decoded address space associated with the AIPS controller. Each AIPS controller decodes the mapped
address space into sixty-four 16 KByte “slots” (32 on-platform and 32 off-platform) plus a 63 MByte
off-platform global region. The PPMR provides a unique control bit for each of these address spaces that
defines whether the module clock for the given space is enabled or disabled. It is software’s responsibility
to appropriately disable module clocks using the PPMR only when a module is completely unused or
quiescent.
Since the operation of the crossbar switch, the AIPS controller and the Miscellaneous Control Module
(MCM) are fundamental to the operation of the core platform, the clocks for these three modules cannot
be disabled.
The individual bits of the PPMR can be modified using a read-modify-write to this register directly or
indirectly through writes to the PPMRS and PPMRC registers to set/clear individual bits. If the static
module enable is negated, the appropriate PPMR bit is automatically set by MCM after the negation of the
platform reset and cannot be altered by any subsequent IPS writes.
See Figure 13-19, Figure 13-20, and Figure 13-18 for the PPMR definition.
Register address: MCM Base + 0x0030 (PPMRH)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CD63 CD62 CD61 CD60 CD59 CD58 CD57 CD56 CD55 CD54 CD53 CD52 CD51 CD50 CD49 CD48
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CD47 CD46 CD45 CD44 CD43 CD42 CD41 CD40 CD39 CD38 CD37 CD36 CD35 CD34 CD33 CD32
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-19. Peripheral Power Management Register High (PPMRH)
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Memory Map/Register Definition
Register address: MCM Base + 0x0034 (PPMRL)
31
30
29
28
27
26
25
24
23
22
R
21
20
19
18
17
0
CD31 CD30 CD29 CD28 CD27 CD26 CD25 CD24 CD23 CD22
16
0
CD20 CD19 CD18 CD17
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
CD15 CD14 CD13 CD12 CD11 CD10 CD09 CD08 CD07 CD06 CD05 CD04 CD03 CD02 CDG
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-20. Peripheral Power Management Register Low (PPMRL)
Table 13-18. Peripheral Power Management (PPMRH, PPMRL) Field Description
Field
63–2
CD[63:2]
1
CDG
0
Description
Clock Disable, Module Slot n.
0 The clock for this IPS module is enabled.
1 The clock for this IPS module is disabled.
0 The clock for the global IPS space is enabled.
1 The clock for the global IPS space is disabled.
Reserved, should be cleared.
13.2.2.14.6 Peripheral Power Management Register 1 (PPMR1{H,L})
The PPMR1{H,L} registers provide a bit map for controlling the generation of the module clocks for each
decoded address space associated with the optional AIPS1 controller. Recall each AIPS controller decodes
the mapped address space into sixty-four 16 KByte “slots” (32 on-platform and 32 off-platform) and a 63
MByte off-platform global region. The PPMR1 provides a unique control bit for each of these address
spaces that defines whether the module clock for the given space is enabled or disabled. It is software’s
responsibility to appropriately disable module clocks using the PPMR1 only when a module is completely
unused or quiescent.
The individual bits of the PPMR1 can be modified using a read-modify-write to this register directly or
indirectly through writes to the PPMRS1 and PPMRC1 registers to set/clear individual bits. If the static
module enable is negated, the appropriate PPMR1 bit is automatically set by MCM after the negation of
the platform reset and cannot be altered by any subsequent IPS writes.
See Figure 13-21, Figure 13-22, and Figure 13-19 for the PPMR1 definition.
MAC7200 Microcontroller Family Reference Manual, Rev. 2
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Memory Map/Register Definition
Register address: MCM Base + 0x0038 (PPMR1H)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
CD63 CD62 CD61 CD60 CD59 CD58 CD57 CD56 CD55 CD54 CD53 CD52 CD51 CD50 CD49 CD48
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
CD47 CD46 CD45 CD44 CD43 CD42 CD41 CD40 CD39 CD38 CD37 CD36 CD35 CD34 CD33 CD32
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-21. Peripheral Power Management Register 1 High (PPMR1H)
Register address: MCM Base + 0x003c (PPMR1L)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
W
Reset
R
0
CDG
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-22. Peripheral Power Management Register 1 Low (PPMR1L)
Table 13-19. Peripheral Power Management (PPMR1H, PPMR1L) Field Description
Field
63–32
CD[63:32]
Description
Clock Disable, Module Slot n.
0 The clock for this IPS module is enabled.
1 The clock for this IPS module is disabled.
31–2
Reserved, should be cleared.
1
CDG
0 The clock for the global IPS space is enabled.
1 The clock for the global IPS space is disabled.
0
Reserved, should be cleared.S
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13.2.2.15 ECC Registers
For designs including error-correcting code (ECC) implementations to improve the quality and reliability
of memories, there are a number of program-visible registers for the sole purpose of reporting and logging
of memory failures. These optional registers include:
• ECC Configuration Register (ECR)
• ECC Status Register (ESR)
• ECC Error Generation Register (EEGR)
• Flash ECC Address Register (FEAR)
• Flash ECC Master Number Register (FEMR)
• Flash ECC Attributes Register (FEAT)
• Flash ECC Data Register (FEDR)
• RAM ECC Address Register (REAR)
• RAM ECC Syndrome Register (RESR)
• RAM ECC Master Number Register (REMR)
• RAM ECC Attributes Register (REAT)
• RAM ECC Data Register (REDR)
The details on the ECC registers are provided in the subsequent sections. If the design does not include
ECC on the memories, these addresses are reserved locations within the MCM’s programming model.
13.2.2.15.1 ECC Configuration Register (ECR)
The ECC Configuration Register is an 8-bit control register for specifying which types of memory errors
are reported. In all systems with ECC, the occurrence of a non-correctable error causes the current access
to be terminated with an error condition. In many cases, this error termination is reported directly by the
initiating bus master. However, there are certain situations where the occurrence of this type of
non-correctable error is not reported by the master. Examples include speculative instruction fetches which
are discarded due to a change-of-flow operation, and buffered operand writes. The ECC reporting logic in
the MCM provides an optional error interrupt mechanism to signal all non-correctable memory errors. In
addition to the interrupt generation, the MCM captures specific information (memory address, attributes
and data, bus master number, etc.) which may be useful for subsequent failure analysis.
The reporting of single-bit memory corrections can only be enabled via a an SoC-configurable module
input signal. While not directly accessible to a user, this capability is viewed as important for error logging
and failure analysis.
See Figure 13-23 and Table 13-20 for the ECC Configuration Register definition.
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Memory Map/Register Definition
Register address: MCM Base + 0x43
R
7
6
0
0
5
4
ER1BR
EF1BR
0
0
3
2
0
0
1
0
ERNCR
EFNCR
0
0
W
Reset
0
0
0
0
Figure 13-23. ECC Configuration (ECR) Register
Table 13-20. ECR Field Descriptions
Field
7–6
5
ER1BR
Description
Reserved, should be cleared.
Enable RAM 1-bit Reporting.
0 Reporting of single-bit RAM corrections is disabled.
1 Reporting of single-bit RAM corrections is enabled.
This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a
single-bit RAM correction generates a MCM ECC interrupt request as signalled by the assertion of
ESR[R1BC]. The address, attributes and data are also captured in the REAR, RESR, REMR, REAT and
REDR registers.
4
EF1BR
Enable Flash 1-bit Reporting.
0 Reporting of single-bit flash corrections is disabled.
1 Reporting of single-bit flash corrections is enabled.
This bit can only be set if the SoC-configurable input enable signal is asserted. The occurrence of a
single-bit flash correction generates a MCM ECC interrupt request as signalled by the assertion of
ESR[F1BC]. The address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR
registers.
3–2
1
ERNCR
Reserved, should be cleared.
Enable RAM Non-Correctable Reporting.
0 Reporting of non-correctable RAM errors is disabled.
1 Reporting of non-correctable RAM errors is enabled.
The occurrence of a non-correctable multi-bit RAM error generates a MCM ECC interrupt request as
signalled by the assertion of ESR[RNCE]. The faulting address, attributes and data are also captured in
the REAR, RESR, REMR, REAT and REDR registers.
0
EFNCR
Enable Flash Non-Correctable Reporting.
0 Reporting of non-correctable flash errors is disabled.
1 Reporting of non-correctable flash errors is enabled.
The occurrence of a non-correctable multi-bit flash error generates a MCM ECC interrupt request as
signalled by the assertion of ESR[FNCE]. The faulting address, attributes and data are also captured in
the FEAR, FEMR, FEAT and FEDR registers.
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Memory Map/Register Definition
13.2.2.15.2 ECC Status Register (ESR)
The ECC Status Register is an 8-bit control register for signaling which types of properly-enabled ECC
events have been detected. The ESR signals the last, properly-enabled memory event to be detected. The
generation of the MCM ECC interrupt request is defined by the boolean equation:
MCM_ECC_IRQ
= ECR[ER1BR]
| ECR[EF1BR]
| ECR[ERNCR]
| ECR[EFNCR]
&
&
&
&
ESR[R1BC]//
ESR[F1BC]//
ESR[RNCE]//
ESR[FNCE]//
ram,
flash,
ram,
flash,
1-bit correction
1-bit correction
noncorrectable error
noncorrectable error
where the combination of a properly-enabled category in the ECR and the detection of the corresponding
condition in the ESR produces the interrupt request.
The MCM allows a maximum of one bit of the ESR to be asserted at any given time. This preserves the
association between the ESR and the corresponding address and attribute registers, which are loaded on
each occurrence of an properly-enabled ECC event. If there is a pending ECC interrupt and another
properly-enabled ECC event occurs, the MCM hardware automatically handles the ESR reporting,
clearing the previous data and loading the new state and thus guaranteeing that only a single flag is
asserted.
To maintain the coherent software view of the reported event, the following sequence in the MCM error
interrupt service routine is suggested:
1. Read the ESR and save it.
2. Read and save all the address and attribute reporting registers.
3. Re-read the ESR and verify the current contents matches the original contents. If the two values
are different, go back to step 1 and repeat.
4. When the values are identical, write a 1 to the asserted ESR flag to negate the interrupt request.
See Figure 13-24 and Table 13-21 for the ECC Status Register definition.
Register address: MCM Base + 0x47
R
7
6
0
0
5
4
R1BC
F1BC
0
0
3
2
0
0
1
0
RNCE
FNCE
0
0
W
Reset
0
0
0
0
Figure 13-24. ECC Status (ESR) Register
In the event that multiple status flags are signaled simultaneously, MCM records the event with the R1BC
as highest priority, then F1BC, then RNCE, and finally FNCE.
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Memory Map/Register Definition
Table 13-21. ESR Field Descriptions
Field
7–6
5
R1BC
Description
Reserved, should be cleared.
RAM 1-bit Correction.
0 No reportable single-bit RAM correction has been detected.
1 A reportable single-bit RAM correction has been detected.
This bit can only be set if ECR[EPR1BR] is asserted. The occurrence of a properly-enabled single-bit
RAM correction generates a MCM ECC interrupt request. The address, attributes and data are also
captured in the REAR, RESR, REMR, REAT and REDR registers. To clear this interrupt flag, write a 1 to
this bit. Writing a 0 has no effect.
4
F1BC
Flash 1-bit Correction.
0 No reportable single-bit flash correction has been detected.
1 A reportable single-bit flash correction has been detected.
This bit can only be set if ECR[EPF1BR] is asserted. The occurrence of a properly-enabled single-bit
flash correction generates a MCM ECC interrupt request. The address, attributes and data are also
captured in the FEAR, FEMR, FEAT and FEDR registers. To clear this interrupt flag, write a 1 to this bit.
Writing a 0 has no effect.
3–2
1
RNCE
Reserved, should be cleared.
RAM Non-Correctable Error.
0 No reportable non-correctable RAM error has been detected.
1 = A reportable non-correctable RAM error has been detected.
The occurrence of a properly-enabled non-correctable RAM error generates a MCM ECC interrupt
request. The faulting address, attributes and data are also captured in the REAR, RESR, REMR, REAT
and REDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
0
FNCE
Flash Non-Correctable Error.
0 No reportable non-correctable flash error has been detected.
1 A reportable non-correctable flash error has been detected.
The occurrence of a properly-enabled non-correctable flash error generates a MCM ECC interrupt
request. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT and FEDR
registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
13.2.2.15.3 ECC Error Generation Register (EEGR)
The ECC Error Generation Register is a 16-bit control register used to force the generation of single- and
double-bit data inversions in the memories with ECC, most notably the RAM. This capability is provided
for two purposes:
• It provides a software-controlled mechanism for “injecting” errors into the memories during data
writes to verify the integrity of the ECC logic.
• It provides a mechanism to allow testing of the software service routines associated with memory
error logging.
It should be noted that while the EEGR is associated with the RAM, similar capabilities exist for the flash,
i.e., the ability to program the non-volatile memory with single- or double-bit errors is supported for the
same two reasons previously identified.
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Memory Map/Register Definition
For both types of memories (RAM and flash), the intent is to generate errors during data write cycles, such
that subsequent reads of the corrupted address locations generate ECC events, either single-bit corrections
or double-bit non-correctable errors that are terminated with an error response.
The enabling of these error generation modes requires the same SoC-configurable input enable signal (as
that used to enable single-bit correction reporting) be asserted.
See Figure 13-25 and Table 13-22 for the ECC Configuration Register definition.
15
14
13
12
11
10
9
8
7
0
0
FRC1BI
FR11BI
0
0
FRCNCI
FR1NCI
Register address: MCM Base + 0x4a
0
0
0
0
0
0
0
R
W
Reset
0
0
0
6
5
4
3
2
1
0
0
0
0
ERRBIT[6:0]
0
0
0
0
Figure 13-25. ECC Error Generation (EEGR) Register
If an attempt to force a non-correctable inversion (by asserting EEGR[FRCNCI] or EEGR[FRC1NCI])
and EEGR[ERRBIT] equals 64, then no data inversion will be generated.
Table 13-22. EEGR Field Descriptions
Field
15–14
13
FRC1BI
Description
Reserved, should be cleared.
Force RAM Continuous 1-Bit Data Inversions.
0 No RAM continuous 1-bit data inversions are generated.
1 1-bit data inversions in the RAM are continuously generated.
The assertion of this bit forces the RAM controller to create 1-bit data inversions, as defined by the bit
position specified in ERRBIT[6:0], continuously on every write operation.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared
before being set again to properly re-enable the error generation logic.
This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit
correction reporting) is asserted.
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Memory Map/Register Definition
Table 13-22. EEGR Field Descriptions (Continued)
Field
12
FR11BI
Description
Force RAM One 1-bit Data Inversion.
0 No RAM single 1-bit data inversion is generated.
1 One 1-bit data inversion in the RAM is generated.
The assertion of this bit forces the RAM controller to create one 1-bit data inversion, as defined by the bit
position specified in ERRBIT[6:0], on the first write operation after this bit is set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT is inverted to introduce a 1-bit ECC event in the RAM.
After this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being
set again to properly re-enable the error generation logic.
This bit can only be set if the same SoC configurable input enable signal (as that used to enable single-bit
correction reporting) is asserted.
11–10
9
FRCNCI
Reserved, should be cleared.
Force RAM Continuous Non-correctable Data Inversions.
0 No RAM continuous 2-bit data inversions are generated.
1 2-bit data inversions in the RAM are continuously generated.
The assertion of this bit forces the RAM controller to create 2-bit data inversions, as defined by the bit
position specified in ERRBIT[6:0] and the overall odd parity bit, continuously on every write operation.
After this bit has been enabled to generate another continuous non-correctable data inversion, it must be
cleared before being set again to properly re-enable the error generation logic.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
8
FR1NCI
Force RAM One Non-correctable Data Inversions.
0 No RAM single 2-bit data inversions are generated.
1 One 2-bit data inversion in the RAM is generated.
The assertion of this bit forces the RAM controller to create one 2-bit data inversion, as defined by the bit
position specified in ERRBIT[6:0] and the overall odd parity bit, on the first write operation after this bit is
set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position
defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again
to properly re-enable the error generation logic.
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Memory Map/Register Definition
Table 13-22. EEGR Field Descriptions (Continued)
Field
7
6–0
ERRBIT[6:0]
Description
Reserved, should be cleared.
Error Bit Position. The vector defines the bit position which is complemented to create the data inversion
on the write operation. For the creation of 2-bit data inversions, the bit specified by this field plus the odd
parity bit of the ECC code are inverted.
The RAM controller follows a vector bit ordering scheme where LSB=0. Errors in the ECC syndrome bits
can be generated by setting this field to a value greater than the RAM width. For example, consider a
32-bit RAM implementation.
The 32-bit ECC approach requires 7 code bits for a 32-bit word. For PRAM data width of 32 bits, the actual
SRAM (32b data + 7b for ECC) = 39 bits. The following association between the ERRBIT field and the
corrupted memory bit is defined:
if ERRBIT = 0, then RAM[0] of the odd bank is inverted
if ERRBIT = 1, then RAM[1] of the odd bank is inverted
...
if ERRBIT = 31, then RAM[31] of the odd bank is inverted
if ERRBIT = 64,then ECC Parity[0] of the odd bank is inverted
if ERRBIT = 65,then ECC Parity[1] of the odd bank is inverted
...
if ERRBIT = 70,then ECC Parity[6] of the odd bank is inverted
For ERRBIT values of 32 to 63 and greater than 70, no bit position is inverted.
The only allowable values for the 4 control bit enables {FR11BI, FRC1BI, FRCNCI, FR1NCI} are
{0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0} and {0,0,0,1}. All other values result in undefined behavior.
13.2.2.15.4 Flash ECC Address Register (FEAR)
The FEAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in the flash
memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash causes the
address, attributes and data associated with the access to be loaded into the FEAR, FEMR, FEAT and
FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-26 and Table 13-23 for the Flash ECC Address Register definition.
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Memory Map/Register Definition
Register address: MCM Base + 0x50
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
FEAR[31:16]
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
FEAR[15:0]
W
Reset
—
—
—
—
—
—
—
—
—
Figure 13-26. Flash ECC Address (FEAR) Register
Table 13-23. FEAR Field Descriptions
Field
Description
31–0
FEAR[31:0]
Flash ECC Address Register. This 32-bit register contains the faulting access address of the last,
properly-enabled flash ECC event.
13.2.2.15.5 Flash ECC Master Number Register (FEMR)
The FEMR is a 4-bit register for capturing the AXBS bus master number of the last, properly-enabled ECC
event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in
the flash causes the address, attributes and data associated with the access to be loaded into the FEAR,
FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register
to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-27 and Table 13-24 for the Flash ECC Master Number Register definition.
Register address: MCM Base + 0x56
R
7
6
5
4
0
0
0
0
0
0
0
0
3
2
1
0
—
—
FEMR[3:0]
W
Reset
—
—
Figure 13-27. Flash ECC Master Number (FEMR) Register
Table 13-24. PFEMR Field Descriptions
Field
7–4
3–0
FEMR[3:0]
Description
Reserved, should be cleared.
Flash ECC Master Number Register. This 4-bit register contains the AXBS bus master number of the
faulting access of the last, properly-enabled flash ECC event.
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Memory Map/Register Definition
13.2.2.15.6 Flash ECC Attributes Register (FEAT)
The FEAT is an 8-bit register for capturing the AXBS bus master attributes of the last, properly-enabled
ECC event in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event
in the flash causes the address, attributes and data associated with the access to be loaded into the FEAR,
FEMR, FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register
to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-28 and Table 13-25 for the Flash ECC Attributes Register definition.
Register address: MCM Base + 0x57
7
R
6
5
Write
4
3
Size[2:0]
2
1
0
Protection[3:0]
W
Reset
—
—
—
—
—
—
—
—
Figure 13-28. Flash ECC Attributes (FEAT) Register
Table 13-25. PFEAT Field Descriptions
Field
7
Write
6–4
Size[2:0]
Description
AMBA-AHB HWRITE.
0 AMBA-AHB read access
1 AMBA-AHB write access
AMBA-AHB HSIZE[2:0].
000 8-bit AMBA-AHB access
001 16-bit AMBA-AHB access
010 32-bit AMBA-AHB access
011 Reserved
1xx Reserved
AMBA-AHB HPROT[3:0].
3–0
Protection[3:0] Protection[3]: Cacheable
0 Non-cacheable
1 Cacheable
Protection[2]: Bufferable
0 Non-bufferable
1 Bufferable
Protection[1]: Mode
0 User mode
1 Supervisor mode
Protection[0]: Type
0 I-Fetch
1 Data
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13.2.2.15.7 Flash ECC Data Register (FEDR)
The FEDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event
in the flash memory. Depending on the state of the ECC Configuration Register, an ECC event in the flash
causes the address, attributes and data associated with the access to be loaded into the FEAR, FEMR,
FEAT and FEDR registers, and the appropriate flag (F1BC or FNCE) in the ECC Status Register to be
asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-29 and Table 13-26 for the Flash ECC Data Register definition.
Figure 13-29. Flash ECC Data (FEDR) Register
Register address: MCM Base +0x5c
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
FEDR[31:16]
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
FEDR[15:0]
W
Reset
—
—
—
—
—
—
—
—
—
Figure 13-30. Platform Flash ECC Data (PFEDR) Register
Table 13-26. FEDR Field Descriptions
Field
Description
31–0
FEDR
Flash ECC Data Register. This 64-bit register contains the data associated with the faulting access of the
last, properly-enabled flash ECC event. The register contains the data value taken directly from the data
bus.
13.2.2.15.8 RAM ECC Address Register (REAR)
The REAR is a 32-bit register for capturing the address of the last, properly-enabled ECC event in the
RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM
causes the address, attributes and data associated with the access to be loaded into the REAR, RESR,
REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register
to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-31 and Table 13-27 for the RAM ECC Address Register definition.
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Memory Map/Register Definition
Register address: MCM Base + 0x60
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
REAR[31:16]
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
REAR[15:0]
W
Reset
—
—
—
—
—
—
—
—
—
Figure 13-31. RAM ECC Address (REAR) Register
Table 13-27. REAR Field Descriptions
Field
Description
31–0
REAR[31:0]
RAM ECC Address Register. This 32-bit register contains the faulting access address of the last,
properly-enabled RAM ECC event.
13.2.2.15.9 RAM ECC Syndrome Register (RESR)
The RESR is an 8-bit register for capturing the error syndrome of the last, properly-enabled ECC event in
the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the RAM
causes the address, attributes and data associated with the access to be loaded into the REAR, RESR,
REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register
to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-32 and Table 13-28 for the RAM ECC Syndrome Register definition.
Register address: MCM Base + 0x65
7
6
5
R
4
3
2
1
0
—
—
—
—
RESR[7:0]
W
Reset
—
—
—
—
Figure 13-32. RAM ECC Syndrome (RESR) Register
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Memory Map/Register Definition
Table 13-28. RESR Field Descriptions
Field
Description
7–0
RESR[7:0]
RAM ECC Syndrome Register. This 8-bit syndrome field includes 6 bits of Hamming decoded parity plus
an odd-parity bit for the entire 39-bit (32-bit data + 7 ECC) code word. The upper 7 bits of the syndrome
specify the exact bit position in error for single-bit correctable codewords, and the combination of a
non-zero 7-bit syndrome plus overall incorrect parity bit signal a multi-bit, non-correctable error.
For correctable single-bit errors, the mapping shown in Table 13-29 associates the upper 7 bits of the
syndrome with the data bit in error.
Table 13-29 associates the upper 7 bits of the ECC syndrome with the exact data bit in error for single-bit
correctable codewords. This table follows the bit vectoring notation where the LSB=0. Note that the
syndrome value of 0x01 implies no error condition but this value is not readable when the PRESR is read
for the no error case.
Table 13-29. RAM Syndrome Mapping for Single-Bit Correctable Errors
RESR[7:0]
Data Bit in Error
RESR[7:0]
Data Bit in Error
0x00
ECC ODD[0]
0x28
DATA ODD BANK[17]
0x01
No Error
0x2a
DATA ODD BANK[16
0x02
ECC ODD[1]
0x2c
DATA ODD BANK[15]
0x04
ECC ODD[2]
0x58
DATA ODD BANK[14]
0x06
DATA ODD BANK[31]
0x30
DATA ODD BANK[13]
0x08
ECC ODD[3]
0x32
DATA ODD BANK[12]
0x0a
DATA ODD BANK[30]
0x34
DATA ODD BANK[11]
0x0c
DATA ODD BANK[29]
0x64
DATA ODD BANK[10]
0x0e
DATA ODD BANK[28]
0x38
DATA ODD BANK[9]
0x10
ECC ODD[4]
0x62
DATA ODD BANK[8]
0x12
DATA ODD BANK[27]
0x70
DATA ODD BANK[7]
0x14
DATA ODD BANK[26]
0x60
DATA ODD BANK[6]
0x16
DATA ODD BANK[25]
0x40
ECC ODD[6]
0x18
DATA ODD BANK[24]
0x42
DATA ODD BANK[5]
0x1a
DATA ODD BANK[23]
0x44
DATA ODD BANK[4]
0x1c
DATA ODD BANK[22]
0x46
DATA ODD BANK[3]
0x50
DATA ODD BANK[21]
0x48
DATA ODD BANK[2]
0x20
ECC ODD[5]
0x4a
DATA ODD BANK[1]
0x22
DATA ODD BANK[20]
0x4c
DATA ODD BANK[0]
0x24
DATA ODD BANK[19]
0x03,0x05........0x4d
Multiple bit error
0x26
DATA ODD BANK[18]
> 0x4d
Multiple bit error
13.2.2.15.10 RAM ECC Master Number Register (REMR)
The REMR is a 4-bit register for capturing the AXBS bus master number of the last, properly-enabled ECC
event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in
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the RAM causes the address, attributes and data associated with the access to be loaded into the REAR,
RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-33 and Table 13-30 for the RAM ECC Master Number Register definition.
Register address: MCM Base + 0x66
R
7
6
5
4
0
0
0
0
0
0
0
0
3
2
1
0
—
—
REMR[3:0]
W
Reset
—
—
Figure 13-33. RAM ECC Master Number (REMR) Register
Table 13-30. REMR Field Descriptions
Field
Description
7–4
Reserved, should be cleared.
3–0
REMR[3:0]
RAMECC Master Number Register. This 4-bit register contains the AXBS bus master number of the
faulting access of the last, properly-enabled RAM ECC event.
13.2.2.15.11 RAM ECC Attributes Register (REAT)
The REAT is an 8-bit register for capturing the AXBS bus master attributes of the last, properly-enabled
ECC event in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event
in the RAM causes the address, attributes and data associated with the access to be loaded into the REAR,
RESR, REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status
Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-34 and Table 13-31 for the RAM ECC Attributes Register definition.
Register address: MCM Base + 0x67
7
R
6
Write
5
4
3
Size[2:0]
2
1
0
Protection[3:0]
W
Reset
—
—
—
—
—
—
—
—
Figure 13-34. RAM ECC Attributes (REAT) Register
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Table 13-31. REAT Field Descriptions
Field
7
Write
6–4
Size[2:0]
Description
AMBA-AHB HWRITE.
0 AMBA-AHB read access
1 AMBA-AHB write access
AMBA-AHB HSIZE[2:0].
000 8-bit AMBA-AHB access
001 16-bit AMBA-AHB access
010 32-bit AMBA-AHB access
011 Reserved
1xx Reserved
3–0
AMBA-AHB HPROT[3:0].
Protection[3:0] Protection[3]: Cacheable
0 Non-cacheable
1 Cacheable
Protection[2]: Bufferable
0 Non-bufferable
1 Bufferable
Protection[1]: Mode
0 User mode
1 Supervisor mode
Protection[0]: Type
0 I-Fetch
1 Data
13.2.2.15.12 RAM ECC Data Register (REDR)
The REDR is a 32-bit register for capturing the data associated with the last, properly-enabled ECC event
in the RAM memory. Depending on the state of the ECC Configuration Register, an ECC event in the
RAM causes the address, attributes and data associated with the access to be loaded into the REAR, RESR,
REMR, REAT and REDR registers, and the appropriate flag (R1BC or RNCE) in the ECC Status Register
to be asserted.
The data captured on a multi-bit non-correctable ECC error is undefined.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-35 and Table 13-32 for the RAM ECC Data Register definition.
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Register address: MCM Base +0x6c
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
REDR[31:16]
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
REDR[15:0]
W
Reset
—
—
—
—
—
—
—
—
—
Figure 13-35. RAM ECC Data (REDR) Register
Table 13-32. REDR Field Descriptions
Field
Description
31–0
REDR[31:0]
RAM ECC Data Register. This 32-bit register contains the data associated with the faulting access of the
last, properly-enabled RAM ECC event. The register contains the data value taken directly from the data
bus.
13.2.2.16 Core Data Fault Recovery Registers
To aid in recovery from certain types of data access errors, the MCM module optionally supports a number
of registers which capture access address, attribute and data information on bus cycles terminated with an
error response. These registers can then be read during the resulting exception service routine and the
appropriate recovery performed.
The details on the core fault recovery registers are provided in the subsequent sections. It is important to
note these registers are used to capture fault recovery information only on data access faults, i.e., no
information is captured on instruction fetch faults. If the design does not include the fault recovery
registers, these addresses are reserved locations within the MCM’s programming model.
13.2.2.16.1 Core Fault Address Register (CFADR)
The CFADR is a 32-bit register for capturing the address of the last core data access which was terminated
with an error response. This register can only be read from the IPS programming model; any attempted
write is ignored. See Figure 13-36 and Table 13-33 for the Core Fault Address Register definition.
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Register address: MCM Base + 0x70
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
CFADR[31:16]
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
CFADR[15:0]
W
Reset
—
—
—
—
—
—
—
—
—
Figure 13-36. Core Fault Address (CFADR) Register
Table 13-33. CFADR Field Descriptions
Field
Description
31–0
Core Fault Address Register. This 32-bit register contains the faulting address of the last core data access
CFADR[31:0] terminated with an error response.
13.2.2.16.2 Core Fault Location/Interrupt Enable Register (CFLOC1)
The CFLOC1 is an 8-bit register with multiple functions for SPP implementations. For SPP_Ref_CFx
designs, this register contains a 1-bit enable to generate an error interrupt on the detection of a faulted
processor AHB system bus cycle. See Table 13-37 and Table 13-34 for the Core Fault Location Register
definition.
Register address: MCM Base + 0x75
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
ECFEI
W
Reset
—
0
0
0
0
0
0
0
Figure 13-37. Core Fault Location 1 (CFLOC1) Register
Table 13-34. Core Fault Location 1 (CFLOC1) Field Descriptions
Field
7–1
0
ECFEI
Description
Reserved, should be cleared.
Enable Core Fault Error Interrupt.
0 Do not generate an error interrupt on a faulted processor system bus cycle.
1 Generate an error interrupt on a faulted processor system bus cycle.
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13.2.2.16.3 Core Fault Location Register (CFLOC)
The CFLOC is a 1-bit register indicating the exact location of the captured fault information: a
AMBA-AHB data access or a data access to a tightly-coupled core local memory. This register can only
be read from the IPS programming model; any attempted write is ignored. See Table 13-38 and
Table 13-35 for the Core Fault Location Register definition.
Register address: MCM Base + 0x76
R
7
6
5
4
3
2
1
0
LocalErr
0
0
0
0
0
0
0
—
0
0
0
0
0
0
0
W
Reset
Figure 13-38. Core Fault Location (CFLOC) Register
Table 13-35. CFLOC Field Descriptions
Field
Description
7
LocalErr
Bus Error Indicator.
0 Error occurred on the AMBA-AHB bus
1 Error occurred on the processor core’s local bus
13.2.2.16.4 Core Fault Attributes Register (CFATR)
The CFATR is an 8-bit register for capturing the processor’s attributes of the last faulted data access to the
AMBA-AHB or core’s local bus.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-39 and Table 13-36 for the Core Fault Attributes Register definition.
Register address: MCM Base + 0x77
7
R
6
Write
5
4
3
Size[2:0]
2
1
0
Protection[3:0]
W
Reset
—
—
—
—
—
—
—
—
Figure 13-39. Core Fault Attributes (CFATR) Register
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Table 13-36. CFATR Field Descriptions
Field
7
Write
6–4
Size[2:0]
Description
WRITE.
0 Core read access
1 Core write access
SIZE[2:0].
000 8-bit core access
001 16-bit core access
010 32-bit core access
011 64-bit core access
1xx Reserved
3–0
PROT[3:0].
Protection[3:0] Protection[3]: Cacheable
0 Non-cacheable
1 Cacheable
Protection[2]: Bufferable
0 Non-bufferable
1 Bufferable
Protection[1]: Mode
0 User mode
1 Supervisor mode
Protection[0]: Type
1 Data
13.2.2.16.5 Core Fault Data Register (CFDTR)
The CFDTR is a 32-bit register for capturing the data associated with the last faulted processor write data
access from the device’s AMBA-AHB bus. The CFDTR is valid only for faulted AMBA-AHB write
accesses. The contents of this register are not valid if the last fault occurred on the core’s local bus
(CFLOC[LocalErr] = 1). This register is not updated on AMBA-AHB read access faults.
This register can only be read from the IPS programming model; any attempted write is ignored. See
Figure 13-40 and Table 13-37 for the Core Fault Data Register definition.
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Register address: MCM Base + 0x7c
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
CFDTR[31:16]
W
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
R
CFDTR[15:0]
W
Reset
—
—
—
—
—
—
—
—
—
Figure 13-40. Core Fault Data (CFDTR) Register
Table 13-37. CFDTR Field Descriptions
Field
Description
31–0
Core Fault Data Register. This 32-bit register contains the data associated with the faulting access of the
CFDTR[31:0] last AMBA-AHB write access. The register contains the data value taken directly from the device write
data bus.
13.3
13.3.1
MCM as Implemented on MAC7200
MCM Introduction
The Miscellaneous Control Module implements a number of system level features, including the
following:
• Program-visible information on the device configuration and revision.
• Software watchdog timer (SWT) with programmable system reset or interrupt response which runs
on a separate, asynchronous clock. The SWT also supports a windowed time period, requiring the
writing of the watchdog key within a specified time window. The source for the SWT clock is
controlled by the Clock and Reset Generator.
• Wakeup control for entering and exiting sleep modes, including an enable and an interrupt priority
mask.
• Access address information for faulted memory accesses. When a bus abort occurs in the system,
the exact cause of the abort can be determined by reading the Core Data Fault Recovery Registers
in the MCM.
• Address map for the crossbar switch (AXBS), which is used to steer access to the Crossbar slave
ports in order to provide remapping operations. Following Reset, the contents of the AAMR
register are determined by the mode entered as a result of the default slave mapping, but may be
configured by the application code in order to remap the Flash, External bus and RAM between
AXBS Slave Port 0 and Port 1. Please refer to Chapter 9, “Device Memory Map” for further
details.
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For the MAC7200 family of devices, only certain crossbar switch re-mappings are valid. The reset value
of the register depends on the Chip Mode selected and the security state of the device, and is discussed in
detail in Chapter 9, “Device Memory Map”. After reset, the AAMR register may be re-programmed to
change the memory map of the system as follows:
Table 13-38. AAMR Register Configurability 1
AAMR Bits
Base Address
Allowed Values
31:28
$E000 0000
$f (Peripheral Space)
27:24
$C000 0000
$0 (Unused)
23:20
$A000 0000
$d (BAM)
19:16
$8000 0000
$0 (Unused)
15:12
$6000 0000
$0 (Unused)
11:8
$4000 0000
$b (SRAM)
7:4
$2000 0000
$8 (Program Flash), $9 (External Bus), $b (SRAM)
3:0
$0000 0000
$8 (Program Flash), $9 (External Bus), $b (SRAM)
1. Not all re-mappings may be available in all Chip Modes/Security states. Please refer to Chapter 9, “Device Memory
Map for more details on valid memory map configurations.
NOTE
The SRAM is fixed at address $4000 0000, and may be re-mapped to either
$0000 0000 or $2000 0000. When this is done, the SRAM will appear at
both addresses in the memory map.
Consult the MCM Block Guide for further information about configuring and using the MCM.
13.3.2
MCM Features
The MCM module is an on-platform IPI module that implements several varied SoC level features,
including the following:
13.3.2.1
Processor Core Type (PCT)
This 16-bit register identifies the revision ID of the platform/core pair, as follows:
Table 13-39. Processor Core Type (PCT) Values
Core
PCT
ARM7
$A700
ARM9
$A900
ARM11
$A110
ColdFire v2
$CF20
ColdFire v3
$CF30
Comment
Value for the MAC72xx
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Table 13-39. Processor Core Type (PCT) Values (Continued)
Core
13.3.2.2
PCT
ColdFire v4
$CF40
ColdFire v5
$CF50
Z650 PowerPC
$E650
Comment
Revision ID (REV)
This 16-bit register identifies the revision ID of the device.
Table 13-40. MAC72xx PCT and REV registers
Device
PCT
REV
MAC72x2 (0M84D Maskset)
$A700
$7220 1
MAC72x2 (1M84D Maskset)
$A700
$7220 1
MAC72x1 (0M19G Maskset)
$A700
$7230
1. Due to erratum MUCts03562, 0M84D and 1M84D masks share the same revision number
13.3.2.3
AXBS Master/Slave Configuration
The AMC and ASC registers in the MCM indicate the presence of AXBS masters and slaves. Please refer
to Chapter 15, “MAC7200 Crossbar Switch (AXBS)” for a listing of which AXBS masters/slaves are
present on the MAC72xx.
13.3.2.4
Misc. Reset Status Register (MRSR)
On the MAC72xx, all reset sources all consolidated into the CRG module. Therefore, this feature in the
MCM will not be used, and will be removed from the MCM Block Guide for the MAC72xx.
13.3.2.5
Misc. Wakeup Control Register (MWCR)
Since the MAC72xx only supports DOZE mode, this register is used to control wake-up from DOZE mode
with an interrupt. STOP mode is not supported.
13.3.2.6
Software Watchdog Timer (SWT)
The SWT will interrupt the processor periodically to request servicing (in order to prevent software
deadlock or runaway). The SWT includes enable/disable, interrupt/reset and programmable period
functionality.
The SWT interrupt is connected to on-platform interrupt Request #17, and the SWT reset signal will be
fed off-platform to the CRG to allow for soft-reset on a SWT timeout. The SWT clock may be fed from
either the oscillator clock, in normal mode, or from the PLL, when the system enters Self Clock Mode.
By programming the BDMCTL register in the CRG module, the system can automatically stop and start
the SWT counters when the system enters debug mode.
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13.3.2.7
AXBS Address Map Register (AAMR)
This 32-bit register controls the address mapping for each of the 8 possible AXBS slaves. Please refer to
Section 9.16.4, “Programming the AAMR register in the MCM” for more details on the AAMR
functionality.
13.3.2.8
Misc. User-Defined Control Register (MUDCR)
The MUDCR register will be used on the MAC72xx as the Write Access Control (WACC) register for the
main Flash array. Please refer to Section 18.7.4.2, “Flash MCM Registers” for more information on the
WACC register.
13.3.2.9
ECC
Both the on-chip RAM and Flash memories include ECC with 2-bit detection/1-bit correction. The MCM
ECC registers include a variety of features to utilize the ECC, including full reporting features. Because
the ARM7 core supports Pre-fetch (Instruction) and Data aborts, all code for servicing both of these
exceptions should make use of the ECC reporting registers in the MCM.
13.3.2.10 Fault Registers
The MCM provides several registers that can be used by the Pre-fetch Abort and Data Abort exception
handlers to determine the exact location and type of an illegal instruction or data fetch. Please refer to
Section 7.2.4, “Prefetch (Instruction) Abort” for a list of bus abort sources.
13.3.2.11 Non-Maskable Interrupt (NMI)
Please refer to Section 7.3.4, “Non-Maskable Interrupt (NMI)” for details on the Non-Maskable Interrupt.
The MCM allows enabling/disabling of the NMI feature, as well as polarity configuration and NMI status
information.
13.3.3
MCM External Pins
There are no MCM signals that drive or are driven from MCU pins.
13.3.4
MCM Bus Aborts
The MCM module supports Peripheral Bus bus aborts, and enforces the following memory map:
Table 13-41. MCM Bus Aborts
Abort
Allowed
$0000-$000b
$000c-$000e
$000f
$0010-$0012
$0013
$0014-$0015
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Table 13-41. MCM Bus Aborts (Continued)
Abort
Allowed
$0016-$0017
$0018-$001a
$001b
$001c-$001e
$001f-$0027
$0028-$002a
$002b
$002c-$0042
$0043
$0044-$0046
$0047
$0048-$0049
$004a-$004b
$004c-$004f
$0050-$0053
$0044-$0046
$0047
$0054-$0055
$0056-$0063
$0064
$0065-$0073
$0074-$0075
$0076-$0077
$0078-$007b
$007c-$007f
$0080-$3fff
If any part of a read or write falls within an aborted region, the entire transfer is aborted. For example, a
32-bit read or write to address $0074 would be aborted.
In addition, the following transfers will be aborted:
• Byte write to 16-bit reg (swtcr, eegr)
• Byte or word write to 32-bit reg (paamr, ppmr*)
Supervisor Access: Unused
13.3.5
•
•
MCM Differences from MAC71xx
Obsoleted use of the MRSR register
Added ECC related registers and reporting
— General ECC: Added ECR, ESR, EEGR registers
— Flash ECC: Added FEAR, FEMR, FEAT, FEDRH, FEDRL registers
— SRAM ECC: Added REAR, REDRH, REDRL registers
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•
•
•
•
•
•
Added NMI functionality and NMICR register
Changed AAMR reset value from $F000_xxxx to $F0D0_xxxx
Added MUDCR register (used as the Flash main array WACC register)
REV register value is changed to $7210 (PCT is unchanged)
Single bit ECC error reporting is now enabled (enb_ecc_rpt = 1)
ECC interrupt (ipi_ecc_int) now used (with Request $0017)
13.3.6
MCM Application Usage
Unless explicitly described below, all application information can be found in the MCM Block Guide.
13.3.6.1
Enabling the MCM
It is not necessary to enable the MCM before it can be used.
13.3.6.2
ECC
For special memory initialization requirements of the SRAM, please refer to Section 19.1.6, “SRAM
Application Usage”.
13.3.6.3
Flash
Please refer to Section 18.7.4.2, “Flash MCM Registers”.
13.3.6.4
AAMR
For information on how to use the AAMR register, please refer to Section 9.16.4, “Programming the
AAMR register in the MCM”.
13.3.6.5
NMI
For more information on NMI implementation and usage, please refer to Section 7.3.4, “Non-Maskable
Interrupt (NMI)”. In particular, the following usage points should be noted:
• Existing Instruction Abort service routines must be modified in order to use the NMI feature.
• The NMI may be used either in a re-entrant or non re-entrant manner, selectable in software.
• Once the NMI is enabled, and the polarity set, it can not be disabled or the polarity changed without
resetting the device.
13.3.6.6
REV Register
The lower 4 bits of the REV register are used to indicate the mask revision for a particular device, and are
also readable directly through the JTAG interface.
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Chapter 14
SPP Interrupt Controller Module for ARM (SPP_INTC_ARM)
14.1
Introduction
14.1.1
Overview
The ARM_INTC is a highly-programmable interrupt controller, collecting both on-platform and
off-platform interrupt requests, mapping the requests into 16 priority levels, and then signalling the ARM
processor when a properly enabled non-masked request is active. In response to the service routine’s
memory mapped interrupt acknowledge read cycle, the controller returns a unique vector for each interrupt
request and automatically manages masking of lower level requests. As any interrupt source can be
assigned to any of the sixteen priority levels, and the interrupt controller enables the definition of which
priority levels are assigned to Fast or Normal interrupts, each interrupt source can be selected to generate
either a Fast or Normal interrupt to the core by its assigned level.
Normal or Fast interrupts can enable the cores bus master priority to be elevated on the crossbar switch to
assist with accelerating the handling of interrupts of the specified type.
The MAC7200 family of devices implement one interrupt controller which supports 64 interrupt requests.
The interrupt controller is accessed via the peripheral bus for both configuration and for fetching the
interrupt vector.
Consult Section 14.7, “The Interrupt Controller Module (INTC)” for information about the vector
interrupt controller implemented in the core Platform and Chapter 7, “Exceptions” for a list of the possible
interrupt sources in the system.
14.2
•
•
•
•
•
•
•
INTC Features
64 vectored interrupt sources.
Interrupt sources available from internal peripherals, eDMA controller, software watchdog timer
and external sources.
Supports 16 interrupt levels (0-15) with 64 priorities per level (1-64), to allow maximum flexibility
in configuring the system. Every interrupt source can be programmed to any interrupt level.
Priorities within a level are hard-coded in the MCU.
Multiple level interrupt nesting.
Hardware support for first nesting level.
Normal and Fast interrupts supported with software programmability of sources for both Fast and
Normal Interrupts
Memory Map: 32-bit peripheral with 256 bytes, byte addressable
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INTC External Pins
•
Has purely combinatorial “wakeup” signal for system wakeup
The purely combinatorial “wakeup” signal will be fed directly to the system wakeup input on the CRG
(OR’d with other wakeup sources, of course). For a full list of wakeup sources, please see Section 3.5,
“System Wakeup”.
14.3
INTC External Pins
Table 14-1. INTC Signals
Signals
Description
XIRQ
This external pin, when placed in Primary Peripheral Mode, drives the Interrupt Request #63 directly. This
interrupt source was chosen, because it has the highest priority (given that all interrupts are specified with
the same priority level) of any interrupt source.
IRQ
14.4
This external pin, when placed in Primary Peripheral Mode, drives the Interrupt Request #62 directly.
INTC Bus Aborts
The INTC module supports Peripheral Bus bus aborts, and enforces the following memory map:
Table 14-2. INTC Bus Aborts
Abort
Allowed
$0000-$0017
$0018-$001a
$001b-$001f
$0020-$003c
$0040-$007f
$0080-$00eb
$00ec
$00ed-$00ef
$00f0
$0080-$00eb
$00ec
$00ed-$00ef
$00f0
$00f1-$3fff
If any part of a read or write falls within an aborted region, the entire transfer is aborted. For example, a
32-bit read or write to address $00ec would be aborted.
Supervisor Access: Unused
14.5
•
INTC Differences from MAC71xx
Different mapping of interrupt sources.
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INTC Application Usage
Table 14-3. INTC MAC71x1 versus MAC72xx Interrupt Source Assignment
Interrupt
Request
MAC71x1
MAC72xx
18
CRG
—
19–21
PIT Timer Channel 1-3
—
22
PIT Timer Channel 4 / RTI
—
23
VREG
UNUSED
24
CAN_A Message Buffer 1-13,15-32
—
25
CAN_A Message Buffer 14
—
26
CAN_A
—
27
CAN_B Message Buffer 1-13,15-32
—
28
CAN_B Message Buffer 14
—
29
CAN_B
—
31
CAN_C Message Buffer 1-13,15-32
UNUSED
32
CAN_C Message Buffer 14
UNUSED
33
CAN_C
UNUSED
34
CAN_D Message Buffer 1–13,15–32
UNUSED
35
CAN_D Message Buffer 14
UNUSED
36
CAN_D
UNUSED
37
I2C
—
38
SPI_A
—
39
SPI_B
—
40
SCI_A
—
41
SCI_B
—
42
SCI_C
—
43
SCI_D
—
44–50
eMIOS Channel 1–8
—
51–58
eMIOS Channel 9–16
UNUSED
59
ATD_A / ATD_B
ATD_A only
60
Flash
DSPI_C
61
PIM
—
62
IRQ
—
63
XIRQ
—
14.6
INTC Application Usage
Please refer to the Interrupt Controller Block Guide for specific usage. In addition, the following special
notes apply:
• All interrupt source on the MAC72xx, including external sources, must be cleared at the source.
• The Non Maskable Interrupt (NMI) control registers can be found in the MCM module, not the
INTC module.
• The interrupt vector number is not the same as the physical interrupt request number. The
relationship is defined as vector_number = 64 + Request#, where Request#=0 to 63.
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The Interrupt Controller Module (INTC)
•
If the interrupt vector number returns less than 64 (i.e.-63 or less), this indicates a spurious
interrupt. A spurious interrupt is an interrupt that has been cleared before it was serviced. Since all
interrupt sources on the MAC72xx require explicit clearing, this indicates either a software
problem or an external interrupt that is self clearing.
14.6.1
Enabling the INTC
It is not necessary to enable the Interrupt Controller before it can be used. However, by default after reset,
no interrupts are enabled. Please refer to the INTC Block Guide for information about initialization of the
Interrupt Controller.
14.7
The Interrupt Controller Module (INTC)
For the required controller, the 64 fully-programmable interrupt sources service both the on-platform
peripherals as well as providing interrupt support for off-platform logic. The split between
off-/on-platform interrupt sources is dependent upon the exact platform peripheral configuration and the
number of sources needed to support it. Typically, the optional interrupt controllers support off-platform
requests.
Figure 14-1 presents a simplified block diagram for the interrupt controller.
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The Interrupt Controller Module (INTC)
lp_int_mask[*]
ipi_int[63:0]
ips_wdata
INTC
ips_addr
decode
ipr
&
>
imr
intfrc
&
>
icr0...3
>
Prioritization &
Level Masking
icr60...63
Level
Conversion
Vector
Gen
clmask slmask
iack
mux
ips_rdata
IPS
Bus
IPS Bus
_wakeup _active_* ints to core
Figure 14-1. INTC Block Diagram
14.7.1
Review of ARM Interrupt Architecture
Before continuing with the specifics of the platform interrupt controller, a brief review of the interrupt
architecture of the ARM core family is appropriate.
ARM cores support two direct interrupt request signals: a FIQ (fast interrupt request) and an IRQ (normal
interrupt request). These two inputs are prioritized by the hardware with the FIQ being higher priority than
the IRQ. Like most processor cores, interrupts are sampled once per instruction. If the FIQ input signal is
asserted and enabled in the processor’s status register (CPSR), then the core suspends normal execution
and initiates processing of a fast interrupt exception.
During exception processing, the contents of two key registers are copied into “shadow” or banked
registers. Specifically, the current program counter (R15) is copied into the banked copy of the R14 link
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Memory Map/Register Definition
register named R14_fiq and the current processor status register (CPSR) value is copied into the saved
processor status register (SPSR_fiq). Finally, a unique fast interrupt stack pointer, contained in R13_fiq,
is activated and the core completes the exception processing by setting bits in the CPSR to disable both
FIQ and IRQ interrupts, and then fetching the instruction at address 0x0000_001c. The processor
continues execution in the FIQ mode, as indicated by the low-order 5 bits (the mode field) of the CPSR.
While executing in this mode, banked copies of five additional general purpose registers
(R[8,9,10,11,12]_fiq) are also available. The shadow copies of these registers are intended to minimize the
need to save/restore the machine register state in memory using the fast interrupt stack pointer.
IRQ processing is similar with the following differences: in IRQ mode, shadow copies of only three
registers are active: R13_irq (the interrupt request stack pointer), R14_irq (the PC of the interrupted
instruction) and the SPSR_irq (the saved processor status register). The CPSR is configured to disable only
IRQ interrupts, and the processor completes exception processing by fetching the instruction at address
0x0000_0018.
For all ARM processors, the processing of any exception forces exit from Thumb mode (if enabled), and
the address loaded into the R14_{fiq,irq} link register is actually the program counter of the interrupted
instruction plus 4. Thus, this instruction address must be adjusted before returning to the interrupted
instruction at the completion of the service routine.
A summary of the operations associated with interrupt exception processing is shown in Figure 14-4:
Table 14-4. ARM Interrupt Exception Summary
Register
FIQ
IRQ
Interrupt Sample
Detect FIQ asserted
Detect FIQ negated,
IRQ asserted
Link Register
R14_fiq = nextInst + 4
R14_irq = nextInst + 4
Saved Status Register
SPSR_fiq = CPSR
SPSR_irq = CPSR
Current Processor
Status Register
CPSR[M] = 5’b10001,
CPSR[T] = 1’b0,
CPSR[F] = 1’b1,
CPSR[I] = 1’b1
CPSR[M] = 5’b10010,
CPSR[T] = 1’b0,
CPSR[F] = unaffected,
CPSR[I] = 1’b1
Stack Pointer
Activate R13_fiq
Activate R13_irq
Other Banked Registers
Activate R[8-12]_fiq
None
Program Counter
14.8
PC
= 0x0000_001c
PC
= 0x0000_0018
Memory Map/Register Definition
The register programming model for the interrupt controller is memory-mapped to a 256-byte space within
the addresses serviced by the IPS controller. In the following discussion, there are a number of
program-visible registers greater than 32 bits in size. For these control fields, the physical register is
partitioned into two 32-bit values: a register “high” (the upper word) and a register “low” (the lower word).
The nomenclature <reg_name>H and <reg_name>L is used to reference these values.
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Memory Map/Register Definition
The registers and their locations are defined in Table 14-5. The INTC module does not include any logic
which provides access control. Rather, this function is supported using the standard access control logic
provided by the AIPS controller. Attempted accesses to the reserved locations are terminated with an error.
Table 14-5 is a 32-bit view of the INTC’s memory map.
Table 14-5. INTC 32-bit Memory Map
INTC Offset
Register
0x0000
Interrupt Pending Register High (IPRH, Requests 63-32)
0x0004
Interrupt Pending Register Low (IPRL, Requests 31-00)
0x0008
Interrupt Mask Register High (IMRH, Requests 63-32)
0x000c
Interrupt Mask Register Low (IMRL, Requests 31-00)
0x0010
Interrupt Force Register High (INTFRCH, Requests 63-32)
0x0014
Interrupt Force Register Low (INTFRCL, Requests 31-00)
0x0018
0x001c
Reserved
Set Interrupt Mask
(SIMR)
Interrupt Config
Register (ICONFIG)
Clear Interrupt Mask
(CIMR)
Current Level Mask
(CLMASK)
Saved Level Mask
(SLMASK)
Reserved
0x0020-0x003c
0x0040
Interrupt Control
Register 0 (ICR00)
Interrupt Control
Register 1 (ICR01)
Interrupt Control
Register 2 (ICR02)
Interrupt Control
Register 3 (ICR03)
0x0044
Interrupt Control
Register 4 (ICR04)
Interrupt Control
Register 5 (ICR05)
Interrupt Control
Register 6 (ICR06)
Interrupt Control
Register 7 (ICR07)
0x0048
Interrupt Control
Register 8 (ICR08)
Interrupt Control
Register 9 (ICR09)
Interrupt Control
Register 10 (ICR10)
Interrupt Control
Register 11 (ICR11)
0x004c
Interrupt Control
Register 12 (ICR12)
Interrupt Control
Register 13 (ICR13)
Interrupt Control
Register 14 (ICR14)
Interrupt Control
Register 15 (ICR15)
0x0050
Interrupt Control
Register 16 (ICR16)
Interrupt Control
Register 17 (ICR17)
Interrupt Control
Register 18 (ICR18)
Interrupt Control
Register 19 (ICR19)
0x0054
Interrupt Control
Register 20 (ICR20)
Interrupt Control
Register 21 (ICR21)
Interrupt Control
Register 22 (ICR22)
Interrupt Control
Register 23 (ICR23)
0x0058
Interrupt Control
Register 24 (ICR24)
Interrupt Control
Register 25 (ICR25)
Interrupt Control
Register 26 (ICR26)
Interrupt Control
Register 27 (ICR27)
0x005c
Interrupt Control
Register 28 (ICR28)
Interrupt Control
Register 29 (ICR29)
Interrupt Control
Register 30 (ICR30)
Interrupt Control
Register 31 (ICR31)
0x0060
Interrupt Control
Register 32 (ICR32)
Interrupt Control
Register 33 (ICR33)
Interrupt Control
Register 34 (ICR34)
Interrupt Control
Register 35 (ICR35)
0x0064
Interrupt Control
Register 36 (ICR36)
Interrupt Control
Register 37 (ICR37)
Interrupt Control
Register 38 (ICR38)
Interrupt Control
Register 39 (ICR39)
0x0068
Interrupt Control
Register 40 (ICR40)
Interrupt Control
Register 41 (ICR41)
Interrupt Control
Register 42 (ICR42)
Interrupt Control
Register 43 (ICR43)
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Table 14-5. INTC 32-bit Memory Map (Continued)
0x006c
Interrupt Control
Register 44 (ICR44)
Interrupt Control
Register 45 (ICR45)
Interrupt Control
Register 46 (ICR46)
Interrupt Control
Register 47 (ICR47)
0x0070
Interrupt Control
Register 48 (ICR48)
Interrupt Control
Register 49 (ICR49)
Interrupt Control
Register 50 (ICR50)
Interrupt Control
Register 51 (ICR51)
0x0074
Interrupt Control
Register 52 (ICR52)
Interrupt Control
Register 53 (ICR53)
Interrupt Control
Register 54 (ICR54)
Interrupt Control
Register 55 (ICR55)
0x0078
Interrupt Control
Register 56 (ICR56)
Interrupt Control
Register 57 (ICR57)
Interrupt Control
Register 58 (ICR58)
Interrupt Control
Register 59 (ICR59)
0x007c
Interrupt Control
Register 60 (ICR60)
Interrupt Control
Register 61 (ICR61)
Interrupt Control
Register 62 (ICR62)
Interrupt Control
Register 63 (ICR63)
0x0080-0x00dc
Reserved
0x00e0
Reserved
0x00e4
Reserved
0x00e8
Reserved
0x00ec
IRQ Acknowledge
{IRQIACK)
Reserved
0x00f0
FIQ Acknowledge
(FIQIACK)
Reserved
0x00f4
Reserved
0x00f8
Reserved
0x00fc
Reserved
The platform’s IPS memory map reserves a contiguous 64 KByte space for the interrupt controller(s).
Figure 14-5 shows the 256-byte memory map for a single interrupt controller. For designs with multiple
controllers, see Figure 14-6.
Table 14-6. Multiple Interrupt Controller IPS Memory Map
Configuration
Offset for
intc01
Offset for
intc1
Offset for
intc2
IACK
Addresses
1 controller
0x0000
—
—
0x00ec, 0x00f0
2 controllers
0x0000
+0x4000
—
0xc0ec, 0xc0f0
3 controllers
0x0000
+0x4000
+0x8000
0xc0ec, 0xc0f0
1. The offsets for intc1, intc2 and the IACK addresses are relative to the base of intc0.
14.8.1
14.8.1.1
Register Descriptions
IPR[63:0] - Interrupt Pending Register (IPRH, IPRL)
The IPRH and IPRL registers are each 32 bits in size, and provide a bit map for each interrupt request to
indicate if there is an active request (1 = active request, 0 = no request) for the given source. The state of
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Memory Map/Register Definition
the Interrupt Mask Register does not affect the IPR. The IPR is cleared by reset and updated each platform
clock cycle. The IPR is a read-only register, so any attempted write to this register is terminated with an
error.
Each bit of the IPR[n] is mapped to the corresponding input signal ipi_int[n], i.e., IPR[63:0] is mapped to
ipi_int[63:0].
See Figure 14-2 and Table 14-7 for the IPR definition.
Register address: INTC_Offset + 0x00 (IPRH), + 0x04 (IPRL)
—
—
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
—
—
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
IPR00
—
IPR01
—
IPR02
—
IPR03
—
IPR04
—
IPR05
—
IPR06
—
IPR07
—
IPR08
—
IPR09
—
IPR10
—
IPR11
—
IPR12
—
IPR13
—
IPR14
W
IPR15
R
IPR16
—
IPR17
—
IPR18
—
IPR19
—
IPR20
—
IPR21
—
IPR22
—
IPR23
—
IPR24
—
IPR25
—
IPR26
—
IPR27
—
IPR28
—
IPR29
—
IPR30
W
IPR31
R
IPR32
—
IPR33
—
IPR34
—
IPR35
—
IPR36
—
IPR37
—
IPR38
—
IPR39
—
IPR40
—
IPR41
—
IPR42
—
IPR43
—
IPR44
—
IPR45
—
IPR46
W
IPR47
R
IPR48
16
IPR49
17
IPR50
18
IPR51
19
IPR52
20
IPR53
21
IPR54
22
IPR55
23
IPR56
24
IPR57
25
IPR58
26
IPR59
27
IPR60
28
IPR61
29
IPR62
30
IPR63
31
W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-2. Interrupt Pending (IPRH, IPRL) Registers
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Table 14-7. Interrupt Pending (IPRH, IPRL) Field Descriptions
Name
IPRn,
n = 0,... 63
14.8.1.2
Description
Interrupt Pending Register n
0 The interrupt request n is negated.
1 The interrupt request n is asserted.
IMR[63:0] - Interrupt Mask Register (IMRH, IMRL)
The IMRH and IMRL registers are each 32 bits in size, and provide a bit map for each interrupt to allow
the request to be disabled or “masked” (1 = disable the request, 0 = enable the request). The IMR is set to
all ones by reset, disabling all interrupt requests. The IMR can be read and written directly, or individual
mask flags can be set or cleared by accesses through the SIMR (Set Interrupt Mask) or CIMR (Clear
Interrupt Mask) registers.
Each bit of the IMR[n] is associated with the corresponding bit of the IPR[n].
See Figure 14-3 and Table 14-8 for the IPR definition.
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31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
W
IMR63
IMR62
IMR61
IMR60
IMR59
IMR58
IMR57
IMR56
IMR55
IMR54
IMR53
IMR52
IMR51
IMR50
IMR49
IMR48
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
IMR47
IMR46
IMR45
IMR44
IMR43
IMR42
IMR41
IMR40
IMR39
IMR38
IMR37
IMR36
IMR35
IMR34
IMR33
IMR32
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
W
IMR31
IMR30
IMR29
IMR28
IMR27
IMR26
IMR25
IMR24
IMR23
IMR22
IMR21
IMR20
IMR19
IMR18
IMR17
IMR16
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
IMR15
IMR14
IMR13
IMR12
IMR11
IMR10
IMR09
IMR08
IMR07
IMR06
IMR05
IMR04
IMR03
IMR02
IMR01
IMR00
Register address: INTC_Offset + 0x08 (IMRH), + 0x0c (IMRL)
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R
R
R
R
= Unimplemented or Reserved
Figure 14-3. Interrupt Mask (IMRH, IMRL) Registers
Table 14-8. Interrupt Mask (IMRH, IMRL) Field Descriptions
Name
IMRn,
n = 0,... 63
14.8.1.3
Description
Interrupt Mask Register n
0 The interrupt request n is enabled.
1 The interrupt request n is disabled, i.e., masked.
INTFRC[63:0] - Force Interrupt Register (INTFRCH, INTFRCL)
The INTFRCH and INTFRCL registers are each 32 bits in size, and provide a mechanism to allow
software generation of interrupts for each possible source for functional or debug purposes. The system
design may reserve one or more sources to allow software to self-schedule interrupts by forcing one or
more of these bits (1 = force request, 0 = negate request) in the appropriate INTFRC register. In some
cases, the handling of an interrupt request may cause critical processing by the service routine along with
the scheduling (using the INTFRC register) of a lower-priority interrupt request to be processed at a later
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Memory Map/Register Definition
time for less-critical task handling. The assertion of an interrupt request via the INTFRC register is not
affected by the Interrupt Mask Register. The INTFRC register is cleared by reset.
See Figure 14-4 and Table 14-9 for the INTFRC definition.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
W
IFRC63
IFRC62
IFRC61
IFRC60
IFRC59
IFRC58
IFRC57
IFRC56
IFRC55
IFRC54
IFRC53
IFRC52
IFRC51
IFRC50
IFRC49
IFRC48
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
IFRC47
IFRC46
IFRC45
IFRC44
IFRC43
IFRC42
IFRC41
IFRC40
IFRC39
IFRC38
IFRC37
IFRC36
IFRC35
IFRC34
IFRC33
IFRC32
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
W
IFRC31
IFRC30
IFRC29
IFRC28
IFRC27
IFRC26
IFRC25
IFRC24
IFRC23
IFRC22
IFRC21
IFRC20
IFRC19
IFRC18
IFRC17
IFRC16
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
W
IFRC15
IFRC14
IFRC13
IFRC12
IFRC11
IFRC10
IFRC09
IFRC08
IFRC07
IFRC06
IFRC05
IFRC04
IFRC03
IFRC02
IFRC01
IFRC00
Register address: INTC_Offset + 0x10 (INTFRCH), + 0x14 (INTFRCL)
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R
R
R
R
= Unimplemented or Reserved
Figure 14-4. Force Interrupt (INTFRCH, INTFRCL) Registers
Table 14-9. Force Interrupt (INTFRCH, INTFRCL) Field Descriptions
Description
Value
Name
IFRCn,
n = 0,... 63
Interrupt Force Register n
0 The forced interrupt request n is disabled.
1 A forced interrupt request n is enabled.
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14.8.1.4
Interrupt Configuration (ICONFIG) Register
The ICONFIG register defines the operating configuration for the INTC module. See Figure 14-5 and
Figure 14-10 for the ICONFIG definition.
RESET:
5
EMASK
W
6
EIRQPRI
R
7
EFIQPRI
Register address: INTC_Offset + 0x1b
1
0
1
4
3
2
1
0
0
0
FIQDEF[4:0]
0
0
0
= Unimplemented or Reserved
Figure 14-5. Interrupt Configuration (ICONFIG) Register
Table 14-10. Interrupt Configuration (ICONFIG) Field Descriptions
Name
Description
7
EFIQPRI
Enable Core’s Priority Elevation on FIQ
If set, the assertion of an FIQ request to the core causes the processor’s bus master priority to be temporarily
elevated in the platform’s crossbar switch arbitration logic. The processor’s bus master arbitration priority
remains elevated until the FIQ request is negated. If round-robin arbitration is enabled, this bit has no effect.
If cleared, the assertion of an FIQ request does not affect the processor’s bus master priority.
6
EIRQPRI
Enable Core’s Priority Elevation on IRQ
If set, the assertion of an IRQ request to the core causes the processor’s bus master priority to be temporarily
elevated in the platform’s crossbar switch arbitration logic. The processor’s bus master arbitration priority
remains elevated until the IRQ request is negated. If round-robin arbitration is enabled, this bit has no effect.
If cleared, the assertion of an IRQ request does not affect the processor’s bus master priority.
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Table 14-10. Interrupt Configuration (ICONFIG) Field Descriptions
Name
Description
5
EMASK
Enable Hardware Level Masking
If set, the INTC automatically loads the level of an interrupt request into the CLMASK (current level mask)
when an acknowledge is performed. At the exact same cycle, the value of the current interrupt level mask is
saved in the SLMASK (saved level mask) register.
This feature can be used to support software-managed nested interrupts. The value of SLMASK register
should be read from the INTC and saved in the interrupt stack frame in memory, and restored near the service
routine’s exit.
If cleared, the INTC does not perform any automatic masking of interrupt levels.
4–0
FIQDEF
FIQ Interrupt Level Definition
This 5-bit field defines the mapping of the 16 interrupt levels into the FIQ output signal. The field is defined as:
0x00 = Levels 0 - 15 are mapped as FIQs
0x01 = Levels 1 - 15 are mapped as FIQs
0x02 = Levels 2 - 15 are mapped as FIQs
0x03 = Levels 3 - 15 are mapped as FIQs
0x04 = Levels 4 - 15 are mapped as FIQs
0x05 = Levels 5 - 15 are mapped as FIQs
0x06 = Levels 6 - 15 are mapped as FIQs
0x07 = Levels 7 - 15 are mapped as FIQs
0x08 = Levels 8 - 15 are mapped as FIQs
0x09 = Levels 9 - 15 are mapped as FIQs
0x0a = Levels 10 - 15 are mapped as FIQs
0x0b = Levels 11 - 15 are mapped as FIQs
0x0c = Levels 12 - 15 are mapped as FIQs
0x0d = Levels 13 - 15 are mapped as FIQs
0x0e = Levels 14 - 15 are mapped as FIQs
0x0f = Level
15 is mapped as FIQ
0x1- = No levels are mapped as FIQs; all are IRQs
14.8.1.5
Set Interrupt Mask (SIMR) Register
The SIMR register provides a simple memory-mapped mechanism to set a given bit in the IMR{H,L}
registers to disable (“mask”) a given interrupt request. The data value on a register write causes the
corresponding bit in the IMR{H,L} register to be set. A data value greater than 63 provides a global set
function, forcing the entire contents of IMR{H,L} to be asserted, masking all interrupts. Reads of this
register return all zeroes.
This register is provided so interrupt service routines can easily mask the given interrupt request without
the need to perform a read-modify-write sequence on the IMR{H,L}.
See Figure 14-6 and Figure 14-11 for the SIMR definition.
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Register address: INTC_Offset + 0x1c
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
SIMR[6:0]
RESET:
0
0
0
0
= Unimplemented or Reserved
Figure 14-6. Set Interrupt Mask (SIMR) Register
Table 14-11. Set Interrupt Mask (SIMR) Field Descriptions
Name
6–0
SIMR
Description
Set Interrupt Mask
0-63
Set the corresponding bit in IMR{H,L},
masking the interrupt request
64-127 Set all bits in IMR{H,L}, masking all
interrupt requests
14.8.1.6
Clear Interrupt Mask (CIMR) Register
The CIMR register provides a simple memory-mapped mechanism to clear a given bit in the IMR{H,L}
registers to enable a given interrupt request. The data value on a register write causes the corresponding
bit in the IMR{H,L} register to be cleared. A data value greater than 63 provides a global clear function,
forcing the entire contents of IMR{H,L} to be cleared, enabling all interrupts. Reads of this register return
all zeroes.
This register is provided so interrupt service routines can easily enable the given interrupt request without
the need to perform a read-modify-write sequence on the IMR{H,L}.
In the event of a simultaneous write to both the CIMR and SIMR, the SIMR has priority and the resulting
function would be a set of the interrupt mask register.
See Figure 14-7 and Figure 14-12 for the CIMR definition.
Register address: INTC_Offset + 0x1d
R
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
W
RESET:
CIMR[6:0]
0
0
0
0
= Unimplemented or Reserved
Figure 14-7. Clear Interrupt Mask (CIMR) Register
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Table 14-12. Clear Interrupt Mask (CIMR) Field Descriptions
Name
6–-0
CIMR
Description
Clear Interrupt Mask
0-63
Clear the corresponding bit in IMR{H,L},
enabling the interrupt request
64-127 Clear all bits in IMR{H,L}, enabling all
interrupt requests
14.8.1.7
Current Level Mask (CLMASK) Register
The Current Level Mask Register is provided so the INTC can optionally automatically manage masking
of interrupt requests based on the programmed priority level. If enabled by ICONFIG[EMASK] being set,
an interrupt acknowledge read cycle returns a vector number identifying the physical request source, and
the CLMASK register is loaded with the level number associated with the request. Once the CLMASK
register is updated, then all interrupt requests with level numbers equal to or less than this value are masked
by the controller and are not allowed to cause the assertion of the interrupt signal to the processor core. As
the CLMASK register is updated during the IACK cycle read, the former value is saved in the SLMASK
register. Typically, once a level-n interrupt request is handled, the service routine restores the saved level
mask value into the current level mask register to re-enable the lower priority requests. In addition, an
interrupt service routine can explicitly load this register with a lower priority value to query for any
pending interrupts via software interrupt acknowledge cycles. This topic is covered in more detail in
Section Figure 14.10.3.
See Figure 14-8 and Figure 14-13 for the CLMASK definition.
Register address: INTC_Offset + 0x1e
R
7
6
5
0
0
0
4
3
2
1
0
CLMASK[4:0]
W
RESET:
1
1
1
1
1
= Unimplemented or Reserved
Figure 14-8. Current Level Mask (CLMASK) Register
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Table 14-13. Current Level Mask (CLMASK) Field Descriptions
Name
4–0
CLMASK
Description
Current Level Mask
This 5-bit field is treated as a signed integer within the range [-1, 0, 1,..., 15]. The value defines the level mask,
where only interrupt levels greater than the current value are processed by the controller.
if 0x1f, then level 00 - 15 requests are processed
if 0x00, then level 01 - 15 requests are processed
if 0x01, then level 02 - 15 requests are processed
if 0x02, then level 03 - 15 requests are processed
if 0x03, then level 04 - 15 requests are processed
if 0x04, then level 05 - 15 requests are processed
if 0x05, then level 06 - 15 requests are processed
if 0x06, then level 07 - 15 requests are processed
if 0x07, then level 08 - 15 requests are processed
if 0x08, then level 09 - 15 requests are processed
if 0x09, then level 10 - 15 requests are processed
if 0x0a, then level 11 - 15 requests are processed
if 0x0b, then level 12 - 15 requests are processed
if 0x0c, then level 13 - 15 requests are processed
if 0x0d, then level 14 - 15 requests are processed
if 0x0e, then level
15 requests are processed
if 0x0f - 0x1e,
then all requests are masked
14.8.1.8
Saved Level Mask (SLMASK) Register
The Saved Level Mask Register is provided so the INTC can automatically manage masking of interrupt
requests based on the programmed priority level. If enabled by ICONFIG[EMASK] being set, an interrupt
acknowledge read cycle returns a vector number identifying the physical request source, and the
CLMASK register is loaded with the level number associated with the request and the current contents of
the CLMASK register is loaded into the SLMASK register. Typically, once a level-n interrupt request is
handled, the service routine restores the saved level mask value into the current level mask register to
re-enable the lower priority requests.
See Figure 14-9 and Figure 14-14 for the SLMASK definition.
Register address: INTC_Offset + 0x1f
R
7
6
5
0
0
0
4
3
2
1
0
SLMASK[4:0]
W
RESET:
1
1
1
1
1
= Unimplemented or Reserved
Figure 14-9. Saved Level Mask (SLMASK) Register
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Table 14-14. Saved Level Mask (SLMASK) Field Descriptions
Name
4–0
SLMASK
14.8.1.9
Description
Saved Level Mask
This 5-bit field is treated as a signed integer within the range [-1, 0, 1,..., 15]. The value defines the saved level
mask. See the CLMASK field definition for more information on the specific values.
Interrupt Control Register n (ICRn), n = 0, 1, 2,..., 63
The ICRn registers contain the software-defined interrupt level for each interrupt request. Each ICRn
contains a 4-bit interrupt level [0-15]. These registers are cleared by reset and should be programmed with
the appropriate levels before interrupts are enabled.
When multiple interrupt requests are programmed to the same level number, they are processed in a
descending request number order. As an example, if requests 63, 62, 2, 1 are programmed to a common
level, request 63 is processed first, then request 62, then request 2 and finally request 1.
This definition allows software maximum flexibility in grouping interrupt request sources within any
given priority level.
See Figure 14-10 and Figure 14-15 for the ICRn definition.
Register address: INTC_Offset + 0x40 + n
R
7
6
5
4
3
0
0
0
0
2
1
0
Level[3:0]
W
RESET:
0
0
0
0
= Unimplemented or Reserved
Figure 14-10. Interrupt Control Register n (ICRn)
Table 14-15. Interrupt Control Register n (ICRn) Field Descriptions
Name
Description
3–0
Level
Interrupt Request Level
This 4-bit field maps the given interrupt request to one of 16 levels, where 0x0 is the lowest priority level and 0xf
is the highest priority level.
If interrupt masking is enabled (ICONFIG[EMASK] = 1), the acknowledgment of a level-n request forces the
controller to automatically mask all interrupt requests of level-n and lower.
14.8.1.10 IRQ Interrupt Acknowledge Register (IRQIACK)
The IRQIACK register is a read-only resource containing the vector number of the interrupt request
currently being processed. It is typically read early in an IRQ interrupt service routine. There is a fixed
association between the vector number returned in the IRQIACK register and the physical interrupt request
input signal, namely:
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vector_number =
64 + ipi_int[x] (for a single INTC implementation)
If there is no pending IRQ interrupt request when the read of the IRQIACK is performed, the interrupt
controller returns a value of 63 signalling a spurious interrupt. This is also the reset value of the register.
Any attempted write to this register generates an error termination.
See Figure 14-11 and Figure 14-16 for the IRQIACK definition.
Register address: INTC_Offset + 0xec
7
6
5
R
4
3
2
1
0
Interrupt Vector[7:0]
W
—
—
—
—
—
—
—
—
RESET:
0
0
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 14-11. IRQ Interrupt Acknowledge Register (IRQIACK)
Table 14-16. IRQ Interrupt Acknowledge Register (IRQIACK) Field Descriptions
Name
Description
7–-0
Interrupt Vector Number
Interrupt Vector This 8-bit field provides the vector number for the interrupt request currently being acknowledged. The vector
number is derived from the physical interrupt request signal as:
vector_number = 64 + ipi_int[x]
If there is no pending IRQ request when the IRQIACK is read, a spurious interrupt vector number (63) is returned.
14.8.1.11 FIQ Interrupt Acknowledge Register (FIQIACK)
The FIQIACK register is a read-only resource containing the vector number of the interrupt request
currently being processed. It is typically read early in an FIQ interrupt service routine. There is a fixed
association between the vector number returned in the FIQIACK register and the physical interrupt request
input signal, namely:
vector_number =
64 + ipi_int[x] (for a single INTC implementation)
If there is no pending FIQ interrupt request when the read of the FIQIACK is performed, the interrupt
controller returns a value of 63 signalling a spurious interrupt. This is also the reset value of the register.
Any attempted write to this register generates an error termination.
See Figure 14-12 and Figure 14-17 for the FIQIACK definition.
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Register address: INTC_Offset + 0xf0
7
6
5
R
4
3
2
1
0
Interrupt Vector[7:0]
W
—
—
—
—
—
—
—
—
RESET:
0
0
1
1
1
1
1
1
= Unimplemented or Reserved
Figure 14-12. FIQ Interrupt Acknowledge Register (FIQIACK)
Table 14-17. FIQ Interrupt Acknowledge Register (FIQIACK) Field Descriptions
Name
Description
7–0
Interrupt Vector Number
Interrupt Vector This 8-bit field provides the vector number for the interrupt request currently being acknowledged. The
vector number is derived from the physical interrupt request signal as:
vector_number = 64 + ipi_int[x]
If there is no pending FIQ request when the FIQIACK is read, a spurious interrupt vector number (63) is
returned.
14.9
Functional Description
This section provides an overview of the functional operation of the INTC module.
14.9.1
Interrupt Controller Theory of Operation
To support the interrupt architecture of the ARM core programming model, the combined 64 interrupt
sources are organized as 16 levels, with an arbitrary number of requests programmed to each level.
Consider the priority structure within a single interrupt level (from highest to lowest priority):
level i:ipi_int[a]
ipi_int[b]
ipi_int[c]
ipi_int[d]
programmed
programmed
programmed
programmed
as
as
as
as
level
level
level
level
i (highest priority)
i
i
i (lowest priority)
where the bit numbers [a,b,c,d] are defined such that a > b > c > d. In this example, 4 programmable
interrupt sources are mapped into a single interrupt level.
The operation of the interrupt controller can be broadly partitioned into three activities:
• Recognition
• Prioritization
• Vector Generation during IACK
Recall the INTC is designed to provide a unique vector number for each interrupt request. This allows the
operating system kernel to manage a vector table of addresses defining the starting location for each
interrupt service routine. Throughout this discussion, it is assumed that the vector table contains 32-bit
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Functional Description
addresses and uses the interrupt vector number as an index into this table so that execution in the
appropriate service routine can begin as quickly as possible.
Refer to the INTC block diagram, Figure 14-1, for the subsequent discussion.
14.9.1.1
Interrupt Recognition
The interrupt controller continuously examines the request sources (the IPR register) and the interrupt
mask register (IMR) to determine if there are active requests. This is the recognition phase. The Interrupt
Force Register (INTFRC) also factors into the generation on an active request. An active request
(assuming the hardware masking is enabled) is defined by the following boolean equation:
active_request[n]
14.9.1.2
= (IPR[n]
& ~IMR[n]
| INTFRC[n]) & (ICRn > CLMASK)
Interrupt Prioritization and Level Masking
As an active request is detected, it is first translated into the programmed interrupt level. Next, the
appropriate level masking is performed, if this feature is enabled. Recall the level of the active request must
be greater than the current mask level before it is signaled to the processor. The resulting 16-bit unmasked
decoded priority level (intc_active_level[15:0]) is then driven out of the interrupt controller. The decoded
priority levels from all the interrupt controllers are logically summed together and the highest priority
interrupt level is then encoded into the 2-bit FIQ/IRQ signals that are sent to the processor core during this
prioritization phase. The mapping of the interrupt levels into the 2-bit FIQ/IRQ signals (the level
conversion) is controlled by the ICONFIG[FIQDEF] field.
14.9.1.3
Vector Generation during IACK
Once the core has sampled for pending interrupts and completed interrupt exception processing, it begins
execution of the interrupt service routine (ISR) and typically generates a byte-sized operand read from the
controller known as an interrupt acknowledge cycle. The type of interrupt request being acknowledged
(FIQ or IRQ) determines the access address. The IACK transfer is a memory-mapped byte read via the
AIPS controller of the FIQIACK or IRQIACK register,which, in the case of multiple interrupt controller
instantiations, is routed into a separate interrupt arbiter module that determines the interrupt controller that
gets the IACK transfer based upon which controller has the appropriate level pending. Interrupt arbitration
priority is discussed in Section Figure 14.9.1.4. Next, the interrupt controller determines the highest
unmasked level for the type of interrupt being acknowledged, and generates an 8-bit interrupt vector for
that request to complete the cycle. The 8-bit interrupt vector is formed using the following algorithm:
For intc0,
For optional intc1,
For optional intc2,
vector_number =
64 + ipi_int[x]
vector_number = 128 + ipi_int[x]
vector_number = 192 + ipi_int[x]
where the bit position [x] within the ipi_int[63:0] source directly determines the vector number. Vector
numbers 0 - 63 are reserved for the processor and its internal exceptions. Thus, the following mapping of
bit positions to vector numbers applies for the mandatory intc0:
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Functional Description
if ipi_int[0] is active and acknowledged,
if ipi_int[1] is active and acknowledged,
if ipi_int[2] is active and acknowledged,
...
if ipi_int[63] is active and acknowledged,
then vector_number =
then vector_number =
then vector_number =
64
65
66
then vector_number = 127
The net effect is a fixed mapping between the bit position within the source requests to the actual interrupt
vector number.
If there is no active unmasked interrupt source at the time of the IACK, a special “spurious interrupt”
vector (vector_number = 63) is returned and it is the responsibility of the service routine to handle this
error situation. For interrupting devices following the IPI Indigo protocol, this error condition should never
be encountered.
Note this protocol implies the interrupting peripheral is not accessed during the acknowledge cycle since
the interrupt controller completely services the acknowledge. This means the interrupt source must be
explicitly disabled in the interrupt service routine. This design provides unique vector capability for all
interrupt requests, regardless of the “complexity” of the peripheral device.
In most applications, it is expected that the hardware masking of interrupt levels by the INTC is enabled.
In this mode of operation, the IACK read cycle also causes the current interrupt level mask to be saved in
the SLMASK register, and the new level being acknowledged loaded into the CLMASK register. This
operation then automatically masks the new level (and all lower levels) while in the service routine.
Generally, as the service routine completes execution and the initiating request source has been negated,
the saved mask level is restored into the current mask level to re-enable the lower priority levels.
Finally, the vector number returned during the IACK cycle provides the association with the request and
the physical interrupt signal.
The CLMASK and SLMASK registers are all loaded (if properly enabled) during the interrupt
acknowledge read cycle.
For more information on the specific operations typically performed in an interrupt service routine, see
Section Figure 14.10.3.
It is anticipated that this interrupt controller can be modified to supply the vector number at the same time
as the FIQ/IRQ signals are asserted to the core for future ARM microarchitectures supporting vectored
interrupts, e.g., the ARM11 core.
14.9.1.4
Multiple Controller Requirements
For platform configurations with multiple interrupt controllers, there are additional guidelines which must
be followed to insure correct operation. See Figure 14-6 for information about the mapping of the multiple
controllers within the IPS memory region. For these configurations, there is a separate interrupt arbiter
module that interfaces between the IPS bus and the multiple interrupt controllers. The interrupt arbiter, on
the interrupt controller side, inputs the level pending and the read data from an IACK transfer and outputs
a modified module enable that is based on ’global’ write and IACK transfer information. On the IPS bus
side, the interrupt arbiter inputs the module enables, and special IACK module enable, and the IPS address
bus and outputs the encoded active interrupt request value and the muxed IACK transfer data from all three
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interrupt controllers. The interrupt arbiter is completely combinatorial and does not need to be configured,
however the interrupt controller does have some requirements when more than one is present.
First, the Interrupt Configuration Register (ICONFIG) must be loaded with the exact same value in all
instantiations of the interrupt controller. This is accomplished by writing to the ICONFIG register of intc0.
This single write is then broadcast to all the controllers in the device via the interrupt arbiter.
Second, all reads and writes of the Current Level Mask (CLMASK) and Saved Level Mask (SLMASK)
register must reference the mandatory intc0 controller. For multiple controller designs, the master copy of
these two control registers is maintained in intc0.
Third, the interrupt controllers have a fixed priority, where intc0 is the highest, and intc2 is the lowest. The
net effect is the combined interrupt levels across the multiple controllers are defined as (highest to lowest):
intc0:
intc1:
intc2:
intc0:
intc1:
intc2:
intc0:
intc1:
intc2:
level
level
level
level
level
level
level
level
level
15
15
15
14
14
14
0
0
0
The resulting logic to steer an IACK read in a three-controller configuration using the
intcx_active_level[15:0] output vector is defined in Figure 14-18:
Table 14-18. Global IACK Steering Algorithm1 (3 Controllers)
intc0_active_level
[15:0]
intc1_active_level
[15:0]
intc2_active_level
[15:0]
Level
Acknowledged
IACK Steering
1---------------
----------------
----------------
Level 15
Route to intc0
0---------------
1---------------
----------------
Level 15
Route to intc1
0---------------
0---------------
1---------------
Level 15
Route to intc2
01--------------
0---------------
0---------------
Level 14
Route to intc0
00--------------
01--------------
0---------------
Level 14
Route to intc1
00--------------
00--------------
01--------------
Level 14
Route to intc2
...
...
...
0000000000000001
00000000000000-
000000000000000-
Level 0
Route to intc0
0000000000000000
000000000000001
000000000000000-
Level 0
Route to intc1
0000000000000000
000000000000000
0000000000000001
Level 0
Route to intc2
1. “-” indicates a don’t care logic value.
14.9.2
Performance
There are two key performance parameters for the interrupt controller: latency from the assertion of an
interrupt request, and vector generation timing.
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Initialization/Application Information
As can be seen in the INTC block diagram (Figure 14-1), there are two levels of hardware registers
between the assertion of an interrupt request on the ipi_int[63:0] input and the posting of the FIQ/IRQ
request to the processor core. Thus, if an interrupt request is first asserted in cycle i, then the first assertion
of a properly-enabled request to the processor core occurs in cycle i+2. The processor’s sampling of the
interrupt request signals is then dependent on the instruction stream being executed. For more information
on the core behavior, see the appropriate ARM reference manual. As an example, see Section 2.9, page 69
of the ARM7TDMI Technical Reference Manual, Rev. 4.
As the IACK cycle is performed during the interrupt service routine, it appears as a normal IPS read cycle,
and requires three platform cycles in the AMBA-AHB data phase (2 wait-states).
14.10 Initialization/Application Information
14.10.1 Initialization
The interrupt controller’s reset state has all requests masked via the IMR. Before any interrupt requests are
enabled, the following steps must be taken:
1. The ICONFIG register needs to be set to the desired system configuration.
2. All the ICRn registers need to be programmed with the appropriate interrupt levels.
3. The reset value for the Level Mask registers (CLMASK and SLMASK) are set to -1, the value with
no levels masked. Typically, these registers do not need to be modified before interrupts are
enabled.
4. The appropriate interrupt vector tables and interrupt service routines must be loaded into memory.
Additionally, the memory address pointers for the FIQ and IRQ stacks loaded into the
R13_{fiq,irq} registers.
5. Enable the interrupt requests by clearing the appropriate bits in the IMR and the CPSR[F,I] .
14.10.2 Typical Applications
In many real-time system designs, a typical configuration for supporting priority-based preemptive task
scheduling requires only a single interrupt signal to the processor core. Stated differently, the two levels of
interrupt support provided by an ARM core (FIQ/IRQ) are not necessarily required, and a single level is
sufficient. For ARM cores with only a single interrupt level is implemented, the FIQ exception mode is
typically the one to be used since it provides significantly more hardware resources for the interrupt
processing than IRQ.
By setting ICONFIG[FIQDEF] = 0x00, all interrupt requests are mapped into the FIQ request signal, and
the IRQ core functionality is completely unused.
Another common configuration may chose to define certain “non-maskable” interrupt requests. Typically,
these requests are programmed as level 15, and would be logically connected to the FIQ core input. In this
configuration, priority levels 0-14 would then be available for use of normal (IRQ) requests.
For applications where the wakeup functionality is used, the interrupt controller includes logic that limits
the largest value of the interrupt mask level to “maximum – 1" so the controller can always generate an
sleep mode exit. Thus, if ipg_lp_int_mask is set to the maximum value, the interrupt controller converts
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this value to “maximum – 1" in the wakeup logic. This guarantees that a level 15 interrupt request
generates the sleep mode exit.
14.10.3 Interrupt Service Routines
This section focuses on the interaction of the interrupt masking functionality with the service routine.
Figure 14-13 presents a timing diagram showing various phases during the execution of an interrupt
service routine with the controller level masking functionality enabled. It is important to note the time scale
in this diagram is not meant to be accurate.
A
B
C
D
E
F
G
ipi_int
Interrupt Service Routine
iack
fiq xcpt
CORE
iack
CPSR[F]
CLMASK
n
-1
-1
SLMASK
Interrupts
-1
Enabled
Disabled
Enabled
Disabled
Figure 14-13. Interrupt Service Routine and Masking (Not To Scale)
Consider the events depicted in each “segment” [A-G] of this diagram.
In A, an interrupt request is asserted, which is mapped into the FIQ core signal.
As B begins, the interrupt request is recognized and the core begins FIQ exception processing. During the
core’s exception processing, the CPSR sets the F bit, disabling all interrupts. At the end of the core’s
exception processing, control passes to the interrupt service routine, shown as the beginning of segment C.
During C, the ISR performs the interrupt acknowledge read cycle to retrieve the vector number associated
with the request. As the interrupt acknowledge read is performed, the vector number is returned to the core,
and the CLMASK register raised to level n, the interrupt level being acknowledged. The former contents
of the CLMASK is loaded into the SLMASK register at this time, at the end of C.
During segment D, the ISR accesses the peripheral to negate the interrupt request source. At the conclusion
of segment D, the CPSR[F] flag is cleared to re-enable interrupts.
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The bulk of the interrupt service routine executes in segment E, with interrupts enabled.
Near the end of the service routine, the CPSR[F] flag is again set, disabling interrupt requests, and
preparing to perform the context switch.
At the end of segment F, the original value in the saved level mask (SLMASK) is restored to the current
level mask (CLMASK). Optionally, the service routine can directly load the CLMASK register with any
value with pending interrupt requests of certain levels need to be examined.
In segment G, the interrupt service routine completes execution. During this period of time (recall
interrupts are disabled in the CPSR), it is possible to access the interrupt controller to see if there are any
pending properly-enabled requests. Checking for any pending interrupt requests at this time provides the
ability to initiate processing of another interrupt without the need to return from the original ISR and then
incur the overhead of another interrupt exception.
At the conclusion of segment G, the processor core returns to the original interrupted task, or a different
task that is ready to execute.
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Chapter 15
MAC7200 Crossbar Switch (AXBS)
15.1
Introduction
This section provides information on the layout, configuration, and programming of the crossbar switch
bus. The crossbar switch bus is a two master by five slave (2Mx5S) configuration where the core complex
and the direct memory access controller are the two masters (2M) and the flash controller, FlexBus, RAM
controller, external AHB and the peripheral controller are the five slaves (5S).
Figure 15-1 is a block diagram of the crossbar switch bus connections.
Direct
Memory
Access
Core
Complex
Master
Modules
Crossbar
Switch
Bus
Flash
Controller
FlexBus
Random
Access
Memory
Controller
Slave
Modules
External
AHB
Peripheral
Interface
Controller
Figure 15-1. Crossbar Switch Bus Block Diagram
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Introduction
15.1.1
Overview
The crossbar switch bus connects the bus masters and bus slaves using a crossbar switch structure. This
structure allows bus masters to simultaneously access different bus slaves with no interference while
providing arbitration among the bus masters when they access the same slave. A variety of bus arbitrations
methods and attributes may be programmed on a bus slave by bus slave basis.
15.1.2
Features
The crossbar switch bus includes these distinctive features:
• Symmetric crossbar bus switch implementation
— Allows concurrent accesses from different masters to different slaves
— Slave arbitration attributes configured on a slave by slave basis
• The crossbar switch bus is 32 bits wide and supports byte, half-word (2byte), word (4byte), and
16byte burst transfers
• 32-bit address bus width, 32-bit data bus width
• Crossbar switch bus operates at a 1-to-1 clock frequency with the bus masters
• Support for AHB v2.0 AHB-Lite bus protocol
• Up to 8x8 simultaneous Master => Slave connections
• Each Slave Port is individually configurable via a Peripheral Bus interface
• Memory Map: 32-bit peripheral with 256 bytes per slave port, word addressable only
• Each slave port has a 3-bit base address, to select a 512Mb address space within the 4Gb
addressable space. All combinations of master/slave are valid. The crossbar switch can support
simultaneous master transactions, as long as the slave being accessed is different.
Table 15-1. Crossbar Slave Port Addresses
15.1.3
Slave Port
Address Range
S0
$0000_0000 - $1FFF_FFFF
S1
$2000_0000 - $3FFF_FFFF
S2
$4000_0000 - $5FFF_FFFF
S3
$6000_0000 - $7FFF_FFFF
S4
$8000_0000 - $9FFF_FFFF
S5
$A000_0000 - $BFFF_FFFF
S6
$C000_0000 - $DFFF_FFFF
S7
$E000_0000 - $FFFF_FFFF
AXBS Integration
The AXBS is integrated with the following configuration:
• Alternate Master Priority (AMPR) register is not enabled
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External Signal Description
•
•
•
•
•
•
•
•
•
Alternate Slave General Purpose (ASGPR) register is not enabled
Master Port 0 (ARM7 core) is present with burst enabled
Master Port 1 (DMA) is present with burst disabled
Slave Port 0 (Flash) is present
Slave Port 1 (FlexBus) is present
Slave Port 3 (SRAM) is present
Slave Port 5 (BAM) is present
Slave Port 7 (AIPS) is present
32-bit datapath
Table 15-2. MAC72xx AXBS Master and Slave Ports
Master Port
Slave Port
M0: ARM7 Core
S0: Selectable
M1: eDMA
S1: Selectable
S3: SRAM Controller
S5: Boot Assist Module (BAM)
S7: Peripheral Bus Bridge (AIPS)
15.1.4
Modes of Operation
The crossbar switch bus provides two arbitration modes, fixed or round-robin. The arbitration mode may
be set on a slave by slave basis. For slaves configured for fixed arbitration mode, a unique arbitration level
is assigned to each bus master.
For a given slave with fixed arbitration operation, the highest priority active master accessing that slave is
granted the master bus switch path to that slave. A higher priority master will block access to a given slave
from a lower priority master as long as the higher priority master continuously requests that slave.
For a given slave with round-robin arbitration, active masters accessing that slave are initially granted the
slave based on their master port number. Master priority is then modified in a wrap-around manner to give
all masters fair access to the slave.
15.2
External Signal Description
There are no AXBS signals that drive or are driven from MCU pins.
15.3
Memory Map Definition
There are two registers that reside in each slave port of the crossbar switch bus. Read and write transfers
both require two IP bus clock cycles. The registers can only be read from and written to in supervisor
mode. Additionally, these registers can only be read from or written to by 32-bit accesses. Non 32-bit
accesses to legal registers are ignored.
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Register Descriptions
The registers are fully decoded and a bus error response is returned if an unimplemented location is
accessed within the crossbar switch bus.
The slave registers also feature a bit, which when written with a 1, will prevent the registers from being
written to again. The registers will still be readable, but future write attempts will have no effect on the
registers and will be terminated with an error response.
Table 15-3 is the memory map for the crossbar switch bus program-visible registers.
Table 15-3. Module Memory Map
Offset from
crossbar_base
Register Name and Use
Access
0x000
Priority Register for Flash Controller Slave port (PR_FC)
word (4byte)
0x010
Control Register for Flash Controller Slave port (CR_FC)
word (4byte)
0x100
Priority Register for FlexBus Slave port (PR_FB)
word (4byte)
0x110
Control Register for FlexBus Slave port (CR_FB)
word (4byte)
0x300
Priority Register for RAM Controller Slave port (PR_RC)
word (4byte)
0x310
Control Register for RAM Controller Slave port (CR_RC)
word (4byte)
0x500
Priority Register for external AHB Slave port (PR_AHB)
word (4byte)
0x510
Control Register for external AHB Slave port (CR_AHB)
word (4byte)
0x700
Priority Register for Peripheral Controller Slave port (PR_PC)
word (4byte)
0x710
Control Register for Peripheral Controller Slave port (CR_PC)
word (4byte)
15.4
Register Descriptions
This section consists of register descriptions for the crossbar switch bus.
15.4.1
Priority Register
The Priority Register (PR) sets the priority of each master port on a per slave port basis and resides in each
slave port.
Table 15-4. Priority Register Summary
PR_FC
PR_FB
PR_RC
PR_AHB
PR_PC
Bit
Priority Register for Slave Port to Flash Controller
Priority Register for Slave Port to FlexBus
Priority Register for Slave Port to RAM Conttroller
Priority Register for Slave Port to external AHB
Priority Register for Slave Port to Peripheral Controller
31
30
29
28
27
26
25
Name
24
23
crossbar_base + 0x000
crossbar_base + 0x100
crossbar_base + 0x300
crossbar_base + 0x500
crossbar_base + 0x700
22
21
20
19
18
17
16
Reserved
Type
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
r
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
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Register Descriptions
Table 15-4. Priority Register Summary (Continued)
Name
Reserved
DMA
Core
Type
r
r
r
r
r
r
r
r
r
r
r
rw
r
r
r
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Table 15-5. Priority Register Descriptions
Field
Description
31–5
Priority Register Reserved. These bits are reserved for future expansion. They read as zeros and should be written
with zeros for upward compatibility.
4
DMA_
MSTR
3–1
0
CORE_
MSTR
DMA Master Priority. This bit sets the arbitration priority for this port on the associated slave port.
This bit is initialized by hardware reset. The reset value is 1.
0 This master has the highest priority when accessing the slave port.
1 This master has the lowest priority when accessing the slave port.
Priority Register Reserved.These bits are reserved for future expansion. They read as zeros and should be written
with zeros for upward compatibility.
Core Master Priority. This bit sets the arbitration priority for this port on the associated slave port.
This bit is initialized by hardware reset. The reset value is 0
0 This master has the highest priority when accessing the slave port.
1 This master has the lowest priority when accessing the slave port.
The Priority Register can only be accessed with 32-bit accesses. Once the RO (Read Only) bit has been set
in the slave Control Register the Priority Register can only be read, attempts to write to it will have no
effect on the PR and result in a bus error response.
Additionally, no two available master ports may be programmed with the same priority level. Attempts to
program two or more available masters with the same priority level will result in an error response and the
PR will not be updated.
15.4.2
Control Register
The Control Register (CR) controls several features of each slave port.
The Read Only (RO) bit will prevent any registers associated with this slave port from being written to
once set. This bit may be written with 0 as many times as the user desires, but once it is written to a 1 only
a reset condition will allow it to be written again.
The Halt Low Priority (HLP) bit will set the priority of a request to enter low power mode to the lowest
possible priority for initial arbitration of the slave ports. By default it is the highest priority. Please note,
setting this bit will not effect the request for low power mode from attaining highest priority once it has
control of the slave ports.
The Arbitration Mde (ARB) bits control the arbitration mode. The arbitration mode may be fixed or
round-robin.
The Parking Control (PCTL) bits determine how the slave port will park when no master is actively
making a request. The available options are to park on the master defined by the PARK bits, park on the
last master to use the slave port, or go into a low power park mode which will force all the outputs of the
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Register Descriptions
slave port to inactive states when no master is requesting an access. The low power park feature can result
in an overall power savings if the slave port is not saturated; however, it will force an extra clock of latency
whenever any master tries to access it when it is not in use because it will not be parked on any master.
The PARK bits determine which master the slave will park on when no master is making an active request
and there is no request for low power mode. Please use caution to only select master ports that are actually
present in the design.
Table 15-6. Control Register Summary
CR_FC
CR_FB
CR_RC
CR_AHB
CR_PC
Control Register for Slave Port to Flash Controller
Control Register for Slave Port to FlexBus
Control Register for Slave Port to RAM Conttroller
Control Register for Slave Port to external AHB
Control Register for Slave Port to Peripheral Controller
Bit
31
30
Name
RO
HLP
Type
rw1
Reset
Bit
crossbar_base + 0x010
crossbar_base + 0x110
crossbar_base + 0x310
crossbar_base + 0x510
crossbar_base + 0x710
29
28
27
26
25
24
23
22
21
20
19
18
17
16
rw
r
r
r
r
r
r
r
r
r
r
r
r
r
r
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
ARB
PCTL
Park
Type
r
r
r
r
r
r
rw
rw
r
r
rw
rw
r
r
r
rw
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1. Once this bit is written to a 1 only hardware reset will return it to a 0.
Table 15-7. Control Register Descriptions
Name
Description
31
RO
Read Only. This bit is used to force all of a slave port’s registers to be read only. Once written to 1 it can only be
cleared by hardware reset.
This bit is initialized by hardware reset. The reset value is 0.
0 All this slave port’s registers can be written.
1 All this slave port’s registers are read only and cannot be written (attempted writes have no effect and result in an
error response).
30
HLP
Halt Low Priority. This bit is used to set the initial arbitration priority for low power mode requests.
This bit is initialized by hardware reset. The reset value is 0
0 The low power mode request has the highest priority for arbitration on this slave port.
1 The low power mode request has the lowest initial priority for arbitration on this slave port.
29–10
9–8
ARB
Control Register Reserved. These bits are reserved for future expansion. They read as zero and should be written
with zero for upward compatibility.
Arbitration Mode. These bits are used to select the arbitration policy for the slave port.
These bits are initialized by hardware reset. The reset value is 00.
00 Fixed Priority.
01 Round Robin (rotating) Priority.
10 Reserved
11 Reserved
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Functional Description
Table 15-7. Control Register Descriptions (Continued)
Name
7–6
Description
Control Register Reserved. These bits are reserved for future expansion. They are read as zero and should be
written with zero for upward compatibility.
5–4
PCTL
Parking Control. These bits determine the parking control used by this slave port.
These bits are initialized by hardware reset. The reset value is 00.
00 When no master is making a request the arbiter will park the slave port on the master port defined by the PARK
bit field.
01 When no master is making a request the arbiter will park the slave port on the last master to be in control of the
slave port.
10 When no master is making a request the arbiter will park the slave port on no master and will drive all outputs to
a constant safe state.
11 Reserved
3–1
Slave General Purpose Control Register Reserved. This bit is reserved for future expansion. It is read as zero and
should be written with zero for upward compatibility.
0
PARK
PARK - This bit is used to determine which master port this slave port parks on when no masters are actively making
requests and the PCTL bits are set to 00.
This bit is initialized by hardware reset. The reset value is 0.
0 Park on CORE Master Port.
1 Park on DMA Master Port.
The CR can only be accessed with 32-bit accesses. Once the RO (Read Only) bit has been set in the CR
the CR can only be read, attempts to write to it will have no effect on the CR and result in an error response.
15.5
Functional Description
This section describes in more detail the functionality of the crossbar switch bus.
15.5.1
Arbitration
The crossbar switch bus supports two arbitration schemes; a simple fixed-priority comparison algorithm,
and a simple round-robin fairness algorithm. The arbitration scheme is independently programmable for
each slave port.
15.5.1.1
Fixed Priority Operation
When operating in fixed-priority mode, each master is assigned a unique priority level in the PR (Priority
Register). If two masters both request access to a slave port the master with the highest priority in the
selected priority register will gain control over the slave port.
Any time a master makes a request to a slave port the slave port checks to see if the new requesting master’s
priority level is higher than that of the master that currently has control over the slave port (unless the slave
port is in a parked state). The slave port does an arbitration check at every bus transfer boundary to ensure
that the proper master (if any) has control of the slave port.
If the new requesting master’s priority level is higher than that of the master that currently has control of
the slave port the new requesting master will be granted control over the slave port at the next clock edge.
The exception to this rule is if the master that currently has control over the slave port is running a fixed
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Initialization/Application Information
length burst transfer or a locked transfer. In this case the new requesting master will have to wait until the
end of the burst transfer or locked transfer before it will be granted control of the slave port.
If the new requesting master’s priority level is lower than that of the master that currently has control of
the slave port the new requesting master will be forced to wait until the master that currently has control
of the slave port either runs an IDLE cycle or runs a non IDLE cycle to a location other than the current
slave port.
15.5.1.2
Round-Robin Priority Operation
When operating in round-robin mode, each master is assigned a relative priority based on the master port
number. This priority is based on how far ahead the master port number of the requesting master is to the
master port number of the current bus master for this slave. Master port numbers are compared modulo the
total number of bus masters, i. e. take the requesting master port number minus the current bus master’s
port number modulo the total number of bus masters. The master port whose priority is the highest based
on this comparison will be granted control over the slave port at the next bus transfer boundary.
For the case of only the two bus masters on this device, this means when operating in round-robin mode,
if the core complex is the current bus master for a given slave, than the DMA has the highest priority when
requesting that slave. Likewise, if the DMA is the current bus master for a given slave, then the core
complex has the highest priority when requesting that slave.
Once granted access to a slave port, a master may perform as many transfers as desired to that port until
another master makes a request to the same slave port. The next master in line will be granted access to
the slave port at the next transfer boundary.
Parking may still be used in a round-robin mode, but will not affect the round-robin pointer unless the
parked master actually performs a transfer. Handoff will occur to the next master in line after one cycle of
arbitration. If the slave port is put into low power park mode the round-robin pointer will be reset to point
at master port 0, giving it the highest priority.
15.5.2
Priority Assignment
Each master port needs to be assigned a unique 1 bit priority level. If an attempt is made to program
multiple master ports with the same priority level within the priority register (PR) the crossbar switch bus
will respond with a bus error and the registers will not be updated.
15.6
Initialization/Application Information
No initialization is required by or for the crossbar switch bus. Hardware reset ensures all the register bits
used by the crossbar switch bus are properly initialized.
15.7
15.7.1
AXBS Bus Aborts
IPI Register Interface
The AXBS module supports Peripheral Bus bus aborts, and enforces the following memory map:
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AXBS Bus Aborts
Table 15-8. AXBS Bus Aborts
Abort
Allowed
$0000-$0007
$0008-$000f
$0010-$0017
$0018-$00ff
$0100-$0107
$0108-$010f
$0110-$0117
$0118-$01ff
$0200-$0207
$0208-$020f
$0210-$0217
$0218-$02ff
$0300-$0307
$0308-$030f
$0310-$0317
$0318-$03ff
$0400-$0407
$0408-$040f
$0410-$0417
$0418-$04ff
$0500-$0507
$0508-$050f
$0510-$0517
$0518-$05ff
$0600-$0607
$0608-$060f
$0610-$0617
$0618-$06ff
$0700-$0707
$0708-$070f
$0710-$0717
$0718-$07ff
$0800-$0804
$0805-$08ff
$0900-$0904
$0905-$09ff
$0a00-$0a04
$0a05-$0aff
$0b00-$0b04
$0b05-$0bff
$0c00-$0c04
$0c05-$0cff
$0d00-$0d04
$0d05-$0dff
$0e00-$0e04
$0e05-$0eff
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AXBS Differences from MAC71xx
Table 15-8. AXBS Bus Aborts (Continued)
Abort
Allowed
$0f00-$0f04
$0f05-$3fff
If any part of a read or write falls within an aborted region, the entire transfer is aborted. Since all AXBS
registers are 32-bit, you can not have the situation where an access is partially in an aborted region.
Supervisor Access: All accesses to the AXBS registers must be in Supervisor Mode. All User Mode
accesses are aborted.
NOTE
If the RO bit in a slave port’s Slave General Purpose Control Register is set,
then any write access to that slave’s registers will be aborted.
15.7.2
Master/Slave Interface
In addition to the IPI interface, the AXBS can abort transfers through the crossbar itself. The following
transfers will be aborted:
• Transfers to an unused slave port, as follows:
— S2: $4000_0000 - $5FFF_FFFF
— S4: $8000_0000 - $9FFF_FFFF
— S6: $C000_0000 - $DFFF_FFFF
• Writing to a slave address when the RO bit in the slave’s SGPCR register is set (1).
15.8
•
•
AXBS Differences from MAC71xx
Addition of Slave 5 port (BAM). Note that the BAM code is accessible by the application software.
Replaced tightly coupled Flash bus with Slave 0 port. This means that the DMA may also access
the Flash through the same bus as the ARM7 core.
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Chapter 16
AHB to IPI Bridge (AIPS)
16.1
Introduction
The AIPS provides the interface between the 32-bit system bus (AHB-Lite 2.v6) and the 32-bit peripheral
bus. The AIPS can support up to 32 peripherals, and implements various levels of protection for each
peripheral, including a trusted master scheme for both the ARM7 core (MASTER0) and the eDMA
(MASTER1).
Not all peripherals are present on all devices. It is the responsibility of the application to ensure that no
accesses to reserved address ranges are performed.
16.1.1
Features
The following list summarizes the key features of the AIPS:
• Support for AHB v2.0 AHB-Lite bus protocol
• 32-bit address bus width
• 32-bit data bus width
• 2 clocks for READs, 3 clocks for WRITEs
• 32 on-platform peripheral module enables
• 32 off-platform peripheral module enables (+ one bit-wise OR signal)
• 2 global off-platform address space module enables
• Supervisor/User/Test access support
• Software enabled write buffering (posted write)
• Memory Map: 64MByte (ADDR[25:0]), byte addressable
— 512KByte: Platform Peripherals #0-#31 (32 modules x 16KBytes each)
– $0000_0000 - $0007_FFFF
— 512KByte: MAC72xx Peripherals (32 peripherals x 16KBytes each)
– $0008_0000 - $00F_FFFF
— 63MBytes: Global External Address Space
– $0010_0000 - $03FF_FFFF
• The AIPS is not relocatable under any circumstances
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Introduction
16.1.2
General Operation
The AIPS is the interface between the AHB-Lite 2.v6 interface and on-chip IPS v3.0 peripherals as shown
in Figure 16-1.
ARM7TDMI-S
CPU
Direct Memory
Access
32
32
Master Modules
Cross-Bar
Switch
Slave Modules
32
External
Interface Module
32
32
Random Access
Memory Controller
Peripheral
Bus Bridge
32
SPP
Peripherals
SPP
Peripheral 0
SPP
Peripheral 31
IPS
Peripheral 0
IPS
Peripheral 31
IPS
Global 0
IPS
Global 1
IPS
Peripherals
Figure 16-1. AIPS Interface Block Diagram
IPS peripherals are modules that contain readable/writable control and status registers. The AHB master
reads and writes these registers through the AIPS. The AIPS generates module enables, the module
address, transfer attributes, byte enables and write data as inputs to the IPS peripherals. The AIPS captures
read data from the IPS interface and drives it on the AHB.
The AIPS occupies a 64MByte portion of the address space. A 0.5MByte portion of this space is allocated
to on-platform peripherals. The remaining 63.5MBytes are available for off-platform devices. The register
maps of the IPS peripherals are located on 16Kbyte boundaries. Each IPS peripheral is allocated one
16Kbyte block of the memory map, and is activated by one of the module enables from the AIPS. Up to
thirty-two 16Kbyte external IPS peripherals may be implemented, occupying contiguous blocks of
16Kbytes. Two global external IPS module enables are available for the remaining 63Mbytes of address
space to allow for customization and expansion of addressed peripheral devices. In addition, a single
“non-global” module enable is also asserted whenever any of the thirty-two non-global module enables is
asserted.
The AIPS memory map is shown in Figure 16-2.
The connection of a particular module enable to a peripheral, and hence the exact address assignment for
an IPS peripheral is system dependent, and is defined in the system specification. Each IPS peripheral
selects its internal registers based on the address driven.
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AIPS Protocol
0x0000 0000
0x0000 4000
0x0000 8000
0x0000 C000
0x0007 8000
0x0007 C000
0x0008 0000
0x0008 4000
0x0008 8000
0x0008 C000
0x000F C000
–
–
–
–
•
•
•
–
–
–
–
–
–
•
•
•
–
0x0000
0x0000
0x0000
0x0000
3FFF
7FFF
BFFF
FFFF
0x0007
0x0007
0x0008
0x0008
0x0008
0x0008
BFFF
FFFF
3FFF
7FFF
BFFF
FFFF
0x000F FFFF
AIPS (SPP Module 0)
SPP Module 1
SPP Module 2
SPP Module 3
•
•
•
SPP Module 30
SPP Module 31
IPS Module 0
IPS Module 1
IPS Module 2
IPS Module 3
•
•
•
IPS Module 31
0x0010 0000 – 0x01FF FFFF
IPS
Global Module 0
0x0200 0000 – 0x03FF FFFF
IPS
Global Module 1
Figure 16-2. AIPS Memory Map
The AIPS is responsible for indicating to IPS peripherals if an access is in supervisor or user mode. The
AIPS may block user mode accesses to certain IPS peripherals or it may allow the individual IPS
peripherals to determine if user mode accesses are allowed. In addition, peripherals may be designated as
write-protected. The AIPS supports the notion of “trusted” masters for security purposes. Masters may be
individually designated as trusted for reads, trusted for writes, or trusted for both reads and writes, as well
as being forced to look as though all accesses from a master are in user-mode privilege level. Refer to
Section 16.4.2, “Control Registers,” for more information.
All peripheral devices require aligned accesses equal to or smaller in size than the peripheral size. An
exception to this rule is supported for 32-bit peripherals to allow memory to be placed on the IPS.
16.2
16.2.1
AIPS Protocol
8/16/32--bit accesses
The following table defines the byte ordering scheme on the IPI bus in the MAC72xx.
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AIPS Protocol
Table 16-1. AIPS 32-bit byte lanes
ips_addr[1:0]
data[31:24]
00
X
data[23:16]
Byte
01
data[15:8]
data[7:0]
X
10
X
Halfword
11
X
00
X
X
01
ERR
ERR
Word
10
ERR
ERR
X
X
11
ERR
ERR
ERR
ERR
00
X
X
X
X
01
ERR
ERR
ERR
ERR
10
ERR
ERR
ERR
ERR
11
ERR
ERR
ERR
ERR
Essentially, this is a “big endian like” bus, in the sense that high-order bits are stored at the lowest address.
32-bit register
Implement one 32-bit register REG1 with base address $00.
31
30
29
28
27
26
25
R
24
23
22
21
20
19
18
17
16
6
5
4
3
2
1
0
REG1[31:16]
W
RESET:
15
14
13
12
11
10
R
9
8
7
REG1[15:0]
W
RESET:
= Unimplemented or Reserved
Register address: Base + $00
Figure xx: Register #1 Description (REG1)
Performing a READ operation will return the following data:
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Word Halfword
Byte
AIPS Protocol
Address
Data
$00
REG1[31:24]
$01
REG1[23:16]
$02
REG1[15:8]
$03
REG1[7:0]
$00
REG1[31:16]
$02
REG1[15:0]
$00
REG1[31:0]
Two 16-bit registers
Implement two 16-bit registers REG1 and REG2, with REG1 having a base address of $00, and REG2
having a base address of $02.
15
14
13
12
11
10
9
R
8
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
REG1
W
RESET:
= Unimplemented or Reserved
Register address: $00
Figure xx: Register #1 Description (REG1)
15
14
13
12
11
10
R
9
8
7
REG2
W
RESET:
= Unimplemented or Reserved
Register address: $02
Figure xx: Register #2 Description (REG2)
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AIPS Protocol
Word Halfword
Byte
Performing a READ operation will return the following data:
Table 1:
Address
Data
$00
REG1[15:8]
$01
REG1[7:0]
$02
REG2[15:8]
$03
REG2[7:0]
$00
REG1[15:0]
$02
REG2[15:0]
$00
{REG1[15:0] , REG2[15:0] }
Four 8-bit registers
Implement four 8-bit registers REG1, REG2, REG3 and REG4, with addresses of $00, $01, $02 and $03,
respectively.
7
6
5
R
4
3
2
1
0
1
0
REG1
W
RESET:
= Unimplemented or Reserved
Register address: $00
Figure xx: Register #1 Description (REG1)
7
6
R
5
4
3
2
REG2
W
RESET:
= Unimplemented or Reserved
Register address: $01
Figure xx: Register #2 Description (REG2)
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External Signal Description
7
6
5
R
4
3
2
1
0
1
0
REG3
W
RESET:
= Unimplemented or Reserved
Register address: $02
Figure xx: Register #3 Description (REG3)
7
6
5
R
4
3
2
REG4
W
RESET:
= Unimplemented or Reserved
Register address: $03
Figure xx: Register #4 Description (REG4)
Word Halfword
Byte
Performing a READ operation will return the following data:
16.3
Address
Data
$00
REG1[7:0]
$01
REG2[7:0]
$02
REG3[7:0]
$03
REG4[7:0]
$00
{REG1[7:0] , REG2[7:0]}
$02
{REG3[7:0] , REG4[7:0]}
$00
{REG1[7:0] , REG2[7:0] , REG3[7:0] , REG4[7:0]}
External Signal Description
The AIPS has no external pins.
16.4
Memory Map/Register Definition
This section provides information on AIPS registers.
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Memory Map/Register Definition
16.4.1
Overview
There are eleven registers that control the AIPS. All registers are 32-bit registers and can only be accessed
in supervisor mode by trusted bus masters. Additionally, these registers must only be read from or written
to by a 32-bit aligned access. AIPS registers are mapped into the PACR0 address space.
Two system clocks are required for read accesses and three system clocks are required for write accesses
to the AIPS registers.
16.4.2
Control Registers
The memory map for the AIPS program-visible registers is shown in Table 16-2. The MPROT fields of
the MPR and the PACR and OPACR registers are 4 bits in width.
Table 16-2. AIPS Register Memory Map
AIPS Offset
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]
0x0000
MPROT0
MPROT1
RFU
RFU
RFU
RFU
RFU
RFU
0x0004
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
0x0020
PACR0
PACR1
PACR2
RFU
RFU
RFU
RFU
RFU
0x0024
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
0x0028
PACR16
PACR17
PACR18
RFU
RFU
RFU
RFU
RFU
0x002c
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
0x0040
OPACR0
OPACR1
OPACR2
OPACR3
RFU
OPACR5
OPACR6
RFU
0x0044
RFU
RFU
RFU
OPACR11
RFU
OPACR13
OPACR14
OPACR15
0x0048
RFU
OPACR17
OPACR18
RFU
RFU
RFU
RFU
OPACR23
0x004c
OPACR24
RFU
OPACR26
RFU
OPACR28
RFU
RFU
RFU
0x0050
Reserved
For the MAC7200, the processor complex is master zero and the enhanced direct memory access module
is master one. The mapping between access control registers and peripheral modules is shown in the
following table. Note that not all peripherals can be accessed in all MAC7200 operational modes.
Table 16-3. MAC7200 Peripheral to Access Control Register Map
Address Range
Module
Access Control Register
0xFC00_0000 – 0xFC00_3FFF
AIPS – AMBA to IP Bus Bridge
PACR0
0xFC00_4000 – 0xFC00_7FFF
AXBS – AMBA Crossbar Switch
PACR1
PACR2
0xFC00_8000 – 0xFC00_BFFF
FlexBus – External Interface Module
0xFC00_C000 – 0xFC03_FFFF
RFU
0xFC04_0000 – 0xFC04_3FFF
MCM – Miscellaneous Control Module
PACR16
0xFC04_4000 – 0xFC04_7FFF
eDMA – Enhanced Direct Memory Access Controller
PACR17
PACR18
0xFC04_8000 – 0xFC04_BFFF
INTC – Interrupt Controller
0xFC04_C000 – 0xFC07_FFFF
RFU
0xFC08_0000 – 0xFC08_3FFF
SSM – System Service Module
OPACR0
0xFC08_4000 – 0xFC08_7FFF
DMA Mux – Direct Memory Access Controller Mux
OPACR1
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Memory Map/Register Definition
Table 16-3. MAC7200 Peripheral to Access Control Register Map (Continued)
Address Range
Module
Access Control Register
0xFC08_8000 – 0xFC08_BFFF
CRG – Clock and Reset Generator
OPACR2
0xFC08_C000 – 0xFC08_FFFF
PIT – Programmable Interval Timer
OPACR3
0xFC09_0000 – 0xFC09_3FFF
RFU
0xFC09_4000 – 0xFC09_7FFF
FlexCAN_A – CAN Controller 0
OPACR5
OPACR6
0xFC09_8000 – 0xFC09_BFFF
FlexCAN_B – CAN Controller 1
0xFC09_C000 – 0xFC0A_BFFF
RFU
0xFC0A_C000 – 0xFC0A_FFFF
IIC – Inter-IC bus
0xFC0B_0000 – 0xFC0B_3FFF
RFU
OPACR11
0xFC0B_4000 – 0xFC0B_7FFF
DSPI_A – Serial Peripheral Interface 0
OPACR13
0xFC0B_8000 – 0xFC0B_BFFF
DSPI_B – Serial Peripheral Interface 1
OPACR14
0xFC0B_C000 – 0xFC0B_FFFF
DSPI_C – Serial Peripheral Interface 2
OPACR15
0xFC0C_0000 – 0xFC0C_3FFF
RFU
0xFC0C_4000 – 0xFC0C_7FFF
ESCI_A – Enhanced Serial Communication Interface 0
OPACR17
0xFC0C_8000 – 0xFC0C_BFFF
ESCI_B – Enhanced Serial Communication Interface 1
OPACR18
0xFC0C_C000 – 0xFC0D_BFFF
RFU
0xFC0D_C000 – 0xFC0D_FFFF
eMIOS – Enhanced Modular I/O Subsystem
OPACR23
0xFC0E_0000 – 0xFC0E_3FFF
ATD – Analog to Digital Converter
OPACR24
0xFC0E_4000 – 0xFC0E_7FFF
RFU
0xFC0E_8000 – 0xFC0E_BFFF
PIM – Port Integration Module
0xFC0E_C000 – 0xFC0E_FFFF
RFU
OPACR26
0xFC0F_0000 – 0xFC0F_3FFF
PFM – Platform Flash Module registers
0xFC0F_4000 – 0xFFFF_FFFF
RFU
16.4.3
16.4.3.1
OPACR28
Register Descriptions
Master Privilege Registers (MPROT)
Each MPR specifies eight 4-bit fields defining the access privilege level associated with a bus master. The
registers provide one field per bus master.
Access: User read/write
3
R
2
1
0
MTR
MTW
MPL
1
1
1
0
W
Reset
0
Figure 16-3. Master Protection Registers (MPROT)
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Memory Map/Register Definition
Table 16-4. MPROT Field Descriptions
Field
Description
0
MPL
Master Privilege Level. This bit determines how the privilege level of the master is determined.
0 Accesses from this master are forced to user-mode regardless of the master’s access attribute.
1 Accesses from this master are not forced to user-mode. The master’s access attribute is used directly to
determine the peripheral’s access attribute
1
MTW
Master Trusted for Writes. This bit determines whether the master is trusted for write accesses
0 This master is not trusted for write accesses.
1 This master is trusted for write accesses.
2
MTR
Master Trusted for Reads. This bit determines whether the master is trusted for read accesses
0 This master is not trusted for read accesses.
1 This master is trusted for read accesses.
3
Reserved, should be cleared.
Accesses to registers or register fields which correspond to master or peripheral locations which are not
implemented will return zeros on reads, and will be ignored on writes.
16.4.3.2
Peripheral Access Control Registers (PACR)
Each of the on-platform peripherals have a Peripheral Access Control Register which defines the access
levels supported by the given module. Each PACR has the following format:
Access: User read/write
3
R
2
1
0
SP
WP
TP
0
W
Reset, PACR0
0
1
0
1
Reset, PACRn
0
1
0
0
Figure 16-4. Peripheral Access Control Registers (PACR)
Table 16-5. PACR Field Descriptions
Field
Description
0
TP
Trusted Protect. This bit determines whether the peripheral allows accesses from an untrusted master.
0 Accesses from an untrusted master are allowed.
1 Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master, the access
is terminated with an error response and no peripheral access is initiated on the IPS bus.
1
WP
Write Protect. This bit determines whether the peripheral allows write accesses
0 This peripheral allows write accesses.
1 This peripheral is write protected. If a write access is attempted, the access is terminated with an error response
and no peripheral access is initiated on the IPS bus.
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Functional Description
Table 16-5. PACR Field Descriptions (Continued)
Field
Description
2
SP
Supervisor Protect. This bit determines whether the peripheral requires supervisor privilege level for access.
0 This peripheral does not require supervisor privilege level for accesses.
1 This peripheral requires supervisor privilege level for accesses. The master privilege level must indicate
supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must be set. If not,
the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
3
Reserved, should be cleared.
Presence or absence of a particular PACR is based on whether the associated peripheral is present in the
platform, as denoted by the synthesis configuration parameters defined in Section 16.5.1, “AIPS
Scalability.” When absent, the corresponding PACR is not implemented and will read as 0’s. Writes will
be ignored.
16.4.3.3
Off-Platform Peripheral Access Control Registers (OPACRs)
Each of the off-platform peripherals have an Off-platform Peripheral Access Control Register (OPACR)
which defines the access levels supported by the given module. Each OPACR has a format identical to the
PACR described in Section 16.4.3.2, “Peripheral Access Control Registers (PACR).”
Each OPACR corresponds to the equivalent off-platform peripheral; OPACR0 corresponds to off-platform
peripheral0, etc., with OPACR32 corresponding to off-platform global peripheral0, and OPACR33
corresponding toff-platform global peripheral1.
Presence or absence of a particular OPACR is design implementation dependent. When absent, the
corresponding OPACR is not implemented and will read as 0’s. Writes will be ignored.
16.5
Functional Description
The AIPS serves as an interface between an AHB 2.v6 system bus and the IPS peripheral bus. It functions
as a protocol translator. Accesses which fall within the address space of the AIPS are decoded to provide
individual module selects for peripheral devices on the IPS interface.
16.5.1
AIPS Scalability
The AIPS is configurable to support eight masters, from one to thirty-two fixed-size on-platform
peripherals, thirty-two fixed-size off-platform peripherals, and two off-platform global peripherals.
16.5.1.1
Peripheral Presence
When a particular peripheral or set of peripherals are not present in a design, those peripheral memory
spaces which are not present will not be accessible by software and will be terminated with an AHB
ERROR response by the AIPS.
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Functional Description
16.5.1.2
Registers
Any attempt to access registers or register bitfields which are not present in the final instantiation will
result in a read returning zeroed data and writes being ignored.
16.5.2
Access Protections
The AIPS provides programmable access protections for both masters and peripherals. It allows the
privilege level of a master to be overridden, forcing it to user-mode privilege, and allows masters to be
designated as trusted or untrusted. Peripherals may require supervisor privilege level for access, may
restrict access to a trusted master only, and may be write-protected.
This functionality is described in Section 16.4.3.1, “Master Privilege Registers (MPROT),”
Section 16.4.3.2, “Peripheral Access Control Registers (PACR),” and Section 16.4.3.3, “Off-Platform
Peripheral Access Control Registers (OPACRs).”
16.5.3
Access Support
Aligned word and halfword accesses, as well as byte accesses are supported for 32-bit peripherals.
Peripheral registers must not be misaligned, although no explicit checking is performed by the AIPS.
16.5.4
Read Cycles
Two clock read accesses are possible to on-platform peripherals with the AIPS when the requested access
size is 32-bits or smaller.
16.5.5
Write Cycles
Three clock write accesses are possible to on-platform peripherals with the AIPS when the requested
access size is 32-bits or smaller.
16.5.6
Aborted Cycles
The AIPS follows a standard procedure when a system bus cycle is aborted and the abort is initiated by the
AIPS itself or the targeted IP bus peripheral. The AIPS either blocks initiation or immediately terminates
any IP bus activity that is ongoing.
There are several conditions that can cause the AIPS to abort the current operation and report an error. The
first is the case in which the targeted IP bus peripheral asserts a bus error. In this case the AIPS immediately
terminates access to the targeted IP bus peripheral and follows the abort procedure described above.
Whether the current IP bus access is a multi-cycle access or a single cycle access has no bearing on the
behavior of the AIPS. The AIPS responds identically in both cases.
The second case that can cause an error response to the AHB is when an access is attempted to an IP bus
peripheral whose corresponding PACR or OPACR settings do not allow the access, thus causing a
permissions violation. In this case the AIPS does not initiate any IP bus activity, but instead responds by
following the abort procedure described above.
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Initialization/Application Information
The third case that can cause an error response to the AHB is when an access is attempted to a location at
which there is no IP bus peripheral. In this case the AIPS does not initiate any IP bus activity but instead
responds by following the same abort procedure described above for a permissions violation.
16.6
Initialization/Application Information
The AIPS is configured at reset with all masters trusted for both reads and writes, all masters using their
supervisor access attribute, and all peripherals supervisor protected. After reset, a bus master may be used
to change the Master Privilege Registers (MPRs), the Peripheral Access Control registers (PACRs), and
the Off-platform Peripheral Access Control registers (OPACRs) as needed as described in Section 16.4.2,
“Control Registers.”
16.7
16.7.1
AIPS Bus Aborts
IPI Register Interface
The AIPS module supports Peripheral Bus bus aborts, and enforces the following memory map:
Table 16-6. AIPS Bus Aborts
Abort
Allowed
$0000-$0007
$0008-$001f
$0020-$002f
$0030-$003f
$0040-$0057
$0058-$3fff
Address aborting in the AIPS is done only on a 32-bit address boundary.
Supervisor Access: All accesses to the AIPS registers must be in Supervisor Mode. All User Mode
accesses are aborted.
16.7.2
IPI Bridge Interface
In addition to the IPI interface, the AIPS can abort transfers through the bridge itself. The following
transfers will be aborted:
— User mode access to any AIPS slave with the corresponding SP bit set in the PACR/OPACR
register.
— Write to any AIPS slave with the corresponding WP bit set in the PACR/OPACR register.
— Any access from an untrusted master to any AIPS slave with the corresponding TP bit set in
the PACR/OPACR register.
— Any access to an AIPS slave that is not implemented (i.e.-marked as “Reserved” in the
documentation)
(See Section 9.9, “Peripheral Bus Memory Map” for a list of PACR/OPACR registers)
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AIPS Differences from MAC71xx
16.8
•
AIPS Differences from MAC71xx
Different mix of peripherals, as follows:
Table 16-7. MAC71x1 versus MAC72xx AIPS PACR Assignment
Address
MAC71x1
MAC72xx
PACR register
$FC00 0000
AIPS
AIPS
PACR0
$FC00 4000
AXBS
AXBS
PACR1
$FC00 8000
EIM
FlexBus
PACR2
$FC00 C000
to
$FC03 FFFF
Reserved
Reserved
$FC04 0000
MCM
MCM
PACR16
$FC04 4000
DMA
DMA
PACR17
PACR18
$FC04 8000
INTC
INTC
$FC04 C000
to
$FC07 FFFF
Reserved
Reserved
$FC08 0000
SSM
SSM
OPACR0
$FC08 4000
DMA Mux
DMA Mux
OPACR1
$FC08 8000
CRG
CRG
OPACR2
$FC08 C000
PIT
PIT
OPACR3
$FC09 0000
VREG
Reserved
$FC09 4000
CAN_A
CAN_A
OPACR5
$FC09 8000
CAN_B
CAN_B
OPACR6
$FC09 C000
CAN_C
Reserved
$FC0A 0000
CAN_D
Reserved
$FC0A 4000
Reserved
Reserved
$FC0A 8000
Reserved
Reserved
$FC0A C000
IIC_A
IIC_A
$FC0B 0000
Reserved
Reserved
$FC0B 4000
SPI_A
SPI_A
OPACR13
$FC0B 8000
SPI_B
SPI_B
OPACR14
$FC0B C000
Reserved
SPI_C
OPACR15
$FC0C 0000
Reserved
Reserved
$FC0C 4000
SCI_A
SCI_A
OPACR17
$FC0C 8000
SCI_B
SCI_B
OPACR18
$FC0C C000
SCI_C
Reserved
OPACR11
$FC0D 0000
SCI_D
Reserved
$FC0D 4000
Reserved
Reserved
$FC0D 8000
Reserved
Reserved
$FC0D C000
eMIOS
eMIOS
OPACR23
$FC0E 0000
ADC_A
ADC_A
OPACR24
$FC0E 4000
ADC_B
Reserved
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AIPS Differences from MAC71xx
Table 16-7. MAC71x1 versus MAC72xx AIPS PACR Assignment (Continued)
Address
MAC71x1
MAC72xx
PACR register
OPACR26
$FC0E 8000
PIM
PIM
$FC0E C000
Reserved
Reserved
$FC0F 0000
CFM_REGS
H7FB_REGS
$FC0F 4000
to
$FC0F FFFF
OPACR28
Reserved
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Chapter 17
External Bus Interface (FlexBus)
17.1
Introduction
This chapter describes data transfer operations, error conditions, and reset operations. It describes transfers
initiated by the MAC7200 and includes detailed timing diagrams showing the interaction of signals in
supported bus operations.
NOTE
Unless otherwise noted, in this chapter “clock” refers to the CLKOUT used
for the bus.
The external bus interface on the MAC7200 can be used as a bus interface to external peripherals or
memories. In general, the external bus is available on larger pin count packages only, which also makes it
ideal for debugging purposes. It is a simple, flexible bus that supports a variety of external memory devices
with little or no external logic needed, and is based on the external bus of the 68000/Coldfire family of
devices. All transfers on the external bus are controlled by the MCU masters (CPU or eDMA) only (i.e.,
the MAC7200 device may not be used as an external bus slave).
The interface is implemented with a 16-bit data bus capable of supporting byte, half word (2 byte) and
word (4 byte) transfers.
Accesses which are greater than the selected port width of the data bus (i.e.,16-bit access with an 8-bit Port
Size) are automatically decomposed into a sequence of individual transfers. The address bus has up to 22
address lines (ADDR0[0:21]), allowing access to up to 4Mbytes of external addresses.
Three chip select signals (CS[0:2]) can be configured for different address ranges and transfers types,
including Auto Acknowledge with a defined number of wait states. If an access to the external bus maps
to no chip selects, the FlexBus will return a bus abort. Accesses that map to multiple chip selects will cause
multiple chip selects to be asserted. It is the responsibility of the external hardware to correctly handle this
situation, especially in the case of a read.
Chip select CS0 can be dedicated to boot ROM access and can be programmed to be byte (8 bits), word
(16 bits), or longword (32 bits) wide. Control signal timing is compatible with common ROM / flash
memories.
The port width of the data bus can be selected as either 8-bits or 16-bits wide. The value of Port F3 on reset
is used to determine the external data bus port width, as described in Section 2.2, “MCU Hardware
Configuration Summary” and Table 17-2.
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Introduction
Table 17-1. External Bus Auto Acknowledge Configuration
PF2/AA
Description
0
Disabled. Use the TA input to acknowledge transfers
1
Enabled. Transfers are acknowledged internally, but may also be
acknowledged using the TA input
Table 17-2. External Bus Port Size Configuration
17.1.1
PF3/PS
Description
0
Port Size is 8-bits (DATA0 to DATA7)
1
Port Size is 16-bits (DATA0 to DATA15)
Block Diagram
The block diagram of the FlexBus is shown in Figure 17-1.
Internal
Peripheral Bus
IPBI
Chip-Select
Chip-Select
Module
Module
CS[2:0]
ADDR (Address)
DATA (Data)
OE
R/W
External
Slaves
TBST
Master
FlexBus
Interface
Controller
BWE[0:1]
TA
Figure 17-1. FlexBus Controller Conceptual Diagram
(Non-Muxed Implementation)
17.1.2
Features
The following list summarizes the key FlexBus features on the MAC7200:
• 22-bit address bus (Maximum of 22 bits pinned out on the MAC72xx)
• 8/16-bit data bus (Maximum of 16-bits pinned out on the MAC72xx)
• 3 dedicated Chip Selects (Maximum of 3 chip selects pinned out on the MAC72xx)
• Slave only (MAC72xx is always Master)
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External Signals
•
•
•
•
•
Implements a programmable version of the MCF5407 External Bus protocol
Byte, word, longword, and line sized transfers
Programmable burst and burst-inhibited transfers selectable for each chip select and transfer
direction
Programmable address setup time with respect to the assertion of chip select
Programmable address hold time with respect to the negation of chip select and transfer direction
17.1.3
FlexBus Implementation
The FlexBus is an enhanced version of the EIM bus implemented on the MAC71xx family of devices. It
has the following special enhancements over the FlexBus controllers found on other devices:
• Issues a bus abort for all transfers that do not hit any chip selects
17.1.4
FlexBus Memory Map Relocation
As discussed in Section 9.16, “Memory Map Relocation”, there is the possibility to relocate the base
address of the FlexBus at reset, including the option of removing it completely from the memory map (for
security reasons).
17.2
External Signals
This section describes the external signals that are involved in data transfer operations. Table 17-3
summarizes the MAC7200 FlexBus signals.
Table 17-3. FlexBus Signal Summary
Signal Name
Direction
Description
Reset State
CS[2:0]1
O
General purpose chip-selects
Hi-Z
ADDR[21:0]
O
Address bus
Hi-Z
DATA[15:0]
I/O
Data bus
Hi-Z
BWE[1:0]1
O
Byte Selects
Hi-Z
OE1
O
Output Enable
Hi-Z
R/W
O
Read/Write. 1 = Read, 0 = Write
Hi-Z
TBST
O
Burst Transfer indicator
Hi-Z
TA
I
Transfer Acknowledge
—
1. On maskset 0M34D, output is always enabled
If full address decoding is done externally for anything other than an 8-bit port size, then ADDR[21:0] and
SIZE[1:0] is required, otherwise only ADDR[21:1] and BS0/BS1 are required. The basis for this required
scheme is:
• On a 8-bit port size, only pins DATA[7:0] are available
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External Signals
•
For an even address 8-bit access with a 16-bit port, the data should appear on DATA[15:8] in order
to be consistent
17.2.1
Chip-Select (CS[2:0])
The chip-select signal indicates which device is being selected. A particular chip-select asserts when the
transfer address is within the device’s address space as defined in the base and mask address registers, see
Section 17.3.2, “Chip-Select Registers.”
17.2.2
Address Bus (ADDR[21:0])
The ADDR[21:0] bus carries address. The address is always driven on the first clock of a bus cycle
(address phase).
17.2.3
Data Bus (DATA[15:0])
The DATA[15:0] bus carries data. The number of byte lanes used to carry the data during the data phase
is determined by the port size associated with the matching chip select.
17.2.4
Read/Write (R/W)
The MAC7200 drives the R/W signal to indicate the direction of the current bus operation. It is driven high
during read bus cycles and driven low during write bus cycles.
17.2.5
Transfer Burst (TBST)
Transfer Burst indicates that a burst transfer is in progress as driven by the MAC7200. A burst transfer can
be 2 to 16 beats depending on the port size.
NOTE
When burst (TBST = 0) and the address is misaligned within the 16-byte
boundary, the external device must be able to wrap around the address.
17.2.6
Byte Write Enable/Byte Select (BWE[1:0])
The byte strobe BWE[1:0]) outputs indicate that data is to be latched or driven onto a byte of the data when
driven low. BWEn signals are asserted only to the memory bytes used during a read or write access.
17.2.7
Output Enable (OE)
The output enable signal (OE) is sent to the interfacing memory and/or peripheral to enable a read transfer.
OE is asserted only when a chip select matches the current address decode.
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Chip-Select Operation
17.2.8
Transfer Acknowledge (TA)
This signal indicates that the external data transfer is complete. During a read cycle, when the processor
recognizes TA, it latches the data and then terminates the bus cycle. During a write cycle, when the
processor recognizes TA, the bus cycle is terminated.
If auto-acknowledge is disabled, the external device drives TA to terminate the bus transfer; if
auto-acknowledge is enabled, the TA is generated internally after a specified wait states or the external
device may assert external TA before the wait-state countdown which in turn terminates the cycle early.
The MAC7200 negates CSn a cycle after the last TA asserts. During read cycles, the peripheral must
continue to drive data until TA is recognized. For write cycles, the processor continues to drive data one
clock after CSn is negated.
The number of wait states is determined either by internally programmed auto acknowledgement or by the
external TA input. If the external TA is used, the peripheral has total control on the number of wait states.
17.3
Chip-Select Operation
Each chip-select has a dedicated set of the following registers for configuration and control.
• Chip-select address registers (CSARn) control the base address space of the chip-select.
Section 17.3.2.1, “Chip-Select Address Registers (CSAR0–CSAR2).
• Chip-select mask registers (CSMRn) provide 16-bit address masking and access control.
Section 17.3.2.2, “Chip-Select Mask Registers (CSMR0–CSMR2).
• Chip-select control registers (CSCRn) provide port size and burst capability indication, wait-state
generation, address setup and hold times, and automatic acknowledge generation features.
Section 17.3.2.3, “Chip-Select Control Registers (CSCR0–CSCR2).
CS0 is a global chip-select after reset and provides re-locatable boot ROM capability.
17.3.1
General Chip-Select Operation
When a bus cycle is initiated, the MAC7200 first compares its address with the base address and mask
configurations programmed for chip-selects 0–2 (configured in CSCR0–CSCR2). If the driven address
matches a programmed chip-select, the appropriate chip-select is asserted fulfilling the requirements as
programmed in the respective configuration register.
17.3.1.1
8-bit and 16-bit Port Sizing
Static bus sizing is programmable through the port size bits, CSCR[PS]. See Section 17.3.2.3,
“Chip-Select Control Registers (CSCR0–CSCR2).” Note that the MAC7200 always drives a 22-bit
address on the address bus in the first cycle regardless of the external device’s address size. The external
device must connect its address lines to the appropriate ADDR bits starting from ADDR0 and upward. It
must also connect its data lines to the DATA bus starting from the DATA15 and downward. No bit ordering
is required when connecting address and data lines to the bus. For example, a 16-bit address/16-bit data
device would connect its addr[15:0] to ADDR[15:0] and data[15:0] to DATA[15:0]. See Figure 17-5 for
graphical connection.
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Chip-Select Operation
17.3.1.2
Global Chip-Select Operation
CS0, the global (boot) chip-select, allows address decoding for boot ROM before system initialization. Its
operation differs from other external chip-select outputs after system reset.
After system reset, CS0 is asserted for every external access. No other chip-select can be used until the
valid bit, CSMR0[V], is set, at which point CS0 functions as configured. After this, CS[2:1] can be used
as well. At reset, the port size, and automatic acknowledge functions of the global chip-select are
determined by the logic levels on the PF[3:2] signals (see Table 17-1 and Table 17-2).
17.3.2
Chip-Select Registers
The following tables describe in detail the registers and bit meanings for configuring chip-select operation.
The chip-select controller register map is accessed relative to the memory base address register (MBAR).
Table 17-4 shows the chip-select register memory map. Reading unused or reserved locations terminates
normally and returns zeros.
Table 17-4. Chip-Select Registers
Offset
0x00
[31:24]
[23:16]
Chip-select address
register—bank 0 (CSAR0)
[15:8]
[7:0]
Reserved 2
ResetValue
Access 1
0x0000_0000
R/W
0x04
Chip-select mask register—bank 0 (CSMR0)
0x0000_0000
R/W
0x08
Chip-select control register—bank 0 (CSCR0)
BSTW = 0
BSTR = 0
PS = AD[1:0]
AA = AD[2]
WS = 111111
WRAH = 11
RDAH = 11
ASET = 11
SWSEN = 0
SWS = 000000
R/W
0x0000_0000
R/W
0x0C
Chip-select address
register—bank 1 (CSAR1)
Reserved 2
0x10
Chip-select mask register—bank 1 (CSMR1)
0x0000_0000
R/W
0x14
Chip-select control register—bank 1 (CSCR1)
0x0000_0000
R/W
Reserved 2
0x0000_0000
R/W
0x18
Chip-select address
register—bank 2 (CSAR2)
0x1C
Chip-select mask register—bank 2 (CSMR2)
0x0000_0000
R/W
0x20
Chip-select control register—bank 2 (CSCR2)
0x0000_0000
R/W
1. The access column indicates whether the corresponding register allows both read/write functionality (R/W), read-only
functionality (R), or write-only functionality (W). A read access to a write-only register returns zeros. A write access
to a read-only register has no effect.
2. Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these
reserved address spaces and reserved register bits have no effect.
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Chip-Select Operation
17.3.2.1
Chip-Select Address Registers (CSAR0–CSAR2)
CSARn, Figure 17-2, specify the chip-select base addresses.
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
BA
W
Reset
0
0
0
0
Reg
Addr
R
0
0
0
0
MBAR + 0x00 (CSAR0); 0x0C (CSAR1); 0x18 (CSAR2)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0x00 (CSAR0); 0x0C (CSAR1); 0x18 (CSAR2)
Figure 17-2. Chip-Select Address Registers (CSARn)
Table 17-5. CSARn Field Descriptions
Bits
Name
Description
31–16
BA
Base address. Defines the base address for memory dedicated to chip-select CSn. BA is
compared to bits 31–16 on the internal address bus to determine if chip-select memory is
being accessed.
15–0
—
Reserved, should be cleared
17.3.2.2
Chip-Select Mask Registers (CSMR0–CSMR2)
CSMRn, Figure 17-2, are used to specify the address mask and allowable access types for the respective
chip-selects.
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Chip-Select Operation
31
30
29
28
27
26
25
24
R
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
BAM
W
Reset
0
0
0
0
Reg
Addr
R
0
0
0
0
MBAR + 0x04 (CSMR0); 0x10 (CSMR1); 0x1C (CSMR2)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
WP
0
0
0
0
0
0
0
V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
Reg
Addr
MBAR + 0x04 (CSMR0); 0x10 (CSMR1); 0x1C (CSMR2)
Figure 17-3. Chip-Select Mask Registers (CSMRn)
Table 17-6 describes CSMR fields.
Table 17-6. CSMRn Field Descriptions
Bits
Name
Description
31–16
BAM
Base address mask. Defines the chip-select block size by masking address bits. Setting a
BAM bit causes the corresponding CSAR bit to be a “don’t care” in the decode.
0 Corresponding address bit is used in chip-select decode.
1 Corresponding address bit is a don’t care in chip-select decode.
The block size for CSn is 2n; n = (number of bits set in respective CSMR[BAM]) + 16.
For example, if CSAR0 = 0x0000 and CSMR0[BAM] = 0x0008, CS0 would address two
discontinuous 64-Kbyte memory blocks: one from 0x0000–0xFFFF and one from
0x8_0000–0x8_FFFF.
In another example, CS0 is setup to access 32 Mbytes of address space starting at
location 0x0 and CS1 is setup to access 16 Mbytes at the next byte after CS0. Then
CSAR0 = 0x0000, CSMR0[BAM] = 0x01FF, CSAR1 = 0x0200, and CSMR1[BAM] =
0x00FF.However, the size of the window may also physically be constrained by the size of
the data port, which constrains the number of address lines available in some modes.
15–9
—
8
WP
7–1
—
Reserved, should be cleared
0
V
Valid bit. Indicates whether the corresponding CSAR, CSMR, and CSCR contents are
valid. Programmed chip-selects do not assert until V bit is set (except for CS0, which acts
as the global chip-select). Reset clears each CSMRn[V]. At reset, no chip-select other than
CS0 can be used until the CSMR0[V] is set. At which point CS[2:0] functions as configured.
0 chip-select invalid
1 chip-select valid
Reserved, should be cleared
Write protect. Controls write accesses to the address range in the corresponding CSAR.
Attempting to write to the range of addresses for which CSARn[WP] = 1 results in the
appropriate chip-select not being selected and . No exception occurs.
0 Both read and write accesses are allowed
1 Only read accesses are allowed
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Chip-Select Operation
17.3.2.3
Chip-Select Control Registers (CSCR0–CSCR2)
Each CSCRn, Figure 17-3, controls the auto acknowledge, external master support, address setup and hold
times, port size, burst capability, and activation of each chip-select. Note that to support the global
chip-select, CS0, the CSCR0 reset values differ from the other CSCRs. CS0 allows address decoding for
boot ROM before system initialization.
31
30
R
29
28
27
26
SWS
25
24
23
22
0
0
SWSEN
—
21
20
19
ASET
18
RDAH
17
16
WRAH
W
Reset: CSCR0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Reset: CSCRs
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
3
2
1
0
0
0
0
Reg
Addr
MBAR + 0x08 (CSCR0); 0x14 (CSCR1); 0x20 (CSCR2)
15
14
13
R
12
11
10
WS
9
8
7
6
5
4
0
AA
PS
0
AD[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
BSTR BSTW
W
Reset: CSCR0
1
1
1
1
1
1
0
AD2
Reset: CSCRs
0
0
0
0
0
0
0
0
Reg
Addr
0
0
MBAR + 0x08 (CSCR0); 0x14 (CSCR1); 0x20 (CSCR2)
Figure 17-4. Chip-Select Control Registers (CSCRn)
Table 17-7 describes CSCRn fields.
Table 17-7. CSCRn Field Descriptions
Bits
Name
Description
31–26
SWS
Secondary wait states. The number of wait states inserted before an internal transfer
acknowledge is generated for burst transfer except for the first termination, which is
controlled by the wait state count. The secondary wait state is only used if the secondary
wait state enable is set, otherwise the wait state value is used for all burst transfers.
25–24
—
23
SWSEN
22
—
Reserved, should be cleared
Secondary wait state enable.
0 The wait state value is used to insert wait states before an internal transfer acknowledge
is generated for all transfers.
1 The secondary wait state value is used to insert wait states before an internal transfer
acknowledge is generated for burst transfer secondary terminations.
Reserved, should be cleared
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Chip-Select Operation
Table 17-7. CSCRn Field Descriptions (Continued)
Bits
Name
Description
21–20
ASET
Address setup. This field controls the asserting of chip-select with respect to assertion of
a valid address and attributes.
00 Assert chip-select on rising clock edge after address is asserted. (Default CSn)
01 Assert chip-select on second rising clock edge after address is asserted.
10 Assert chip-select on third rising clock edge after address is asserted.
11 Assert chip-select on fourth rising clock edge after address is asserted.(Reset CS0)
19–18
RDAH
Read Address Hold or (Deselect). This field controls the address and attribute hold time
after the termination during a read cycle that hits in the chip-select address space.
00 Hold address and attributes one cycle after CSn negates on reads. (Default CSn)
01 Hold address and attributes two cycles after CSn negates on reads.
10 Hold address and attributes three cycles after CSn negates on reads.
11 Hold address and attributes four cycles after CSn negates on reads. (Reset CS0)
17–16
WRAH
Write Address Hold or (Deselect). This field controls the address, data and attribute hold
time after the termination of a write cycle that hits in the chip-select address space.The
hold time only applies at the end of a transfer. Therefore, a burst transfer which is burst
inhibited only has a hold time added after the last bus cycle.]
00 Hold address and attributes one cycle after CSn negates on writes. (Default CSn)
01 Hold address and attributes two cycles after CSn negates on writes.
10 Hold address and attributes three cycles after CSn negates on writes.
11 Hold address and attributes four cycles after CSn negates on writes. (Reset CS0)
15–10
WS
Wait states. The number of wait states inserted after CSn asserts and before an internal
transfer acknowledge is generated (WS = 0 inserts zero wait states, WS = 0x3F inserts 63
wait states). If AA = 0, TA must be asserted by the external system regardless of the
number of wait states generated. In that case, the external transfer acknowledge ends the
cycle. An external TA supersedes the generation of an internal TA.
9
—
Reserved, should be cleared.
8
AA
Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge
for accesses specified by the chip-select address.
0 No internal TA is asserted. Cycle is terminated externally.
1 Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn
and the external system asserts an external TA before the wait-state countdown
asserts the internal TA, the cycle is terminated. Burst cycles increment the address bus
between each internal termination.
7–6
PS
Port size. Specifies the width of the data port associated with each chip-select. It
determines where data is driven during write cycles and where data is sampled during read
cycles.
00 32-bit port size. Valid data sampled and driven on D[31:0]. Not valid on MAC72xx.
01 8-bit port size. Valid data sampled and driven on D[7:0]
1x 16-bit port size. Valid data sampled and driven on D[15:0]
5
—
Reserved, should be cleared.
4
BSTR
Burst read enable. Specifies whether burst reads are used for memory associated with
each CSn.
0 Data exceeding the specified port size is broken into individual, port-sized non-burst
reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads.
1 Enables data burst reads when the transfer size is larger than the specified port size,
including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line
reads from 8- and 16-bit ports.
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Functional Description
Table 17-7. CSCRn Field Descriptions (Continued)
Bits
Name
Description
3
BSTW
Burst write enable. Specifies whether burst writes are used for memory associated with
each CSn.
0 Break data larger than the specified port size into individual port-sized, non-burst
writes. For example, a longword write to an 8-bit port takes four byte writes.
1 Enables burst write of data when the transfer size is larger than the specified port size,
including longword writes to 8 and 16-bit ports, word writes to 8-bit ports and line writes
to 8- and 16--bit ports.
2–0
—
17.4
17.4.1
Reserved, should be cleared.
Functional Description
Data Transfer Operation
Data transfers between the MAC7200 and other devices involve the following signals:
• Address / data bus (ADDR[21:0] / DATA[15:0])
• Control signal TA
• CSn
• OE
• BWE[1:0]
• Attribute signals (R/W, TBST)
The address and write data (ADDR[21:0] and DATA[15:0]), R/W, CSn, and all attribute signals change on
the rising edge of the clock. Read data is registered in the MAC7200 on the rising edge of the clock.
The MAC7200 FlexBus supports byte, word, longword, and 16-byte cache line operand transfers and
allows accesses to 8- and 16-bit data ports. Transfer parameters such as address setup and hold, port size,
the number of wait states for the external device being accessed, automatic internal transfer termination
enable or disable, and burst enable or disable are programmed in the chip-select control registers (CSCRs),
Section 17.3.2.3, “Chip-Select Control Registers (CSCR0–CSCR2).
17.4.2
Data Byte Alignment and Physical Connections
The MAC7200 aligns data transfers in FlexBus byte lanes, the number of lanes depending on the width of
the data port. Figure 17-5 shows the byte lanes that external memory should be connected to and the
sequential transfers if a longword is transferred for two port sizes. For example, an 8-bit memory should
be connected to the single lane DATA[7:0]. A longword transfer through this 8-bit port takes four transfers
on DATA[7:0], starting with the MSB and going to the LSB. A longword transfer through a 16-bit port
requires two transfers on each of the two byte lanes of the FlexBus.
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Functional Description
BWE0
BWE1
MAC72xx
External Data Bus
Byte Lanes
DATA[15:8]
DATA[7:0]
16-Bit Port Memory
Byte 0 (MSB)
Byte 2
Byte 1
Byte 3 (LSB)
Byte Select
8-Bit Port Memory
Byte 0 (MSB)
Byte 1
Byte 2
Byte 3 (LSB)
Figure 17-5. Connections for External Memory Port Sizes
17.4.3
Bus Cycle Execution
Basic bus operations occur in four clocks, as follows:
1. At the first clock edge, the address, and attributes are driven.
2. CSn is asserted at the second rising clock edge to indicate which device has been selected and by
that time the address and attributes are valid and stable. is negated at this edge.
For a write transfer, data is driven on the bus at this clock edge and continues to be driven until one
clock cycle after CSn negates. For a read transfer, data is also returned at this cycle.
External slave asserts TA at this clock edge.
3. Read data and TA are sampled on the third clock edge. TA can be negated after this edge and read
data can then be tristated.
4. CSn is negated at the fourth rising clock edge. This last clock of the bus cycle uses what would be
an idle clock between cycles to provide hold time for address, attributes, and write data.
17.4.3.1
Data Transfer Cycle States
The data transfer operation in the MAC7200 is controlled by an on-chip state machine. The state transition
diagram for basic read and write cycles is shown in Figure 17-6.
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FlexBus Bus Aborts
S0
Next Cycle
Wait States
S3
S1
S2
Figure 17-6. Data Transfer State Transition Diagram
Table 17-8 describes the states as they appear in subsequent timing diagrams.
Table 17-8. Bus Cycle States
State
Cycle
Description
S0
All
The read or write cycle is initiated. On the rising clock edge, the MAC7200 places
a valid address on ADDR[21:0]and drives R/W high for a read and low for a write,
if these signals are not already in the appropriate state.
S1
All
On the rising edge of CLK, CSn is asserted. Data is driven on DATA[15:Y] for
writes, and DATA[15:Y] is three-stated for reads. Address continues to be driven
on ADDR[X:0] pins that are unused for data.
If TA is recognized asserted, then the cycle moves on to S2. If TA is not asserted
either internally or externally, then the S1 state continues to repeat.
Read
S2
All
Read
S3
17.5
17.5.1
All
Data is made available by the external device before the rising edge of CLK with
TA asserted. The MAC7200 will latch data on this rising clock edge.
For internal termination the chip select will negate the internal TA signal. For
external termination, the external device should negate TA. Chip select is
negated after the rising edge of CLK at the end of S2.
The external device can stop driving data after the rising edge of CLK at the
beginning of S2. However, data can be driven until the end of S3 or any additional
address hold cycles.
Address, data, and R/W go invalid off the rising edge of CLK at the end of S3,
terminating the read or write cycle.
FlexBus Bus Aborts
IPI Register Interface
The FlexBus module does not support Peripheral Bus aborts, and has the following memory map:
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FlexBus Differences from MAC71xx
Table 17-9. FlexBus Bus Aborts
Abort
Allowed
$0000-$3fff
None
Supervisor Access: Unused
17.5.2
FlexBus Interface
In addition to the IPI interface, the FlexBus can also abort external bus transfers. The following transfers
will be aborted:
• Transfers to an external bus address which does not map into any chip select address range
17.6
•
FlexBus Differences from MAC71xx
The FlexBus interface has numerous small differences from the EIM. Please refer to the respective
Block Guides for differences in programming interface and protocol.
— Changed offset of registers from $0080 to $0000
— Changed max number of wait states from 15 to 63
— Added Secondary Wait State functionality (SWS, SWSEN bits in the CSCR)
— Added Extended Transfer Start functionality (EXTS bit in the CSCR)
— Added Address Setup and Hold functionality (ASET, RDAH, WDAH bits in the CSCR)
— Added Multiplexed address Mode (MUX bit in the CSCR)
Table 17-10. MAC71x1 to MAC72xx External Bus mapping
MAC71x1
MAC72xx
A[21:0]
ADDR[21:0]
D[15:0]
DATA[15:0]
CS0
CS0
CS1
CS1
CS2
CS2
OE
OE
BS0
BWE0
BS1
BWE1
RW
RW
CLKOUT
CLKOUT
TA
TA
AS
-
-
TBST
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•
•
The mix of external bus signals available at pins is different from the MAC71x1 to the MAC72xx.
Fixed MUCts01460: Thumb mode accesses have incorrect address and/or byte selects
17.7
17.7.1
FlexBus Application Usage
Enabling the FlexBus
It is not necessary to enable the FlexBus before it can be used. Please see Section 17.7.2, “Global Chip
Select Mode below for more information on the behavior of the FlexBus out of reset.
17.7.2
Global Chip Select Mode
After reset, the FlexBus is put into a Global Chip Select Mode, where all external bus accesses map to CS0.
This allows the maximum flexibility to boot from external sources before the FlexBus is configured. The
configuration of CS0 in Global Chip Select Mode is as follows:
Table 17-11. Global Chip Select Mode Configuration
Register
Field Values at Reset
CSAR0
0x0000_0000
CSMR0
0x0000_0000
CSCR0
SWS[31:26] = 0x00
SWSEN[23] = 0
ASET[21:20] = 11
RDAH[19:18] = 11
WRAH[17:16] = 11
WS[15:10] = 0x3f (63 wait states)
MUX[9] = 0
AA[8] = from pin PF2
PS1[7] = from pin PF3
PS0[6] = 1
BEM[5] = 0
BSTR[4] = 0
BSTW[3] = 0
To exit Global Chip select mode, set the Valid bit in the CSMR0 register. The only possibility to enter
Global Chip Select mode again after that is a Reset. Until Global Chip Select Mode is exited, all chip
selects, other than CS0, are unavailable. Outside of Global Chip Select mode, the CS0 registers behave
identically to all other chip select registers.
When modifying the configuration of a chip select, it is generally recommended to first clear the Valid bit
for that chip select in order to avoid possible race conditions between external bus accesses and
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configuring of the external bus. If software can positively assure that no external bus accesses will occur
during the configuration of the chip select(s), then this step is not necessary.
To summarize, a short example is presented. To boot from an external device, and enable three chip selects
on the external bus, you would perform the following steps:
1. Boot the device (either Power On Reset or assert the RESET pin)
2. The external bus (if available) will be in Global Chip Select Mode, with all external bus accesses
mapped to CS0. CS1 and CS2 will be unavailable.
3. If the device is in Expanded Mode, it will boot from the external bus, causing CS0 to be asserted,
and a READ access to appear on the external bus. The Port Size and Auto Acknowledge bits
(CSCR[7] and CSCR[8], respectively) are determined by the value of the PF3 and PF2 pins
(respectively) at Reset.
4. The boot code (from the external device) can now re-configure all of the chip-selects, including
CS0. CS0 should be re-configured in most cases, because the Global Chip Select mode provides
the most flexible (and hence slowest) access to external devices.
5. To configure CS1, program the CSAR1, CSCR1 and CSMR1 register, ensuring that the Valid bit
(CSMR1[0]) is set. Even though the Valid bit is set, CS1 will not become active until Global Chip
Select Mode is exited.
6. Configuring CS2 is similar to configuring CS1.
7. To configure CS0 and exit Global Chip Select Mode, program the CSAR0, CSCR1 and CSMR0
registers. Once the Valid bit (CSMR0[0]) bit is set, the FlexBus will exit Global Chip Select Mode,
and all three chip selects will be active with their programmed configuration. Therefore, the
CSMR0 register should be programmed last.
17.7.3
FlexBus speed
Note that, due to the increase in the number of wait states in Global Chip Select Mode between the
MAC71xx and MAC7200 family of devices, the MAC72xx device will run about 4x slower when booting
from the external bus. For this reason, the FlexBus registers should be programmed as early in the boot
process as possible in order to set the correct number of wait states.
17.7.4
How to use the external bus in Expanded Secured/Unsecured Mode
There is no PIM setup required to use the external bus in Expanded Mode. In this mode, the following pins
are automatically changed to Peripheral Mode and the FlexBus clock is automatically enabled:
• PA0-PA15
• PC0-PC15
• PD0-PD2
• PD5-PD15
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17.7.5
How to Use the External Bus in Single Chip Unsecured Mode
It is possible to use the external bus in Single Chip Unsecured Mode, but the PIM must be setup first. To
do so, set the MODE bits (i.e.-Set Peripheral Mode) in the CONFIG register for each of the following pads:
• PA0-PA15
• PC0-PC15
• PD0-PD2
• PD5-PD15
and enable the clock to the FlexBus module by setting the EIMCLKEN bit in the PIMCONFIG register
in the PIM. The following code example illustrates this:
#include <stdarg.h>
#include "addr_map_defines.vrh"
#include "pim_registers.h"
void main()
{
typedef volatile unsigned char * REG8;
typedef volatile unsigned short * REG16;
volatile unsigned char *pim_pointer;
volatile unsigned short *flexbus_pointer;
int i;
// Turn on the FlexBus clock
pim_pointer = (REG8) (PIM_REGISTER_MAP_OFFSET+0x3C2);
*pim_pointer = 0x002;
// Set PIM base address for Port A CONFIG registers
pim_pointer = (REG8) (PIM_REGISTER_MAP_OFFSET+0x01);
for (i=0; i<=15; i++) {
*pim_pointer = 0x80;
pim_pointer=pim_pointer+2;
}
// Set PIM base address for Port C CONFIG registers
pim_pointer = (REG8) (PIM_REGISTER_MAP_OFFSET+0x81);
for (i=0; i<=15; i++) {
*pim_pointer = 0x80;
pim_pointer=pim_pointer+2;
}
// Set PIM base address for Port D CONFIG registers
pim_pointer = (REG8) (PIM_REGISTER_MAP_OFFSET+0xC1);
for (i=0; i<=2; i++) {
*pim_pointer = 0x80;
pim_pointer=pim_pointer+2;
}
pim_pointer=pim_pointer+2;
pim_pointer=pim_pointer+2;
for (i=5; i<=15; i++) {
*pim_pointer = 0x80;
pim_pointer=pim_pointer+2;
}
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// Now let’s do a 16-bit write and read to/from the external bus
flexbus_pointer = (REG16) (0x20000000);
*flexbus_pointer = 0x8000;
i=*flexbus_pointer;
17.7.6
Enabling and Disabling CLKOUT
Even though the CLKOUT (PD2) signal is intended primarily as the FlexBus clock, it may be desirable in
some cases to enable this clock even when the FlexBus is not being used. If the CLKOUT is used primarily
as part of the FlexBus interface, please see below.
To disable CLKOUT: Change pad PD2 to an input by writing 0x00 to the CONFIG register for PD2
To change the drive strength on CLKOUT: Set/Clear the SLEW and SLEWEN bits in the CONFIG
register for PD2.
NOTE
It is not possible to use pad PD2 as a General Purpose Output.
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Chapter 18
FLASH (H7Fb) and FLASH Controller (PFLASH)
This chapter provides an overview of the flash array and the flash controller as they are implemented on
the MAC72xx. Please refer to Chapter 19, “Hip7a Low-Cost Embedded Flash (H7Fb)” for more detailed
technical information on the flash array, and Chapter 20, “SPP Flash Controller (PFLASH_H7Fb)
Module” for more detailed information on the flash controller.
18.1
Introduction
The Flash Module provides the non-volatile memory and its control interface for the MAC7200 family of
devices. Its implementation offers a range of memory sizes depending on the device and intended function
of the memory. For more information on the non-volatile memory options within the MAC7200 family
please refer to Figure 1-1 in Chapter 1, “Introduction”.
The Flash provides two types of memory, the Flash main array and the Shadow Block. The Flash main
array (also sometimes referred to as the Program Flash) is connected directly to the core via the crossbar
switch (See Chapter 16, “AHB to IPI Bridge (AIPS)”). The Shadow Block can be used to store the primary
boot loader. This memory is accessed across the same interface as the Flash main array and is constructed
using the same basic array and memory cell as the Flash main array.
On the MAC72x1 devices 512 K of Flash main array and a 32K Shadow Block are available, on the
MAC72x2 devices, up to 320K of Flash main array and a 32K Shadow Block are available.
The Shadow Block includes several locations which hold information on the state of the Flash main array
and Shadow Block protection, access and security, as well as a security key to unlock the device, if
enabled. The security state of the entire MCU is determined solely by the security settings stored in the
Shadow Block. The device can only be unlocked by writing this security key or by using a JTAG Lockout
Recovery mechanism to erase and very the contents of the non-volatile memory. Please refer to
Section 18.7.9, “Flash Security” for more details.
Both the Flash main array and Shadow Block memories are provided with protection sectors to help
eliminate errors caused by inadvertent program or erase operations being executed on the wrong area of
the memory. The Flash main array has 6 protected sectors, with 2 sectors of 128K and 4 sectors of 16K.
The Shadow Block has a single sector of 32K.
— Flash Main Array (New): 15x4K + 1x196K + 15x4K + 1x196K
— Shadow Block (New): 8x4K
In addition to the erase/program protection provided, both the Flash main array and Shadow Block may
be protected against unintended accesses, based on the access type (read vs. write, supervisor vs. user
mode and instruction fetch vs. data access). The Flash main array has 32 access protection sectors, 30 with
4K and 2 with the remaining 200K. The Shadow Block has 8 access protection sectors, each with 4K, and
may not be protected against writes. This will restrict accesses to the defined sector to be only possible
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Flash Features
when the ARM7 core is in Supervisor mode and/or when a load/store operation is being performed. Note
that all eDMA transfers are done in Supervisor/Data mode.
For information on the location of the Flash main array and Shadow Block in the memory map, refer to
Chapter 9, “Device Memory Map”.
Consult Chapter 19, “Hip7a Low-Cost Embedded Flash (H7Fb)” and Chapter 20, “SPP Flash Controller
(PFLASH_H7Fb) Module” for information on the operation and control of the on-chip Flash implemented
on the MAC7200 family of devices.
18.2
Flash Features
18.2.1
•
•
READ and WRITE paths through AHB
Configurable line buffers for performance tuning based on application
18.2.2
•
•
•
•
Shadow Block Features
32K Flash
Stores the Primary Boot Loader (PBL) and/or Parameter Data
Memory Map: See Section 9.13, “Shadow Block Memory Map”
Shares a single AHB interface with the main array
18.2.4
•
Main Array Features
512K / 320K Flash
Typically stores Application Code and Data
Memory Map: See Section 9.12, “Flash Main Array Memory Map”
Shares a single AHB interface with the Shadow Block
18.2.3
•
•
•
•
General Features
Flash Modes
Flash User Mode
— Read Operations
— Write (Program) Operations
— Erase Operation
— Entering/Exiting Stop Mode
18.3
18.3.1
Flash Implementation
MAC72x1 Flash
The Flash configuration for the MAC72x1 is as follows:
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Flash Implementation
•
•
•
•
•
SFS = 0 (No special Flash selection)
SIZE = 1 (512k)
LAS = 4 (4*16k, 4*16k, 2*64k)
MAS = 0 (2*128k)
32k Shadow Block
The Flash blocks and partitions are remapped to form the following order:
• 2*64k (Paritition 2: LAS-Blocks )
• 4*16k (Partition 0: )
• 4*16k (Partition 1: )
• 2*128k (Partition 3: MAS-Block 1, MAS-Block 0)
• 32k Shadow Block
Because of this remapping, the addresses of the lower half of each section will appear after the higher half
(see Figure 18-1).
0
MAS
256k
64k
128k
Block 1
64k
64k
128k
Partition 3
Partition 2
Block 8-9
LAS
384k
Partition 0
Block 0-3
16k
128k
Block 0
16k
16k
16k
192k
Partition 1
Block 4-7
16k
16k
16k
32k
Shown are the address
locations for Single
Chip Mode.
Shadow Block
16k
Figure 18-1. MAC72x1 Flash Blocks and Partitions
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LAS
256k
128k
16k Block 0
16k Block 1
288k
Partition 2
128k
Block 0
Partition 0
MAS
Partition 1
0
16k Block 2
16k Block 3
128k
Block 1
32k
Shown are the address
locations for Single
Chip Mode.
Shadow Block
Figure 18-2. MAC72x2 Flash Blocks and Partitions
This remapping needs to be taken into account, when accessing the H7fb control registers. For example
the MLOCK[3:0] field in the Low/Mid Address Space Block Locking Register, is mapped to the following
address ranges (using SC mode):
• MLOCK[0] = address range 384k to 512k-1
• MLOCK[1] = address range 256k to 384k-1
The LLOCK[15:0] mapping for SC mode is:
•
•
•
•
•
•
•
LLOCK[0] = address range 128k to 144k-1
LLOCK[1] = address range 144k to 160k-1
...
LLOCK[4] = address range 192k to 208k-1
...
LLOCK[8]= address range 0 to 64k-1
LLOCK[9]= address range 64kto 128k-1
18.3.2
MAC72x2 Flash
The Flash configuration for the MAC72x2 is as follows:
• SFS = 1 (Special Flash selected: 320k)
• SIZE = 1 (Normal size 512k, with SFS: 320k)
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Flash External Pins
•
•
LAS = 0
MAS = 1
18.4
Flash External Pins
There are no Flash or Flash Controller signals that drive or are driven from MCU pins.
18.5
PFLASH Bus Aborts
18.5.1
IPI Register Interface
The H7Fb module does not support Peripheral Bus bus aborts, but this capability is implemented outside
of the H7Fb block, to give the following:
Table 18-1. PFLASH Bus Aborts
Abort
Allowed
$0000-$002f
$0030-$3fff
Supervisor Access: Unused.
18.5.2
Flash Array Interface
In addition to Peripheral Bus bus aborts, the flash can also abort array interface (AHB for the MAC72xx)
accesses, for a variety of reasons:
• Access generated an ECC error
• Access generated a Read-while-Write violation (e.g.-trying to read the same partition that is being
programmed or erased)
• Aborting a program/erase high voltage operation
18.6
•
•
•
•
•
•
PFLASH Differences MAC72x2 from MAC71xx
All accesses are through a single bus interface, residing on AXBS Slave Port 0
Removed Peripheral Bus read/write interface
Added ECC (1-bit correction, 2-bit detection)
Completely different programming interface for the Flash
Removed Configuration Field. Configuration data is now stored at the upper addresses of the
Shadow Block.
Program/Erase partitioning changed
— Flash Main Array (Old): 15x4K + 2x196K + 15x4K
— Flash Main Array (New - MAC72x2): 2x128K + 4x16K
— Shadow Block (Old): 2x2K + 1x4K + 2x8K + 1x4K + 2x2K
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•
•
•
•
•
•
•
— Shadow Block (New - MAC72x2): 1x32K
Access Protection partitioning changed
— Write protection for DACC/SACC registers changed
— Added WACC (write protect) for Flash main array only(Same partitioning as SACC/DACC)
— Flash Main Array (Old): 15x4K + 2x196K + 15x4K
— Flash Main Array (New): 15x4K + 1x196K + 15x4K + 1x196K
— Shadow Block (Old): 2x2K + 1x4K + 2x8K + 1x4K + 2x2K
— Shadow Block (New - MAC72x2): 8x4K
Read-while-Write (RWW) partitioning changed
— Flash Main Array (Old): 1x512K
— Flash Main Array (New - MAC72x2): 128K + 128K + 2x16K + 2x16K
— Shadow Block (Old): 1x32K
— Shadow Block (New - MAC72x2): 1x32K
Number of wait states increased
Shadow Block base address changed to FLASH_BASE + $00F0 0000
Security enforcement changed
— Removed Backdoor Access functionality
— Remove the KEYEN[1:0] bits from the Security Word
— Renamed CFMSEC register to System Censor Word
Memory map relocation (based on security/chip mode) is unchanged
Lockout Recovery changed
— Lockout Recovery now erases the Shadow Block as well
— Must set "start lockout recovery" bit in SC4 with RESET asserted
— No need to clear the "start lockout recovery" bit in SC4 - self clearing
— No need to re-program security word - done automatically at the end
— Must reset device at end of lockout recovery
— No software lockout recovery (i.e.-from Expanded Mode)
18.7
PFLASH Application Usage
18.7.1
Flash Terminology
Table 18-2. Flash Terminology
Term
Definition
Access Protection
The ability to block accesses of a defined type (i.e.-read vs. write, user vs. supervisor, etc.)
on a section of Flash memory. This differs from Erase/Program Protection.
Erase/Program Protection
The ability to erase or program a section of Flash memory. This differs from Access
Protection.
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Table 18-2. Flash Terminology
Term
Definition
Read-while-Write (RWW)
Block
Partition
Programmed
Erased
Suspend
18.7.2
The ability to read code/data from one partition while erasing or programming another
partition.
The smallest unit to which Erase/Program Protection may be applied.
The smallest unit to which Read-while-Write may be applied.
A bit is programmed when it is logical ‘0’
A bit is erased when it is logical ‘1’
Suspends the current erase of a block so a read could be done within its partition.
Enabling the PFLASH
It is not necessary to enable the Flash controller before it can be used. However, it is generally a good idea
to configure the correct settings in the Flash controller as soon as possible after boot for performance
reasons.
18.7.3
Flash Array Memory Map
Please refer to Section 9.12, “Flash Main Array Memory Map” and Section 9.13, “Shadow Block Memory
Map” for more details on the Flash Main Array and Shadow Block memory map.
18.7.4
Flash Registers
The Flash related registers are located in two places:
• Flash Block - Programming/Erase and BIU registers located within the Peripheral Bus space of the
Flash block itself. The BIU registers are used by the Flash Controller for access protection and
performance tuning.
• MCM - Flash Write ACCess (WACC) register located within the Peripheral Bus space of the MCM
block.
18.7.4.1
Flash Block User Registers
These registers are located within the Peripheral Bus space of the Flash (at $FC0F 0000), and include
program/erase related registers and BIU registers.
Table 18-3. Flash Block IPI User Registers
Register
Address
Offset
Function
Reset Value
MCR
$0000
Module Configuration
$1101 3600
LML
$0004
LAS/MAS/Shadow Erase/Program Protection
From Shadow $7de8
HBL
$0008
HAS Erase/Program Protection
From Shadow $7df0
SLL
$000c
LAS/MAS Erase/Program Protection
From Shadow $7df8
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Table 18-3. Flash Block IPI User Registers
Register
Address
Offset
Function
Reset Value
LMS
$0010
LAS/MAS Erase/Program Block Select
$0000 0000
HBS
$0014
HAS Erase/Program Block Select
$0000 0000
ADR
$0018
Aborted Address
$0000 0000
BIU0
$001c
PFCR1
(Pre-fetch control, # wait states, etc.)
$0001 4a15
BIU1
$0020
PFAPR
(Master access protection)
$0000 0007
BIU2
$0024
PFCR2
(Line Buffer Config + Shadow SACC/DACC)
From Shadow $7e00
BIU3
$0028
PFSACC (Main Array)
From Shadow $7e08
BIU4
$002c
PFDACC (Main Array)
From Shadow $7e10
18.7.4.1.1
PFCR1 - PFLASH Configuration Register 1
The PFCR1 register contains line buffer and pipeline controls.
Bits
[31:18]
Function
MxPFE - Master x Pre-fetch Enable (not used)
Reset
$0000
[17]
M1PFE - DMA Master Pre-fetch Enable
0
[16]
M0PFE - Core Master Pre-fetch Enable
1
[15:13]
APC - Address Pipelining Control
010
[12:11]
WWSC - Write Wait State Control
01
[10:8]
RWSC - Read Wait State Control
010
[7]
Reserved for future use
0
[6]
DPFEN - Data Prefetch Enable
0
[5]
Reserved for future use
0
[4]
IPFEN - Instruction Prefetch Enable
1
[3]
Reserved for future use
0
[2:1]
PFLIM - Prefetch Limit
10
BFEN - Line Read Buffer Enable
1
[0]
The PFCR1 register may be locked (i.e.-writes are not allowed) by clearing PFCR2[23]. In the case of
any problems with the line buffers in the Flash controller (i.e.-functional bugs, etc.), the BFEN bit may be
cleared, thus disabling the buffers and associated logic.
The following table describes the allowed values for each of the fields in the PFCR1 register:
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Table 18-4. Flash PFCR1 Register Settings
Field
PFCR1 Bits
Allowed Values
Reserved
31:18
-
M1PFE
17
{0,1}
M0PFE
16
{0,1}
APC
15:13
{RWSC-1,...,7}
WWSC
12:11
{1,3}
RWSC
10:8
{0,...,7}
Reserved
7
-
DPFEN
6
{0,1}
Reserved
5
-
IPFEN
4
{0,1}
Reserved
3
-
PFLIM
2:1
{0,1,2,3}
BFEN
0
{0,1}
NOTE
RWSC = 0 is allowed, however you must set APC = 0 and you must set the
MCR[PRD] bit = 1. This PRD bit is a H7Fb configuration bit that is located
in the H7Fb MCR register bit [7].
Example — APC and RWSC Valid Configurations
The following table shows the valid configurations of APC and RWSC given a 25MHz frequency and the
rules above. All other configurations are invalid and will cause errors
APC
RWSC
{0,1,2,3,4,5,6,7}
0
{1,2,3,4,5,6,7}
1
{2,3,4,5,6,7}
2
{3,4,5,6,7}
3
{4,5,6,7}
4
{5,6,7}
5
{6,7}
6
7
7
Table 18-5 shows the settings for the APC and RWSC fields, given a few frequencies. These values were
calculated using the following formulas:
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Total Addr Delay
APC = Int ⎛ --------------------------------------------⎞
⎝
⎠
Period
Eqn. 18-1
Total Data Delay
RWSC = Int ⎛ --------------------------------------------⎞
⎝
⎠
Period
Eqn. 18-2
with the following parameters :
• H7fb access delay tacc = 29 ns
• H7fb pipelined read delay trr = 18 ns
• pflash_h7fb delay = 2 ns
• axbs hrdata delay = 1.5 ns
• bus master setup = 2.5 ns
• Total Data Delay = 35 ns
• Total Addr Delay = 24 ns
Table 18-5. Flash Controller APC and RWSC Settings
Frequency (MHz)
Period (ns)
APC
RWSC
PRD
Notes
20
50
0
0
1
See Note a
25
40
0
0
1
See Note a
30
33.33
0
0
1
See Note a
40
25
0
1
1
See Note b
50
20
1
1
1
See Note a
60
16.66
1
1
0
See Note a
70
14.286
1
2
0
See Note b
a. APC must be greater than or equal to RWSC at this frequency. If APC < RWSC, a pipelined read will
return data before the previous read data has been acknowledged. Therefore, the previous read will
return data from the next pipelined read
b. APC must be greater than or equal to RWSC-1 at this frequency. If APC < RWSC-1, a pipelined read
will return data before the previous read data has been acknowledged. Therefore, the previous read
will return data from the next pipelined read
18.7.4.1.2
PFAPR - PFLASH Access Protection Register
The PFAPR register contains access protection controls. The ARM7 core is designated M0, and the DMA
is designated M1.
Bits
Function
Reset
[31:4]
MxAP - Master x Access protection (not used)
$0000000
[3:2]
M1AP - DMA Access protection
00
[1:0]
M0AP - Core Access protection
01
The reset value corresponds to the ARM7 core having read/write access, and the DMA not.
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The PFAPR[31:4] register bits may not be locked. PFAPR[3:2] may be locked by clearing PFCR2[17],
and PFAPR[1:0] may be locked by clearing PFCR2[16]
18.7.4.1.3
PFCR2 - PFLASH Configuration Register 2
The PFCR2 register contains register locking, Shadow SACC/DACC and line buffer configuration.
Bits
Function
[31:30] LBCFG - Line Buffer Configuration
[29:24] Reserved for future use
Reseta
11
11111
[23]
CR1UNL - Enable Writes to the PFCR1 register
1
[22]
SACCUNL - Enable Writes to the PFSACC register
1
[21]
DACCUNL - Enable Writes to the PFDACC register
1
[20:18] Reserved for future use
111
[17:16] MPAUNL - Enable Writes to the M0AP/M1AP bits in the PFAPR
[17] - M1AP
[16] - M0AP
1
1
[15:8]
SHSACC - Shadow Supervisor/User Access
0 = Supervisor only allowed
1 = Supervisor or User allowed
$ff
[7:0]
SHDACC - Shadow Data/Instruction Access
0 = Data only allowed
1 = Data or Instruction allowed
$ff
a. The reset value is determined by the state of the Flash. The reset values shown are for a
fully erased Shadow Block.
The PFCR2 register is not lockable.
18.7.4.1.4
PFSACC - PFLASH Supervisor/user ACCess
The PFSACC register contains the SACC for the main array.
Bits
[31:0]
Function
SACC - Main Array Supervisor/User Access
0 = Supervisor only allowed
1 = Supervisor or User allowed
Reseta
$ffff ffff
a. The reset value is determined by the state of the Flash. The reset values shown are for a
fully erased Shadow Block.
The PFSACC register may be locked (i.e., writes are not allowed) by clearing PFCR2[22].
18.7.4.1.5
PFDACC - PFLASH Data/instruction ACCess
The PFDACC register contains the SACC for the main array.
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Bits
[31:0]
Reseta
Function
DACC - Main Array Data/Instruction Access
0 = Data only allowed
1 = Data or Instruction allowed
$ffff ffff
a. The reset value is determined by the state of the Flash. The reset values shown are for a
fully erased Shadow Block.
The PFDACC register may be locked (i.e., writes are not allowed) by clearing PFCR2[21].
18.7.4.2
Flash MCM Registers
These registers are located within the Peripheral Bus space of the MCM (at $FC04 0000), and include the
Write ACCess protection for the main array.
Table 18-6. MCM Block Flash Registers
18.7.4.2.1
Register
Function
Reset Value
MUDCR
PFWACC (Write ACCess Protection)
$0000 0000
PFWACC - PFLASH Write ACCess
The PFWACC register contains the WACC for the main array. There is no corresponding functionality for
the Shadow Block.
Bits
[31:0]
Function
Reset
WACC - Main Array Write Access
0 = Writes allowed
1 = Writes not allowed
$0000 0000
The PFWACC register may not be locked.
18.7.5
Flash Access Protection
Access Protection refers to the ability to block accesses of a defined type (i.e., read vs. write, user vs.
supervisor, instruction vs. data) on a section of Flash memory.
The Shadow Block has two types of access protection (mapping is shown in Table 18-8):
Table 18-7. Flash Shadow Block Access Protection Types
Field
Definition
SHSACC 0 Supervisor mode only
1 Supervisor and User mode allowed
SHDACC 0 Data fetch only
1 Instruction and Data fetch allowed
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Table 18-8. Flash Shadow Block Access Protection Address Ranges
Address Offset
Size
SHSACC
SHDACC
$0000 0000
4K
SHSACC[0]
SHDACC[0]
4K
SHSACC[1]
SHDACC[1]
4K
SHSACC[2]
SHDACC[2]
4K
SHSACC[3]
SHDACC[3]
4K
SHSACC[4]
SHDACC[4]
4K
SHSACC[5]
SHDACC[5]
4K
SHSACC[6]
SHDACC[6]
4K
SHSACC[7]
SHDACC[7]
$0000 0FFF
$0000 1000
$0000 1FFF
$0000 2000
$0000 2FFF
$0000 3000
$0000 3FFF
$0000 4000
$0000 4FFF
$0000 5000
$0000 5FFF
$0000 6000
$0000 6FFF
$0000 7000
$0000 7FFF
The main array has three types of access protection (Mapping is shown in Table 18-10):
Table 18-9. Flash Shadow Block Access Protection Types
Field
Definition
SACC
0 Supervisor mode only
1 Supervisor and User mode allowed
DACC
0 Data fetch only
1 Instruction and Data fetch allowed
WACC
0 Reads only
1 Reads and Writes allowed
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Table 18-10. Flash Main Array Access Protection
Address Offset
Size
SACC
DACC
WACC
$0000 0000
4K
SACC[0]
DACC[0]
WACC[0]
4K
SACC[1]
DACC[1]
WACC[1]
4K
SACC[2]
DACC[2]
WACC[2]
4K
SACC[3]
DACC[3]
WACC[3]
4K
SACC[4]
DACC[4]
WACC[4]
4K
SACC[5]
DACC[5]
WACC[5]
4K
SACC[6]
DACC[6]
WACC[6]
4K
SACC[7]
DACC[7]
WACC[7]
4K
SACC[8]
DACC[8]
WACC[8]
4K
SACC[9]
DACC[9]
WACC[9]
4K
SACC[10]
DACC[10]
WACC[10]
4K
SACC[11]
DACC[11]
WACC[11]
4K
SACC[12]
DACC[12]
WACC[12]
4K
SACC[13]
DACC[13]
WACC[13]
4K
SACC[14]
DACC[14]
WACC[14]
196K
SACC[15]
DACC[15]
WACC[15]
$0000 0FFF
$0000 1000
$0000 1FFF
$0000 2000
$0000 2FFF
$0000 3000
$0000 3FFF
$0000 4000
$0000 4FFF
$0000 5000
$0000 5FFF
Low Address Space (LAS)
$0000 6000
$0000 6FFF
$0000 7000
$0000 7FFF
$0000 8000
$0000 8FFF
$0000 9000
$0000 9FFF
$0000 A000
$0000 AFFF
$0000 B000
$0000 BFFF
$0000 C000
$0000 CFFF
$0000 D000
$0000 DFFF
$0000 E000
$0000 EFFF
$0000 F000
$0003 FFFF
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Table 18-10. Flash Main Array Access Protection (Continued)
Address Offset
Size
SACC
DACC
WACC
$0004 0000
4K
SACC[16]
DACC[16]
WACC[16]
4K
SACC[17]
DACC[17]
WACC[17]
4K
SACC[18]
DACC[18]
WACC[18]
4K
SACC[19]
DACC[19]
WACC[19]
4K
SACC[20]
DACC[20]
WACC[20]
4K
SACC[21]
DACC[21]
WACC[21]
4K
SACC[22]
DACC[22]
WACC[22]
4K
SACC[23]
DACC[23]
WACC[23]
4K
SACC[24]
DACC[24]
WACC[24]
4K
SACC[25]
DACC[25]
WACC[25]
4K
SACC[26]
DACC[26]
WACC[26]
4K
SACC[27]
DACC[27]
WACC[27]
4K
SACC[28]
DACC[28]
WACC[28]
4K
SACC[29]
DACC[29]
WACC[29]
4K
SACC[30]
DACC[30]
WACC[30]
196K
SACC[31]
DACC[31]
WACC[31]
$0004 0FFF
$0004 1000
$0004 1FFF
$0004 2000
$0004 2FFF
$0004 3000
$0004 3FFF
$0004 4000
$0004 4FFF
$0004 5000
$0004 5FFF
Mid Address Space (MAS)
$0004 6000
$0004 6FFF
$0004 7000
$0004 7FFF
$0004 8000
$0004 8FFF
$0004 9000
$0004 9FFF
$0004 A000
$0004 AFFF
$0004 B000
$0004 BFFF
$0004 C000
$0004 CFFF
$0004 D000
$0004 DFFF
$0004 E000
$0004 EFFF
$0004 F000
$0007 FFFF
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Due to the access protection, there is a possible deadlock situation that the user can find themselves in as
follows: If the DACC is programmed to only allow data fetches on Partition 0 ($0000 0000 to $0000
0FFF), and the device is reset, the user will generally be unable to boot the device from the Flash main
array.
1. Boot from the Shadow Block, and enter debug mode. For this to work, the SDACC[0] must be
cleared (i.e.-Instruction fetches allowed).
2. Boot from the external bus (if available).
3. Perform a JTAG Lockout Recovery sequence, which will erase the DACC.
18.7.6
Flash Program/Erase Protection and Selection
Program and Erase protection refers to the ability to protect flash blocks against program and erase
operations, or to program/erase only particular blocks. Table 18-11 details the block mapping for the
MAC72x2 Flash.
Table 18-11. Flash Program/Erase Blocks - MAC72x2
Address Offset
Block
Number
Size
LML/HBLa
LMS/HBS
$0000 0000
LAS #0
128K (Main Array)
LLOCK[0]
LSEL[0]
LAS #1
128K (Main Array)
LLOCK[1]
LSEL[1]
MAS #0
16K (Main Array)
MLOCK[0]
MSEL[0]
MAS #1
16K (Main Array)
MLOCK[1]
MSEL[1]
MAS #2
16K (Main Array)
MLOCK[2]
MSEL[2]
MAS #3
16K (Main Array)
MLOCK[3]
MSEL[3]
n/a
32K (Shadow Block)
SLOCK
PEASb
$0001 FFFF
$0002 0000
$0003 FFFF
$0004 0000