bq2003 Fast-Charge IC Features General Description ➤ Fast charge and conditioning of nickel cadmium or nickel-metal hydride batteries ➤ Hysteretic PWM switch-mode current regulation or gated control of an external regulator The bq2003 Fast Charge IC provides comprehensive fast charge control functions together with high-speed switching power control circuitry on a monolithic CMOS device. ➤ Easily integrated into systems or used as a stand-alone charger ➤ Pre-charge qualification of temperature and voltage ➤ Direct LED outputs display battery and charge status ➤ Fast-charge termination by ∆ temperature/∆ time, -∆V, maximum voltage, maximum temperature, and maximum time ➤ Optional top-off charge Pin Connections Integration of closed-loop current control circuitry allows the bq2003 to be the basis of a cost-effective solution for stand-alone and systemintegrated chargers for batteries of one or more cells. Switch-activated discharge-beforecharge allows bq2003-based chargers to support battery conditioning and capacity determination. High-efficiency power conversion is accomplished using the bq2003 as a hysteretic PWM controller for switch-mode regulation of the charging current. The bq2003 may alternatively be used to gate an externally regulated charging current. Fast charge may begin on application of the charging supply, replacement of the battery, or switch depression. For safety, fast charge is inhibited unless/until the battery temperature and voltage are within configured limits. Temperature, voltage, and time are monitored throughout fast charge. Fast charge is terminated by any of the following: n Rate of temperature rise (∆T/∆t) n Negative delta voltage (-∆V) n Maximum voltage n Maximum temperature n Maximum time After fast charge, an optional top-off phase is available. Constant-current maintenence charge is provided by an external trickle resistor. Pin Names CCMD Charge command/select SNS Sense resistor input DCMD Discharge command TCO Temperature cutoff DVEN -∆V enable/disable MCV Maximum voltage TM1 Timer mode select 1 TEMP Temperature status output CHG Charging status output MOD Charge current control DIS Discharge control VCC 5.0V ± 10% power CCMD 1 16 VCC DCMD 2 15 DIS DVEN 3 14 MOD TM1 4 13 CHG TM2 Timer mode select 2 TM2 5 12 TEMP TS Temperature sense TS 6 11 MCV BAT Battery voltage BAT 7 10 TCO VSS System ground VSS 8 9 SNS 16-Pin DIP or SOIC PN200301.eps SLUS095A - OCTOBER 1999 I 1 bq2003 TCO Pin Descriptions CCMD, DCMD Input to set maximum allowable battery temperature. If the potential between TS and SNS is less than the voltage at the TCO input, then fast charge or top-off charge is terminated. Charge initiation and discharge-beforecharge control inputs These two inputs control the conditions that b e g i n a ne w cha r g e c y cl e a n d en a b le discharge-before-charge. See Table 1. DVEN MCV -∆V enable input Note: For valid device operation, the voltage level on MCV must not exceed 0.6 ∗ VCC. Timer mode inputs TM1 and TM2 are three-state inputs that configure the fast charge safety timer, -∆V holdoff time, and that enhance/disable top-off. See Table 2. TS TEMP Temperature sense input CHG Single-cell voltage input Ground SNS Charging current sense input Charging status output Push-pull output indicating charging status. See Figure 1. The battery voltage sense input, referenced to SNS. This is created by a high-impedance resistor divider network connected between the positive and the negative terminals of the battery. Vss Temperature status output Push-pull output indicating temperature status. TEMP is low if the voltage at the TS pin is not within the allowed range to start fast charge. Input, referenced to SNS, for an external thermistor monitoring battery temperature. BAT Maximum-Cell-Voltage threshold input Input to set maximum single-cell equivalent voltage. If the voltage between BAT and SNS is greater than or equal to the voltage at the MCV input, then fast charge or top-off charge is inhibited. This input enales/disables -∆V charge termination. If DVEN is high, the -∆V test is enabled. If DVEN is low, -∆V test is disabled. The state of DVEN may be changed at any time. TM1– TM2 Temperature cutoff threshold input MOD Current-switching control output MOD is a push/pull output that is used to control the charging current to the battery. MOD switches high to enable charging current flow and low to inhibit charging current flow. DIS SNS controls the switching of MOD based on the voltage across an external sense resistor in the current path of the battery. SNS is the reference potential for the TS and BAT pins. If SNS is connected to VSS, MOD switches high at the beginning of charge and low at the end of charge. Discharge FET control output Push-pull output used to control an external transistor to discharge the battery before charging. VCC VCC supply input 5.0 V, ±10% power input. 2 bq2003 Functional Description the resistor connected to the positive battery terminal, and RB2 is the resistor connected to the negative battery terminal. See Figure 1. Figure 3 shows a state diagram and Figure 4 shows a block diagram of the bq2003. Note: This resistor-divider network input impedance to end-to-end should be at least 200kΩ and less than 1MΩ. Battery Voltage and Temperature Measurements A ground-referenced negative temperature coefficient thermistor placed in proximity to the battery may be used as a low-cost temperature-to-voltage transducer. The temperature sense voltage input at TS is developed using a resistor-thermistor network between VCC and battery’s negative terminal See Figure 1. Both the BAT and TS inputs are referenced to SNS, so the signals used inside the IC are: Battery voltage and temperature are monitored for maximum allowable values. The voltage presented on the battery sense input, BAT, should represent a single-cell potential for the battery under charge. A resistor-divider ratio of: RB1 =N-1 RB2 VBAT - VSNS = VCELL is recommended to maintain the battery voltage within the valid range, where N is the number of cells, RB1 is VTS - VSNS = VTEMP and Table 1. New Charge Cycle and Discharge Stimulus CCMD DCMD Pulled Up/Down to: VSS VSS VCC VCC VCC VSS VSS VCC New Charge Cycle Started by: Discharge-Before-Charge Started by: VCC rising to valid level Battery replacement (VCELL falling through VMCV) A rising edge on CCMD VCC rising to valid level Battery replacement (VCELL falling through VMCV) A falling edge on CCMD or DCMD A rising edge on CCMD A falling edge on CCMD External Trickle Resistor A rising edge on DCMD A rising edge on DCMD A rising edge on DCMD A rising edge on DCMD Negative Temperature Coefficient Thermister VCC VDC Pass Element bq2003 PACK+ TS RB1 bq2003 BAT RB2 SNS PACK + RT1 MOD SNS PACK- RT2 N T C PACK - Fg2003a2.eps Figure 1. Voltage and Temperature Monitoring and Trickle Resistor 3 bq2003 3. Discharge-Before-Charge The DCMD input is used to command discharge-beforecharge via the DIS output. Once activated, DIS becomes active (high) until VCELL falls below VEDV, at which time DIS goes low and a new fast charge cycle begins. See Table 1 for the conditions that initiate discharge-beforecharge. Discharge-before-charge is qualified by the same voltage and temperature conditions that qualify a new charge cycle start (see below). If a discharge is initiated but the pack voltage or temperature is out of range, the chip enters the charge pending mode and trickle charges the battery until the voltage and temperature qualification conditions are met, and then starts to discharge. Starting a new charge cycle may be limited to a pushbutton or logical pulse input only by pulling one member of the DCMD and CCMD pair up while pulling the other input down. In this configuration a new charge cycle will be started only by a falling edge on CCMD if it is pulled up, and by a falling edge on CCMD if it is pulled down. See Table 1. If the battery is within the configured temperature and voltage limits, the IC begins fast charge. The valid battery voltage range is VEDV < VBAT < VMCV where: VEDV = 0.2 ∗ VCC ± 30mV The valid temperature range is VHTF < VTEMP < VLTF, where: Starting A Charge Cycle The stimulus required to start a new charge cycle is determined by the configuration of the CCMD and DCMD inputs. If CCMD and DCMD are both pulled up or pulled down, then a new charge cycle is started by (see Figure 2): 1. VCC rising above 4.5V 2. VCELL falling through the maximum cell voltage, VMCV. VMCV is the voltage presented at the MCV input pin, and is configured by the user with a resistor divider between VCC and ground. The allowed range is 0.2 to 0.4 ∗ VCC. Charge Pending A rising edge on CCMD if it is pulled down, or a falling edge on CCMD if it is pulled up. Discharge VLTF = 0.4 ∗ VCC ± 30mV VHTF = [(1/8 ∗ VLTF) + (7/8 ∗ VTCO)] ± 30mV VTCO is the voltage presented at the TCO input pin, and is configured by the user with a resistor divider between VCC and ground. The allowed range is 0.2 to 0.4 ∗ VCC. If the temperature of the battery is out of range, or the voltage is too low, the chip enters the charge pending state and waits for both conditions to fall within their allowed limits. There is no time limit on the charge pending state; the charger remains in this state as long as the voltage or temperature conditons are outside of Fast Charging Top-Off (Optional) (Optional) DIS MOD Switch-Mode Configuration or MOD External Regulation (SNS Grounded) 4 sec. 34 sec. CHG Status Output TEMP Status Output Battery discharged to 0.2 VCC. Battery within temperature limits. Charge cycle start. Battery outside temperature limits. TD200301a.eps Figure 2. Charge Cycle Phases 4 bq2003 Table 2. Fast-Charge Safety Time/Hold-Off/Top-Off Table Corresponding Fast-Charge Rate C/4 C/2 1C 2C 4C C/2 1C 2C 4C Note: TM1 Low Float High Low Float High Low Float High Typical Fast Charge and Top-Off Time Limits 360 180 90 45 23 180 90 45 23 TM2 Low Low Low Float Float Float High High High Typical -∆V/MCV Hold-Off Time (seconds) 137 820 410 200 100 820 410 200 100 Top-Off Rate Disabled Disabled Disabled Disabled Disabled C/16 C/8 C/4 C/2 Typical conditions = 25°C, VCC = 5.0V. maximum temperature terminations are not affected by the hold-off period. the allowed limits. If the voltage is too high, the chip goes to the battery absent state and waits until a new charge cycle is started. ∆T/∆t Termination Fast charge continues until termination by one or more of the five possible termination conditions: n Delta temperature/delta time (∆T/∆t) n Negative delta voltage (-∆V) The bq2003 samples at the voltage at the TS pin every 34s, and compares it to the value measured two samples earlier. If VTEMP has fallen 16mV ±4mV or more, fast charge is terminated. The ∆T/∆t termination test is valid only when VTCO < VTEMP < VLTF. n Maximum voltage Temperature Sampling n Maximum temperature n Maximum time Each sample is an average of 16 voltage measurements taken 57µs apart. The resulting sample period (18.18ms) filters out harmonics around 55Hz. This technique minimizes the effect of any AC line ripple that may feed through the power supply from either 50Hz or 60Hz AC sources. Tolerance on all timing is ±16%. -∆V Termination If the DVEN input is high, the bq2003 samples the voltage at the BAT pin once every 34s. If VCELL is lower than any previously measured value by 12mV ±4mV, fast charge is terminated. The -∆V test is valid in the range VMCV - (0.2 ∗ VCC) < VCELL < VMCV. Maximum Voltage, Temperature, and Time Anytime VCELL rises above VMCV, CHG goes high (the LED goes off) immediately. If the bq2003 is not in the voltage hold-off period, fast charging ceases if VCELL remains above MCV for a minimum of tMCV. If VCELL then falls back below VMCV before 1.5tMCV ±50ms, the chip transitions to the Charge Complete state (maximum voltage termination). If VCELL remains above VMCV beyond 1.5tMCV, the bq2003 transitions to the Battery Absent state (battery removal). See Figure 3. Voltage Sampling Each sample is an average of 16 voltage measurements taken 57µs apart. The resulting sample period (18.18ms) filters out harmonics around 55Hz. This technique minimizes the effect of any AC line ripple that may feed through the power supply from either 50Hz or 60Hz AC sources. Tolerance on all timing is ±16%. If the bq2003 is in the voltage hold-off period when VCELL rises above VMCV, the LED goes out but fast charging continues until the expiration of the hold-off period. Temperature sampling continues during the hold-off period as well. If a new battery is inserted before the hold-off period expires, it continues in the fast charge cycle started by its predecessor. No precharge qualification is performed, and a temperature sample Voltage Termination Hold-off A hold-off period occurs at the start of fast charging. During the hold-off period, -∆V termination is disabled. This avoids premature termination on the voltage spikes sometimes produced by older batteries when fast-charge current is first applied. ∆T/∆t, maximum voltage and 5 bq2003 taken on the new battery is compared to ones taken before the original battery was removed and any that may have been taken while no battery was present. If the IC is configured for ∆T/∆t termination, this may result in a premature fast-charge termination on the newly inserted battery. Charge Status Indication Charge status is indicated by the CHG output. The state of the CHG output in the various charge cycle phases is shown in Figure 3 and illustrated in Figure 1. Temperature status is indicated by the TEMP output. TEMP is in the high state whenever VTEMP is within the temperature window defined by the VLTF and VHTF temperature limits, and is low when the battery temperature is outside these limits. Maximum temperature termination occurs anytime the voltage on the TS pin falls below the temperature cut-off threshold VTCO. Charge is also terminated if VTEMP rises above the minimum temperature fault threshold, VLTF, after fast charge begins. In all cases, if VCELL exceeds the voltage at the MCV pin, both CHG and TEMP outputs are held high regardless of other conditions. CHG and TEMP may both be used to directly drive an LED. Maximum charge time is configured using the TM pin. Time settings are available for corresponding charge rates of C/4, C/2, 1C, and 2C. Maximum time-out termination is enforced on the fast-charge phase, then reset, and enforced again on the top-off phase, if selected. There is no time limit on the trickle-charge phase. Charge Current Control The bq2003 controls charge current through the MOD output pin. The current control circuitry is designed to support implementation of a constant-current switching regulator or to gate an externally regulated current source. Top-off Charge An optional top-off charge phase may be selected to follow fast charge termination for the C/2 through 4C rates. This phase may be necessary on NiMH or other battery chemistries that have a tendency to terminate charge prior to reaching full capacity. With top-off enabled, charging continues at a reduced rate after fast-charge termination for a period of time selected by the TM1 and TM2 input pins. (See Table 2.) During top-off, the MOD pin is enabled at a duty cycle of 4s active for every 30s inactive. This modulation results in an average rate 1/8th that of the fast charge rate. Maximum voltage, time, and temperature are the only termination methods enabled during top-off. When used in switch-mode configuration, the nominal regulated current is: IREG = 0.235V/RSNS Charge current is monitored at the SNS input by the voltage drop across a sense resistor, RSNS, between the low side of the battery pack and ground. RSNS is sized to provide the desired fast-charge current. If the voltage at the SNS pin is less than VSNSLO, the MOD output is switched high to pass charge current to the battery. External Trickle Resistor When the SNS voltage is greater than VSNSHI, the MOD output is switched low—shutting off charging current to the battery. Maintenance charging is provided by the use of an external trickle resistor between the high side of the battery pack and VDC, the input charging supply voltage. (See Figure 1.) This resistor is sized to meet two criteria. n n VSNSLO = 0.044 ∗ VCC ± 25mV VSNSHI = 0.05 ∗ VCC ± 25mV With the battery removed, the resistor must pull the voltage at the BAT input above MCV for battery insertion and removal detection. When used to gate an externally regulated current source, the SNS pin is connected to VSS, and no sense resisitor is required. With the battery at its fully charged voltage, the trickle current should be approximately equal to the self-discharge rate of the battery. 6 bq2003 New Charge Cycle Start or Discharge-Before-Charge Command VCELL > VMCV Battery Voltage? VCELL < VEDF Charge Pending VEDV < VCELL < VMCV Battery Temperature? VTEMP > VLTF or VTEMP < VHTF Trickle CHG = 1 3/8s high 1/8s low VCELL > VMCV VHTF < VTEMP < VLTF VEDV < VCELL < VMCV and VHTF < VTEMP < VLTF No Discharge-Before-Charge Commanced? Discharge CHG = 1 3/8s low 1/8s high VCELL > VMCV VCELL < VEDV Fast CHG = Low VCELL > VMCV t Hold-off period expired? Yes Battery Absent > 1.5tMCV Trickle CHG = High Trickle CHG = High No - V or T/ t or VCELL < VMCV VTEMP < VTCO or Maximum Time Out Top-off selected? VCELL < VMCV Hold-off period expires Fast CHG = High VCELL > VMCV VCELL > VMCV Top-off CHG = 1/8s low 1/8s high Yes VTEMP < VTCO or Maximum Time Out No Charge Complete Trickle CHG = 1/8s low 1/8s high SD2003.eps Figure 3. State Diagram 7 bq2003 OSC TEMP CHG TM1 TM2 TCO Timing Control TCO Check TS LTF Check Display Control VTS - VSNS CCMD DCMD DVEN VBAT - VSNS Charge Control State Machine A/D SNS EDV Check Discharge Control MOD Control MCV Check DIS MOD MCV BAT VCC VSS BD200301.eps Figure 4. Block Diagram 8 bq2003 Absolute Maximum Ratings Symbol Parameter Minimum Maximum Unit VCC VCC relative to VSS -0.3 +7.0 V VT DC voltage applied on any pin excluding VCC relative to VSS -0.3 +7.0 V TOPR Operating ambient temperature 0 +70 °C TSTG Storage temperature -55 +125 °C TSOLDER Soldering temperature - +260 °C TBIAS Temperature under bias -40 +85 °C Note: Commercial 10 sec max. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability. DC Thresholds Symbol Notes (TA = TOPR; VCC ± 10%) Parameter Rating Tolerance Unit VSNSHI High threshold at SNS resulting in MOD = Low 0.05 ∗ VCC ± 0.025 V Tolerance is common mode deviation. VSNSLO Low threshold at SNS resulting in MOD = High 0.044 ∗ VCC ± 0.025 V Tolerance is common mode deviation. VLTF Low-temperature fault 0.4 ∗ VCC ± 0.030 V VTEMP ≥ VLTF inhibits/ terminates charge VHTF High-temperature fault (1/8 ∗ VLTF) + (7/8 ∗ VTCO) ± 0.030 V VTEMP ≤ VHTF inhibits fast charge VEDV End-of-discharge voltage 0.2 ∗ VCC ± 0.030 V VCELL < VEDV inhibits fast charge VTHERM TS input change for ∆T/∆t detection -16 ±4 mV VCC = 5V, TA = 25°C -∆V BAT input change for -∆V detection -12 ±4 mV VCC = 5V, TA = 25°C 9 Notes bq2003 Recommended DC Operating Conditions (TA = 0 to +70°C) Symbol Parameter Minimum Typical Maximum Unit Notes VCC Supply voltage 4.5 5.0 5.5 V VBAT Battery input 0 - VCC V VCELL BAT voltage potential 0 - VCC V VTS Thermistor input 0 - VCC V VTEMP TS voltage potential 0 - VCC V VMCV Maximum cell voltage 0.2 ∗ VCC - 0.4 ∗ VCC V VTCO Temperature cutoff 0.2 ∗ VCC - 0.4 ∗ VCC V Logic input high VCC - 1.0 - - V CCMD, DCMD, DVEN Logic input high VCC - 0.3 - - V TM1, TM2 Logic input low - - 1.0 V CCMD, DCMD, DVEN Logic input low - - 0.3 V TM1, TM2 VIH VIL VBAT - VSNS VTS - VSNS VOH Logic output high VCC - 0.5 - - V DIS, TEMP, CHG, MOD, IOH ≤ -5mA VOL Logic output low - - 0.5 V DIS, TEMP, CHG, MOD, IOL ≤ 5mA ICC Supply current - 0.75 2.2 mA Outputs unloaded IOH DIS, TEMP, MOD, CHG source -5.0 - - mA @VOH = VCC - 0.5V IOL DIS, TEMP, MOD, CHG sink 5.0 - - mA @VOL = VSS + 0.5V Input leakage - - ±1 µA CCMD, DCMD, DVEN, V = VSS to VCC Logic input low source - - 70 µA TM1, TM2, V = VSS to VSS + 0.3V IIH Logic input high source -70 - - µA TM1, TM2, V = VCC - 0.3V to VCC IIZ TM1, TM2 tri-state open detection -2.0 - 2.0 µA TM1, TM2 may be left disconnected (floating) for Z logic input state IIL Note: All voltages relative to VSS except as noted. 10 bq2003 Impedance Symbol Parameter Minimum Typical Maximum Unit RBAT Battery input impedance 50 - - MΩ RMCV MCV input impedance 50 - - MΩ RTCO TCO input impedance 50 - - MΩ RSNS SNS input impedance 50 - - MΩ RTS TS input impedance 50 - - MΩ Timing Symbol (TA = 0 to +70°C; VCC ± 10%) Parameter Minimum Typical Maximum Unit Notes tPW Pulse width for CCMD, DCMD pulse commands 1 - - µs Pulse start for charge or dischargebefore-charge dFCV Time base variation -16 - 16 % VCC = 4.5V to 5.5V fREG MOD output regulation frequency - - 300 kHz tMCV Maximum voltage termination time limit 200 250 300 ms Note: Typical is at TA = 25°C, VCC = 5.0V. 11 Time limit to distinguish battery removed from charge complete bq2003 PN: 16-Pin DIP Narrow 16-Pin PN (DIP Narrow) Dimension Minimum A 0.160 A1 0.015 B 0.015 B1 0.055 C 0.008 D 0.740 E 0.300 E1 0.230 e 0.300 G 0.090 L 0.115 S 0.020 All dimensions are in inches. Maximum 0.180 0.040 0.022 0.065 0.013 0.770 0.325 0.280 0.370 0.110 0.150 0.040 S: 16-Pin SOIC 16-Pin S (SOIC) D Dimension Minimum A 0.095 A1 0.004 B 0.013 C 0.008 D 0.400 E 0.290 e 0.045 H 0.395 L 0.020 All dimensions are in inches. B e E H A C .004 L A1 12 Maximum 0.105 0.012 0.020 0.013 0.415 0.305 0.055 0.415 0.040 bq2003 Data Sheet Revision History Change No. Page No. 5 2 Changed block diagram Changed diagram. 5 8 Added top-off values to Table 2. Added values. 6 All Revised and expanded format of this data sheet Clarification 7 9 TOPR Deleted industrial temperature range. 8 3 Corrected Table 1 Correction 8 5, 7 Corrected and expanded the explanation for maximum voltage conditions Clarification Notes: Description Changes 1–4: Please refer to the 1997 Data Book. Change 5 = Sept. 1996 F changes from Oct. 1993 E. Change 6 = Oct. 1997 G changes from Sept. 1996 F. Change 7 = June 1999 H changes from Oct. 1997 G. Change 8 = Oct. 1999 I changes from June 1999 H. Ordering Information bq2003 Package Option: PN = 16-pin narrow plastic DIP S = 16-pin SOIC Device: bq2003 Fast-Charge IC 13 Nature of Change IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright © 1999, Texas Instruments Incorporated 14