ETC CD74AC08M96

CD54AC08, CD74AC08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS307B – JANUARY 2001 – REVISED MAY 2001
D
D
D
D
D
D
D
CD54AC08 . . . F PACKAGE
CD74AC08 . . . E OR M PACKAGE
(TOP VIEW)
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
Balanced Propagation Delays
Buffered Inputs
±24-mA Output Drive Current
– Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
1A
1B
1Y
2A
2B
2Y
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
description
The ’AC08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean function
Y
+ A • B or Y + A ) B in positive logic.
ORDERING INFORMATION
PDIP – E
–40°C to 85°C
ORDERABLE
PART NUMBER
PACKAGE†
TA
SOIC – M
Tube
CD74AC08E
Tube
CD74AC08M
Tape and reel
CD74AC08M96
TOP-SIDE
MARKING
CD74AC08E
AC08M
–55°C to 125°C
CDIP – F
Tube
CD54AC08F3A
CD54AC08F3A
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
logic diagram, each gate (positive logic)
A
Y
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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1
CD54AC08, CD74AC08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS307B – JANUARY 2001 – REVISED MAY 2001
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C
MIN
MAX
VCC
VIH
VIL
Supply voltage
High-level input voltage
Low-level input voltage
VI
VO
Input voltage
IOH
IOL
High-level output current
∆t/∆v
1.5
Input transition rise or fall rate
CD74AC08
MIN
MAX
MIN
MAX
1.5
5.5
1.5
5.5
VCC = 1.5 V
VCC = 3 V
1.2
2.1
2.1
2.1
VCC = 5.5 V
VCC = 1.5 V
3.85
3.85
3.85
0
0
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 1.5 V to 3 V
VCC = 3.6 V to 5.5 V
1.2
0.3
VCC = 3 V
VCC = 5.5 V
Output voltage
Low-level output current
5.5
CD54AC08
0.3
V
0.3
0.9
0.9
0.9
1.65
1.65
0
0
–24
VCC
VCC
0
0
–24
24
V
1.2
1.65
VCC
VCC
UNIT
24
V
VCC
VCC
V
–24
mA
24
mA
0
50
0
50
0
50
0
20
0
20
0
20
V
ns/V
TA
Operating free-air temperature
–55
125
–40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
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CD54AC08, CD74AC08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS307B – JANUARY 2001 – REVISED MAY 2001
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 µA
VOH
VI = VIH or VIL
IOH = –4 mA
IOH = –24 mA
IOH = –50 mA†
IOH = –75 mA†
IOL = 50 µA
VOL
II
ICC
VI = VIH or VIL
VI = VCC or GND
VI = VCC or GND,
TA = 25°C
MIN
MAX
VCC
CD54AC08
CD74AC08
MIN
MIN
MAX
1.5 V
1.4
1.4
1.4
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
3V
2.58
2.4
2.48
4.5 V
3.94
3.7
3.8
5.5 V
MAX
V
3.85
5.5 V
3.85
1.5 V
0.1
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
IOL = 12 mA
IOL = 24 mA
IOL = 50 mA†
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
IOL = 75 mA†
5.5 V
IO = 0
UNIT
5.5 V
V
1.65
1.65
5.5 V
±0.1
±1
±1
µA
5.5 V
4
80
40
µA
10
10
10
Ci
pF
† Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.
switching characteristics over recommended operating free-air temperature range,
VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
Y
CD54AC08
CD74AC08
MIN
MIN
MAX
MAX
109
99
109
99
UNIT
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
Y
CD54AC08
CD74AC08
MIN
MAX
MIN
MAX
3.1
12.2
3.1
11.1
3.1
12.2
3.1
11.1
UNIT
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
Y
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CD54AC08
CD74AC08
MIN
MAX
MIN
MAX
2.2
8.7
2.2
7.9
2.2
8.7
2.2
7.9
UNIT
ns
3
CD54AC08, CD74AC08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS307B – JANUARY 2001 – REVISED MAY 2001
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
4
TYP
50
Power dissipation capacitance
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UNIT
pF
CD54AC08, CD74AC08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS307B – JANUARY 2001 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
S1
R1 = 500 Ω†
From Output
Under Test
2 × VCC
Open
GND
CL = 50 pF
(see Note A)
R2 = 500 Ω†
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
VCC
† When VCC = 1.5 V, R1 = R2 = 1 kΩ
Input
50% VCC
50% VCC
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
CLR
Input
VCC
Reference
Input
VCC
50% VCC
50% VCC
0V
0V
tsu
trec
Data
50%
Input 10%
VCC
50% VCC
CLK
90%
VOLTAGE WAVEFORMS
RECOVERY TIME
tf
VCC
50% VCC
50% VCC
tPLH
tPHL
50%
10%
90%
90%
tr
tPHL
Out-of-Phase
Output
VCC
50% VCC
10% 0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
0V
In-Phase
Output
90%
tr
0V
Input
th
90%
VOH
50% VCC
10%
VOL
tf
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
50% VCC
10%
tf
50%
10%
90%
tr
VOH
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VCC
Output
Control
50% VCC
50% VCC
0V
tPLZ
tPZL
50% VCC
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
≈VCC
20% VCC
VOL
50% VCC
VOH
80% VCC
≈0 V
VOLTAGE WAVEFORMS
OUTPUT ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
Phase relationships between waveforms are arbitrary.
D. For clock inputs, fmax is measured with the input duty cycle at 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLH and tPHL are the same as tpd.
G. tPZL and tPZH are the same as ten.
H. tPLZ and tPHZ are the same as tdis.
Figure 1. Load Circuit and Voltage Waveforms
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