DAC7634 ® DAC 763 4 For most current data sheet and other product information, visit www.burr-brown.com 16-Bit, Quad Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● LOW POWER: 10mW ● UNIPOLAR OR BIPOLAR OPERATION The DAC7634 is a 16-bit, quad voltage output, digitalto-analog converter with guaranteed 15-bit monotonic performance over the specified temperature range. It accepts 24-bit serial input data, has double-buffered DAC input logic (allowing simultaneous update of all DACs), and provides a serial data output for daisy chaining multiple DACs. Programmable asynchronous reset clears all registers to a mid-scale code of 8000H or to a zero-scale of 0000H. The DAC7634 can operate from a single +5V supply or from +5V and –5V supplies. Low power and small size per DAC make the DAC7634 ideal for automatic test equipment, DAC-per-pin programmers, data acquisition systems, and closed-loop servo-control. The DAC7634 is available in a 48-lead SSOP package and offers guaranteed specifications over the –40°C to +85°C temperature range. ● SETTLING TIME: 10µs to 0.003% ● 15-BIT LINEARITY AND MONOTONICITY: –40°C to +85°C ● PROGRAMMABLE RESET TO MID-SCALE OR ZERO-SCALE ● DOUBLE-BUFFERED DATA INPUTS APPLICATIONS ● PROCESS CONTROL ● CLOSED-LOOP SERVO-CONTROL ● MOTOR CONTROL ● DATA ACQUISITION SYSTEMS ● DAC-PER-PIN PROGRAMMERS VDD VSS VREFL AB Sense VCC VREFL AB VREFH AB VREFH AB Sense DAC7634 SDI Shift Register Input Register A DAC Register A DAC A SDO VOUTA VOUTA Sense Input Register B DAC Register B Input Register C DAC Register C DAC B VOUTB VOUTB Sense CS DAC C VOUTC CLOCK RST RESTSEL LDAC Control Logic VOUTC Sense Input Register D DAC Register D DAC D VOUTD LOAD VOUTD Sense AGND VREFL CD Sense DGND VREFL CD VREFH CD VREFH CD Sense International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132 ® © 1999 Burr-Brown Corporation SBAS134 PDS-1563B 1 Printed in U.S.A. January, 2000 DAC7634 SPECIFICATIONS At TA = TMIN to TMAX, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, and VREFL = –2.5V, unless otherwise noted. DAC7634E PARAMETER CONDITIONS ACCURACY Linearity Error Linearity Match Differential Linearity Error Monotonicity, TMIN to TMAX Bipolar Zero Error Bipolar Zero Error Drift Full-Scale Error Full-Scale Error Drift Bipolar Zero Matching Full Scale Matching Power Supply Rejection Ratio (PSRR) ANALOG OUTPUT Voltage Output Output Current Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration TYP MAX ±3 ±4 ±2 ±4 VREF = –2.5V, RL = 10kΩ, VSS = –5V VREFL –1.25 No Oscillation ±2 10 ±2 10 ±2 ±2 100 VREFH +1.25 VREFL + 1.25 –2.5 +2.5 VREFH – 1.25 8 0.5 2 60 40 f = 10kHz 7FFFH to 8000H or 8000H to 7FFFH DIGITAL INPUT VIH VIL IIH IIL UNITS ±2 ±2 ±1 ±3 ✻ ✻ ✻ ✻ ±1 ±1 ✻ ✻ ✻ ✻ ✻ ±2 ±2 ✻ LSB LSB LSB Bits mV ppm/°C mV ppm/°C mV mV ppm/V ✻ ✻ ✻ ✻ ✻ ✻ ✻ 10 POWER SUPPLY VDD VCC VSS ICC IDD ISS Power 3.6 +4.75 +4.75 –5.25 –2.3 TEMPERATURE RANGE Specified Performance –40 V mA pF mA ✻ ✻ V V µA µA ✻ µs LSB nV-s nV/√Hz nV-s ✻ 0.3 • VDD ±10 ±10 IOH = –0.8mA IOL = 1.6mA ✻ ✻ ✻ ✻ 0.7 • VDD DIGITAL OUTPUT VOH VOL ±2 ✻ ✻ ✻ 500 –500 To ±0.003%, 5V Output Step See Figure 5. MAX ✻ ✻ 500 –10, +30 Indefinite GND or VCC or VSS TYP 15 ±1 5 ±1 5 ±1 ±1 10 Channel-to-Channel Matching Channel-to-Channel Matching At Full Scale MIN ±3 14 REFERENCE INPUT Ref High Input Voltage Range Ref Low Input Voltage Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time Channel-to-Channel Crosstalk Digital Feedthrough Output Noise Voltage DAC Glitch MIN DAC7634EB 4.5 0.3 +5.0 +5.0 –5.0 1.5 50 –1.5 15 ✻ 0.4 +5.25 +5.25 –4.75 2 ✻ ✻ ✻ ✻ 20 +85 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V µA µA ✻ V V ✻ ✻ ✻ ✻ ✻ V V V mA µA mA mW ✻ °C ✻ Specifications same as DAC7634E. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. ® DAC7634 2 SPECIFICATIONS At TA = TMIN to TMAX, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, and VREFL = 0V, unless otherwise noted. DAC7634E PARAMETER ACCURACY Linearity Error(1) Linearity Match Differential Linearity Error Monotonicity, TMIN to TMAX Zero Scale Error Zero Scale Error Drift Full-Scale Error Full-Scale Error Drift Zero Scale Matching Full-Scale Matching Power Supply Rejection Ratio (PSRR) ANALOG OUTPUT Voltage Output Output Current Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration CONDITIONS POWER SUPPLY VDD VCC VSS ICC IDD Power MAX ±3 ±4 ±2 ±4 VREFL = 0V, VSS = 0V, RL = 10kΩ 0 –1.25 No Oscillation MIN ±3 ±2 10 ±2 10 ±2 ±2 100 VREFH +1.25 VREFL + 1.25 0 +2.5 VREFH – 1.25 8 0.5 2 60 40 7FFFH to 8000H or 8000H to 7FFFH UNITS ±2 ±2 ±1 ±3 ✻ ✻ ✻ ✻ ±1 ±1 ✻ ✻ ✻ ✻ ✻ ±2 ±2 ✻ LSB LSB LSB Bits mV ppm/°C mV ppm/°C mV mV ppm/V ±2 ✻ ✻ ✻ ✻ ✻ ✻ ✻ 10 +4.75 +4.75 0 TEMPERATURE RANGE Specified Performance –40 ✻ ✻ V V µA µA ✻ µs LSB nV-s nV/√Hz nV-s ✻ 0.3 • VDD ±10 ±10 3.6 V mA pF mA ✻ ✻ 0.7 • VDD IOH = –0.8mA IOL = 1.6mA ✻ ✻ ✻ ✻ ✻ 250 –250 To ±0.003%, 2.5V Output Step See Figure 6. MAX ✻ ✻ 500 ±30 Indefinite GND or VCC TYP 15 ±1 5 ±1 5 ±1 ±1 10 Channel-to-Channel Matching Channel-to-Channel Matching At Full Scale DIGITAL INPUT VIH VIL IIH IIL DIGITAL OUTPUT VOH VOL DAC7634EB TYP 14 REFERENCE INPUT Ref High Input Voltage Range Ref Low Input Voltage Range Ref High Input Current Ref Low Input Current DYNAMIC PERFORMANCE Settling Time Channel-to-Channel Crosstalk Digital Feedthrough Output Noise Voltage, f = 10kHz DAC Glitch MIN 4.5 0.3 +5.0 +5.0 0 1.5 50 7.5 ✻ 0.4 +5.25 +5.25 0 2 ✻ ✻ ✻ 10 +85 ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V µA µA ✻ V V ✻ ✻ ✻ ✻ ✻ V V V mA µA mW ✻ °C NOTE: (1) If VSS = 0V specification applies at Code 0040H and above due to possible negative zero-scale error. ✻ Specifications same as DAC7634E. ® 3 DAC7634 ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS(1) VCC and VDD to VSS .............................................................. –0.3V to 11V VCC and VDD to GND ........................................................... –0.3V to 5.5V VREFL to VSS ............................................................. –0.3V to (VCC – VSS) VCC to VREFH ............................................................ –0.3V to (VCC – VSS) VREFH to VREFL ......................................................... –0.3V to (VCC – VSS) Digital Input Voltage to GND ................................... –0.3V to VDD + 0.3V Digital Output Voltage to GND ................................. –0.3V to VDD + 0.3V Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ........................................ –40°C to +85°C Storage Temperature Range ......................................... –65°C to +125°C Lead Temperature (soldering, 10s) ............................................... +300°C This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. PACKAGE/ORDERING INFORMATION PRODUCT LINEARITY ERROR (LSB) DIFFERENTIAL NONLINEARITY (LSB) DAC7634E PACKAGE PACKAGE DRAWING NUMBER SPECIFICATION TEMPERATURE RANGE ±4 ±3 48-Lead SSOP 333 –40°C to +85°C " " " " " " DAC7634EB ±3 ±2 48-Lead SSOP 333 –40°C to +85°C " " " " " " ORDERING NUMBER(1) TRANSPORT MEDIA DAC7634E DAC7634E/1K DAC7634EB DAC7634EB/1K Rails Tape and Reel Rails Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7634E/1K” will get a single 1000-piece Tape and Reel. PIN DESCRIPTIONS PIN NAME DESCRIPTION PIN NAME 1 NC No Connection 24 VDD Digital +5V Power Supply 2 NC No Connection 25 VCC Analog +5V Power Supply 3 SDI Serial Data Input 26 VCC Analog +5V Power Supply 4 DGND Digital Ground 27 AGND 5 CLK Data Clock Input 28 AGND 6 DGND Digital Ground 29 VSS Analog –5V Power Supply or 0V Single Supply 7 LDAC DAC Register Load Control, Rising Edge Triggered 30 VSS Analog –5V Power Supply or 0V Single Supply 31 VOUTD 32 VOUTD Sense 8 DGND Digital Ground 9 LOAD DAC Input Register Load Control, Active Low 10 DGND Digital Ground 33 VREFL CD Sense 11 CS Chip Select, Active Low 34 VREFL CD 12 DGND Digital Ground 35 VREFH CD 13 SDO Serial Data Output 36 VREFH CD Sense 14 DGND 15 RSTSEL 16 DGND 17 RST 18 19 Digital Ground 37 VOUTC Reset Select. Determines the action of RST. If HIGH, a RST common will set the DAC registers to mid-scale (8000H). If LOW, a RST command will set the DAC registers to zero (0000H). 38 VOUTC Sense Digital Ground Reset, Rising Edge Triggered. Depending on the state of RSTSEL, the DAC registers are set to either mid-scale or zero. DGND NC Digital Ground No Connection 20 NC No Connection 21 DGND Digital Ground 22 DGND Digital Ground 23 VDD Digital +5V Power Supply ® DAC7634 4 DESCRIPTION Analog Ground Analog Ground DAC D Output Voltage DAC D’s Output Amplifier Inverting Input. Used to close feedback loop at load. DAC C and D Reference Low Sense Input DAC C and D Reference Low Input DAC C and D Reference High Input DAC C and D Reference High Sense Input DAC C Output Voltage DAC C’s Output Amplifier Inverting Input. Used to close the feedback loop at the load. 39 VOUTB 40 VOUTB Sense DAC B Output Voltage 41 VREFH AB Sense 42 VREFH AB DAC A and B Reference High Input 43 VOUTL AB DAC A and B Reference Low Input 44 VREFL AB Sense 45 VSS 46 AGND Analog Ground 47 VOUTA DAC A Output Voltage 48 VOUTA Sense DAC B’s Output Amplifier Inverting Input. Used to close the feedback loop at the load. DAC A and B Reference High Sense Input DAC A and B Reference Low Sense Input Analog –5V Power Supply or 0V Single Supply DAC A’s Output Amplifier Inverting Input. Used to close the feedback loop at the load. PIN CONFIGURATION Top View SSOP NC 1 48 VOUTA Sense NC 2 47 VOUTA SDI 3 46 AGND DGND 4 45 VSS CLK 5 44 VREFL AB Sense DGND 6 43 VREFL AB LDAC 7 42 VREFH AB DGND 8 41 VREFH AB Sense LOAD 9 40 VOUTB Sense DGND 10 39 VOUTB CS 11 38 VOUTC Sense DGND 12 37 VOUTC DAC7634 SDO 13 36 VREFH CD Sense DGND 14 35 VREFH CD RSTSEL 15 34 VREFL CD DGND 16 33 VREFL CD Sense RST 17 32 VOUTD Sense DGND 18 31 VOUTD NC 19 30 VSS NC 20 29 VSS DGND 21 28 AGND DGND 22 27 AGND VDD 23 26 VCC VDD 24 25 VCC ® 5 DAC7634 TYPICAL PERFORMANCE CURVES: VSS = 0V At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +85°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 LE (LSB) LE (LSB) DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH +85°C DLE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) +25°C 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code ® DAC7634 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 6 TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. +85°C (cont.) DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, –40°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, –40°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 LE (LSB) LE (LSB) DLE (LSB) LE (LSB) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –40°C DLE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +85°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +85°C) Digital Input Code 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code ® 7 DAC7634 TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. FULL-SCALE ERROR vs TEMPERATURE ZERO-SCALE ERROR vs TEMPERATURE 2 2 Code (0040H) Positive Full-Scale Error (mV) Zero-Scale Error (mV) 1.5 1 DAC C 0.5 DAC A 0 –0.5 DAC D –1 DAC B –1.5 1.5 1 DAC C DAC A 0.5 0 –0.5 DAC B DAC D –1 –1.5 –2 –2 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 –40 –30 –20 –10 90 0 10 20 30 40 50 60 70 Temperature (°C) Temperature (°C) VREFH CURRENT vs CODE (all DACs sent to indicated code) VREFL CURRENT vs CODE (all DACs sent to indicated code) 0.30 0.00 0.25 –0.05 VREF Current (mA) VREF Current (mA) Code (FFFFH) 0.20 0.15 0.10 80 90 –0.10 –0.15 –0.20 0.05 –0.25 0.00 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –0.30 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code POWER SUPPLY CURRENT vs TEMPERATURE POSITIVE SUPPLY CURRENT vs DIGITAL INPUT CODE 2 2 No Load Data = FFFFH (all DACs) No Load 1.5 ICC (mA) ICC (mA) 1.5 1 0.5 All DACs 1 One DAC 0.5 0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code 90 Temperature (°C) ® DAC7634 8 TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. OUTPUT VOLTAGE vs SETTLING TIME (0V to +2.5V) OUTPUT VOLTAGE vs SETTLING TIME (+2.5V to 2mV) +5V LDAC 0 +5V LDAC 0 Output Voltage Output Voltage Large-Signal Settling Time: 0.5V/div Small-Signal Settling Time: 4LSB/div Small-Signal Settling Time: 4LSB/div Large-Signal Settling Time: 0.5V/div Time (2µs/div) Time (2µs/div) OUTPUT VOLTAGE vs MIDSCALE GLITCH PERFORMANCE OUTPUT VOLTAGE vs MIDSCALE GLITCH PERFORMANCE +5V LDAC 0 Output Voltage (50mV/div) Output Voltage (50mV/div) +5V LDAC 0 7FFFH to 8000H 8000H to 7FFFH Time (1µs/div) Time (1µs/div) BROADBAND NOISE OUTPUT NOISE VOLTAGE vs FREQUENCY Noise (nV/√Hz) Noise Voltage (50µV/div) 1000 100 BW = 10kHz Code = 8000H 10 10 Time (10µs/div) 100 1000 10000 100000 1000000 Frequency (Hz) ® 9 DAC7634 TYPICAL PERFORMANCE CURVES: VSS = 0V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = 0V, VREFH = +2.5V, VREFL = 0V, representative unit, unless otherwise specified. VOUT vs RLOAD 5 VOUT (V) 4 3 Source 2 1 Sink 0 0.001 0.01 0.1 1 RLOAD (kΩ) ® DAC7634 10 10 100 1000 TYPICAL PERFORMANCE CURVES: VSS = –5V At TA = +25°C, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) +25°C 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +85°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) +85°C Digital Input Code 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code ® 11 DAC7634 TYPICAL PERFORMANCE CURVES: VSS = –5V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. +85°C (cont.) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +85°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +85°C) 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, –40°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, –40°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) DLE (LSB) LE (LSB) –40°C 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code ® DAC7634 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 12 TYPICAL PERFORMANCE CURVES: VSS = –5V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. VREFL CURRENT vs CODE (all DACs sent to indicated code) +0.6 0.0 +0.5 –0.1 VREF Current (mA) VREF Current (mA) VREFH CURRENT vs CODE (all DACs sent to indicated code) +0.4 +0.3 +0.2 +0.1 –0.3 –0.4 –0.5 0.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH –0.6 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code ZERO-SCALE ERROR vs TEMPERATURE (Code 8000H) POSITIVE FULL-SCALE ERROR vs TEMPERATURE (Code FFFFH) 2 2 1.5 1.5 1 DAC A 0.5 Positive Full-Scale Error (mV) Zero-Scale Error (mV) –0.2 DAC B 0 –0.5 DAC D –1 DAC C –1.5 1 DAC B 0 –0.5 DAC C –1 DAC D –1.5 –2 –2 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 –40 –30 –20 –10 90 0 10 20 30 40 50 60 70 80 90 Temperature (°C) Temperature (°C) NEGATIVE FULL-SCALE ERROR vs TEMPERATURE (Code 0000H) POWER SUPPLY CURRENT vs TEMPERATURE 2 3 1.5 2 Data = FFFFH (all DACs) No Load 1 DAC B ICC 1 0.5 DAC C IQ (mA) Negative Full-Scale Error (mV) DAC A 0.5 0 –0.5 0 ISS –1 DAC A –1 DAC D –2 –1.5 –2 –3 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 –40 –30 –20 –10 Temperature (°C) 0 10 20 30 40 50 60 70 80 90 Temperature (°C) ® 13 DAC7634 TYPICAL PERFORMANCE CURVES: VSS = –5V (Cont.) At TA = +25°C, VDD = VCC = +5V, VSS = –5V, VREFH = +2.5V, VREFL = –2.5V, representative unit, unless otherwise specified. POSITIVE SUPPLY CURRENT vs DIGITAL INPUT CODE VOUT vs RLOAD 2 5 No Load 4 Source 3 1.5 All DACs ICC (mA) 1 0 –1 Sink –2 One DAC 1 0.5 –3 –4 0.01 0.1 1 10 100 0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 1000 RLOAD (kΩ) Digital Input Code OUTPUT VOLTAGE vs SETTLING TIME (–2.5V to +2.5V) OUTPUT VOLTAGE vs SETTLING TIME (+2.5V to –2.5V) Large-Signal Settling Time: 1V/div +5V LDAC 0 +5V LDAC 0 Output Voltage –5 0.001 Output Voltage VOUT (V) 2 Small-Signal Settling Time: 2LSB/div Small-Signal Settling Time: 2LSB/div Large-Signal Settling Time: 1V/div Time (2µs/div) Time (2µs/div) ® DAC7634 14 THEORY OF OPERATION The digital input is a 24-bit serial word that contains a 2-bit address code for selecting one of four DACs, a quick load bit, five unused bits, and the 16-bit DAC code (MSB first). The converters can be powered from either a single +5V supply or a dual ±5V supply. The device offers a reset function which immediately sets all DAC output voltages and DAC registers to mid-scale code 8000H or to zero-scale, code 0000H. See Figures 2 and 3 for the basic operation of the DAC7634. The DAC7634 is a quad voltage output, 16-bit Digital-toAnalog Converter (DAC). The architecture is an R-2R ladder configuration with the three MSB’s segmented, followed by an operational amplifier that serves as a buffer. Each DAC has its own R-2R ladder network, segmented MSBs, and output op amp, as shown in Figure 1. The minimum voltage output (zero-scale) and maximum voltage output (full-scale) are set by the external voltage references (VREFL and VREFH, respectively). RF VOUT Sense VOUT R 2R 2R 2R 2R 2R 2R 2R 2R 2R VREFH VREFH Sense VREFL VREFL Sense FIGURE 1. DAC7634 Architecture. Serial Data In Clock Load DAC Registers Load Chips Select Serial Data Out Reset DAC Registers 1 NC VOUTA Sense 48 2 NC VOUTA 47 3 SDI AGND 46 4 DGND 5 CLK 6 VSS 45 VREFL AB Sense 44 DGND VREFL AB 43 7 LDAC VREFH AB 42 8 DGND VREFH AB Sense 41 9 LOAD VOUTB Sense 40 10 DGND VOUTB 39 11 CS VOUTC Sense 38 12 DGND VOUTC 37 13 SDO VREFH CD Sense 36 14 DGND VREFH CD 35 15 RSTSEL 16 DGND 17 RST 18 DGND 19 NC 20 NC 21 DGND 22 DGND AGND 27 23 VDD VCC 26 24 VDD VCC 25 DAC7634 VREFL CD 34 VREFL CD Sense 33 VOUTD Sense 32 VOUTD 31 VSS 30 VSS 29 AGND 28 0V to +2.5V +2.5000V 0V to +2.5V 0V to +2.5V +2.5000V 0V to +2.5V 0.1µF + 1µF +5V NC = No Connection FIGURE 2. Basic Single-Supply Operation of the DAC7634. ® 15 DAC7634 Serial Data In Clock Load DAC Registers Load Chips Select Serial Data Out +5V Reset DAC Registers + +5V 1µF 1 NC VOUTA Sense 48 2 NC VOUTA 47 3 SDI AGND 46 4 DGND 5 CLK 6 7 –2.5V to +2.5V –5V VSS 45 VREFL AB Sense 44 DGND VREFL AB 43 –2.5000V LDAC VREFH AB 42 +2.5000V 8 DGND VREFH AB Sense 41 9 LOAD VOUTB Sense 40 10 DGND VOUTB 39 11 CS VOUTC Sense 38 12 DGND VOUTC 37 13 SDO VREFH CD Sense 36 14 DGND VREFH CD 35 15 RSTSEL VREFL CD 34 16 DGND VREFL CD Sense 33 17 RST VOUTD Sense 32 18 DGND VOUTD 31 19 NC VSS 30 20 NC VSS 29 21 DGND AGND 28 22 DGND AGND 27 23 VDD VCC 26 24 VDD VCC 25 DAC7634 –2.5V to +2.5V –2.5V to +2.5V +2.5000V –2.5000V –2.5V to +2.5V –5V 0.1µF 0.1µF 0.1µF + + 1µF 1µF +5V NC = No Connection FIGURE 3. Basic Dual-Supply Operation of the DAC7634. ANALOG OUTPUTS The DAC7634 offers a force and sense output configuration for the high open-loop gain output amplifier. This feature allows the loop around the output amplifier to be closed at the load (as shown in Figure 4), thus ensuring an accurate output voltage. When VSS = –5V (dual supply operation), the output amplifier can swing to within 2.25V of the supply rails, guaranteed over the –40°C to +85°C temperature range. When VSS = 0V (single-supply operation), and with RLOAD also connected to ground, the output can swing to ground. Care must also be taken when measuring the zero-scale error when VSS = 0V. Since the output voltage cannot swing below ground, the output voltage may not change for the first few digital input codes (0000H, 0001H, 0002H, etc.) if the output amplifier has a negative offset. At the negative limit of –2mV, the first specified output starts at code 0040H. RW1 DAC7634 Due to the high accuracy of these D/A converters, system design problems such as grounding and contact resistance become very important. A 16-bit converter with a 2.5V fullscale range has a 1LSB value of 38µV. With a load current of 1mA, series wiring and connector resistance of only 40mΩ (RW2) will cause a voltage drop of 40µV, as shown in Figure 4. To understand what this means in terms of a system layout, the resistivity of a typical 1 ounce copperclad printed circuit board is 1/2 mΩ per square. For a 1mA load, a 10 milli-inch wide printed circuit conductor 600 milli-inches long will result in a voltage drop of 30µV. 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUTB Sense 40 VOUTB 39 RW2 VOUT +V +2.5V RW1 RW2 VOUT FIGURE 4. Analog Output Closed-Loop Configuration (1/2 DAC7634). RW represents wiring resistances. ® DAC7634 VOUTA Sense 16 REFERENCE INPUTS The current into the VREFH input and out of VREFL depends on the DAC output voltages, and can vary from a few microamps to approximately 0.5mA. The reference input appears as a varying load to the reference. If the reference can sink or source the required current, a reference buffer is not required. The DAC7634 features a reference drive and sense connection such that the internal errors caused by the changing reference current and the circuit impedances can be minimized. Figures 5 through 13 show different reference configurations, and the effect on the linearity and differential linearity. The reference inputs, VREFL and VREFH, can be any voltage between VSS + 2.5V and VCC – 2.5V, provided that VREFH is at least 1.25V greater than VREFL. The minimum output of each DAC is equal to VREFL plus a small offset voltage (essentially, the offset of the output op amp). The maximum output is equal to VREFH plus a similar offset voltage. Note that VSS (the negative power supply) must either be connected to ground or must be in the range of –4.75V to –5.25V. The voltage on VSS sets several bias points within the converter. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not guaranteed. +V VOUTA Sense 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUTB Sense 40 VOUTB 39 DAC7634 OPA2234 VOUT 100Ω 2200pF –2.5V –5V –V 1000pF +V 100Ω 1000pF +2.5V 2200pF VOUT –V FIGURE 5. Dual Supply Configuration-Buffered References, used for Dual Supply Performance +V VOUTA Sense 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUTB Sense 40 VOUTB 39 DAC7634 OPA2350 VOUT 100Ω 2kΩ 2200pF +0.050V +V 98kΩ 1000pF +2.5V 100Ω 1000pF 2200pF VOUT NOTE: VREFL has been chosen to be 50mV to allow for current sinking voltage drops across the 100Ω resistor and the output stage of the buffer op amp. FIGURE 6. Single-Supply Buffered Reference with a Reference Low of 50mV (1/2 DAC7634). ® 17 DAC7634 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code FIGURE 8. Integral Linearity and Differential Linearity Error Curves for Figure 9. FIGURE 7. Integral Linearity and Differential Linearity Error Curves for Figure 6. +V VOUTA Sense 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUTB Sense 40 VOUTB 39 DAC7634 +V OPA2350 VOUT 100Ω 2200pF +1.25V 1000pF +V 100Ω 1000pF +2.5V 2200pF VOUT FIGURE 9. Single-Supply Buffered Reference with VREFL = +1.25V and VREFH = +2.5V (1/2 DAC7634). VOUTA Sense 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUTB Sense 40 VOUTB 39 DAC7634 VOUT +V +V OPA2350 1000pF VOUT FIGURE 10. Single-Supply Buffered VREFH (1/2 DAC7634). ® DAC7634 +2.5V 100Ω 18 2200pF LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) LE (LSB) LE (LSB) 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 DLE (LSB) DLE (LSB) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code FIGURE 13. Linearity and Differential Linearity Error Curves for Figure 12. FIGURE 11. Linearity and Differential Linearity Error Curves for Figure 10. VOUTA Sense 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUTB Sense 40 VOUTB 39 DAC7634 DIGITAL INTERFACE Table I shows the basic control logic for the DAC7634. The interface consists of a Signal Data Clock (CLK) input, Serial Data (SDI), DAC Input Register Load Control Signal (LOAD), and DAC Register Load Control Signal (LDAC). In addition, a Chip Select (CS) input is available to enable serial communication when there are multiple serial devices. An asynchronous Reset (RST) input, by the rising edge, is provided to simplify start-up conditions, periodic resets, or emergency resets to a known state, depending on the status of the reset select (RSTSEL) signal. VOUT +V The DAC code, quick load control, and address are provided via a 24-bit serial interface (see Figure 15). The first two bits select the input register that will be updated when LOAD goes LOW. The third bit is a “Quick Load” bit such that if HIGH, the code in the shift register is loaded into ALL DAC's input register when LOAD signal goes LOW. If the “Quick Load” bit is LOW, the content of shift register is loaded only to the DAC input register that is addressed. The “Quick Load” bit is followed by five unused bits. The last sixteen bits (MSB first) are the DAC code. +2.5V VOUT FIGURE 12. Low Cost Single-Supply Configuration. SERIAL DATA INPUT B23 A1 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A0 QUICK LOAD X X X X X D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A1 A0 CS RST RSTSEL LDAC LOAD INPUT REGISTER DAC REGISTER MODE DAC L L H H X X X X L H L H X X X X L L L L H H X X H H H H H H ↑ ↑ X X X X X X L H X X X X ↑ H X X L L L L H H X X Write Write Write Write Hold Hold Reset to Zero Reset to Midscale Hold Hold Hold Hold Write Hold Reset to Zero Reset to Midscale Write Input Write Input Write Input Write Input Update Hold Reset to Zero Reset to Midscale A B C D All All All All TABLE I. DAC7634 Logic Truth Table. ® 19 DAC7634 The internal DAC register is edge triggered and not level triggered. When the LDAC signal is transitioned from LOW to HIGH, the digital word currently in the DAC input register is latched. The first set of registers (the DAC input registers) are level triggered via the LOAD signal. This double-buffered architecture has been designed so that new data can be entered for each DAC without disturbing the analog outputs. When the new data has been entered into the device, all of the DAC outputs can be updated simultaneously by the rising edge of LDAC. Additionally, it allows the DAC input registers to be written to at any point, then the DAC output voltages can be synchronously changed via a trigger signal (LDAC). The Serial-Data Output (SDO) is the internal shift register's output. For DAC7634, the SDO is a driven output and does not require an external pull-up. Any number of DAC7634's can be daisy chained by connecting the SDO pin of one device to the SDI pin of the following device in the chain, as shown in Figure 14. Note that CS and CLK are combined with an OR gate, which controls the serial-to-parallel shift register. These two inputs are completely interchangeable. In addition, care must be taken with the state of CLK when CS rises at the end of a serial transfer. If CLK is LOW when CS rises, the OR gate will provide a rising edge to the shift register, shifting the internal data one additional bit. The result will be incorrect data and possible selection of the wrong input register(s). If both CS and CLK are used, CS should rise only when CLK is HIGH. If not, then either CS or CLK can be used to operate the shift register. See Table II for more information. The DAC7634 input data is in Straight Binary format. The output voltage is given by Equation 1. DIGITAL TIMING Figure 15 and Table III provide detailed timing for the digital interface of the DAC7634. DIGITAL INPUT CODING where N is the digital input code. This equation does not VOUT = VREF L + CLK(1) H(2) X(3) H H No Change L(4) L H H No Change L ↑(5) H H Advanced One Bit ↑ L H H Advanced One Bit H(6) X L(7) H No Change H(6) X H ↑(8) No Change LOAD RST The DAC7634 offers a unique set of features that allows a wide range of flexibility in designing applications circuits such as programmable current sources. The DAC7634 offers both a differential reference input, as well as an open-loop configuration around the output amplifier. The open-loop configuration around the output amplifier allows a transistor to be placed within the loop to implement a digitallyprogrammable, unidirectional current source. The availability of a differential reference allows programmability for both the full-scale and zero-scale currents. The output current is calculated as: NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH value is suggested in order to avoid a “false clock” from advancing the shift register and changing the shift register. (7) If data is clocked into the serial register while LOAD is LOW, the selected DAC register will change as the shift register bits “flow” through A1 and A0. This will corrupt the data in each DAC register that has been erroneously selected. (8) Rising edge of RST causes no change in the contents of the serial shift register. V H – VREF L N I OUT = REF • R SENSE 65, 536 TABLE II. Serial Shift Register Truth Table. SCK CLK DIN SDI CS CS + (VREF L / R SENSE ) DAC7634 CLK SDO DAC7634 CLK SDO SDI CS SDI CS FIGURE 14. Daisy-Chaining DAC7634. ® DAC7634 (1) DIGITALLY-PROGRAMMABLE CURRENT SOURCE SERIAL SHIFT REGISTER DAC7634 65, 536 include the effects of offset (zero-scale) or gain (full-scale) errors. SERIAL-DATA OUTPUT CS(1) (VREF H – VREF L) • N 20 SDO To Other Serial Devices (2) (LSB) (MSB) SDI A0 A1 QUICK LOAD X X X X X D15 D1 D0 CLK tcss tCSH tLD1 tLD2 CS tLDDD LOAD tLDRW LDAC tDS tDH SDI tCL tCH CLK tLDDL tLDDH LDAC tS tS ±1 LSB ERROR BAND VOUT tRSTL ±1 LSB ERROR BAND tRSTH RESET tRSSH tRSSS RESETSEL FIGURE 15. Digital Input and Output Timing. SYMBOL DESCRIPTION MIN UNITS t DS tDH tCH t CL tCSS tCSH tLD1 tLD2 Data Valid to CLK Rising Data Held Valid after CLK Rises CLK HIGH CLK LOW CS LOW to CLK Rising CLK HIGH to CS Rising LOAD HIGH to CLK Rising CLK Rising to LOAD LOW LOAD LOW Time LDAC LOW Time LDAC HIGH Time RESETSEL Valid to RESET HIGH RESET HIGH to RESETSEL Not Valid RESET LOW Time RESET HIGH Time Settling Time 10 20 25 25 15 0 10 30 30 100 150 0 100 10 10 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs tLDRW tLDDL t LDDH t RSSS tRSSH tRSTL t RSTH tS TABLE III. Timing Specifications (TA = –40°C to +85°C). ® 21 DAC7634 Figure 16 shows a DAC7634 in a 4mA to 20mA current output configuration. The output current can be determined by Equation 3: (3) At full-scale, the output current is 16mA, plus the 4mA, for the zero current. At zero scale the output current is the offset current of 4mA (0.5V/125Ω). 2.5V – 0.5V N 0.5V • I OUT = + 125Ω 65, 536 125Ω IOUT VPROGRAMMED 125Ω VOUTA Sense 48 VOUTA 47 AGND 46 VSS 45 VREFL AB Sense 44 VREFL AB 43 VREFH AB 42 VREFH AB Sense 41 VOUTB Sense 40 VOUTB 39 DAC7634 +V OPA2350 2200pF 100Ω 20kΩ +V 80kΩ 1000pF +2.5V 100Ω 1000pF 2200pF IOUT VPROGRAMMED 125Ω GND FIGURE 16. 4-to-20mA Digitally Controlled Current Source (1/2 DAC7634). ® DAC7634 22 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. 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