DAC7617 DAC 761 7 DAC ® 761 7 www.ti.com Quad, Serial Input, 12-Bit, Voltage Output DIGITAL-TO-ANALOG CONVERTER FEATURES APPLICATIONS ● LOW POWER: 3mW ● SETTLING TIME: 10µs to 0.012% ● ● ● ● ● ● ● 12-BIT LINEARITY AND MONOTONICITY: –40°C to +85°C ● DOUBLE-BUFFERED DATA INPUTS ● SO-16 or SSOP-20 PACKAGES ● SINGLE-SUPPLY +3V OPERATION PROCESS CONTROL ATE PIN ELECTRONICS CLOSED-LOOP SERVO-CONTROL MOTOR CONTROL DATA ACQUISITION SYSTEMS DAC-PER-PIN PROGRAMMERS DESCRIPTION for simultaneous update of all DAC outputs. The device is powered from a single +3V supply. The DAC7617 is a quad, serial input, 12-bit, voltage output Digital-to-Analog Converter (DAC) with guaranteed 12-bit monotonic performance over the –40°C to +85°C temperature range. An asynchronous reset clears all registers to either mid-scale (800H) or zeroscale (000H), selectable via the RESETSEL pin. The individual DAC inputs are double buffered to allow Low power and small size makes the DAC7617 ideal for automatic test equipment, DAC-per-pin programmers, data acquisition systems, and closed-loop servocontrol. The device is available in SO-16 and SSOP-20 packages and is guaranteed over the –40°C to +85°C temperature range. VDD GND VREFH Input Register A DAC Register A DAC A Input Register B DAC Register B DAC B Input Register C DAC Register C DAC C Input Register D DAC Register D DAC D VOUTA SDI Serial-toParallel Shift Register CLK CS VOUTB 12 DAC Select LOADREG Copyright © 2001, Texas Instruments Incorporated RESETSEL RESET SBAS185 LDAC VOUTC VOUTD VREFL AGND Printed in U.S.A. February, 2001 SPECIFICATIONS At TA = –40°C to +85°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, unless otherwise noted. DAC7617E, U PARAMETER ACCURACY Linearity Error(1) Linearity Matching(3) Differential Linearity Error Monotonicity Zero-Scale Error Zero-Scale Drift Zero-Scale Matching(3) Full-Scale Error Full-Scale Matching(3) Power Supply Rejection ANALOG OUTPUT Voltage Output(4) Output Current Load Capacitance Short-Circuit Current Short-Circuit Duration CONDITIONS Output Noise Voltage DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIH VIL Data Format POWER SUPPLY REQUIREMENTS VDD IDD Power Dissipation TEMPERATURE RANGE Specified Performance TYP DAC7617EB, UB MAX MIN TYP ±2 ±2 ±1 5 ±1 Code = FFFH ±1 30 VREFL –625 No Oscillation VREFH +625 0 0 | IIH | ≤ 10µA | IIL | ≤ 10µA ±2.4 10 ±2 ±2.4 ±2 ✻ ✻ ✻ ✻ ✻ ✻ +1.25 5 0.1 –40 ✻ ✻ ✻ ✻ 10 65 ✻ CMOS ✻ VDD • 0.7 VDD –0.3 VDD • 0.3 Straight Binary 3.0 UNITS ±1 ±1 ±1 LSB(2) LSB LSB Bits mV ppm/°C mV mV mV ppm/V 3.3 0.8 2.4 ✻ ✻ ±1.2 ✻ ±1.2 ✻ ✻ V µA pF mA ✻ V V ✻ µs LSB ✻ ✻ ✻ 100 +8, –2 Indefinite To ±0.012% Full-Scale Step On Any Other DAC Bandwidth: 0Hz to 1MHz MAX ✻ 12 Code = 00AH REFERENCE INPUT VREFH Input Range VREFL Input Range DYNAMIC PERFORMANCE Settling Time Channel-to-Channel Crosstalk MIN ✻ ✻ nV/√Hz ✻ ✻ V V ✻ ✻ ✻ V mA mW ✻ °C ✻ 3.6 1 3 ✻ +85 ✻ ✻ ✻ ✻ ✻ Specification same as DAC7617E, U. NOTES: (1) Specification applies at code 00AH and above. (2) LSB means Least Significant Bit, with V REFH equal to +1.25V and VREFL equal to 0V, one LSB is 0.305mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage does not take into account zero or full-scale error. 2 DAC7617 SBAS185 ABSOLUTE MAXIMUM RATINGS(1) VDD to GND ........................................................................ –0.3V to +5.5V VREFL to GND ........................................................... –0.3V to (VDD + 0.3V) VDD to VREFH .......................................................................... –0.3V to VDD VREFH to VREFL ........................................................................ –0.3V to VDD Digital Input Voltage to GND ...................................... –0.3V to VDD + 0.3V Maximum Junction Temperature ................................................... +150°C Operating Temperature Range ......................................... –40°C to +85°C Storage Temperature Range .......................................... –65°C to +150°C Lead Temperature (soldering, 10s) ............................................... +300°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT MAXIMUM LINEARITY ERROR (LSB) MAXIMUM DIFFERENTIAL LINEARITY (LSB) DAC7617U PACKAGE PACKAGE DRAWING NUMBER SPECIFICATION TEMPERATURE RANGE ±2 ±1 SO-16 211 –40°C to +85°C " " " " " " DAC7617UB ±1 ±1 SO-16 211 –40°C to +85°C " " " " " " ±2 ±1 SSOP-20 334 –40°C to +85°C " " " " " " DAC7617EB ±1 ±1 SSOP-20 334 –40°C to +85°C " " " " " " DAC7617E ORDERING NUMBER(1) TRANSPORT MEDIA DAC7617U DAC7617U/1K DAC7617UB DAC7617UB/1K Rails Tape and Reel Rails Tape and Reel DAC7617E DAC7617E/1K DAC7617EB DAC7617EB/1K Rails Tape and Reel Rails Tape and Reel NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of “DAC7617EB/1K” will get a single 1000-piece Tape and Reel. DAC7617 SBAS185 3 PIN CONFIGURATION—U Package PIN CONFIGURATION—E Package Top View SO VDD 1 20 RESETSEL 1 16 RESETSEL VOUTD 2 19 RESET VOUTD 2 15 RESET VOUTC 3 18 LOADREG VOUTC 3 14 LOADREG VREFL 4 17 LDAC VREFL 4 13 LDAC NIC 5 16 NIC VREFH 5 12 CS NIC 6 15 NIC VOUTB 6 11 CLK VREFH 7 14 CS VOUTA 7 10 SDI VOUTB 8 13 CLK AGND 8 9 GND VOUTA 9 12 SDI AGND 10 11 GND DAC7617U DAC7617E LABEL PIN DESCRIPTIONS—E Package DESCRIPTION PIN LABEL DESCRIPTION Positive Analog Supply Voltage, +3V nominal. 1 VDD Positive Analog Supply Voltage, +3V nominal. 1 VDD 2 VOUTD DAC D Voltage Output 2 VOUTD DAC D Voltage Output 3 VOUTC DAC C Voltage Output 3 VOUTC DAC C Voltage Output 4 VREFL Reference Input Voltage Low. Sets minimum output voltage for all DACs. 4 VREFL Reference Input Voltage Low. Sets minimum output voltage for all DACs. 5 VREFH Reference Input Voltage High. Sets maximum output voltage for all DACs. 5 NIC 6 VOUTB DAC B Voltage Output NIC 7 VREFH Reference Input Voltage High. Sets maximum output voltage for all DACs. 8 VOUTB DAC B Voltage Output 9 VOUTA DAC A Voltage Output Serial Data Clock 10 AGND Chip Select Input 11 GND Ground All DAC registers become transparent when LDAC is LOW. They are in the latched state when LDAC is HIGH. 12 SDI Serial Data Input 13 CLK Serial Data Clock DAC A Voltage Output VOUTA 8 AGND 9 GND Ground 10 SDI Serial Data Input CLK 12 CS 13 LDAC 14 LOADREG Not Internally Connected. 6 7 11 4 SSOP VDD PIN DESCRIPTIONS—U Package PIN Top View Analog Ground The selected input register becomes transparent when LOADREG is LOW. It is in the latched state when LOADREG is HIGH. 15 RESET Asynchronous Reset Input. Sets DAC and input registers to either zero-scale (000H) or mid-scale (800H) when LOW. RESETSEL determines which code is active. 16 RESETSEL When LOW, a LOW on RESET will cause the DAC and input registers to be set to code 000H. When RESETSEL is HIGH, a LOW on RESET will set the registers to code 800H. Not Internally Connected. Analog Ground 14 CS Chip Select Input 15 NIC Not Internally Connected. 16 NIC 17 LDAC All DAC registers becomes transparent when LDAC is LOW. They are in the latched state when LDAC is HIGH. Not Internally Connected. 18 LOADREG The selected input register becomes transparent when LOADREG is LOW. It is in the latched state when LOADREG is HIGH. 19 RESET Asynchronous Reset Input. Sets all DAC registers to either zero-scale (000H) or mid-scale (800H) when LOW. RESETSEL determines which code is active. 20 RESETSEL When LOW, a LOW on RESET will cause all DAC registers to be set to code 000H. When RESETSEL is HIGH, a LOW on RESET will set the registers to code 800H. DAC7617 SBAS185 TYPICAL PERFORMANCE CURVES At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified. 0.50 0.25 0.25 0 –0.25 –0.25 0.50 0.25 0.25 DLE (LSB) –0.50 0.50 0 –0.25 200H 400H 600H 800H A00H C00H E00H 0 –0.25 –0.50 000H FFFH 800H A00H C00H E00H LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +25°C) 0.25 LE (LSB) 0.25 0 –0.25 –0.25 0.50 0.50 0.25 0.25 DLE (LSB) –0.50 0 –0.25 200H 400H 600H 800H A00H C00H E00H 0 –0.25 –0.50 000H FFFH 200H 400H 600H 800H A00H C00H E00H Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, +85°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC B, –40°C) 0.50 0.50 0.25 0.25 0 –0.25 –0.25 –0.50 0.50 0.50 0.25 0.25 –0.25 200H 400H 600H 800H A00H Digital Input Code C00H E00H FFFH FFFH 0 –0.50 0 FFFH 0 –0.50 SBAS185 600H LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, –40°C) 0.50 DAC7617 400H Digital Input Code 0.50 –0.50 000H 200H Digital Input Code LE (LSB) LE (LSB) DLE (LSB) 0 –0.50 –0.50 000H LE (LSB) LE (LSB) 0.50 –0.50 000H DLE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +85°C) DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC A, +25°C) 0 –0.25 –0.50 000H 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code 5 TYPICAL PERFORMANCE CURVES At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified. 0.50 0.25 0.25 0 –0.25 –0.25 0.50 0.25 0.25 DLE (LSB) –0.50 0.50 0 –0.25 200H 400H 600H 800H A00H C00H E00H 0 –0.25 –0.50 000H FFFH 400H 600H 800H A00H C00H E00H Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, –40°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +25°C) 0.50 0.25 0.25 LE (LSB) 0.50 0 –0.25 –0.25 0.50 0.50 0.25 0.25 DLE (LSB) –0.50 0 –0.25 200H 400H 600H 800H A00H C00H E00H 0 –0.25 –0.50 000H FFFH 200H 400H 600H 800H A00H C00H E00H Digital Input Code Digital Input Code LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, +85°C) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC D, –40°C) 0.50 0.50 0.25 0.25 0 –0.25 0 –0.50 0.50 0.50 0.25 0.25 –0.25 200H 400H 600H 800H A00H Digital Input Code C00H E00H FFFH FFFH –0.25 –0.50 0 FFFH 0 –0.50 –0.50 000H 200H Digital Input Code LE (LSB) LE (LSB) DLE (LSB) LE (LSB) 0 –0.50 –0.50 000H DLE (LSB) LE (LSB) 0.50 –0.50 000H 6 LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +85°C) DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (DAC C, +25°C) 0 –0.25 –0.50 000H 200H 400H 600H 800H A00H C00H E00H FFFH Digital Input Code DAC7617 SBAS185 TYPICAL PERFORMANCE CURVES At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified. NEGATIVE FULL-SCALE ERROR vs TEMPERATURE POSITIVE FULL-SCALE ERROR vs TEMPERATURE 2.0 2.0 Code Code(0040 (000HH)) 1.0 DAC D DAC C DAC B 0.5 0 DAC A –0.5 1.5 Positive Full-Scale Error (mV) Negative Full-Scale Error (mV) 1.5 –1.0 –1.5 Code Code (0040 (FFFHH)) 1.0 0 DAC A –0.5 DAC B –1.0 –1.5 –2.0 –2.0 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 –40 –30 –20 –10 0 Temperature (°C) 10 20 30 40 50 60 70 80 90 Temperature (°C) VREFL CURRENT vs CODE VREFH CURRENT vs CODE 0.000 0.200 0.050 0.150 VREF Current (mA) VREF Current (mA) DAC D DAC C 0.5 –0.100 –0.150 0.100 0.050 –0.200 000H 200H 400H 600H 800H A00H C00H E00H FFFH 0.000 000H 200H 400H Digital Input Code 600H 800H A00H C00H E00H FFFH Digital Input Code SUPPLY CURRENT LIMIT vs INPUT CODE SUPPLY CURRENT vs DIGITAL INPUT CODE 10 0.8 No Load 0.7 8 Short to VDD 6 0.5 IOUT (mA) IDD (mA) 0.6 0.4 0.3 4 2 0 0.2 0.1 –2 0.0 000H –4 000H 200H 400H 600H 800H A00H Digital Input Code DAC7617 SBAS185 C00H E00H FFFH Short to Ground 200H 400H 600H 800H A00H C00H E00H FFFH Input Code 7 TYPICAL PERFORMANCE CURVES At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified. POWER SUPPLY CURRENT vs TEMPERATURE OUTPUT VOLTAGE vs RLOAD 1000 3.0 2.5 800 700 2.0 600 VOUT (V) Quiescent Current (uA) 900 500 400 1.5 Source 1.0 300 200 0.5 100 Sink 0 –40 –20 0 20 40 60 80 100 0.0 0.01 0.1 1 10 100 Temperature (°C) RLOAD (kΩ) OUTPUT VOLTAGE vs SETTLING TIME (0V to +1.25V) OUTPUT VOLTAGE vs SETTLING TIME (+1.25V to 0V) Large-Signal Output (0.5V/div) Large-Signal Output (0.5V/div) Small-Signal Error (1mV/div) Small-Signal Error (1mV/div) LDAC (5.0V/div) Time (2µs/div) Time (2µs/div) MID-SCALE GLITCH PERFORMANCE (CODE 7FFH to 800H) MID-SCALE GLITCH PERFORMANCE (CODE 800H to 7FFH) Glitch Waveform (20mV/div) LDAC (5.0V/div) Time (1µs/div) 8 LDAC (5.0V/div) Glitch Waveform (20mV/div) LDAC (5.0V/div) Time (1µs/div) DAC7617 SBAS185 TYPICAL PERFORMANCE CURVES At TA = +25°C, VDD = +3V, VREFH = +1.25V, and VREFL = 0V, representative unit, unless otherwise specified. OUTPUT NOISE VOLTAGE vs FREQUENCY WIDEBAND NOISE (Bandwidth = 10kHz) 120 Code FFFH Noise (nV/√Hz) Noise Voltage (20µV/div) 100 80 60 40 20 0 Time (100µs/div) 100 1k 10k 100k 1M Frequency (Hz) DAC7617 SBAS185 9 THEORY OF OPERATION ANALOG OUTPUTS The DAC7617 is a quad, serial input, 12-bit, voltage output DAC. The architecture is a classic R-2R ladder configuration followed by an operational amplifier that serves as a buffer. Each DAC has its own R-2R ladder network and output op amp, but all share the reference voltage inputs. The minimum voltage output (“zero-scale”) and maximum voltage output (“full-scale”) are set by external voltage references (VREFL and VREFH, respectively). The digital input is a 16-bit serial word that contains the 12-bit DAC code and a 2-bit address code that selects one of the four DACs (the two remaining bits are unused). The converter can be powered from a single +3V supply. Each device offers a reset function which immediately sets all DAC output voltages and internal registers to either zero-scale (code 000H) or mid-scale (code 800H). The reset code is selected by the state of the RESETSEL pin (LOW = 000H, HIGH = 800H). See Figure 1 for the basic operation of the DAC7617. +3V + The output of the DAC7617 can swing to ground. Note that the settling time of the output op amp will be longer with voltages very near ground. Additionally, care must be taken when measuring the zero-scale error. If the output amplifier has a negative offset, the output voltage may not change for the first few digital input codes (000H, 001H, 002H, etc.) since the output voltage cannot swing below ground. The behavior of the output amplifier can be critical in some applications. Under short-circuit conditions (DAC output shorted to VDD), the output amplifier can sink a great deal more current than it can source. See the Specifications Table for more details concerning short-circuit current. DAC7617(1) 1µF to 10µF 0.1µF 0V to +1.25V 0V to +1.25V RESETSEL 16 VOUTD RESET 15 Reset DACs(2) 3 VOUTC LOADREG 14 Update Selected Register 4 VREFL LDAC 13 Update All DAC Registers 5 VREFH CS 12 Chip Select 6 VOUTB CLK 11 Clock 7 VOUTA SDI 10 Serial Data In 8 AGND GND 9 1 VDD 2 +1.25V 0.1µF 0V to +1.25V 0V to +1.25V NOTE: (1) U package pin configuration shown. (2) As configured, RESET LOW sets all internal registers to code 000H (0V). If RESETSEL is HIGH, RESET LOW sets all internal registers to code 800H (1.25V). FIGURE 1. Basic Single-Supply Operation of the DAC7617. 10 DAC7617 SBAS185 REFERENCE INPUTS SYMBOL The minimum output of each DAC is equal to VREFL plus a small offset voltage (essentially, the offset of the output op amp). The maximum output is equal to VREFH – 1LSBplus a similar offset voltage. The current into the reference inputs depends on the DAC output voltages and can vary from a few microamps to approximately 0.4 milliamp. Bypassing the reference voltage or voltages with a 0.1µF capacitor placed as close as possible to the DAC7617 package is strongly recommended. DIGITAL INTERFACE Figure 2 and Table I provide the basic timing for the DAC7617. The interface consists of a serial clock (CLK), serial data (SDI), a load register signal (LOADREG), and a “load all DAC registers” signal (LDAC). In addition, a chip select (CS) input is available to enable serial communication when there are multiple serial devices. An asynchronous reset input (RESET) is provided to simplify start-up conditions, periodic resets, or emergency resets to a known state. DESCRIPTION MIN A1 A0 X X D11 MAX UNITS tDS Data Valid to CLK Rising 25 ns tDH Data Held Valid after CLK Rises 20 ns tCH CLK HIGH 30 ns tCL CLK LOW 50 ns tCSS CS LOW to CLK Rising 55 ns tCSH CLK HIGH to CS Rising 15 ns tLD1 LOADREG HIGH to CLK Rising 40 ns tLD2 CLK Rising to LOADREG LOW 15 ns tLDRW LOADREG LOW Time 45 ns tLDDW LDAC LOW Time 45 ns tRSSH RESETSEL Valid to RESET LOW 25 ns tRSTW RESET LOW Time 70 ns Settling Time 10 µs tS TABLE I. Timing Specifications (TA = –40°C to +85°C). The DAC code and address are provided via a 16-bit serial interface, as shown in Figure 2. The first two bits select the input register that will be updated when LOADREG goes LOW (see Table II). The next two bits are not used. The last 12 bits are the DAC code which is provided, most significant bit first. (MSB) SDI TYP (LSB) D10 D9 D3 D2 D1 D0 CLK tcss tCSH tLD1 tLD2 CS LOADREG tLDRW tDS tDH SDI tCL tCH CLK tLDDW LDAC tS VOUT tS 1 LSB ERROR BAND 1 LSB ERROR BAND tRSTW RESET tRSSH RESETSEL FIGURE 2. DAC7617 Timing. DAC7617 SBAS185 11 STATE OF SELECTED INPUT REGISTER STATE OF ALL DAC REGISTERS A1 A0 LOADREG LDAC RESET SELECTED INPUT REGISTER L(1) L L H(2) H A Transparent Latched L H L H H B Transparent Latched H L L H H C Transparent Latched H H L H H D Transparent Latched X(3) X H L H NONE (All Latched) Transparent X X H H H NONE (All Latched) Latched X X X X L ALL Reset(4) Reset(4) NOTES: (1) L = Logic LOW. (2) H = Logic HIGH. (3) X = Don’t Care. (4) Resets to either 000H or 800H, per the RESETSEL state (LOW = 000H, HIGH = 800H). When RESET rises, all registers that are in their latched state retain the reset value. TABLE II. Control Logic Truth Table. CS(1) CLK(1) H(2) X(3) H H No Change L(4) L H H No Change L ↑(5) H H Advanced One Bit LOADREG RESET SERIAL SHIFT REGISTER ↑ L H H Advanced One Bit H(6) X L(7) H No Change H(6) X H L(8) No Change NOTES: (1) CS and CLK are interchangeable. (2) H = Logic HIGH. (3) X = Don’t Care. (4) L = Logic LOW (5) = Positive Logic Transition. (6) A HIGH value is suggested in order to avoid a “false clock” from advancing the shift register and changing the shift register. (7) If data is clocked into the serial register while LOADREG is LOW, the selected input register will change as the shift register bits “flow” through A1 and A0. This will corrupt the data in each input register that has been erroneously selected. (8) RESET LOW causes no change in the contents of the serial shift register. TABLE III. Serial Shift Register Truth Table. Note that CS and CLK are combined with an OR gate and the output controls the serial-to-parallel shift register internal to the DAC7617 (see the block diagram on the front of this data sheet). These two inputs are completely interchangeable. In addition, care must be taken with the state of CLK when CS rises at the end of a serial transfer. If CLK is LOW when CS rises, the OR gate will provide a rising edge to the shift register, shifting the internal data one additional bit. The result will be incorrect data and possible selection of the wrong input register. 12 If both CS and CLK are used, then CS should rise only when CLK is HIGH. If not, then either CS or CLK can be used to operate the shift register. See Table III for more information. The digital data into the DAC7617 is double-buffered. This allows new data to be entered for each DAC without disturbing the analog outputs. When the new settings have been entered into the device, all of the DAC outputs can be updated simultaneously. The transfer from the input registers to the DAC registers is accomplished with a HIGH to LOW transition on the LDAC input. It is possible to keep this pin LOW and update each DAC via LOADREG because the DAC registers become transparent when LDAC is LOW. However, as each new data word is entered into the device, the corresponding output will update immediately when LOADREG is taken LOW. Digital Input Coding The DAC7617 input data is in Straight Binary format. The output voltage is given by the following equation: VOUT = VREFL + (VREFH – VREFL) • N 4096 where N is the digital input code (in decimal). This equation does not include the effects of offset (zero-scale) or gain (full-scale) errors. DAC7617 SBAS185 LAYOUT The power applied to VDD should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. As the DAC7617 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to keep digital noise from appearing at the converter output. As with the GND connection, VDD should be connected to a +3V power supply plane or trace that is separate from the connection for digital logic until they are connected at the power entry point. In addition, the 1µF to 10µF and 0.1µF capacitors shown in Figure 3 are strongly recommended. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a π filter made up of inductors and capacitors—all designed to essentially lowpass filter the +3V supply, removing the high-frequency noise (see Figure 3). Due to the DAC7617’s single ground pin, all return currents, including digital and analog return currents, must flow through the GND pin. Ideally, GND would be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power entry point of the system (see Figure 3). Digital Circuits +3V +3V Power Supply Ground +3V DAC7617 Ground VDD 100µF + + 1µF to 10µF 0.1µF AGND Optional Other Analog Components FIGURE 3. Suggested Power and Ground Connections for a DAC7617 Sharing a +3V Supply with a Digital System. DAC7617 SBAS185 13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. 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