ETC DEM-ADS78DIP

DEM-ADS78DIP
®
EVALUATION FIXTURE
FEATURES
DESCRIPTION
● ANALOG BREADBOARD AREA
The DEM-ADS78DIP evaluation fixture is designed
for quick evaluation of Burr-Brown’s line of 8-pin
plastic DIP analog-to-digital converter including,
ADS1286, ADS7816, ADS7817, ADS7818, ADS7822,
ADS7834, and ADS7835. Although these products
are available in other package types, such as MSOP,
SSOP, and SOIC, the DEM-ADS78DIP provides an
excellent way to evaluate all of these products in their
DIP packages with one board. The board has features
that allow the user to evaluate all the functions of these
A/D converters. The options offered to the user includes an easily configurable voltage reference, a
flexible clock generator circuit, an analog breadboard,
digital breadboard and an isolated digital breadboard
areas. Optional power supply connections are also
available on the DEM-ADS78DIP board to assist in
the evaluation of possible transducer input circuits on
the analog breadboard as well as digital isolation
circuits on the isolated digital breadboard. The DEMADS78DIP has been designed to accommodate standalone operation, allowing the user to easily connect to
an external processor.
● DIGITAL BREADBOARD AREA
● FLEXIBLE CLOCK PROGRAMMING
● FLEXIBLE REFERENCE VOLTAGE
PROGRAMMING
● STAND-ALONE CAPABILITY
APPLICATIONS
● SMALL DYNAMIC RANGE DIGITIZING
● ISOLATED DATA ACQUISITION
● TRANSDUCER INTERFACE
● BATTERY OPERATED SYSTEMS
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1997 Burr-Brown Corporation
LI-491B
Printed in U.S.A. April, 1998
USING THE VARIOUS A/D CONVERTERS
WITH THIS BOARD
consequently the LSB size. Low power, automatic power
down, and small size make these A/D converters ideal for
battery operated systems. They are also ideal for remote or
isolated data acquisition applications. Although this evaluation fixture is designed to evaluate the devices in an 8-pin
DIP, each product has a surface-mount option available.
The product line that is compatible with this evaluation
fixture is listed in Table I. This product line features low
power operation with automatic power down, asynchronous
serial interface and a differential input. The reference voltage can be varied in order to change the input range and
+VD
+VD
R21
1kΩ
C4
0.1µF
E10
1
2
3
NC1
CATHODE 2
NC2
CATHODE 2
NC3
4
U2
8
6
R8
1kΩ
E4
E9
C3
0.1µF
5
NC4
ANODE
E3
7
NC5
R5
1kΩ
E2
R4
1kΩ
REF1004-2.5
R6
1kΩ
E5
13
4
5
E6
E1
6
E7
R7
1kΩ
7
E8
12
11
10
Reference
Select
P5
J8
9
C
5
B
3
4
D
7
6
8
A
1
2
1
16
C2
0.1µF
15
J10
6
VREF
3
2
8
C1
0.1µF
P3
2
E
P4
P4
C6
2.2µF
3
A0
A1
A2
EN
+VD
14
R15
10kΩ
R3
100Ω
1
37
3
39
2
41
1
Ref Input Control
R19
100kΩ
U5
6
ADS7822PD OUT
DUT
20
–IN
CS
U4
5
1
19
U4
74AC11004
R11
100Ω
2
43
4
J6
BB17
1
BB5
74AC11074
PR
13
BB6
D
J4
DIV 4
BB4
Q
2
C
To Breadboard CS/SHDN
J5
DIV 100
B
DIV 20
A
47
P1
BB16
R10
100Ω
To Breadboard EXT CLOCK In
D
DIV 10
P1
EXT CLOCK In
R13
49.9Ω
B
A
Clock Select
18
Timing Select
3
U4
74AC11004
U9
13
U4
14
8
CK
Q
CLR
74AC11004
3
12
BB10
+VISO
+
P7
P8
P8
P8
C8
2.2µF
2
1
CS/SHDNISO
2
SDATAISO
3
CLOCKISO
7
BB11
8
BB13
9
2
5
1
CS Control
3
4
+VD
U6
CTX129-ND
ENT
ENP
A
B
C
D
14
QA
QB
12
U10
QC
74HC163N
11
QD
LD
CK
U8
14
Q
CK
CLR
3
7
C10
0.1µF
9
74AC11074
PR
D
Q
R27
100Ω
R28
10kΩ
R30
100Ω
R31
10kΩ
R33
100Ω
Slider
4
11
Slider
Slider
Slider
FIGURE 1. DEM-ADS78DIP Circuit Diagram.
®
2
P1
2
7
R32
100kΩ
P1
3
9
1
CK
Q
CLR
10
P1
P1
12
CKA
CKB
74hc390n
6
U7
13
13
QA
11
QB
U8 QC 10
9
14
QD
CLR
15
12
8
R25
10kΩ
DEM-ADS78DIP
32MHz
RCO
CL
R29
100kΩ
2
U7
8
+VD
15
Q
D
U7
C11
0.1µF
74AC11074
PR
7
13
R24
100Ω
R26
100kΩ
13
+VD
R22
10kΩ
R23
100kΩ
1
C12
0.1µF
J9
14
10
5
2
5
+5V
BB15
6
1
CK
Q
CLR
BB14
+5V
6
6
10
4
7
Q
U7
3
8
D
BB12
7
J7
74AC11074
PR
9
GNDISO
P1
P1
SDATA OUT 45
To Breadboard SDATA Out
BB7
1
P1
74AC11004
CS/SHDN
GND
BB9
P7
P1
R20
100kΩ
CLK IN/OUT
BB3
BB8
GND
R9
100Ω
7
+5V
C7
2.2µF
U3
ADG608BN
S8
R2
100Ω
BB18
–VCC
1
2
S7
R16
10kΩ
C5
2.2µF
+
S6
+IN
C
+VCC
2
3
2
B
A
1
+
P3
BB VIN–
BB2
3 VIN–
+
CLK
F
J3
D
P3
VCC
VREF
G
BB1
8
R1
100Ω
R18
100kΩ
H
Voltage In Select
1 VIN+
D
S5 4/5
R17
10kΩ
J3
P2
P2
P2
S4
3
+VD
6
7
P2
S3 3/5
V–
U1
3 OPA234P
4
C9
47µF
BB19
V+
S2 2/5
2
R12
100Ω
P2
BB VIN+
2
+VD
R14
49.9Ω
S1 1/5
5
3
QA
5
QB
U8 QC 6
7
2
QD
CLR
1
4
CKA
CKB
74hc390n
P6
PRODUCT
CLOCK RATE
SAMPLE RATE
VREF RANGE
ADS1286
320kHz
20kHz
0.1V - 5V
ADS7816
3.2MHz
200kHz
0.1V - 5V
ADS7817
3.2MHz
200kHz
0.4V - 5V
ADS7818
8MHz
500kHz
2V - 2.55V
ADS7822
1.6MHz
100kHz
0.1V - 5V
ADS7834
8MHz
500kHz
2V - 2.55V
ADS7835
8MHz
500kHz
2V - 2.55V
J3-E. This type of flexibility allows the user to easily attach
the inputs of the DUT to the input terminal block, P2, the
breadboard, or ground. The input jumper connections (J3)
are shown in Figure 2 and summarized in Table II.
Optional R || C input networks (J3-A and J3-H) are designed
to allow the user to generate a DC offset off set from the
power supply to the input pin(s) or design an R || C low pass
filter. Both configurations are shown in Figure 3.
TABLE I. Some of the Products that can be Demonstrated
with this Fixture are Shown Above.
JUMPER
POSITION
DEM-ADS78DIP BOARD
DESCRIPTION
A circuit diagram of the DEM-ADS78DIP is shown in
Figure 1. This demonstration fixture has four fundamental
active sections on the board which eases the evaluation
process of the Device Under Test (DUT). These sections are
the analog input, the voltage reference block, clock generation network and the digital interface. Each section is
configurable to accommodate the differences between the 8pin DIP A/D products available from Burr-Brown. The DUT
socket (U5) allows for the easy evaluation of any number of
A/D converters without doing tedious soldering and
desoldering. Additionally, analog and digital breadboard
sections are available in the event the user requires further
customization of the circuit.
DESCRIPTION
A
Connects pin 3 of DUT (VIN–) to P2 through adjustable R || C network.
B
Connects pin 3 of the DUT (VIN–) directly to the
input connector P2 : VIN–
C
Connects pin 3 of the DUT (VIN–) to the breadboard
bus in the center of the analog breadboard area.
D
Connects pin 3 of the DUT (VIN–) to GND.
E
Connects pin 2 of the DUT (VIN+) to GND.
F
Configures pin 2 of the DUT (VIN+) directly to the
breadboard bus.
G
Configures pin 2 of the DUT (VIN+) to the input
connector P2: VIN+
H
Connects pin 2 of the DUT (VIN+) to R2 through
adjustable R || C network.
TABLE II. J3: Input Configuration Jumper. Both inputs to
the DUT (pins 2 and 3) must be connected to
one of the three options described above in order
to obtain a sensible output.
The power supply terminal block P4 should be connected
with +VD = +5V (nominal). P3 and P7 are available as
optional supply terminal blocks to be powered at the discretion of the user.
There are five jumpers (J3, J4, J5, J8, and J9) on the board
that allow the flexibility needed during the evaluation phase
of the DUT. J4 is directly connected to the clock generation
network. This network divides the oscillator clock, U6, by 4
10, 20, or 100. To further enhance the flexibility of the
clocking capability, J5 can be used to jumper an external
clock into the circuit. Finally, J8 can be used to select the
voltage reference source to the DUT pin 1 (VREF). The
jumper options are listed in Tables II through VI. Each of the
four active sections and the three breadboard sections are
discussed below.
J3
To VIN+ of P2 thru R || C Network
H
IN–
To VIN+ of P2
G
IN+
To VIN+ of Analog Breadboard
F
IN+
To GND of P2, P4, P5 and
Analog Breadboard
E
IN+
D
IN–
To VIN– of Analog Breadboard
C
IN–
To VIN– of P2
B
IN–
To VIN– of P2 thru R || C Network
A
IN–
U5
FIGURE 2. Analog Input Jumper Configuration, J3.
ANALOG INPUT SECTION
The analog inputs of the DUT are accessible from the
terminal block P2 or from the center signal busses on the
analog breadboard area. In all cases, J3 must be properly
configured.
The analog breadboard section, located nearest to the DUT,
is provided to allow the user to configure their own front end
circuits. Nine power and signal busses in conjunction with
two supply terminals provide enough flexibility for this area,
making it easy to build any desired analog and/or reference
circuit. The nine power and signal busses are separated into
three groups; (a) VREF, GND, +VD, (b) VIN+, GND, VIN–,
and (c) +VCC, GND, –VCC (see Figure 4 for detailed layout).
The inverting and non-inverting analog inputs of the A/D
converter (DUT in U5 socket) are available from pins 3 and
2, inclusive. These pins are connected to the four pins on the
jumper, J3. The inverting input of the A/D converter (DUT
pin 3) can be connected to the pins of J3-A, J3-B, J3-C and
J3-D. The non-inverting input of the A/D converter (DUT
pin 2) can be connected to the pins of J3-H, J3-G, J3-F and
VREF is connected directly to the A/D converter’s reference
pin (pin 1). This allows the user to design and build custom
reference circuits on the analog breadboard. If the VREF bus
®
3
DEM-ADS78DIP
signal from U6 by 4, 10, 20 and 100, as described in Table III.
This entire clock section can be powered down by removing
the J9 jumper top. An external clock can be connected via the
BNC connector, P6 (EXT CLK). The best performance is
achieved with a 50% clock duty cycle (in the case of J4-A and
J4-D). The external clock instead of J4-B and J4-C is recommended for best results. In all cases, refer to Table III and IV
for the correct jumper configuration.
+5V
2.5V DC Level
R
J3-H or J3-A
C
P2-1
or
P2-3
2 or 3
R
A/D
Converter
(DUT)
a)
JUMPER
POSITION
+5V
FACTORY
FREQUENCY
BEST
SUITED FOR
ADS7822
A
Divides the clock oscillator, U6, by 20.
1.6MHz
B
Divides the clock oscillator, U6, by 100.
320kHz
ADS1286
C
Divides the clock oscillator, U6, by 10.
3.2MHz
ADS7616
ADS7817
D
Divides the clock oscillator, U6, by 4.
8MHz
ADS7818
ADS7834
ADS7835
J3-H or J3-A
R
P2-1
or
P2-3
DESCRIPTION
2 or 3
Low-Pass
R || C Filter
C
A/D
Converter
DUT
TABLE III. J4: Clock Divider Control. The stated factory
frequency assumes a 32MHz clock oscillator is
inserted in U6.
b)
FIGURE 3. The R || C network at the input of the DUT
(J3-H and J3-A) can be configured to provide a
dc level shift (a) for the input signal at P2 or a
low pass filter (b).
JUMPER
POSITION
is used, J8 should be open. A GND is in between the VREF
and the +VD busses. This is the same GND that is connected
to the power supply terminal, P4. The third bus in this area
is +VD. +VD is powered from the terminal block, P4. This
terminal block powers the DUT and must be in compliance
with the DUT’s specified power supply range. This terminal
block also supplies power to the other devices on the board.
A
Selects the clock input to the DUT to come from the
Clock Divider portion of the demo board. Use J4 to
configure the desired frequency.
B
Selects the clock input to the DUT to come from the
External Clock BNC connector, P6.
TABLE IV. J5: External Clock Control.
U9, U10, J6 and J7 are provided to control the function of
CS to the device. U10 is a 4-bit Synchronous Binary Center.
In conjunction with U9 (D-type Flip Flop) and J7 the CS can
be programmed for 12-bit, 10-bit or 8-bit operation. Refer to
Table V for details. J6 disconnects this function completely.
VIN+ and VIN–, along with another GND bus, are placed
through the center of the analog breadboard area. VIN+ and
VIN– are made available on the analog breadboard by connecting the appropriate jumper with J3 (as described in
Table II). The GND bus is also connected to the power
supply terminal, P4.
SLIDER POSITION
The third group power consists of VCC+, GND, and VCC–.
VCC+ and VCC– are independent supplies that are powered
through the supply terminal, P3.
Note: Some of the DUT devices for this board have
power supply pin labels of +VCC in their data sheet. This
is not the same as the VCC+ connection on the board.
These supplies can be any value, dependent on the user’s
needs. All GND connections on the analog breadboard area
are also used as the ground reference for the devices installed on the remainder of the board.
DESCRIPTION
1
2
3
4
Off
Off
Off
Off
17 clock cycles
Off
Off
Off
On
16 clock cycles per conversion for 12-bit operation.
Off
Off
On
Off
15 clock cycles
Off
Off
On
On
14 clock cycles per conversion for 10-bit operation.
Off
On
Off
Off
13 clock cycles
Off
On
Off
On
12 clock cycles per conversion for 8-bit operation
Off
On
On
Off
11 clock cycles
Off
On
On
On
10 clock cycles
On
Off
Off
Off
9 clock cycles, etc.
TABLE V. J7; CS Control.
VOLTAGE REFERENCE BLOCK
The voltage that is supplied to the A/D converter can be
provided through one of five sources; an external reference
(P5, VREF), a precision 2.5V reference (U2), a digital programmable reference (U3 and J10), the power supply or
CLOCK CIRCUITRY
The clock section of the board consists of U6, U7, U8, U9,
U10, J4, J6, J7, J9, and P6. A 32MHz oscillator chip is
installed in the U6 socket. This chip can be replaced as deemed
necessary by the user. U7 and U8 are used to divide the clock
®
DEM-ADS78DIP
DESCRIPTION
4
4
J10 SWITCH POSITIONS
3
2
1
MATHEMATICAL
VALUE (If E1 through E10 are changed by user)
FACTORY SET
VOLTAGE
X
OFF
OFF
OFF
+VD (R4)/(R4 + R5 + R6 + R7 +R8)
1V
X
OFF
OFF
ON
+VD (R4 + R5 + R6 + R7)/(R4 + R5 + R6 + R7 + R8)
4V
X
OFF
ON
OFF
+VD (R4 + R5 + R6)/(R4 + R5 + R6 + R7 + R8)
3V
X
ON
OFF
OFF
+VD (R4 + R5)/(R4 + R5 + R6 + R7 + R8)
2V
X
ON
ON
ON
X
OFF
ON
ON
X
ON
OFF
ON
X
ON
ON
OFF
0V
TABLE VII. J10: Multiplexed Reference Voltage Selection. All other switch settings are invalid, however, other combinations
will not cause damage. (X = Don’t Care).
JUMPER
POSITION
A
P1
CONNECTOR
PIN
DESCRIPTION
The Voltage Reference Input to the DUT is selected
to be the digitally programmable reference, implemented with U3, J10, R4, R5, R6, R7 and R8. This voltage
reference function is fully implemented with the selection of this jumper in conjunction with instructions for
J10 found in Table V.
All even pins
DESCRIPTION
GND
41
Interface through J10 to A2 of U3 (analog multiplexer)
Slider 1, Table VII
39
Interface through J10 to A1 of U3 (analog multiplexer)
Slider 2, Table VII
B
The Voltage Reference Input to the DUT is selected to
be the power supply voltage, +VD.
37
Interface through J10 to A0 of U3 (analog multiplexer)
Slider 3, Table VII
C
The Voltage Reference Input to the DUT is selected to
be connected to the REF1004-2.5, a 2.5V precision
reference (U2).
43
Clock interface to the DUT and clock section on the board
45
DATA OUT interface from the DUT
47
CS/SHDN interface to the DUT
13
Interface through J7 (CS control), Slider 4, Table V
11
Interface through J7 (CS control), Slider 3, Table V
9
Interface through J7 (CS control), Slider 2, Table V
7
Interface through J7 (CS control), Slider 1, Table V
D
No Jumper Top
The Voltage Reference Input to the DUT is selected to
come from the VREF BNC connector, P5.
If the A/D converter has an internal reference (such as
the ADS7818) or if reference circuit is built on the
analog breadboard area and soldered to the VREF bus.
TABLE VI. J8 : Reference Voltage Configuration.
TABLE VIII. P1 Interface to the DEM-ADS78DIP Evaluation Fixture.
from a circuit built on the analog breadboard area. The
origin of the voltage reference is configured using jumper,
J8, per Table VI.
Isolated Digital Breadboard Area
The isolated digital breadboard section is laid out in such a
way that the power supply terminals P3 (VCC +, VCC –, GND)
and P4 (+VD, GND) are not connected to the power planes
in this section (see Figure 6). The two terminal blocks, P8
and P7, are provided to allow the user easy access to the
power busses CS/SHDNISO (P8), SDATAISO (P8), CLKISO
(P8), +VISO (P7) and GNDISO (P7).
If the jumper top for J8 is placed in position A, an analog
multiplexer (U3) is used to switch in various voltages to the
reference pin of the DUT. The sockets E1 through E10 allow
for easy insertion of standard through-hole resistors. With
these sockets the user can easily configure a custom array of
reference voltages for the DUT. See Table VII for details.
This breadboard section was designed to allow the user to
breadboard an isolated power and isolated signal interface
to the DEM-ADS78DIP board. This is accomplished by
separating the power and ground planes of the isolated
breadboard section from the rest of the board.
DIGITAL BREADBOARD
Non-isolated Digital Breadboard Area
The non-isolated digital breadboard area shown in Figure 4
has five power/signal busses available. +VD is connected
directly to the power terminal, P4, having a nominal voltage
of +5V. The bus GND is directly connected to the board
ground plane. CS is connected directly to the DUT’s
CS/SHDN (pin 5). SDATA is connected directly to the
DUT’s DOUT (pin 6). CLK is connected directly to the
clocking network (per Tables III and IV) and to the DUT’s
DCLOCK (pin 7).
This area is not designed to withstand high isolation voltages.
It has been included to help the designer evaluate the effects
of isolated power sources such as DC to DC converters.
®
5
DEM-ADS78DIP
DIGITAL INTERFACE
The A/D converter, analog multiplexer (U3) and the onboard clock are all accessible through the digital interface
socket, P1. All even pins of P1 are connected to the board
GND (per power terminal, P4). See Table VIII for more
details.
DUT
PIN
NAME
DESCRIPTION
The remainder of the layout information is shown in Figures
4 through 7. Table IX summarizes the external terminal
connections to the DEM-ADS78DIP board as well as the
connections from the breadboard to the evaluation fixture
circuitry. The parts list for this evaluation fixture is listed in
Table X.
DUT
PIN
BREADBOARD
NUMBER
BUS NAME
TERMINAL #/PIN
A/D Voltage Reference
VREF
1
VREF
P5
A/D Non-inverting Input
+IN
2
VIN+
P2/1
A/D Inverting Input
–IN
3
VIN–
P2/3
A/D Ground
GND
4
GND
P2/2
P3/2
P4/2
P1 All Even Pins
A/D Chip Select
/Shut Down
CS/SHDN
5
CS
P1/47
A/D Digital Out
DOUT
6
SDATA
P1/45
A/D Clock Input
DCLOCK
7
CLK
P1/43
+VCC
8
+VD
P4/1
Auxiliary Breadboard
Power Supply
+VCC
P3/1
Auxiliary Breadboard
Power Supply
–VCC
P3/3
Isolated Bus
CS/SHDNISO
P8/1
Isolated Bus
SDATAISO
P8/2
Isolated Bus
CLOCKISO
P8/3
+VISO
P7/1
GNDISO
P7/2
A/D Power Supply
Isolated Power
Isolated Ground Plane
TABLE IX. General Summary of External Pin Connections
and Breadboard Bus Connections for the DEMADS78DIP Evaluation Fixture.
DESIGNATOR
DESCRIPTION
PART NUMBER
QTY
VENDOR(S)
Burr-Brown
U1
Single-Supply Op Amp, PDIP
OPA234P
1
U2
2.5V Reference, Surface Mount
REF1004C-2.5
1
Burr-Brown
U3
Single-Supply Analog Multiplexer
ADG608BN
1
Analog Devices
U4
Digital Buffer
74AC11004
1
T.I.
U5
DUT 8-pin, 12-Bit A/D Converter
ADS7816P
1
Burr-Brown
U6
32MHz Clock Oscillator
CTX129-ND
1
CTS (DigiKey #)
Dual D-Type Flip-Flop
74AC11074
2
T.I.
4-Bit Synchronous Binary Counter
74HC163N
1
T.I.
U7, U9
U10
U8
R1-R3, R9-R12, R24, R27, R30, R33
Dual Decade Counter
74HC390N
1
T.I.
100Ω, 0.125W, 1% MF Resistor
RN55C1000F
11
Dale
R4-R8, R21
1kΩ, 0.125W, 1%, MF Resistor
RN55C1001F
6
Dale
R15-R17, R22, R25, R28, R31
10kΩ, 0.125W, 1%, MF Resistor
RN55C1002F
7
Dale
R18-R20, R23, R26, R29, R32
100kΩ, 0.125W, 1%, MF Resistor
RN55C1003F
7
Dale
R13, R14
49.9Ω, 0.125W, 1%, MF Resistor
RN55C49R9
2
Dale
0.1µF, 50VX7R Ceramic Capacitor
CK05BX104K
9
Kemet
C9
47µF, 10V, 10%, Tantalum Dipped Radial
T350H476K010AS
1
Kemet
C5-C8
2.2µF, Tantalum Dipped/Radial, 25V, 10%
T350B225K025AS
4
Kemet
25 x 2 Contact, Right-angle, Connector
IDH-50LP-SR3-TG
1
Robinson-Nugent
P2, P3, P8
3-Pin Term Block
ED300/3
3
On-Shore Technology
P4, P7
2-Pin Term Block
ED300/2
3
On-Shore Technology
P5, P6
BNC Connector, PCB Mount
KC-79-274-M06
2
King
J10, J7
Switch Low-Profile DIP
LD04
2
C&K Components
C1-C4, C10-C14
P1
Jumper Tops
SNT-100-BK-T-H
6
Samtec
DEM-ADS78DIP Board
A2206-1 Rev C
1
Burr-Brown
U4 Socket
20-pin, DUT Socket
520AG-11-DES
1
Aries
U5 Socket
8-pin DUT Socket
508AG-11-DES
1
Augat
U6 Socket
14-pin Oscillator Socket
1107741
1
Augat
TABLE X. Parts List.
®
DEM-ADS78DIP
6
DESCRIPTION
PART NUMBER
QTY
VENDOR(S)
8-pin A/D Converter
ADS7822P
1
Burr-Brown
8-pin A/D Converter
ADS7817P
1
Burr-Brown
ADS7816 Product Data Sheet
PDS-1355
1
Burr-Brown
ADS7817 Product Data Sheet
PDS-1369
1
Burr-Brown
ADS7822 Product Data Sheet
PDS-1358
1
Burr-Brown
DEM-ADS78DIP Product Data Sheet
LI-491
1
Burr-Brown
TABLE XI. Packing List.
FIGURE 4. Component Side.
®
7
DEM-ADS78DIP
FIGURE 5. Silkscreen.
FIGURE 6. Solder Side.
®
DEM-ADS78DIP
8
FIGURE 7. Top Soldermask.
®
9
DEM-ADS78DIP