EVB9S12NE64 Development Board for the M9S12NE64 ! Axiom Manufacturing • 2813 Industrial Lane • Garland, TX 75041 Email: [email protected] Web: http://www.axman.com ! E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 CONTENTS CAUTIONARY NOTES ...........................................................................................................................................................3 TERMINOLOGY ......................................................................................................................................................................3 FEATURES................................................................................................................................................................................4 GETTING STARTED...............................................................................................................................................................5 SPECIAL OPERATING NOTES .....................................................................................................................................................5 REFERENCE DOCUMENTATION .................................................................................................................................................5 EVB9S12NE64 STARTUP ........................................................................................................................................................5 MONITOR OPERATION ........................................................................................................................................................6 MONITOR MEMORY MAP ..................................................................................................................................................6 RUN / LOAD SWITCH .............................................................................................................................................................6 EVB9S12NE64 OPERATION ..................................................................................................................................................7 MODE OPTIONS....................................................................................................................................................................7 MODA, MODB, MODC ......................................................................................................................................................7 ROM_OFF...........................................................................................................................................................................7 MODE_CHART ...................................................................................................................................................................7 POWER SUPPLY ...................................................................................................................................................................7 FUSE – FZ1.........................................................................................................................................................................8 Power Port...........................................................................................................................................................................8 Power Jack ..........................................................................................................................................................................8 PWR_SW – ON/OFF ...........................................................................................................................................................8 VRH_EN and VRL_EN ........................................................................................................................................................9 RESET OPERATION .................................................................................................................................................................9 OSC_SEL ................................................................................................................................................................................9 X1 CLOCK OSCILLATOR ....................................................................................................................................................9 EXTERNAL BUS .................................................................................................................................................................10 CONFIG SWITCH ...................................................................................................................................................................10 J1 ETHERNET PORT ................................................................................................................................................................10 STATUS Indicators ............................................................................................................................................................11 COM PORTS ...........................................................................................................................................................................11 COM_Switch......................................................................................................................................................................11 FLOW_SEL Options ..........................................................................................................................................................12 COM1 ................................................................................................................................................................................12 COM2 ................................................................................................................................................................................13 IRDA Port and JP3............................................................................................................................................................13 LCD PORT1 AND 2 ...............................................................................................................................................................14 I2C EEPROM MEMORY ........................................................................................................................................................14 KEYPAD ...............................................................................................................................................................................15 USER COMPONENTS .........................................................................................................................................................15 USER_ENABLE.................................................................................................................................................................15 USER_IO Connector .........................................................................................................................................................16 RV1 User Potentiometer ....................................................................................................................................................16 SW1 – SW4 Push Switches.................................................................................................................................................16 LED1 – 4 Indicators ..........................................................................................................................................................16 BREADBOARD....................................................................................................................................................................16 M9S12NE64 PORT CONNECTORS ....................................................................................................................................17 MCU1_PORT........................................................................................................................................................................17 MCU2_GP PORT..................................................................................................................................................................18 BDM PORT...........................................................................................................................................................................18 TROUBLESHOOTING ............................................................................................................................................................19 2 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 TABLE 1: LCD COMMAND AND CHARACTER CODES..............................................................................................20 Cautionary Notes 1) Electrostatic Discharge (ESD) prevention measures should be applied whenever handling this product. ESD damage is not a warranty repair item. 2) Axiom Manufacturing reserves the right to make changes without further notice to any products to improve reliability, function or design. Axiom Manufacturing does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under patent rights or the rights of others. 3) EMC Information on the EVB9S12NE64 board: a) This product as shipped from the factory with associated power supplies and cables, has been tested and meets with requirements of CE and the FCC as a CLASS A product. b) This product is designed and intended for use as a development platform for hardware or software in an educational or professional laboratory. c) In a domestic environment this product may cause radio interference in which case the user may be required to take adequate prevention measures. d) Attaching additional wiring to this product or modifying the products operation from the factory default as shipped may effect its performance and also cause interference with other apparatus in the immediate vicinity. If such interference is detected, suitable mitigating measures should be taken. Terminology This development board applies option selection jumpers. Terminology for application of the option jumpers is as follows: Jumper on, in, or installed = jumper is a plastic shunt that fits across 2 pins and the shunt is installed so that the 2 pins are connected with the shunt. Jumper off, out, or idle = jumper or shunt is installed so that only 1 pin holds the shunt, no 2 pins are connected, or jumper is removed. It is recommended that the jumpers be idled by installing on 1 pin so they will not be lost. This development board applies hardwired option selections (VRL_EN and CUTAWAY 1 – 3). These option selections apply a circuit trace between the option pads to complete a default connection. This type connection places an equivalent Jumper Installed type option. The circuit trace between the option pads maybe cut with a razor blade or similar type knife to isolate the default connection provided. Applying the default connection again can be performed by installing the option post pins and shunt jumper, or by applying a wire between the option pads. 3 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 FEATURES The EVB9S12NE64 is an evaluation or development board for the Motorola M9S12NE64 microcontroller. Development of applications is quick and easy with the included DB9 serial cable, sample software tools, examples, and debug monitor. The prototyping area provides space to apply the CPU I/O to your needs. The BDM port is provided for development tool application and is compatible with HCS12 BDM interface cables and software. Features: ♦ MC9S12NE64 CPU * 64K Byte Flash * 8K Bytes Ram * 70 I/O lines (112 pins) * 10/100 EMAC and EPHY * 4 channel Timer w/PWM * 8 Channel 10 BIT A/D * SPI and I2C Serial Ports * 2 x SCI Serial Ports * 21 Key Wake-up Ports * BDM Port * Clock generator w/ PLL * 0 - 25Mhz operation ♦ 25MHz reference Crystal oscillator ♦ External Clock oscillator optional ♦ Regulated +3.3V and 5V power supplies ♦ COM1 Serial Port w/ RS232 DB9-S Connector EVB9S12NE64 * SCI0 Serial Port ♦ COM2 Serial Port w/ RS232 DB9-S Connector * SCI1 Serial Port ♦ IRDA wireless port on SCI1 ♦ 10/100T Ethernet Port, 802.3 ♦ ON/OFF switch w/ Power Indicators ♦ Option Switches for I/O assignments ♦ User Components Provided * 4 LED Indicators (PTF0-3) * 4 Push Switches (PTA4-7) * LCD PORT (SPI) * Keypad Port ♦ MCU PORT1 and 2 connectors provides all CPU digital I/O ♦ BUS PORT connector provides address/data and control in Expanded modes ♦ Breadboard and Prototype Areas ♦ Supplied with DB9 Serial Cable, Ethernet cable, Utility and Support CD, Manuals, and Wall plug type power supply. Specifications: Board Size 5.0 x 7.0 inches Power Input: +6 - +16VDC, 9VDC typical Current Consumption: 120ma @ 9VDC input typical The EVB9S12NE64 is provided operating the Motorola binary serial monitor. The monitor allows serial interface to host based development environments for source level debugging operations. 4 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 GETTING STARTED The EVB9S12NE64 single board computer is a fully assembled, fully functional development board for the Motorola MC9S12NE64 microcontroller. Support software for this development board is provided for Windows 95/98/NT/2000/XP operating systems. Development board users should also be familiar with the hardware and software operation of the target HCS12 device, refer to the provided Motorola User Guide for the device and the HCS12 Reference Manual for details. The development board purpose is to assist the user in quickly developing an application with a known working environment or to provide an evaluation platform for the target HCS12. Users should be familiar with memory mapping, memory types, and embedded software design for the quickest successful application development. Application development maybe performed by applying the embedded serial interface monitor, or by applying a compatible HCS12 BDM cable with supporting host software. The monitor provides an effective and low cost debug method. Special Operating Notes The EVB9S12NE64 board provides Expanded Wide Mode operation of external on-board SRAM development memory. For compatibility with the Ethernet 100T operation of the NE64 device, the expanded bus will operate at 25Mhz in a lab environment (25 degrees C). This bus operating frequency is well beyond the specified expanded bus operating frequency of 16Mhz and should not be applied in user designs. The Expanded Wide Mode operation on the EVB board requires the MODE register EMK bit to be enabled for proper operation of the external SRAM board memory. Reference Documentation Reference documents are provided on the support CD in Acrobat Reader format. M9S12NE64 user manual CPU12 core user manual with instruction set EVB9S12NE64_SCH_B.pdf – EVB9S12NE64 board schematics AN2548 Serial Monitor application note EVB9S12NE64 Startup Follow these steps to connect and power on the board for the default Monitor operation. 1) With EVB board ON/OFF switch in the off position, configure these options for default settings: MODA, MODB, MODC, and ROM_OFF option jumpers Open or Idle. RUN/LOAD Switch in the LOAD position. 5 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 FLOW_SEL option jumpers in default positions (no flow enabled). COM_Switch positions 1 and 2 ON, other as needed for application. CONFIG_Switch as needed for application. USER_Enables as needed for application. 2) Connect the EVB COM1 port to the host PC with the 9 pin serial cable. 3) Connect the EVB POWER JACK with the provided power supply and install the power supply into a local wall or power strip outlet. 4) Turn the EVB board ON/OFF switch to the ON position and observe the +V, +3.3V, and +5V indicators are ON. 5) Launch the desired monitor IDE software on the host PC and establish communication with the EVB target. Verify target is the Serial Monitor in the IDE software if optional. You are now ready to load and debug your application code or examples. MONITOR OPERATION Refer to application note AN2548 for complete details of the Serial Monitor. The monitor firmware resides in the 9S12NE64 flash memory from addresses 0xF800 > 0xFFFF (2K bytes). Monitor operation applies the SCI0 serial port and internal ram space starting at 0x3FFF (grows downward) for Stack and variables. All other memory space and peripherals are available to the user. MONITOR MEMORY MAP Address (Hex) 0000 > 03FF 0400 > 1FFF 2000 > 3FFF 4000 > F77F F780 > F7FF F800 > FFFF Memory Type NE64 Registers External SRAM if enabled Internal SRAM, STACK = 3FFF User Internal flash Memory (Program space) User Interrupt vectors Monitor firmware (protected) RUN / LOAD Switch The RUN/ LOAD switch allows selection of monitor operation or user code application during RESET condition. If the User Reset vector at address 0xFBFE/F is programmed to a nonerased state value and the RUN/LOAD switch is in the RUN condition, the monitor will apply the user Reset vector to start the user application. The RUN/LOAD switch allows the user to force the monitor to start when the LOAD position is selected. 6 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 EVB9S12NE64 OPERATION The EVB9S12NE64 board provides many input and output features to assist in application development. These features may be isolated from the applied HCS12 I/O ports by the option switches or jumpers. This allows alternate use of the HCS12 I/O ports for other application and connection on the MCU1_PORT or MCU2_GP_PORT connectors. Caution should be observed so that the HCS12 I/O port pin applied to an on board feature is not also applied to external components by the user. MODE OPTIONS The EVB board provides options for Mode selection or memory configuration during power-on or Reset. User should properly apply these options for correct development mode and memory map. MODA, MODB, MODC The MODA, MODB, and MODC options provide selection of the default operating mode of the 9S12NE64 at Reset. Default option position for the MODA, MODB, and MODC options is open or idle. The default setting places the NE64 in normal Single-chip Mode for operation of the serial monitor located in the internal flash memory. Some configuration settings provided by the Mode selection can be modified in software during initialization, refer to the 9S12NE64 user documents for more details. See the MODE CHART below for valid Mode option settings on the EVB9S12NE64 board. ROM_OFF The ROM_OFF option is default open or idle. Installation of the ROM_OFF option will disable the internal flash memory of the NE64 device at Reset. This option should only be installed during application of Background Debug Module (BDM) type tools. MODE_CHART MODE Option MODA / MODB Option Position Open (Default) MODC ROM_OFF Open (Default) Open (Default) Operating Notes Single-chip Mode (Expanded Modes maybe configured in software during initialization). Special Modes enable. Install with BDM cable application only. Internal Flash Memory Disable. Install with BDM application only. POWER SUPPLY Input power is applied by external connection to the Power Jack or Power Port terminal block. The input supply is enabled to the voltage regulator by the ON_OFF switch. The regulators are protected from reverse voltage by diode D2 and current limited by fuse FZ1. Input voltage is regulated to +3.3V supply by VR1. With +5 to +16VDC applied and the ON_OFF switch in the ON position, the +V, +3.3V, and +5V Indicators should be ON. 7 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 FUSE – FZ1 Fuse FZ1 will open during an over current condition. The cause of an over current condition that opens FZ1 should be corrected before fuse replacement. FZ1 is a 5x20mm 500ma slow blow type fuse. Power Port Power Port terminal block provides access to the +VIN, +5V, +3.3V, and GND (power ground) supplies. The +VIN connection is not switched by the ON-OFF switch or fused and is directly connected to the Power Jack. The +3.3V position can source 200ma to external circuits. Applying +3.3V or +5V externally to power the board from the Power Port should not be performed. If the user needs more power, an additional voltage regulator or source should be applied with a common ground connected at the Power Port GND connection. Power Port 4 GND 3 +5V 2 1 3.3V +VIN Power Jack The Power Jack provides the default power input to the board. The jack accepts a standard 2.0 ~ 2.1mm center barrel plug connector (positive voltage center) to provide the +VIN supply of +5 to +25 VDC (+9VDC typical). +Volts, 2mm center PWR_SW – ON/OFF The PWR Switch provides board power ON and OFF control. The +VIN supply from either the PWR Switch or the POWER_PORT is applied via the switch. 8 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 VRH_EN and VRL_EN VRH and VRL analog signals are connected to VDDA and Ground potentials respectfully by the VRH_EN and VRL_EN option positions. The VRL_EN signal has a wired connection that may be isolated from the default potentials by a cut with a razor blade or knife between the option pads on the development board. Alternate VRH or VRL signals may then be applied at the ANALOG Port. To restore the default connection, a 1x2 pin post header can be installed to allow option jumper use or a wire jumper can be installed between the option pads. RESET Operation The RESET switch, BDM if applied, or NE64 device generate the HCS12 RESET* signal. The RESET indicator will light for the duration of the active RESET signal. Mode configuration options are input by the NE64 during the reset. OSC_SEL The OSC_SEL option jumper provides selection between the Y1 crystal oscillator circuit and an external X1 clock source or MCU2_GP_Port XCLK signal. The Y1 25Mhz crystal oscillator is selected by default. 1 OSC_SEL = Y1 operation 1 OSC_SEL = X1 / XCLK X1 CLOCK OSCILLATOR The X1 socket is provided to install a standard 3.3V compatible CAN type clock oscillators so that alternate reference frequencies maybe applied to the NE64. User should refer to the NE64 device user manual for information on frequency selection. X1 clock signal XCLK is provided at the MCU2_GP_Port pin 24. The port pin may be applied to output the X1 clock or to input a 3.3V peak to peak clock signal. If a signal is input to the XCLK connection on the MCU2 port, the X1 clock oscillator should not be installed in the socket. Note that the X1 clock XCLK signal maybe applied for output to the MCU2_GP_Port without application to the NE64 by placing the OSC_SEL option in the Y1 position. 9 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 EXTERNAL BUS The EVB board provides an external address and data bus with control signals. Bus operation requires the NE64 MODE register EMK bit to be set. EVB board Bus application is dedicated to the 512K Byte external ram memory access to provide development memory. EVB board operation allows 25Mhz external bus operation at 0 clock stretch cycles for development purposes. User should note that the NE64 device has a 16Mhz rated external bus capability and that 25Mhz operation should not be expected in NE64 product designs. Refer to the EVB board schematic drawing for bus connection details. CONFIG Switch The CONFIG switch provides options for the EVB9S12NE64 development board external bus, external SRAM, LCD Ports, Ethernet PHY status indications, and IRDA shut down features. CONFIG_SW 1 OPERATION Expanded Bus Logic Enable 2 3 RAM Select 1 = All expanded memory space RAM Select = XCS* 4 Ram Select = ECS* 5 LCD Port Enable 6 Ethernet Status Enable Operation Notes ON = Expanded Wide BUS is enabled and BUS_PORT is active. NE64 Ports A, B, E, and K applied for BUS operation. NE64 should be in Expanded Wide Mode with MODE EMK bit enabled for operation. OFF = Bus logic is disabled and external memory will not operate. ON (2 ON, 3 and 4 OFF) = External ram is available for the entire accessible external expanded memory space. ON (3 ON, 2 and 4 OFF) = External ram is available for the XCS* chip select memory space. NE64 MODE must be Expanded Wide with EMK bit set. ON (4 ON, 2 and 3 OFF) = External ram is available for the NE64 Flash space (MISC = flash off, EMK = ON) Note: Only applied with BDM. ON = LCD Ports are enabled on the NE64 SPI port. Port S7 / SS* signal operation will access the LCD port shift register. OFF= SPI is not applied to the LCD Ports. ON = Ethernet PHY status indicators TX_RX, LNK, 100, DUP, and COL are enabled on NE64 Port L 0 – 4. NE64 PHY register settings must also enable operation. Note that the status indicators may also be applied under Port L manual operation if wanted. OFF = Ethernet status indicators are not enabled on NE64 Port L. J1 Ethernet Port J1 provides the standard RJ45 endpoint connection for a 10/100T type Ethernet port. The Ethernet cable provided with the EVB board is a CAT5E crossover type for connection directly to a PC type Ethernet port. A standard CAT5E Ethernet cable should be applied to connect a HUB type Ethernet port. The port is driven directly from the NE64 EPHY connections. Refer to board schematic for connection details and the MC9S12NE64 EPHY manual for additional details. 10 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 STATUS Indicators The EVB board provides 5 Ethernet status indicators, TX_RX, LNK, 100, DUP, and COL, that are controlled by NE64 port PTL0 – 4 outputs respectfully. CONFIG switch position 6 must be ON to enable these indicators on the EVB board. Ethernet status indicator operation is provided by NE64 PHY control or the user may apply under application software control of the individual PTL ports. Active port level is logic 0 or 0V. Indicator ACT LNK SPD DUP COL Color RED GREEN GREEN GREEN RED Control Port PTL0 PTL1 PTL2 PTL3 PTL4 Operation Indication Transmit or Receive in progress Network Link is detected 100 base Network detected. Full duplex Network detected Network experiencing collisions, trouble detected COM Ports The EVB9S12NE64 provides two RS232 type COM1 / 2 ports or a RS232 COM1 port and an IRDA type communication port. COM1 or COM2 may be optioned with flow controls with the FLOW_SEL options. COM_SW options enable the communication and flow control connections in hardware. User must apply correct software operation to the associated SCI port for the communication type selected. COM_Switch The COM_SW provides NE64 I/O port to communication peripheral connections on the evaluation board. This allows the user to apply the provided communication transceivers and ports, or to apply the associated I/O to other purposes. The switch positions and FLOW_SEL options should be reviewed first if any operational problems are encountered with the COM1, COM2, or IRDA ports. COM_SW HCS12 Port COM Signal 1 2 3 PTS01/RXD0 PTS1/TXD0 PTS2/RXD1 COM1 RXD IN COM1 TXD OUT COM2 RXD IN EVB I/O Port Connection MCU2_GP pin 22 MCU2_GP pin 21 MCU2_GP pin 30 4 PTS3/TXD1 COM2 TXD OUT MCU2_GP pin 29 5 PTL5 COM1 RTS OUT MCU1 Pin 30 6 PTG7 COM1 CTS IN MCU2_GP pin 2 7 PTS2/RXD1 IRDA RXD IN MCU2_GP pin 30 8 PTS3/TXD1 IRDA TXD OUT MCU2_GP pin 29 11 Operation Notes SCI0 to COM1 RS232 RCV SCI0 to COM1 RS232 XMT SCI1 to COM2 RS232 RCV Note: Switch position 7 must be open SCI1 to COM2 RS232 XMT Note: Switch position 8 must be open NE64 Port L5 output is RTS signal output. See FLOW_SEL options NE64 Port G7 input is CTS signal input. See FLOW_SEL options SCI1 to IRDA RCV Note: Switch position 3 must be open SCI1 to IRDA XMT Note: Switch position 4 must be open E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 FLOW_SEL Options The FLOW_SEL option provides configuration of the RTS / CTS flow control signals to the COM1 and COM2 port. FLOW Selection requires NE64 Port L5 to be enabled by the COM Switch position 5 as the RTS output and NE64 Port G7 to be enabled by the COM Switch position 6 as the NE64 board CTS input. User application software must also support the flow control operation of RTS / CTS signaling on PTL5 and PTG7. Following are the 3 basic option settings: FLOW_SEL Idle, no RTS / CTS FLOW_SEL with COM1 RTS / CTS enabled 3 3 2 2 1 1 FLOW_SEL with COM2 RTS / CTS enabled 3 2 1 RTS signal active output level is logic 0. User should place port PTL5 at logic low (0) to enable the RTS signal and reception of bytes if applied. User should apply a logic high signal under software control inform host or connected RS232 device to STOP transmitting (stop sending incoming bytes). CTS signal active input level is logic 0. User should apply software to detect a logic high signal on Port PTG7 and STOP transmitting bytes to the host or connected device to implement hardware flow control. Detection of a logic low input indicates the host is ready to receive bytes and the user (NE64) may transmit. COM1 The COM1 port provides standard 9 pin connection with RS232 type interface to the HCS12 SCI0 peripheral. Refer to the COM_SW for enabling the HCS12 RXD0 and TXD0 signals applied to this port. Refer to the COM_SW and FLOW_SEL options for enabling RTS/CTS flow controls on this port. The COM1 port is applied by default with the embedded Monitor. HCS12 SCI0 TXD0 and RXD0 signals are converted to RS232 levels by U13 and provided to the COM1 connector. The HCS12 PTL5 and PTG7 signals may be applied for the optional RTS/CTS flow control on this port. Following is the DB9S connection reference. COM1 1 TXD0 RXD0 4 GND 1 2 3 4 5 6 7 8 9 X The COM-1 port is a Female (socket type) DB9 connector. 6 CTS IN Pins 1, 4, and 6 connected for status null to host. RTS OUT 9 Pins 7 and 8 optioned by COM_SW and FLOW_SEL 12 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 COM SW positions 1 and 2 will isolate the HCS12 SCI0 signals from the transceiver. The 1, 4, 6, and 9 pins provide RS232 status. The status pins 1, 4, and 6 are connected on the on the bottom of the development board to provide a NULL status returned to the host. DB9 connector pin locations are provided access pads behind the connector on the EVB board. User may isolate the connection pads by cutting the associated circuit trace on the bottom of the board. The user may then apply status connections to the host by applying HCS12 I/O signals and additional RS232 level conversion. COM2 The COM2 port provides standard 9 pin connection with RS232 type interface to the HCS12 SCI1 peripheral. Note that the HCS12 SCI1 signals are shared with COM2 and the IRDA port. Refer to the COM_SW for enabling the HCS12 RXD1 and TXD1 signals applied to this port. Refer to the COM_SW and FLOW_SEL options for enabling RTS/CTS flow controls on this port. HCS12 SCI1 TXD1 and RXD1 signals are converted to RS232 levels by U13 and provided to the COM2 connector. The HCS12 PTL5 and PTG7 signals may be applied for the optional RTS/CTS flow control on this port. Refer to the COM_SW and FLOW_SEL options for proper option selections for this port. Following is the DB9S connection reference. COM2 1 TXD1 RXD1 4 GND 1 2 3 4 5 6 7 8 9 X 6 CTS IN RTS OUT 9 The COM-2 port has a Female (socket type) DB9 connector. Pins 1, 4, 6 connected for status NULL to host. Pins 7 and 8 optioned by COM_SW and FLOW_SEL COM SW positions 3 and 4 will isolate the HCS12 SCI1 signals from the COM2 port transceiver. The 1, 4, 6, 7, 8, and 9 pins provide RS232 flow control and status. These pins are connected on the on the bottom of the development board to provide a NULL status and flow control returned to the host. DB9 connector pin locations are provided access pads behind the connector on the EVB board. User may isolate the connection pads by cutting the associated circuit trace on the bottom of the board. The user may then apply status connections to the host by applying HCS12 I/O signals and additional RS232 level conversion. IRDA Port and JP3 The IRDA port provides the HCS12 SCI1 operation of a 115.2K baud compatible IRDA interface. An IRDA transceiver is applied to provide up to 30 inches of wireless IRDA link (line of sight, indoors only). The HCS12 SCI1 module must be configured for IRDA communication to apply this port. See the COM_SW option positions 3, 4, 7, and 8 for properly enabling the IRDA port hardware with the SCI1 module. 13 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 The IRDA port has an optional Shut Down control option that may be enabled by installing the JP3 option jumper. HCS12 port L6 will provide the shutdown control signal when JP3 is installed. User application software must provide the shutdown control operation with JP3 installed. IRDA shut down is accomplished by a logic 1 (+3.3V) signal being applied. IRDA is enabled by default. LCD PORT1 and 2 The LCD_PORT(S) interface are connected to the HCS12 SPI-0 port and are enabled by CONFIG Switch position 5 ON. The interface applies a 5Volt level serial shift register to convert the data to parallel interface for LCD input. This is required due to the fast timing characteristics of the HCS12 data bus and the slow timing of the standard LCD Modules. Example LCD Port assembly language driver software is provided on the support CD to demonstrate typical LCD module operation using this technique. The interface supports all OPTREX™ DMC series and similar displays with up to 80 characters in 4 bit bus mode and provides the most common pin configuration for a dual row rear mounted display connector (LCD_PORT1) or an in-line connector type (LCD_PORT2). Only one connector maybe applied at a time for LCD connection. The LCD Module is configured in a Write only mode, it is not possible to read current cursor position or the busy status back from the module. The LCD module VEE or contrast potential is adjustable by the CONTRAST potentiometer between –5V and +5V. The Axiom Mfg. HC-LCD module is compatible for connection to LCD_PORT1. LCD_PORT1 Connector +5V RS EN DB1 DB3 DB5 DB7 2 4 6 8 10 12 14 1 3 5 7 9 11 13 GND VEE-Contrast R/W-GND DB0 DB2 DB4 DB6 SPI data bit definitions to LCD Port: D0 - D3 = DB4 - 7, LCD data in 4 bit mode. D4 - D5 = Spare pins S1 and S2, not connected D6 = RS, 0 = LCD Command, 1 = LCD Data D7 = EN, 1 = LCD enable. DB0 -DB3 are not applied and have 10K pull-down resistance. LCD_PORT2 Connector has the same pin number and signal association in a single row connector. The LCD write requires 3 SPI transfers. Transfer 1 provides data 0 - 3 and RS (register select) value. Transfer 2 provides the same data with the EN (D7) bit set. Transfer 3 provides same data with the EN bit clear. I2C EEPROM Memory A 2432 type I2C compatible EEprom is provided on the EVB board for user application. The EEprom is made available to the 9S12NE64 ports PJ6/SDA and PJ7/SCL pins by the EE_EN option jumper. Install both option jumpers for EEprom access. 14 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 KEYPAD The KEYPAD connector provides interface for applying a passive 4 x 4 matrix (16 key, HC-KP) keypad. Note that the NE64 ports applied may be enabled as EMAC MII signals. 1 2 3 4 5 6 7 8 PTH0/KWH0 PTH1/KWH1 PTH2/KWH2 PTH3/KWH3 PTJ0/KWJ0 PTJ1/KWJ1 PTJ2/KWJ2 PTJ3/KWJ3 This interface is implemented as a software key scan. Pins PTH0-3 are applied as column drivers which are active high outputs. Pins PTJ0-3 are applied for row input and will read high when the keypad key is pressed. Scan software then determines the key number from valid column and row combination. See the file Key12.ASM for an example program using this connector. USER COMPONENTS The EVB9S12NE64 board provides 4 push button switches (SW1 – 4), 4 buffered LED indicators (LED1 – 4), and a user potentiometer (RV1). All the user components can be applied to dedicated NE64 I/O ports by the USER_EN Switch or RV1_EN option jumper. The user components may be provided for other I/O or application at the USER_IO header also. Use caution and disable USER_EN connections when applying the USER_IO connections to prevent port conflicts. USER_ENABLE The USER ENABLE options provide a method to enable or connect the EVB user components applied to the HCS12 I/O ports. The development board user should be familiar with the input and output application so that I/O port conflicts do not occur. Following is the connection reference table: USER ENABLE POSITIO N 1 2 3 4 5 6 7 8 RV1_EN USER DEVICE LED 1 LED 2 LED 3 LED 4 SW 1 SW 2 SW 3 SW 4 RV1 POT HCS12 I/O PORT PTG0 / EMAC RXD0 PTG1 / EMAC RXD1 PTG2 / EMAC RXD2 PTG3 / EMAC RXD3 PTE0 / XIRQ* PTH4 / EMAC TCLK PTH5 / EMAC TXEN PTH6 / EMAC TXER PAD0 / AN0 PORT DIRECTION and Active Level ALTERNATE EVB I/O PORT Output, active Low Output, active Low Output, active Low Output, active Low Input, active Low Input, active Low Input, active Low Input, active Low Input, 0 to 3.3V MII Port, MCU2_GP pin 7 MII Port, MCU2_GP pin 8 MII Port, MCU2_GP pin 5 MII Port, MCU2_GP pin 6 BUS Port, MCU1 pin 33 MII Port, MCU2_GP pin 23 MII Port, MCU2_GP pin 36 MCU2_GP pin 25 MCU2_GP pin 17 NOTE: If the NE64 device EMAC signals are enabled to appear on the device I/O ports, User Enable positions 1 to 9 cannot be applied. 15 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 USER_IO Connector User components maybe applied alternately at the USER-IO connector. Associated USER_EN options should be opened to prevent I/O conflicts when applying this connector. USER I/O POSITIO N 1 2 3 4 5 6 7 8 9 USER DEVICE LED 1 LED 2 LED 3 LED 4 RV1 SW 1 SW 2 SW 3 SW 4 ACTIVE LEVEL to / from circuit USER_EN or Option Input, active Low Input, active Low Input, active Low Input, active Low Output, 0 – 3.3V Output active Low Output active Low Output, active Low Output, active Low USER_EN Switch 1 USER_EN Switch 2 USER_EN Switch 3 USER_EN Switch 4 RV1_EN option jumper USER_EN Switch 5 USER_EN Switch 6 USER_EN Switch 7 USER_EN Switch 8 RV1 User Potentiometer The User Potentiometer provides an adjustable linear voltage output from 0 to 3.3V. The voltage potential is provided to HCS12 port PAD0 / AN0 by the RV1_EN option jumper being installed on both pins. The HCS12 port PAD0/AN0 should be placed in analog input mode while RV1_EN is installed. SW1 – SW4 Push Switches The push switches provide momentary active low input for user applications. Switch idle level of logic 1 or +3.3V is provided by discreet pull-up resistors on the EVB board, internal port pullups are not required. SW1 – 4 provide input to HCS12 ports PTE0/XIRQ*, and PTH4 - 6 when USER EN switch positions 5 to 8 are enabled respectfully. Input port PTE0/XIRQ may be configured as the XIRQ interrupt input by clearing the HCS12 X bit in the CCR register with user software. PTH4 – PTH6 provide input interrupt capability also. User should note that the NE64 EMAC MII signals may also be enabled to appear on this port. LED1 – 4 Indicators The LED indicators provide an active low output indication for user applications. Indicators are buffered to reduce NE64 device I/O current. LED 1 – 4 are driven from NE64 I/O ports PTG0 – PTG3 respectfully when USER_EN switch positions 1 – 4 are enabled. User should note that the NE64 EMAC MII signals may also be enabled to appear on this port. BREADBOARD The Breadboard area provides a convenient and fast interconnection for prototyping circuits on the EVB9S12NE64 board. User may apply 22-24GA solid core wire (stripped) to make connections between the I/O port connectors and the breadboard. Soldering not required. 16 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 M9S12NE64 PORT CONNECTORS MCU1_PORT The MCU1 Port provides access to the MC9S12NE64 I/O ports A, B, E, K and L. The A, B, E and K I/O ports are also applied as the expanded address and data bus. User should not apply these port pins if the expanded bus is operating. Port L is also the Ethernet PHY status LED port. User should not apply PTL0 – 4 if Ethernet PHY status indication is being provided. PB0 / D0 PB2 / D2 PB4 / D4 PB6 / D6 PA0 / D8 PA2 / D10 PA4 / D12 PA6 / D14 PK0 / XA14 PK2 / XA16 PK4 / XA18 PK6 / XCS* PL0 PL2 PL4 PL6 PE0 / XIRQ* PE2 / R/W* PE4 / ECLK PE6 / MODB 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PB1 / D1 PB3 / D3 PB5 / D5 PB7 / D7 PA1 / D9 PA3 / D11 PA5 / D13 PA7 / D15 PK1 / XA15 PK3 / XA17 PK5 / XA19 PK7 / ECS* PL1 PL3 PL5 GND PE1 / IRQ* PE3 / LSTRB* PE5 / MODA PE7 17 Notes: 1) PA0-7 and PB0-7 are also the Address and Data Bus in Expanded Modes. 2) PK0-7 also provide Expanded Address signals in Expanded Modes with the MODE EMK bit set. 3) PL0-4 provide Ethernet PHY status signals if enabled. 4) PE2-4 provide Data Bus controls in Expanded Modes. E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 MCU2_GP PORT The MCU2_GP Port provides access to the M9S12NE64 I/O ports G, H, J, S, T and AD. The PG0-6, PH0-7, and PJ0-3 I/O ports are also applied as the EMAC MII signals if enabled. User should not apply these port pins if the EMAC MII expansion is operating. Ports PJ 6 and 7 are also the I2C interface for the EVB EEprom. PB0 / D0 PB2 / D2 PB4 / D4 PB6 / D6 PA0 / D8 PA2 / D10 PA4 / D12 PA6 / D14 PK0 / XA14 PK2 / XA16 PK4 / XA18 PK6 / XCS* PL0 PL2 PL4 PL6 PE0 / XIRQ* PE2 / R/W* PE4 / ECLK PE6 / MODB 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 PB1 / D1 PB3 / D3 PB5 / D5 PB7 / D7 PA1 / D9 PA3 / D11 PA5 / D13 PA7 / D15 PK1 / XA15 PK3 / XA17 PK5 / XA19 PK7 / ECS* PL1 PL3 PL5 GND PE1 / IRQ* PE3 / LSTRB* PE5 / MODA PE7 Notes: 6) PA0-7 and PB0-7 are also the Address and Data Bus in Expanded Modes. 7) PK0-7 also provide Expanded Address signals in Expanded Modes with EMK bit set. 8) PL0-4 provide Ethernet PHY status signals if enabled. 9) PE2-4 provide Data bus controls in Expanded Modes. BDM PORT The BDM port is a 6 pin header compatible with a Motorola Background Debug Mode (BDM) Pod. This allows the connection of a background debugger for software development, programming and debugging in real-time without using HCS12 I/O resources. BGND/MODC 1 2 GND 3 4 RESET* 5 6 +3.3V See the HCS12 Technical Reference Manual for complete documentation of the BDM. 18 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 TROUBLESHOOTING The EVB9S12NE64 is fully tested and operational before shipping. If it fails to function properly, inspect the board for obvious physical damage first. Verify the communications setup as described under GETTING STARTED. The most common problems are improperly configured communications parameters, and attempting to use the wrong COM port. 1. Verify that your communications port is working by substituting a known good serial device or by doing a loop back diagnostic. 2. Verify the power source, ON/OFF switch is ON, Indicators are ON? You should measure a minimum of 9 volts between the GND and +VIN connections on the TB1 power connector with the standard power supply provided. 3. Disconnect all external connections to the board except for COM1 to the PC and the wall plug power supply. 4. If no power indications, verify the fuse FZ1 is not open. If the +VIN supply is good and the fuse is ok, immediately disconnect power from the board. Contact [email protected] by email for instructions and provide board name and problem. 5. Make sure that the RESET line is not being held low or the RESET indicator is not lit. 6. Contact [email protected] by email for further assistance. Provide board name and describe problem. 19 E V B 9 S 1 2 N E 6 4 0 5 / 2 4 / 0 4 TABLE 1: LCD Command and Character Codes Command codes are used for LCD setup and control of character and cursor position. The BUSY flag (bit 7) may be tested before any command updates to verify that any previous command is completed. A read of the command address will return the BUSY flag status and the current display character location address. Command Clear Display, Cursor to Home Cursor to Home Entry Mode: Cursor Decrement, Shift off Cursor Decrement, Shift on Cursor Increment, Shift off Cursor Increment, Shift on Display Control: Display, Cursor, and Cursor Blink off Display on, Cursor and Cursor Blink off Display and Cursor on, Cursor Blink off Display, Cursor, and Cursor Blink on Cursor / Display Shift: (nondestructive move) Cursor shift left Cursor shift right Display shift left Display shift right Display Function (default 2x40 size) Character Generator Ram Address set Display Ram Address and set cursor location Code $01 $02 Delay 1.65ms 1.65ms $04 $05 $06 $07 40us 40us 40us 40us $08 $0C $0E $0F 40us 40us 40us 40us $10 $14 $18 $1C $3C $40-$7F $80-$FF 40us 40us 40us 40us 40us 40us 40us LCD Character Codes $20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C Space ! “ # $ % & ‘ ( ) * + , $2D $2E $2F $30 $31 $32 $33 $34 $35 $36 $37 $38 $39 . / 0 1 2 3 4 5 6 7 8 9 $3A $3B $3C $3D $3E $3F $40 $41 $42 $43 $44 $45 $46 : ; { = } ? Time A B C D E F $47 $48 $49 $4A $4B $4C $4D $4E $4F $50 $51 $52 $53 G H I J K L M N O P Q R S 20 $54 $55 $56 $57 $58 $59 $5A $5B $5C $5D $5E $5F $60 T U V W X Y Z [ Yen ] ^ _ ` $61 $62 $63 $64 $65 $66 $67 $68 $69 $6A $6B $6C $6D A B C D E F G H I J K L M $6E $6F $70 $71 $72 $73 $74 $75 $76 $77 $78 $79 $7A n $7B o $7C p $7D q $7E r $7F s t u v w x y z { | } > <