NSC CGS74B303M

CGS74B303 Octal Divide-by-2 Skew Clock Driver
General Description
Features
These minimum skew clock drivers are designed for high
frequency Clock Generation and Support (CGS) applications. These devices are ideal for duty cycle recovery applications with internal frequency divide-by-2 circuitry. The devices guarantee minimum skew across the outputs of a given device. Skew parameters are also provided as a means
to measure duty cycle requirements as those found in high
speed clocking systems.
Y
Y
Y
Y
Y
Functional Description
Y
The CGS74B303 contains eight flip-flops designed to have
low skew between outputs. The eight outputs (six in-phase
with CLK and two out-of-phase) toggle on successive CLK
pulses. PRE and CLR inputs are provided to set Q and Q
outputs high or low independent of CLK pin.
Logic Diagram
Y
Clock Generation and Support (CGS) Devices ideal for
high frequency signal generation or clock distribution
applications
Fabricated on National’s Advanced Bipolar FASTTM LSl
process
1 ns pin-to-pin output skew
Specification for transition skew to meet duty cycle
requirements
Current sourcing 24 mA and current sinking of 48 mA
Low dynamic power consumption above 20 MHz
Guaranteed 4 kV ESD protection
Connection Diagram
Pin Assignment
SOlC (M)
TL/F/10966 – 1
TL/F/10966 – 3
Pin Description
Truth Table
Pin Names
Description
CLK
Q0 – Q 7
PRE
CLR
Clock Input
Outputs
Preset
Clear
Inputs
Outputs
CLR
PRE
CLK
Q0 –Q5
Q6 –Q7
L
H
L
H
H
H
L
L
H
H
X
X
X
L
H
L*
Q
Q
H
L
L*
Q
Q
u
L
*This state will not persist when CLR/PRE returns to high.
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
FASTTM is a trademark of National Semiconductor Corporation.
C1996 National Semiconductor Corporation
TL/F/10966
RRD-B30M86/Printed in U. S. A.
http://www.national.com
CGS74B303 Octal Divide-by-2 Skew Clock Driver
July 1996
Absolute Maximum Ratings (Note)
Recommended Operating
Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
7.0V
Input Voltage (VI)
7.0V
Operating Free Air Temperature
0§ C to a 70§ C
b 65§ C to a 150§ C
Storage Temperature Range
Typical iJA
Airflow (LFM)
0 225
500
Jedec SOIC (M) Package 118
96
86 § C/W
Supply Voltage (VCC)
4.5V to 5.5V
Input Rise and Fall Times
(0.8V to 2.0V)
Free Air Operating Temperature (TA)
2 ns max
0§ C to 70§ C
NOTE: The Absolute Maximum Ratings are those values
beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The
parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions will
define the conditions for actual device operation.
DC Electrical Characteristics
Over recommended operating conditions unless specified otherwise. All typical values are measured at VCC e 5V, TA e 25§ C.
Symbol
Parameter
VIK
Input Clamp Voltage
VIH
Minimum Input
High Level Voltage
VIL
Maximum Input
Low Level Voltage
VOH
High Level Output Voltage
Conditions
Typ
Max
Unit
b 1.2
V
2.0
V
0.8
IOH e b2 mA, VCC e 4.5V
VCC b 2
IOH e b24 mA, VCC e 4.5V
2.0
VOL
Low Level Output Voltage
VCC e 4.5V, IOL e 48 mA
II
Input Current @ Max
Input Voltage
VCC e 5.5V, VIH e 7V
IIH
High Level Input Current
VCC e 5.5V, VIH e 2.7V
IIL
Low Level Input Current
VCC e 5.5V, VIL e 0.4V
IO
Output Drive Current
VCC e 5.5V, VO e 2.25V
ICC
Supply Current
VCC e 5.5V
CIN
Input Capacitance
VCC e 5V
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Min
VCC e 4.5V, II e b18 mA
V
0.35
b 0.1
b 50
0.5
V
0.1
mA
20
mA
b 0.50
mA
b 150
mA
Outputs High
27
60
mA
Outputs Low
45
60
mA
5
2
V
pF
AC Electrical Characteristics
Over recommended operating conditions unless specified otherwise. All typical values are measured at VCC e 5V, TA e 25§ C.
Symbol
VCC e 4.5V to 5.5V
TA e 0§ C to a 70§ C
CL e 0 pF – 50 pF
RL e 500X
Parameter
Min
Typ
Units
Max
fMAX
Maximum Input Frequency (Note 2)
110
tPLH,
tPHL
Propagation Delay CLKn to On
(Note 2)
MHz
tPLH,
tPHL
Propagation Delay PRE/CLR
tSU
Set Up Time before CLK
5
ns
tW
CLK HI
CLK LO
CLR/PRE
4
4
4
ns
4
8.5
ns
4
11
ns
Extended AC Electrical Characteristics
Over recommended operating conditions unless specified otherwise. All typical values are measured at VCC e 5V, TA e 25§ C.
Symbol
VCC e 4.5V to 5.5V
TA e 0§ C to a 70§ C
CL e 0 pF – 50 pF
RL e 500X
Parameter
Min
Units
Typ
Max
tOSHL Q
Maximum Skew Common Edge
Output-to-Output Variation (Notes 1, 2)
0.5
1.0
ns
tOSLH Q
Maximum Skew Common Edge
Output-to-Output Variation (Notes 1, 2)
0.5
1.0
ns
tOSHL Q
Maximum Skew Common Edge
Output-to-Output Variation
(Notes 1, 2)
0.3
0.75
ns
Maximum Skew Common Edge
Output-to-Output Variation
(Notes 1, 2)
0.3
0.75
ns
tOSLH/HL Q,Q
Maximum Skew Common Edge
Output-to-Output Variation (Notes 1, 2)
1.0
1.6
ns
tPS Q
Maximum Skew Pin (Signal)
Transition Variation (Notes 1, 2)
1.0
ns
trise,
tfall
Rise/Fall Time
(from 0.8V/2.0V to 2.0V/0.8V)
0 pF–30 pF Loads
2.0
2.0
ns
tOSLH Q
1.1
0.9
Note 1: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH) or in opposite directions both
HL and LH (tOST). Parameters tOST and tPS guaranteed by design.
Note 2: This device is sensitive to noise due to the large transient currents which occur during multiple switching of the eight outptus. VCC by-pass capacitor(s),
chip types, must be placed as closely as possible to the VCC pin.
Note 3: Refer to Minimum Skew Parameters Measurement Information Chart for definitions of each skew specification.
Note 4: All input pulses are from 3.5V to 0.3V with rise and fall times of 2.0 ns.
Note 5: Load capacitance includes the test jig.
3
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Timing Diagrams
Minimum Skew Divide-by-2 Clock Drivers
TL/F/10966 – 4
TL/F/10966 – 5
Test Circuit
RL is 500X
CL is 50 pF for all prop delays and skew measurements.
CL is 30 pF for trise and tfall measurements.
TL/F/10966 – 6
Ordering Information
Contact NSC Marketing for specific date of availability
TL/F/10966 – 7
http://www.national.com
4
5
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CGS74B303 Octal Divide-by-2 Skew Clock Driver
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (S)
NS Package Number M16A
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