HM62G18256 Series 4M Synchronous Fast Static RAM (256k-word × 18-bit) ADE-203-1144A (Z) Rev. 1.0 Mar. 10, 2000 Description The HM62G18256 is a synchronous fast static RAM organized as 256-kword × 18-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-bump BGA. Note: All power supply and ground pins must be connected for proper operation of the device. Features • • • • • • • • • • • • • Power supply: 3.3 V +10%, –5% Clock frequency: 200 MHz to 250 MHz Internal self-timed late write Byte write control (2 byte write selects, one for each 9-bit) Optional ×36 configuration HSTL compatible I/O Programmable impedance output drivers User selective input trip-point Differential, HSTL clock inputs Asynchronous G output control Asynchronous sleep mode Limited set of boundary scan JTAG IEEE 1149.1 compatible Protocol: Single clock register-register mode HM62G18256 Series Ordering Information Type No. Access time Cycle time Package HM62G18256BP-4 HM62G18256BP-5 2.1 ns 2.5 ns 4.0 ns 5.0 ns 119-bump 1. 27 mm 14 mm × 22 mm BGA (BP-119A) Pin Arrangement 2 HM62G18256 Series Pin Description Name I/O type Descriptions Notes VDD Supply Core power supply VSS Supply Ground VDDQ Supply Output power supply VREF Supply Input reference: provides input reference voltage K Input Clock input. Active high. K Input Clock input. Active low. SS Input Synchronous chip select SWE Input Synchronous write enable SAn Input Synchronous address input n = 0, 1, 2...17 SWEx Input Synchronous byte write enables x = a, b G Input Asynchronous output enable ZZ Input Power down mode select ZQ Input Output impedance control 1 DQxn I/O Synchronous data input/output x = a, b n = 0, 1, 2...8 M1, M2 Input Output protocol mode select TMS Input Boundary scan test mode select TCK Input Boundary scan test clock TDI Input Boundary scan test data input TDO Output Boundary scan test data output NC — No connection M1 M2 Protocol Notes VSS VDD Synchronous register to register operation 2 Notes: 1. ZQ is to be connected to VSS via a resistance RQ where 150 Ω ≤ RQ ≤ 300 Ω, if ZQ = VDDQ or open, output buffer impedance will be maximum. A case of minimum impedance, it needs to connect over 120 Ω between ZQ and VSS. 2. There is 1 protocol with mode pin. Mode control pins (M1, M2) are to be tied either VDD or VSS respectively. The state of the Mode control inputs must be set before power-up and must not change during device operation. Mode control inputs are not standard inputs and may not meet VIH or VIL specification. This SRAM is tested only in the synchronous register to register operation. 3 HM62G18256 Series Block Diagram 4 HM62G18256 Series Operation Table ZZ SS G SWE SWEa SWEb K K Operation DQ (n) DQ (n + 1) H × × × × × × × sleep mode High-Z High-Z L H × × × × L-H H-L Dead (not selected) × High-Z L × H × × × × × Dead (Dummy read) High-Z High-Z L L L H × × L-H H-L Read × Dout (a,b)0-8 L L × L L L L-H H-L Write a, b byte High-Z Din (a,b)0-8 L L × L L H L-H H-L Write a byte High-Z Din (a)0-8 L L × L H L L-H H-L Write b byte High-Z Din (b)0-8 Notes: 1. × means don’t care for synchronous inputs, and H or L for asynchronous inputs. 2. SWE, SS, SWEa to SWEb, SA are sampled at the rising edge of K clock. 3. Although differential clock operation is implied, this SRAM will operate properly with one clock phase (either K or K) tied to VREF. Under such single-ended clock operation, all parameters specified within this document will be met. 5 HM62G18256 Series Absolute Maximum Ratings Parameter Symbol Value Unit Notes Input voltage on any pin VIN –0.5 to VDDQ + 0.5 V 1, 4 Core supply voltage VDD –0.5 to 3.9 V 1 Output supply voltage VDDQ –0.5 to 2.2 V 1, 4 Operating temperature TOPR 0 to 70 °C Storage temperature TSTG –55 to 125 °C Junction temperature Tj 110 °C Output short–circuit current IOUT 25 mA Latch up current ILI 200 mA Package junction to case thermal resistance θJC 2 °C/W 5, 7 Package junction to ball thermal resistance θJB 5 °C/W 6, 7 Notes: 1. All voltage is referred to VSS. 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The supply voltage application sequence need to be powered up in the following manner: VSS, VDD, VDDQ, VREF then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 3.9 V, whatever the instantaneous value of VDDQ. 5. θJC is measured at the center of mold surface in fluorocarbon (See Figure “Definition of Measurement”). 6. θJB is measured on the center ball pad after removing the ball in fluorocarbon (See Figure “Definition of Measurement”). 7. These thermal resistance values have error of ± 5°C/W. Definition of Measurement 6 HM62G18256 Series Note: The following the DC and AC specifications shown in the Tables, this device is tested under the minimum transverse air flow exceeding 500 linear feet per minute. DC Operating Conditions (Ta = 0 to 70°C [Tj max = 110°C]) Parameter Symbol Min Typ Max Unit Notes Supply voltage (Core) VDD 3.135 3.30 3.63 V Supply voltage (I/O) VDDQ 1.4 1.5 1.6 V Supply voltage VSS 0 0 0 V Input reference voltage (I/O) VREF 0.65 0.75 0.90 V 1 Input high voltage VIH VREF + 0.1 — VDDQ + 0.3 V 4 Input low voltage VIL –0.5 — VREF – 0.1 V 4 Clock differential voltage VDIF 0.1 — VDDQ + 0.3 V 2, 3 Clock common mode voltage VCM 0.55 — 0.90 V 3 Notes: 1. 2. 3. 4. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF. Minimum differential input voltage required for differential input clock operation. See following figure. VREF = 0.75 V (typ). Differential Voltage/Common Mode Voltage 7 HM62G18256 Series DC Characteristics (Ta = 0 to 70°C, [Tj max = 110°C], VDD = 3.3 V +10%, –5%) Parameter Symbol Min Typ Max Unit Notes Input leakage current ILI — — 2 µA 1 Output leakage current ILO — — 5 µA 2 Standby current — — 100 mA 3 VDD operating current, IDD4 excluding output drivers 4 ns cycle — — 700 mA 4 VDD operating current, IDD5 excluding output drivers 5 ns cycle — — 600 mA 4 Quiescent active power IDD2 supply current — — 180 mA 5 Output low voltage VOL VSS — VSS + 0.4 V 6 Output high voltage VOH VDDQ – 0.4 — VDDQ V 6 ZQ pin connect resistance RQ 150 250 300 Ω Output low current IOL (VDDQ/2)/[(RQ/5)–15%] — (VDDQ/2)/[(RQ/5)+15%] mA 7, 9 Output high current IOH (VDDQ/2)/[(RQ/5–4)+15%] — (VDDQ/2)/[(RQ/5–4)–15%] mA 8, 9 ISBZZ Notes: 1. 0 ≤ Vin ≤ VDDQ for all input pins (except VREF, ZQ, M1, M2 pin). 2. 0 ≤ Vout ≤ VDDQ, DQ in High-Z. 3. All inputs (except clock) are held at either VIH or VIL, ZZ is held at VIH, Iout = 0 mA, Spec is guaranteed at 75°C junction temperature. 4. Iout = 0 mA, read 50%/write 50%, VDD = VDD max, VIN = VIH or VIL, Frequency = minimum cycle. 5. Iout = 0 mA, read 50%/write 50%, VDD = VDD max, VIN = VIH or VIL, Frequency = 3 MHz. 6. Minimum impedance push pull output buffer mode, IOH = –6 mA, IOL = 6 mA. 7. Measured at VOL = 1/2 VDDQ. 8. Measured at VOH = 1/2 VDDQ. 9. Output buffer impedance can be programmed by terminating the ZQ pin to VSS through a precision resister (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 150 Ω and 300 Ω. If the status of ZQ pin is open, output impedance is maximum. Maximum impedance occurs with ZQ connected to VDDQ. The impedance update of the output driver occurs when the SRAM is in High-Z. Write and Deselect operations will synchronously switch the SRAM into and out of High-Z, therefore triggering an update. The user may choose to invoke asynchronous G updates by providing a G setup and hold about the K clock to guarantee the proper update. At power-up, the output impedance defaults to minimum impedance. It will take 2048 cycles for the impedance to be completely updated if the programmed impedance is much higher than minimum impedance. 8 HM62G18256 Series Capacitance (Ta = 25°C, f = 1 MHz) Parameter Symbol Min Max Unit Note Input capacitance (SAn, SS, SWE, SWEx) CIN — 4 pF 1 Input capacitance (K, K, G) CCLK — 7 pF 1 Input/Output capacitance (DQxn) CIO — 5 pF 1 Note: 1. This parameter is sampled and not 100% tested. AC Characteristics (Ta = 0 to 70°C, [Tj max = 110°C], VDD = 3.3 V +10%, –5%) Test Conditions • • • • • • Input pulse levels (K, K): VDIF = 0.75 V, VCM = 0.75 V Input timing reference level (K, K): Differential cross point Input pulse levels (except K, K): VIL = 0.25 V, VIH = 1.25 V Input and output timing reference levels (except K, K): VREF = 0.75 V Input rise and fall time: 0.5 ns (10% to 90%) Measurement condition: the minimum impedance push pull output buffer mode, IOH = –6 mA, IOL = 6 mA • Output driver supply voltage: VDDQ = 1.5 V • Output load: See figure 9 HM62G18256 Series Single Differential Clock Register-Register Mode (M1 = VSS, M2 = VDD) HM62G18256 -4 -5 Parameter Symbol Min Max Min Max Unit CK clock cycle time tKHKH 4.0 — 5.0 — ns CK clock high width tKHKL 1.5 — 1.5 — ns CK clock low width tKLKH 1.5 — 1.5 — ns Address setup time tAVKH 0.5 — 0.5 — ns Data setup time tDVKH 0.5 — 0.5 — ns Address hold time tKHAX 0.75 — 1.0 — ns 1 Data hold time tKHDX 0.75 — 1.0 — ns 1 Clock high to output valid tKHQV — 2.1 — 2.5 ns 2 Clock high to output hold tKHQX 0.5 — 0.5 — ns 2 Clock high to output valid (SS control) tKHQX2 — 2.1 — 2.5 ns 2, 5 Clock high to output High-Z tKHQZ — 2.5 — 3.0 ns 2, 3 Output enable low to output Low-Z tGLQX 0.5 — 0.5 — ns 2, 5 Output enable low to output valid tGLQV — 2.5 — 2.5 ns 2, 3 Output enable low to output High-Z tGHQZ — 2.5 — 2.5 ns 2, 3 Sleep mode recovery time tZZR 10.0 — 10.0 — ns 6 Sleep mode enable time tZZE — 10.0 — 10.0 ns 2, 3, 6 Notes: 1. 2. 3. 4. 5. 6. 10 Notes Guaranteed by design. Refer to the Test Conditions. Transitions are measured at start point of output high impedance from output low impedance. Output driver impedance updates during High-Z. Transitions are measured ±50 mV from steady state voltage. When ZZ is switching, clock input K must be at same logic levels for reliable operation. HM62G18256 Series Timing Waveforms Read Cycle-1 11 HM62G18256 Series Read Cycle-2 (SS Controlled) 12 HM62G18256 Series Read Cycle-3 (G Controlled) 13 HM62G18256 Series Write Cycle 14 HM62G18256 Series Read-Write Cycle ZZ Control 15 HM62G18256 Series Boundary Scan Test Access Port Operations In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 1990. But does not implement all of the functions required for 1149.1 compliance The HM62Gxx series contains a TAP controller. Instruction register, Boundary scans register, Bypass register and ID register. Test Access Port Pins Symbol I/O Name TCK Test clock TMS Test mode select TDI Test data in TDO Test data out Note: This Device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. To disable the TAP, TCK must be connected to VSS. TDO should be left unconnected. To test Boundary scan, ZZ pin need to be kept below VREF – 0.4 V. TAP DC Operating Conditions (Ta = 0 to 70°C, [Tj max = 110°C]) Parameter Symbol Min Max Unit Notes Boundary scan input high voltage VIH 2.0 VDD + 0.3 V Boundary scan input low voltage VIL –0.5 0.8 V Boundary scan input leakage current ILI –2 2 µA 1 Boundary scan output low voltage VOL — 0.4 V 2 Boundary scan output high voltage VOH 2.4 — V 3 Notes: 1. 0 ≤ Vin ≤ VDD for all logic input pin. 2. IOL = 8 mA. 3. IOH = –8 mA. 16 HM62G18256 Series TAP AC Characteristics (Ta = 0 to 70°C, [Tj max = 110°C]) Parameter Symbol Min Max Unit Test clock cycle time tTHTH 67 — ns Test clock high pulse width tTHTL 30 — ns Test clock low pulse width tTLTH 30 — ns Test mode select setup tMVTH 10 — ns Test mode select hold tTHMX 10 — ns Capture setup tCS 10 — ns 1 Capture hold tCH 10 — ns 1 TDI valid to TCK high tDVTH 10 — ns TCK high to TDI don’t care tTHDX 10 — ns TCK low to TDO unknown tTLQX 0 — ns TCK low to TDO valid tTLQV — 20 ns Note: Note 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture. TAP Test Conditions • • • • Input pulse levels: 0 to 3.0 V Input and output timing reference levels: 1.5 V Input rise and fall time: 2 ns (10% to 90%) (typ) Output Load: See figure 17 HM62G18256 Series TAP Controller Timing Diagram Test Access Port Registers Register name Length Symbol Instruction register 3 bits IR [0;2] Bypass register 1 bit BP ID register 32 bits ID [0;31] Boundary scan register 51 bits BS [1;51] 18 Note HM62G18256 Series TAP Controller Instruction Set IR2 IR1 IR0 Instruction Operation 0 0 0 SAMPLE-Z Tristate all data drivers and capture the pad value 0 0 1 IDCODE 0 1 0 SAMPLE-Z 0 1 1 BYPASS 1 0 0 SAMPLE 1 0 1 BYPASS 1 1 0 BYPASS 1 1 1 BYPASS Tristate all data drivers and capture the pad value Note: This Device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command in IEEE 1149.1. 19 HM62G18256 Series Boundary Scan Order Bit No. Bump ID Signal name Bit No. Bump ID Signal name 1 5R M2 27 2B NC 2 6T SA15 28 3A SA6 3 4P SA14 29 3C SA3 4 6R SA10 30 2C SA13 5 5T SA12 31 2A SA0 6 7T ZZ 32 1D DQb0 7 7P DQa0 33 2E DQb1 8 6N DQa1 34 2G DQb2 9 6L DQa2 35 1H DQb3 10 7K DQa3 36 3G SWEb 11 5L SWEa 37 4D ZQ 12 4L K 38 4E SS 13 4K K 39 4G NC 14 4F G 40 4H NC 15 6H DQa8 41 4M SWE 16 7G DQa7 42 2K DQb8 17 6F DQa6 43 1L DQb7 18 7E DQa5 44 2M DQb6 19 6D DQa4 45 1N DQb5 20 6A SA2 46 2P DQb4 21 6C SA1 47 3T SA11 22 5C SA5 48 2R SA9 23 5A SA4 49 4N SA16 24 6B NC 50 2T SA17 25 5B SA8 51 3R M1 26 3B SA7 Notes: 1. Bit number1 is the first scan bit to exit the chip. 2. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register by a “Place Holder”. Placeholder registers are internally connected to VSS. 3. In Boundary scan mode, differential input K and K are referred to each other and must be at opposite logic levels for reliable operation. 4. ZZ must remain at VIL during boundary scan. 5. In boundary scan mode, ZQ must be driven to VDDQ or VSS supply rail to ensure consistent results. 6. M1 and M2 must be driven to VDD or VSS supply rail to ensure consistent results. 20 HM62G18256 Series ID register TAP Controller State Diagram 21 HM62G18256 Series Package Dimensions HM62G18256BP Series (BP-119A) 22 HM62G18256 Series Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. 23 HM62G18256 Series Revision Record Rev. Date Contents of Modification Drawn by Approved by 0.0 Jan. 10, 2000 Initial issue M. Ikeda S. Nakazato 1.0 Mar. 10, 2000 DC Characteristics RQ max: 350 Ω to 300 Ω IOH min: (VDDQ/2)/[(RQ/5)+15%] mA to (VDDQ/2)/[(RQ/5–4)+15%] mA IOH max: (VDDQ/2)/[(RQ/5)–15%] mA to (VDDQ/2)/[(RQ/5–4)–15%] mA 24