RENESAS HM64YGB36100

HM64YGB36100 Series
32M Synchronous Late Write Fast Static RAM
(1-Mword × 36-bit)
REJ03C0271-0100
(Previous ADE-203-1374 (Z) Rev. 0.0)
Rev.1.00
Jun.27.2005
Description
The HM64YGB36100 is a synchronous fast static RAM organized as 1-Mword × 36-bit. It has realized high speed
access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most
appropriate for the application which requires high speed, high density memory and wide bit width configuration, such
as cache and buffer memory in system. It is packaged in standard 119-bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
2.5 V ± 5% operation and 1.5 V (VDDQ)
32-Mbit density
Synchronous register to register operation
Internal self-timed late write
Byte write control (4 byte write selects, one for each 9-bit)
Optional ×18 configuration
HSTL compatible I/O
Programmable impedance output drivers
Differential HSTL clock inputs
Asynchronous G output control
Asynchronous sleep mode
FC-BGA 119pin package with SRAM JEDEC standard pinout
Limited set of boundary scan JTAG IEEE 1149.1 compatible
Ordering Information
Type No.
HM64YGB36100BP-33
Organization
1M × 36
Access time
3.3 ns
Package
119-bump 1.27 mm
14 mm × 22 mm BGA
PRBG0119DC-A (BP-119F)
Note: HM: Hitachi Memory prefix, 64: External Cache SRAM, Y: VDD = 2.5 V, G: Late Write SRAM, B: VDDQ = 1.5 V
Rev.1.00 Jun 27, 2005 page 1 of 19
1.6 ns
Cycle time
HM64YGB36100 Series
Pin Arrangement
1
2
3
4
A
VDDQ
SA14
SA13
NC
B
NC
SA15
SA12
SA20
5
6
7
SA6
SA7
VDDQ
SA5
SA9
NC
C
NC
SA16
SA11
VDD
SA4
SA8
NC
D
DQc7
DQc8
VSS
ZQ
VSS
DQb8
DQb7
E
DQc5
DQc6
VSS
SS
VSS
DQb6
DQb5
F
VDDQ
DQc4
VSS
G
VSS
DQb4
VDDQ
G
DQc3
DQc2
SWEc
NC
SWEb
DQb2
DQb3
H
DQc1
DQc0
VSS
NC
VSS
DQb0
DQb1
J
VDDQ
VDD
VREF
VDD
VREF
VDD
VDDQ
K
DQd1
DQd0
VSS
K
VSS
DQa0
DQa1
L
DQd3
DQd2
SWEd
K
SWEa
DQa2
DQa3
M
VDDQ
DQd4
VSS
SWE
VSS
DQa4
VDDQ
N
DQd5
DQd6
VSS
SA17
VSS
DQa6
DQa5
P
DQd7
DQd8
VSS
SA19
VSS
DQa8
DQa7
R
NC
SA10
M1
VDD
M2
SA1
NC
T
NC
NC
SA18
SA3
SA2
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
(Top view)
Block Diagram
SA1 to SA20
Read
add. reg.
Write
add. reg.
1
Memory array
0
1M × 36
SA1 to SA20
compare
Match0
SWEx
(x: a to d)
SS
SWE
SWEx
1st reg.
SWEx
2nd reg.
Byte write
control
0
1
Din
reg.
Output
reg.
SS
reg.
SWE
reg.
Output enable
K
G
ZQ
Rev.1.00 Jun 27, 2005 page 2 of 19
Impedance
control
DQxn
(x: a to d,
n: 0 to 8)
HM64YGB36100 Series
Pin Descriptions
Name
VDD
VSS
VDDQ
VREF
K
K
SS
SWE
SAn
SWEx
G
ZZ
ZQ
DQxn
I/O type
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Descriptions
Core power supply
Ground
Output power supply
Input reference, provides input reference voltage
Clock input, active high
Clock input, active low
Synchronous chip select
Synchronous write enable
Synchronous address input
Synchronous byte write enables
Asynchronous output enable
Power down mode select
Output impedance control
Synchronous data input/output
M1, M2
TMS
TCK
TDI
TDO
NC
Input
Input
Input
Input
Output

Output protocol mode select
Boundary scan test mode select
Boundary scan test clock
Boundary scan test data input
Boundary scan test data output
No connection
Notes
n: 1 to 20
x: a to d
1
x: a to d
n: 0 to 8
M1
M2
Protocol
Notes
VSS
VDD
Synchronous register to register operation
2
Notes: 1. ZQ is to be connected to VSS via a resistance RQ where 175 Ω ≤ RQ ≤ 300 Ω. If ZQ = VDDQ or open, output
buffer impedance will be maximum.
2. Mode control input pins M1 and M2 are set at power-up and will not change the states during the SRAM
operates.
This SRAM supports only single clock, pipelined read protocol.
Other settings are not applicable.
Mode control pin M2 can be set to VDDQ instead of VDD.
Rev.1.00 Jun 27, 2005 page 3 of 19
HM64YGB36100 Series
Truth Table
ZZ
H
SS
×
G
×
SWE
×
SWEa
×
SWEb
×
SWEc
×
SWEd
×
K
×
K
×
L
H
×
×
×
×
×
×
L-H
H-L
L
×
H
H
×
×
×
×
×
×
L
L
L
H
×
×
×
×
L-H
H-L
L
L
×
L
L
L
L
L
L-H
H-L
L
L
×
L
H
L
L
L
L-H
H-L
L
L
×
L
L
H
L
L
L-H
H-L
L
L
×
L
L
L
H
L
L-H
H-L
L
L
×
L
L
L
L
H
L-H
H-L
L
L
×
L
H
H
L
L
L-H
H-L
L
L
×
L
L
H
H
L
L-H
H-L
L
L
×
L
L
L
H
H
L-H
H-L
L
L
×
L
H
L
L
H
L-H
H-L
L
L
×
L
H
H
H
L
L-H
H-L
L
L
×
L
H
H
L
H
L-H
H-L
L
L
×
L
H
L
H
H
L-H
H-L
L
L
×
L
L
H
H
H
L-H
H-L
Operation
Sleep
mode
Dead
(not
selected)
Dead
(dummy
read)
Read
Write
a, b, c, d
byte
Write
b, c, d
byte
Write
a, c, d
byte
Write
a, b, d
byte
Write
a, b, c
byte
Write
c, d byte
Write
a, d byte
Write
a, b byte
Write
b, c byte
Write
d byte
Write
c byte
Write
b byte
Write
a byte
Notes: 1. H: VIH, L: VIL, ×: VIH or VIL
2. SWE, SS, SWEa to SWEd and SA are sampled at the rising edge of K clock.
Rev.1.00 Jun 27, 2005 page 4 of 19
DQ (n)
High-Z
DQ (n+1)
High-Z
×
High-Z
High-Z
×
×
DOUT
(a, b, c, d)
0 to 8
DIN
(a, b, c, d)
0 to 8
DIN
(b, c, d)
0 to 8
DIN
(a, c, d)
0 to 8
DIN
(a, b, d)
0 to 8
DIN
(a, b, c)
0 to 8
DIN (c, d)
0 to 8
DIN (a, d)
0 to 8
DIN (a, b)
0 to 8
DIN (b, c)
0 to 8
DIN (d)
0 to 8
DIN (c)
0 to 8
DIN (b)
0 to 8
DIN (a)
0 to 8
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
HM64YGB36100 Series
Programmable Impedance Output Drivers
Output buffer impedance can be programmed by terminating the ZQ pin to VSS through a precision resistor (RQ). The
value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching
with a tolerance of 15% is 250 Ω typical. If the status of ZQ pin is open, output impedance is maximum value.
Maximum impedance also occurs with ZQ connected to VDDQ. The impedance update of the output driver occurs when
the SRAM is in high-Z. Write and deselect operations will synchronously switch the SRAM into and out of high-Z,
therefore will trigger an update. At power up, the output buffer is in high-Z. It will take 4,096 cycles for the impedance
to be completely updated.
Absolute Maximum Ratings
Parameter
Symbol
Rating
−0.5 to VDDQ + 0.5
−0.5 to +3.13
−0.5 to +2.1
0 to +85
−55 to +125
25
200
6.5
12
Unit
Notes
1, 4
1
1, 4
Input voltage on any pin
VIN
V
Core supply voltage
VDD
V
Output supply voltage
VDDQ
V
Operating temperature
TOPR
°C
Storage temperature
TSTG
°C
Output short-circuit current
IOUT
mA
Latch up current
ILI
mA
Package junction to top thermal resistance
θJ-top
°C/W 5
Package junction to board thermal resistance
θJ-board
°C/W 5
Notes: 1. All voltage is referenced to VSS.
2. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
should be restricted the operation conditions. Exposure to higher voltages than recommended voltages for
extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the
tables after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN.
Remember, according to the absolute maximum ratings table, VDDQ is not to exceed 2.1 V, whatever the
instantaneous value of VDDQ.
5. See figure below.
θJ-top
θJ-board
Thermocouple
Thermo grease
Teflon block
Thermocouple
SRAM
Water
Cold plate
Water
SRAM
Water
Teflon block
Rev.1.00 Jun 27, 2005 page 5 of 19
JEDEC/2S2P BGA
Thermal board
Thermo grease
Water
Cold plate
JEDEC/2S2P
Thermal board
BGA
HM64YGB36100 Series
Note: The following DC and AC specifications shown in the tables, this device is tested under the minimum transverse
air flow exceeding 500 linear feet per minute.
Recommended DC Operating Conditions
(Ta = 0 to +85°C)
Parameter
Symbol
Min
Typ
Max
Power supply voltage: core
VDD
2.38
2.50
2.63
Power supply voltage: I/O
VDDQ
1.40
1.50
1.60
Input reference voltage: I/O
VREF
0.60
0.75
0.90
Input high voltage
VIH
VREF + 0.10 
VDDQ + 0.30
Input low voltage
VIL
−0.30

VREF − 0.10
Clock differential voltage
VDIF
0.10

VDDQ + 0.30
Clock common mode voltage
VCM
0.60

0.90
Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF.
2. Minimum differential input voltage required for differential input clock operation.
3. See figure below.
4. VREF = 0.75 V (typ).
Differential Voltage / Common Mode Voltage
VDDQ
VDIF
VCM
VSS
Rev.1.00 Jun 27, 2005 page 6 of 19
Unit
V
V
V
V
V
V
V
Notes
1
4
4
2, 3
3
HM64YGB36100 Series
DC Characteristics
(Ta = 0 to +85°C, VDD = 2.5 V ± 5%)
Parameter
Input leakage current
Output leakage current
Standby current
VDD operating current, excluding output drivers
Quiescent active power supply current
Maximum power dissipation, including output drivers
Symbol
ILI
ILO
ISBZZ
IDD
IDD2
P
Min






Max
2
5
150
550
200
2.3
Unit
µA
µA
mA
mA
mA
W
Notes
1
2
3
4
5
6
Parameter
Symbol
Min
Typ
Max
Unit Notes
Output low voltage
VOL
VSS

VSS + 0.4
V
7
Output high voltage
VOH
VDDQ − 0.4

VDDQ
V
8
ZQ pin connect resistance
RQ

250 
Ω
Output “Low” current
IOL
(VDDQ/2) / {(RQ/5) − 15%}
(VDDQ/2) / {(RQ/5) + 15%}
mA 9, 11
Output “High” current
IOH
(VDDQ/2) / {(RQ/5) + 15%}
(VDDQ/2) / {(RQ/5) − 15%}
mA 10, 11
Notes: 1. 0 ≤ VIN ≤ VDDQ for all input pins (except VREF, ZQ, M1, M2 pin)
2. 0 ≤ VOUT ≤ VDDQ, DQ in high-Z
3. All inputs (except clock) are held at either VIH or VIL, ZZ is held at VIH, IOUT = 0 mA. Specification is
guaranteed at +75°C junction temperature.
4. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = min. cycle
5. IOUT = 0 mA, read 50% / write 50%, VDD = VDD max, frequency = 3 MHz
6. Output drives a 12 pF load and switches every cycle. This parameter should be used by the SRAM designer
to determine electrical and package requirements for the SRAM device.
7. RQ = 250 Ω, IOL = 6.8 mA
8. RQ = 250 Ω, IOH = −6.8 mA
9. Measured at VOL = 1/2 VDDQ
10. Measured at VOH = 1/2 VDDQ
11. The total external capacitance of ZQ pin must be less than 7.5 pF.
Rev.1.00 Jun 27, 2005 page 7 of 19
HM64YGB36100 Series
AC Characteristics
(Ta = 0 to +85°C, VDD = 2.5 V ± 5%)
Single Differential Clock Register-Register Mode
Parameter
Symbol
HM64YGB36100BP
-33
Min
Max







1.6


2.0

2.0
2.0

15.0
Unit
CK clock cycle time
tKHKH
3.3
ns
CK clock high width
tKHKL
1.3
ns
CK clock low width
tKLKH
1.3
ns
Address setup time
tAVKH
0.3
ns
Data setup time
tDVKH
0.3
ns
Address hold time
tKHAX
0.6
ns
Data hold time
tKHDX
0.6
ns
Clock high to output valid
tKHQV

ns
Clock high to output hold
tKHQX
0.65
ns
Clock high to output low-Z (SS control)
tKHQX2
0.65
ns
Clock high to output high-Z
tKHQZ
0.65
ns
Output enable low to output low-Z
tGLQX
0.1
ns
Output enable low to output valid
tGLQV

ns
Output enable high to output high-Z
tGHQZ

ns
Sleep mode recovery time
tZZR
20.0
ns
Sleep mode enable time
tZZE

ns
Notes: 1. See figure in ”AC Test Conditions”.
2. Parameters may be guaranteed by design, i.e., without tester guardband.
3. Transitions are measured ±50 mV of output high impedance from output low impedance.
4. Transitions are measured ±50 mV from steady state voltage.
5. When ZZ is switching, clock input K must be at the same logic level for the reliable operation.
6. Minimum value is verified by design and tested without guardband.
Rev.1.00 Jun 27, 2005 page 8 of 19
Notes
2
2
1
1, 6
1, 4, 6
1, 3, 6
1, 4, 6
1, 4
1, 3
5
1, 3, 5
HM64YGB36100 Series
Timing Waveforms
Read Cycle-1
tKHKH
tKHKL
tKLKH
K, K
tAVKH
SA
A1
tKHAX
A2
SS
tAVKH
tKHAX
tAVKH
tKHAX
A3
A4
Q1
Q2
SWE
SWEx
tKHQX
DQ
tKHQV
Read Cycle-2 (SS Controlled)
tKHKH
tKHKL
tKLKH
K, K
tAVKH
SA
A1
tKHAX
A3
A4
tAVKH
tKHAX
tAVKH
tKHAX
SS
SWE
SWEx
tKHQZ
DQ
Rev.1.00 Jun 27, 2005 page 9 of 19
Q0
Q1
tKHQX2
Q3
HM64YGB36100 Series
Read Cycle-3 (G Controlled)
tKHKH
tKHKL
tKLKH
K, K
tAVKH
SA
A1
tKHAX
A2
A3
tAVKH
tKHAX
tAVKH
tKHAX
A4
SS
SWE
SWEx
G
tGHQZ
DQ
Q0
tGLQX
Q1
Q3
tGLQV
Read operation
During read cycle, the address is registered during the first rising clock edge, the internal array is read between this
first edge and second edge, and data is captured in the output register.
Rev.1.00 Jun 27, 2005 page 10 of 19
HM64YGB36100 Series
Write Cycle
tKHKH
tKHKL
tKLKH
K, K
tAVKH
SA
A1
tKHAX
A2
tAVKH
tKHAX
tAVKH
tKHAX
tAVKH
tKHAX
A3
A4
D2
D3
SS
SWE
SWEx
G
tDVKH
DQ
D0
tKHDX
D1
Notes: ZZ = VIL, x: a to d
Write operation
During write cycle, the write data follows the write address by one cycle. All N bits of address are presented during
the same cycle. Any subsequent read to this address should get the latest data. Because in the actual implementation
the data will be written into the SRAM array only after the next write address is received, a one-entry buffer is
needed to hold the write data and to allow bypassing of data from the write buffer to the output if there is a read of
the same address.
Rev.1.00 Jun 27, 2005 page 11 of 19
HM64YGB36100 Series
Read-Write Cycle
READ
tKHKH
READ
(G control)
tKHKL tKLKH
WRITE
tAVKH
tKHAX
READ
DEAD
WRITE
(SS control)
K, K
SA
A1
A3
A4
tAVKH
tKHAX
tAVKH
tKHAX
tAVKH
tKHAX
A6
A7
Q4
Q6
SS
SWE
SWEx
G
tGHQZ tDVKH tKHDX
tKHQV
DQ
Q0
Q1
tGLQV
D3
tGLQX
tKHQX
tKHQZ
Notes: ZZ = VIL, x: a to d
ZZ Control
tKHKL tKLKH
tKHKH
K, K
tAVKH
SA
SS
tKHAX
A1
tAVKH
tKHAX
tAVKH
tKHAX
SWE
SWEx
ZZ Sleep active
Sleep off
Sleep active
Q1
DQ
tZZR
tZZE
Notes: G = VIL, x: a to d
When ZZ is switching, clock input K must be at the same logic level for the reliable operation.
Rev.1.00 Jun 27, 2005 page 12 of 19
HM64YGB36100 Series
Input Capacitance
(VDD = 2.5 V, VDDQ = 1.5 V, Ta = +25°C, f = 1 MHz)
Parameter
Symbol
Min Max Unit
Pin name
Input capacitance
CIN

4
pF
SAn, SS, SWE, SWEx
Clock input capacitance
CCLK

5
pF
K, K
I/O capacitance
CIO

5
pF
DQxn
Notes: 1. This parameter is sampled and not 100% tested.
2. Exclude G
3. Connect pins to GND, except VDD, VDDQ, and the measured pin.
Notes
1, 3
1, 2, 3
1, 3
AC Test Conditions
Parameter
Symbol
Input and output timing reference levels
VREF
Input signal amplitude
VIL, VIH
Input rise / fall time
tr, tf
Clock input timing reference level
VDIF to clock
VCM to clock
Output loading conditions
Note: Parameters are tested with RQ = 250 Ω and VDDQ = 1.5 V.
Conditions
0.75
0.25 to 1.25
0.5 (10% to 90%)
Differential cross point
0.75
0.75
See figure below
Unit
V
V
ns
V
V
Output Loading Conditions
16.7 Ω
0.75 V
16.7 Ω
DQ
50 Ω
50 Ω
5 pF
16.7 Ω
50 Ω
50 Ω
0.75 V
5 pF
0.75 V
Rev.1.00 Jun 27, 2005 page 13 of 19
Note
HM64YGB36100 Series
Boundary Scan Test Access Port Operations
Overview
In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary scan test access
port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 - 1990. But does not implement all
of the functions required for 1149.1 compliance. The HM64YGB series contains a TAP controller. Instruction register,
boundary scans register, bypass register and ID register.
Test Access Port Pins
Symbol I/O
Name
TCK
Test clock
TMS
Test mode select
TDI
Test data in
TDO
Test data out
Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1.
To disable the TAP, TCK must be connected to VSS. TDO should be left unconnected.
To test boundary scan, the ZZ pin needs to be kept below VREF − 0.4 V.
TAP DC Operating Characteristics
(Ta = 0 to +85°C)
Parameter
Boundary scan input high voltage
Boundary scan input low voltage
Boundary scan input leakage current
Boundary scan output low voltage
Boundary scan output high voltage
Notes: 1. 0 ≤ VIN ≤ 3.6 V for all logic input pin
2. IOL = 2 mA at VDD = 2.5 V.
3. IOH = −2 mA at VDD = 2.5 V.
Rev.1.00 Jun 27, 2005 page 14 of 19
Symbol
VIH
VIL
ILI
VOL
VOH
Min
1.4 V
−0.3 V
−10 µA

2.1 V
Max
3.6 V
0.8 V
+10 µA
0.2 V

Notes
1
2
3
HM64YGB36100 Series
TAP AC Operating Characteristics
(Ta = 0 to +85°C)
Parameter
Symbol
Min
Max
Unit
Test clock cycle time
tTHTH
67

ns
Test clock high pulse width
tTHTL
30

ns
Test clock low pulse width
tTLTH
30

ns
Test mode select setup
tMVTH
10

ns
Test mode select hold
tTHMX
10

ns
Capture setup
tCS
10

ns
Capture hold
tCH
10

ns
TDI valid to TCK high
tDVTH
10

ns
TCK high to TDI don’t care
tTHDX
10

ns
TCK low to TDO unknown
tTLQX
0

ns
TCK low to TDO valid
tTLQV

20
ns
Note: 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
Note
1
1
TAP AC Test Conditions
(VDD = 2.5 V)
Temperature
0°C ≤ Ta ≤ +85°C
Input timing measurement reference level
1.1 V
Input pulse levels
0 to 2.5 V
Input rise/fall time
1.5 ns typical (10% to 90%)
Output timing measurement reference level
1.25 V
Test load termination supply voltage (VT)
1.25 V
Output load
See figure below
Boundary Scan AC Test Load
VT
DUT
50 Ω
Z0 = 50 Ω
TDO
Rev.1.00 Jun 27, 2005 page 15 of 19
HM64YGB36100 Series
TAP Controller Timing Diagram
tTHTH
tTHTL tTLTH
TCK
tMVTH tTHMX
TMS
tDVTH tTHDX
TDI
tTLQV
TDO
tCS tCH
tTLQX
RAM
ADDRESS
Test Access Port Registers
Register name
Instruction register
Bypass register
ID register
Boundary scan register
Length
3 bits
1 bit
32 bits
70 bits
Symbol
IR [2:0]
BP
ID [31:0]
BS [70:1]
Note
TAP Controller Instruction Set
IR2
0
0
0
0
1
1
1
1
Note:
IR1 IR0
Instruction
Operation
0
0
SAMPLE-Z
Tristate all data drivers and capture the pad value
0
1
IDCODE
1
0
SAMPLE-Z
Tristate all data drivers and capture the pad value
1
1
BYPASS
0
0
SAMPLE
0
1
BYPASS
1
0
PRIVATE
Do not use. They are reserved for vendor use only
1
1
BYPASS
This device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command in IEEE
1149.1.
Rev.1.00 Jun 27, 2005 page 16 of 19
HM64YGB36100 Series
Boundary Scan Order (HM64YGB36100)
Bit #
Bump ID
Signal name
Bit #
Bump ID
Signal name
1
5R
M2
36
3B
SA12
2
4P
SA19
37
2B
SA15
3
4T
SA3
38
3A
SA13
4
6R
SA1
39
3C
SA11
5
5T
SA2
40
2C
SA16
6
7T
ZZ
41
2A
SA14
7
6P
DQa8
42
2D
DQc8
8
7P
DQa7
43
1D
DQc7
9
6N
DQa6
44
2E
DQc6
10
7N
DQa5
45
1E
DQc5
11
6M
DQa4
46
2F
DQc4
12
6L
DQa2
47
2G
DQc2
13
7L
DQa3
48
1G
DQc3
14
6K
DQa0
49
2H
DQc0
15
7K
DQa1
50
1H
DQc1
16
5L
SWEa
51
3G
SWEc
17
4L
K
52
4D
ZQ
18
4K
K
53
4E
SS
19
4F
G
54
4B
SA20
20
5G
SWEb
55
4H
NC
21
7H
DQb1
56
4M
SWE
22
6H
DQb0
57
3L
SWEd
23
7G
DQb3
58
1K
DQd1
24
6G
DQb2
59
2K
DQd0
25
6F
DQb4
60
1L
DQd3
26
7E
DQb5
61
2L
DQd2
27
6E
DQb6
62
2M
DQd4
28
7D
DQb7
63
1N
DQd5
29
6D
DQb8
64
2N
DQd6
30
6A
SA7
65
1P
DQd7
31
6C
SA8
66
2P
DQd8
32
5C
SA4
67
3T
SA18
33
5A
SA6
68
2R
SA10
34
6B
SA9
69
4N
SA17
35
5B
SA5
70
3R
M1
Notes: 1. Bit#1 is the first scan bit to exit the chip.
2. The NC pads listed in this table are indeed no connects, but are represented in the boundary scan register
by a “Place Holder”. Place holder registers are internally connected to VSS.
3. In boundary scan mode, differential input K and K are referenced to each other and must be at the opposite
logic levels for the reliable operation.
4. ZZ must remain VIL during boundary scan.
5. In boundary scan mode, ZQ must be driven to VDDQ or VSS supply rail to ensure consistent results.
6. M1 and M2 must be driven to VDD, VDDQ or VSS supply rail to ensure consistent results.
Rev.1.00 Jun 27, 2005 page 17 of 19
HM64YGB36100 Series
ID Register
Revision
number
(31:28)
0000
Part
HM64YGB36100
Vendor
definition
(17:12)
xxxxxx
Device density
and configuration
(27:18)
0100000100
Vendor JEDEC
code (11:1)
00000000111
Start
bit (0)
1
TAP Controller State Diagram
1
Test-logicreset
0
0
Run-test/
idle
1
1
SelectDR-scan
0
1
0
1
Capture-DR
Capture-IR
0
0
Shift-DR
Shift-IR
0
1
1
0
0
Pause-DR
0
Pause-IR
1
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
Note:
1
Exit1-IR
0
1
0
1
Exit1-DR
0
1
SelectIR-scan
Update-IR
0
1
0
The value adjacent to each state transition in this figure represents the signal present at TMS at the
time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-logic-reset when TMS is held high
for at least five rising edges of TCK.
Rev.1.00 Jun 27, 2005 page 18 of 19
HM64YGB36100 Series
Package Dimensions
HM64YGB36100BP Series (PRBG0119DC-A / Previous Code: BP-119F)
JEITA Package Code
P-BGA119-14x22-1.27
RENESAS Code
PRBG0119DC-A
Previous Code
BP-119F
MASS[Typ.]
1.0g
D
A
B
E
INDEX
×4
v
y1 S
y
A1
A
S
S
e
e
U
T
R
Reference
Symbol
P
N
Dimension in Millimeters
Min
Nom
D
14.00
L
E
22.00
K
v
M
J
Max
0.20
w
H
G
A
1.78
1.98
2.18
F
A1
0.58
0.66
0.74
0.84
0.90
E
e
1.27
D
0.96
C
b
B
x
0.30
A
y
0.20
y1
0.35
1
2
3
4
φ b
5
6
7
φ× M S A B
φ0.15 M S
SD
SE
ZD
ZE
Rev.1.00 Jun 27, 2005 page 19 of 19
Revision History
Rev.
0.0
1.00
Date
Dec. 5, 2002
Jun. 27, 2005
HM64YGB36100 Series Data Sheet
Description
Summary
Page

Initial issue
Change format issued by Renesas Technology Corp.

Ordering Information
1
Addition of Renesas package codes
Change of
5
Programmable Impedance
Output Drivers
Package Dimensions
19
Addition of Renesas package codes
Changed to Renesas formats
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