HY51V65400HG 16M x 4Bit Fast Page DRAM PRELIMINARY DESCRIPTION This familiy is a 64Mbit dynamic RAM organized 16,777,216 x 4 bit configuration with Fast Page mode CMOS DRAMs. Fage page mode offers high speed of random access memory within the same row. The advanced circuit and process allow this device to achieve high performance and low power dissipation. features are access time(45ns or 50ns) and refresh cycle(4K ref ) and power consumption (Normal or low power with self refresh). Advanced CMOS process as well as circuit techniques for wide operating margins allow this device to achieve high speed access and high reliability FEATURES • • • • • • • Fast page mode operation Read-modify-write capability Multi-bit parallel test capability LVTTL(3.3V) compatible inputs and outputs /RAS only, CAS-before-/RAS, Hidden Refresh • • • • JEDEC standard pinout 32pin plastic SOJ/TSOP-II(400mil) Single power supply of 3.3V +/- 10% Early write or output enable controlled write Fast access time and cycle time Part No tRAC tAA tCAC tRC tHPC HY51V65400HG-45 45ns 23ns 12ns 74ns 17ns HY51V65400HG-5 50ns 25ns 13ns 84ns 20ns HY51V65400HG-6 60ns 30ns 15ns 104ns 25ns Power dissipation Active Standby • 45ns 50ns 60ns 468mW 432mW 396mW Refresh cycle Part No Ref Normal HY51V65400HG 4K 64ms 1.8mW(CMOS level Max) 0.72mW (L-version : Max) ORDERING INFORMATION Part Number Access Time Package HY51V65400HGJ-45 HY51V65400HGJ-5 HY51V65400HGJ-6 45ns 50ns 60ns 400mil 32pin SOJ HY51V65400HGT-45 HY51V65400HGT-5 HY51V65400HGT-6 45ns 50ns 60ns 400mil 32pin TSOP-II This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev.0.1/Apr.01 HY51V65400HG PIN CONFIGURATION VCC 1 32 VSS I/O0 2 31 I/O3 I/O1 3 30 I/O2 NC 4 29 NC NC 5 28 NC NC 6 27 VSS VCC 7 26 CAS WE 8 25 OE RAS 9 24 A12 A0 10 23 A11 A1 11 22 A10 A2 12 21 A9 A3 13 20 A8 A4 14 19 A7 A5 15 18 A6 VCC 16 17 VSS 32 Pin Plastic SOJ / TSOP-II PIN DESCRIPTION Pin Function /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable /OE Output Enable A0-A11 Address Inputs A0-A11 Refresh Address Inputs I/O 0- I/O 3 Data Input / Output Vcc Power (3.3V) Vss Ground NC No connection Rev.0.1/Apr.01 2 HY51V65400HG ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Unit Ambient Temperature TA 0 ~ 70 o C Storage Temperature TSTG -55 ~ 125 o C Voltage on Any Pin relative to Vss VT -0.5 ~ Vcc + 0.5 (Max 4.6V) V Voltage on Vcc relative to Vss Vcc -0.5 ~ 4.6 V Short Circuit Output Current IOUT 50 mA Power Dissipation PT 1 W Note : Operation at above absolute maximum rating can adversely affect device reliability. Recommended DC OPERATING CONDITIONS (TA=0 to 70 oC) Parameter Symbol Min Typ. Max Unit Note Power Supply Voltage Vcc 3.0 3.3 3.6 V 1,2 Power Supply Voltage Vss 0 0 0 V 2 Input High Voltage VIH 2.0 - Vcc + 0.3 V 1 Input Low Voltage VIL -0.3 - 0.8 V 1 Note : All voltages are referenced to Vss 1. 6.0V at pulse width 10ns which is measured at Vcc 2. -0.1V at pulse width 10ns which is measured at Vss Rev.0.1/Apr.01 3 HY51V65400HG DC CHARACTERISTICS (Vcc = 3.3V +/- 10%, TA=0 to 70°C) Symbol Parameter Min Max Unit 2.4 Vcc V 0 0.4 V 45ns - 120 50ns - 110 60ns - 100 - 2 45ns - 190 50ns - 170 60ns - 150 45ns - 110 50ns - 100 60ns - 90 CMOS interface ( /RAS, /UCAS, /LCAS >= Vcc-0.2V, Dout = High-Z) - 0.5 mA Standby current ( L-version) - - uA 45ns - 140 50ns - 130 60ns - 120 VOH Output Level Output Level voltage(Iout= -2mA) VOL Output Level Output Level voltage(Iout=2mA) ICC1 ICC2 ICC3 ICC4 Operating current ( tRC = tRC min) Standby current (TTL interface) Power supply standby current (/RAS, /UCAS,/LCAS=VIH, Dout = High-Z) /RAS only refresh current (tRC= tRC min) Extended data out page mode current (/RAS=VIL, /CAS, Address cycling : tHPC=tHPC min) mA Note 1, 2 mA mA 2 mA 1, 3 ICC5 ICC6 /CAS-before-/RAS refresh current (tRC=tRC min) mA ICC7 Battery back up operating current (standby with CBR) (tRC=31.25us, tRAS=300ns, Dout=High-Z) - 5 mA II(L) Input leakage current, Any input (0V<= Vin<=Vcc) -5 5 uA IO(L) Output leakage current, (Dout is disabled, 0V<= Vout<=Vcc) -5 5 uA Note : 1. Icc depends on output load condition when the device is selected, Icc(max) is specified at the output open condition 2. Address can be changed once or less while RAS=VIL 3. Address can be changed once or less while RAS=VIH Rev.0.1/Apr.01 4 HY51V65400HG CAPACITANCE (Vcc=3.3V +/-10%, TA=25°C) Parameter Symbol Min. Max Unit Note Input capacitance (Address) CI1 - 5 pF 1 Input capacitance (Clocks) CI2 - 5 pF 1 Output capacitance (Data-in, Data-out) CI/O - 7 pF 1, 2 Note : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. /RAS, /CAS = VIH to disable Dout AC CHARACTERISTICS (Vcc=3.3V +/-10%, TA=0~70C, Note 1, 14,15,19) Test Condition • • • Input rise and fall times = 5ns Input timing reference level : VIL/VIH = 0.8/2.4V Output timing reference level : VOL/VOH=0.8/0.2V Output load : 1 TTL gate + CL (100pF) including scope and jig • Read, Write, Read-modify-Write and Refresh Cycles -45 Parameter -50 -60 Symbol Unit Min Max Min Max Min Max Note Random read or write cycle time tRC 80 - 90 - 110 - ns /RAS precharge time tRP 25 - 30 - 40 - ns /CAS precharge time tCP 10 - 10 - 10 - ns /RAS pulse width tRAS 45 10,000 50 10,000 60 10,000 ns /CAS pulse width tCAS 12 10,000 13 10,000 15 10,000 ns Row address set-up time tASR 0 - 0 - 0 - ns Row address hold time tRAH 10 - 10 - 10 - ns Column address set-up time tASC 0 - 0 - 0 - ns Column address hold time tCAH 10 - 10 - 15 - ns /RAS to /CAS delay time tRCD 20 33 20 37 20 45 ns 8 /RAS to Column address delay time tRAD 15 22 15 25 15 30 ns 9 /RAS hold time tRSH 12 - 13 - 15 - ns /CAS hold time tCSH 45 - 50 - 60 - ns /CAS to /RAS precharge time tCRP 5 - 5 - 5 - ns Rev.0.1/Apr.01 5 HY51V65400HG - continued -45 Parameter -50 -60 Symbol Unit Min Max Min Max Min Max Note /OE to Din delay time tODD 12 - 13 - 15 - ns /OE delay time from Din tDZO 0 - 0 - 0 - ns /CAS delay time from Din tDZC 0 - 0 - 0 - ns Transition time ( Rise and Fall) tT 3 50 3 50 3 50 ns 7 Refresh period tREF - 64 - 64 - 64 ms 8K Ref. Unit Note Read Cycles -45 Parameter -50 -60 Symbol Min Max Min Max Min Max Access time from /RAS tRAC - 45 - 50 - 60 ns 2,3,17 Access time from /CAS tCAC - 12 - 13 - 15 ns 3,4 13,17 Access time from column address tAA - 23 - 25 - 30 ns 3,5 13,17 Access time from /OE tOAC - 12 - 13 - 15 ns 3,17 Read command set-up time tRCS 0 - 0 - 0 - ns Read command hold time to /CAS tRCH 0 - 0 - 0 - ns Read command hold time to /RAS tRRH 0 - 0 - 0 - ns Column address to /RAS lead time tRAL 23 - 25 - 30 - ns Column address to /CAS lead time tCAL 23 - 25 - 30 - ns Output buffer turn off delay time from /CAS tOFF 0 12 0 13 0 15 ns 6 Output buffer turn off delay time from /OE tOEZ 0 12 0 13 0 15 ns 6 /CAS to Din delay time tCDD 12 - 13 - 15 - ns /OE pulse width tOEP 12 - 13 - 15 - ns Rev.0.1/Apr.01 6 HY51V65400HG Write Cycles -45 Parameter -50 -60 Symbol Min Max Min Max Min Max Unit Note 10 Write command set-up time tWCS 0 - 0 - 0 - ns Write command hold time tWCH 8 - 10 - 15 - ns Write command pulse width tWP 8 - 10 - 10 - ns Write command to /RAS lead time tRWL 13 - 15 - 15 - ns Write command to /CAS lead time tCWL 12 - 13 - 15 - ns Data-in set-up time tDS 0 - 0 - 0 - ns 11 Data-in hold time tDH 8 - 10 - 15 - ns 11 Unit Note Read-Modify-Write Cycles -45 Parameter -50 -60 Symbol Min Max Min Max Min Max Read-modify-write cycle time tRWC 133 - 133 - 155 - ns /RAS to /WE delay time tRWD 67 - 73 - 85 - ns 10 /CAS to /WE delay time tCWD 32 - 36 - 40 - ns 10 Column address to /WE delay time tAWD 43 - 48 - 55 - ns 10 /OE hold time from /WE tOEH 12 - 13 - 15 - ns Refresh cycles -45 Parameter -50 -60 Symbol Unit Min Max Min Max Min Max /CAS set-up time ( /CAS-before-/RAS Refresh Cycle) tCSR 10 - 10 - 10 - ns /CAS hold time ( /CAS-before-/RAS Refresh Cycle) tCHR 10 - 10 - 10 - ns /RAS precharge to /CAS hold time tRPC 10 - 10 - 10 - ns /CAS precharge time in normal mode tCPN 10 - 10 - 10 - ns Rev.0.1/Apr.01 Note 7 HY51V65400HG Fast Page Mode Cycles -45 Parameter -50 -60 Symbol Unit Min Max Min Max Min Max Note Fast page mode cylce time tPC 31 - 35 - 40 - ns Fast page mode /CAS precharge time tCP 9 - 10 - 10 - ns Fast page mode /RAS pulse width tRASP - 100K - 100K - 100K ns 12 Access time from /CAS precharge tACP - 26 - 30 - 35 ns 3,13,17 /RAS hold time from /CAS precharge tRHCP 28 - 30 - 35 - ns Fast page mode read-modify-write cycle /CAS precharge to /WE delay time tCPW 48 - 50 - 55 - ns 10 Fast page mode read-modify-write cycle time tPRWC 70 - 76 - 85 - ns 10 Unit Note Test Mode Cycle -45 Parameter -50 -60 Symbol Min Max Min Max Min Max Test mode /WE set-up time tWS 0 - 0 - 0 - ns Test mode /WE hold time tWH TBD - 10 - 10 - ns Counter Test Cycles -45 Parameter /CAS precharge time in Counter test cycle Rev 0.1 / Apr. 01 -50 -60 Symbol tCPT Unit Min Max Min Max Min Max TBD - 40 - 40 - ns Note HY51V65400HG Notes : 1. AC measurements assume t T = 5ns 2. Assumes that tRCD<=tRCD(max) and tRAD<=tRAD(max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, tRAC exceeds the value shown 3. Measured with a load circuit equivalent to 1 TTL loads and 100pF. 4. Assumes that tRCD>=tRCD(max) and tRAD <= tRCD(max) 5. Assumes that tRCD<=t RCD(max) and tRAD >= tRAD(max) 6. tOFF(max) defines the time at which the outputs achieve the open circuit condition and is not referenced to output voltage levels 7. VIH(min) and VIL(max) are reference levels for measuring timing of input signals, Also, transition times are measured between V IH and VIL 8. Operation with the tRCD(max) limit insures that tRAC(max) can be met, t RCD(max) is specified as a reference point only : if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 9. Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a reference point only : if tRAD is greater than the specified tRAD(max) limit, then access time is controlled exclusively by tAA. 10. tWCS, tRWD, tCWD, tAWD and tCPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only : If tWCS >=tWCS(min), the cycle is an early write cycle and the data out pin will remain open circuit(high impedance) throughout the entire cycle : If tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min), the cycle is a read-modify-write and the data output will contain data read from the selected cell : if neither of the above sets of conditions is satified, the condition of the data out (at access time) is indeterminate. 11.These parameters are referenced to /CAS leading edge in early write cycles and to /WE leading edge in delayed write or a read modify write cycle 12. tRASP defines /RAS pulse width in fast page mode cycles 13. Access time is determined by the longer of tAA or tCAC ro tACP 14. An initial pause of 100us is required after power up followed by a minimum of eight initialization cycles (/RAS only refresh cycle or /CAS before /RAS refresh cycle) If the internal refresh counter is used, a minimum of eight /CAS before /RAS refresh cycles is required. 15. In delaying write or read-modify-write cycles, /OE must disable output buffer prior to applying data to the device. 16.Test mode operation specified in this data sheet is 2-bit test function controlled by control address bits ----- CA0. This test mode operation can be performed by /WE- and /CAS-before-/RAS(WCBR) refresh cycles. Refresh during test mode operation will be performed by normal read cycles or by refresh cycles. When the state of two test bits accord each other, the condition of the output data is high level. When the state of two test bits do not accord, the condition of the output data is low level. in order to Rev 0.1 / Apr. 01 HY51V65400HG end this test mode operation, perform a /RAS only refresh cylce or a /CAS-before-/RAS refresh cycle 17. In a test mode read cycle, the value of tRAC, tAA, tCAC, tOAC and tACP is delayed for 2ns to 5ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. Rev 0.1 / Apr. 01 HY51V65400HG PACKAGE INFORMATION 400mil 32pin SOJ Dimension Unit: Inches (mm) 0.820(20.83) MIN 0.835(21.21) MAX 0.435(11.06) MIN 0.445(11.31) MAX 0.361(9.17) MIN 0.379(9.63) MAX 0.395(10.03) MIN 0.405(10.29) MAX 0.025(0.64) MIN 0.083(2.10) MIN 0.128(3.25) MIN 0.148(3.75) MAX 0.026(0.67) MIN 0.032(0.81) MAX 0.050(1.27) TYP 0.015(0.38) MIN 0.020(0.50) MAX 400mil 32pin TSOP-II Dimension Unit: Inches (mm) 0.016(0.40) MIN 0.024(0.60) MAX 0.400(0.10) 0.455(11.56) MIN 0.471(11.96) MAX 0 ~ 8 deg. 0.004(0.10) MIN 0.010(0.25) MAX 0.821(20.85) MIN 0.829(21.05) MAX 0.047(1.20) 0.037(0.95) Rev.0.1/Apr.01 0.050(1.27 ) TYP 0.012(0.30) MIN 0.020(0.50) MAX 11