www.fairchildsemi.com LM1851 Ground Fault Interrupter Features • • • • No potentiometer required Direct interface to SCR Supply voltage derived from AC line—26V shunt Adjustable sensitivity • • • • Grounded neutral fault detection Meets UL943 standards 450 mA quiescent current Ideal for 120V or 220V systems Description The LM1851 is a controller for AC outlet ground fault interrupters. These devices detect hazardous grounding conditions (example: a pool of water and electrical equipment connected to opposite phases of the AC line) in consumer and industrial environments. The output of the IC triggers an external SCR, which in turn opens a relay circuit breaker to prevent a harmful or lethal shock. to line noise. A special feature is found in circuitry that rapidly resets the integrating timing capacitor in the event that noise pulses introduce unwanted charging currents. Also, flip-flop is included that ensures firing of even a slow circuit breaker relay on either half-cycle of the line voltage when external full wave rectification is used. The application circuit can be configured to detect both normal faults (hot wire to ground) and grounded neutral faults. Full advantage of the U.S. UL943 timing specification is taken to ensure maximum immunity to false triggering due Block Diagram Timing Capacitor +VS Sensitivity Set Resistor Sense Amplifier Output ITH ITH = ITH for IF > 0 3ITH for IF = 0 I2 D3 Q2 SCR Trigger IF Latch Q3 Q1 D1 Q5 +VS A1 Q4 D2 IF 10V Ground 65-1851-01 Inverting Input Non-Inverting Input Rev. 1.0.0 LM1851 PRODUCT SPECIFICATION Functional Description present, then I1 discharges CT with a current equal to 3 ITH, where ITH is the value of current set by the external RSET resistor. If fault signals are present at the input of A1 (which is held at virtual ground, +10V), one of the two current mirrors in the feedback path of A1 (Q4 and Q5) will become active, depending on which half-cycle the fault occurs. This action will raise the voltage at VS, switching I1 to a value equal to ITH, and reducing the discharge rate of CT to better allow fault currents to charge it. The voltage at the supply pin is clamped to +26V by the internal shunt regulator D3. This shunt regulator also generates an artificial ground voltage for the noninverting input of A1 (shown as a +10V source). A1, Q1, and Q2 act a a current mirror for fault current signals (which are derived from an external transformer). When a fault signal is present, the mirrored current charges the external timing capacitor until its voltage exceeds the latch trigger threshold (typically 17.5V). When then this threshold is exceeded, the latch engages and Q3 turns off, allowing I2 to drive the SCR connected to pin 1. Notice that ITH discharges CT during both half-cycles of the line, while IF only charges CT during the half-cycle in which IF exits pin 2 (since Q1 will only carry fault current in one direction). Thus, during one half-cycle, IF-ITH charges CT, while during the other half-cycle ITH discharges it. Extra Circuitry in the feedback path of A1 works with the switched current source I1 to remove any charge on CT induced by noise in the transformer. If no fault current is Pin Assignments SCR Trigger 1 8 +VS – Input 2 7 CT + Input 3 6 RSET Ground 4 5 Amp Out 65-1851-02 Definition of Terms Normal Fault Grounded Neutral Fault An unintentional electrical path, RB, between the load terminal of the hot line and the ground, as shown by the dashed lines in Figure1. An unintentional electrical path between the load terminal of the neutral line and the ground, as shown by the dashed lines in Figure 2. Hot GFI Line Hot Hot RLOAD RB Line Hot GFI Neutral Neutral Neutral RIN RG RG 65-1851-03 Figure 1. Normal Fault 2 RLOAD Neutral 65-1851-05 Figure 2. Grounded Neutral Fault PRODUCT SPECIFICATION LM1851 Normal Fault Plus Grounded Neutral Fault The combination of the normal fault and the grounded neutral fault, as shown by the dashed lines in Figure 3. Hot Hot GFI Line RLOAD RB Neutral Neutral RN RG 65-1851-04 Figure 3. Normal Fault Plus Grounded Neutral Fault Absolute Maximum Ratings Parameter Conditions Min Max Units Supply Current 19 mA Power Dissipation 570 mW 70 °C SOIC, 10 seconds 260 °C DIP, 60 seconds 300 °C Max Units 125 °C DIP 468 mW SOIC 300 DIP 160 Operating Temperature Lead Soldering Temperature -40 Thermal Characteristics Parameter Conditions Maximum Junction Temperature Maximum PDTA < 50°C Thermal Resistance, qJA For TA > 50°C, derate at Min SOIC 240 DIP 6.25 SOIC 4.17 °C/W mW/°C 3 LM1851 PRODUCT SPECIFICATION DC Electrical Characteristics (TA = +25°C, ISHUNT = 5 mA) Parameters Test Conditions Min Typ Max Units Power Supply Shunt Regulator Voltage Pin 8, Average Value 22 26 30 V Latch Trigger Voltage Pin 7 15 17.5 20 V Sensitivity Set Voltage Pin 8 to Pin 6 6 7 8.2 V Output Drive Current Pin 1 With Fault 0.5 1 2.4 mA Output Saturation Voltage Pin 1 Without Fault 100 240 mV Output Saturation Resistance Pin 1 Without Fault 100 W Output External Current Sinking Capability1 Pin 1 Without Fault, VPIN1 Held to 0.3V 2 5 mA Noise Integration Sink Current Ratio Pin 7, Ratio of Discharge Currents Between No Fault Fault and Fault Conditions 2.0 2.8 3.6 mA/mA Typ Max Units 5 7 mA Notes: 1. This external applied current is in addition to the internal “output drive current” source. AC Electrical Characteristics (TA = +25°C, ISHUNT = 5 mA) Parameters 2 Conditions Min 3 Normal Fault Current Sensitivity See Figure 9 Normal Fault Trip Time1 500W Fault, see Figure 10 18 mS Normal Fault With Grounded 500W Normal Fault 18 mS Neutral Fault Trip Time1 2W Neutral, see Figure 10 Notes: 1. Average of 10 trials. 2. Required UL sensitivity tolerance is such that external trimming of LM1851 sensitivity is necessary. 4 PRODUCT SPECIFICATION LM1851 100 UL943 Normal Fault 10 65-1851-06 0 0.01 0.1 10 1 100 RSET = IF (rms)* x (0.91) Sense Transformer 1000:1 10 1 100K 1M 10M RSET (W) Trip Time (Seconds) Figure 4. Average Trip Time vs. Fault Current Figure 5. Normal Fault Current Threshold vs. RSET 1000 5 mA 8 100 1 1 mA A VPIN1 4 10 0 0 5 10 15 20 25 30 35 Output Voltage @ VPIN1(V) Figure 6. Output Drive Current vs. Output Voltage Pin 1 Saturation Voltage (V) 10 31V 65-1851-08 Output Drive Current @ Pin 1 (µA) 7V 1 31V 5 mA 8 0.1 IL 1 1 mA A 4 0.01 0.1 1 10 65-1851-09 Fault Current (mA) Circuit of Figure 10 65-1851-07 1000 Fault Current on Line [mA(rms)] Typical Performance Characteristics (TA = +25°C) 100 External Load Current (mA) Figure 7. Pin 1 Saturation Voltage vs. External Load Current, IL 5 LM1851 PRODUCT SPECIFICATION Applications Discussion A typical ground fault interrupter circuit is shown in Figure 10. It is designed to operate on 120 VAC line voltage with 5 mA normal fault sensitivity. A full-wave rectifier bridge and a 15k/2W resistor are used to supply the dc power required by the IC. A 1 mF capacitor at pin 8 is used to filter the ripple of the supply voltage and is also connected across the SCR to allow firing of the SCR on either half-cycle. When a fault causes the SCR to trigger, the circuit breaker is energized and line voltage is removed from the load. At this time no fault current flows and the CT discharge current increases from ITH to 3ITH (see Block Diagram). This quickly resets both the timing capacitor and the output latch. The circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault has been removed. A 1000:1 sense transformer is used to detect the normal fault. The fault current, which is basically the difference current between the got and neutral lines, is stepped down by 1000 and fed into the input pin of the operational amplifier through a 10 mF capacitor. The 0.0033 mF capacitor between pin 2 and pin 3 and the 200 pF between pins 3 and 4 are added to obtain better noise immunity. The normal fault sensitivity is determined by the timing capacitor discharging current, ITH. ITH can be calculated by: 7V I TH = ------------- ¸ 2 R SET The correct value for RSET can also be determined from the characteristic curve that plots equation (3). Note that this is an approximate calculation; the exact value of RSET depends on the specific sense transformer used and LM1851 tolerances. Inasmuch as UL943 specifies a sensitivity “window” of 4 mA to 6mA, provision should be made to adjust RSET with a potentiometer. Independent of setting sensitivity, the desired integration time can be obtained through proper selection of the timing capacitor, CT. Due to the large number of variables involved, proper selection of CT is best done empirically. The following design example should only be used as a guideline. Assume the goal is to meet UL943 timing requirements. Also assume that worst case timing occurs during GFI startup (S1 closure) with both a heavy normal fault and a 2W grounded neutral fault present. This situation is shown diagrammatically in Figure 8. S1 Hot Line GFI Neutral (1) (3) For example, to obtain 5 mA(rms) sensitivity for the circuit in Figure 7 we have: 7V R SET = ------------------------------ = 1.5MW 5 mA ´ 0.91 -----------------------------1000 6 RN 0.4 RB 500 I RB 500 (0.2)I 65-1851-12 Figure 8. (2) Where IF(rms) is the rms input fault current to the operational amplifier and the factor of 2 is due to the fact that IF charges the timing capacitor only during one half-cycle, while ITH discharges the capacitor continuously. The factor 0.91 converts the rms value to an average value. Combining equations (1) and (2) we have: 7V R SET = -----------------------------------I F ( rms ) ´ 0.91 Neutral (0.8)I At the decision point, the average fault current just equals the threshold current, ITH. I F ( rms ) I TH = ------------------- ´ 0.91 2 Hot (4) UL943 specifies £25 ms average trip time under these conditions. Calculation of CT based upon charging currents due to normal fault only is as follows: 1. Start with a £25 ms specification. Subtract 3 ms GFI turn-on time (15k and 1 mF). Subtract 8 ms potential loss of one half-cycle due to fault current sense of halfcycles only. 2. Subtract 4 ms time required to open a sluggish circuit breaker. 3. This gives a total £10 ms maximum integration time that could be allowed. 4. To generate 8 ms value of integration time that accommodates component tolerances and other variables: 1´T C T = -----------V (5) PRODUCT SPECIFICATION LM1851 In practice, the actual value of CT will have to be modified to include the effects of the neutral loop upon the net charging current. The effect of neutral loop induced currents is difficult to quantize, but typically they sum with normal fault currents, thus allowing a larger value of CT. where: T = integration time V = threshold voltage I = average fault current into CT 120 V AC ( rms ) I = æ -------------------------------------ö è ø RB RN ö æ ---------------------è RG + RNø heavy fault current generated (swamps ITH) 1 turn ´ æ -------------------------ö è 1000 turnsø current division of input sense transformer ´ For UL943 requirements, 0.015 mF has been found to be the best compromise between timing and noise. portion of fault current shunted around GFI æ 1---ö è 2ø CT charging on halfcycles only ´ ( 0.91 ) For those GFI standards not requiring grounded neutral detection, a still larger value capacity can be used and better noise immunity obtained. (6) The larger capacitor can be accommodated because RN and RG are not present, allowing the full fault current, I, to enter the GFI. In Figure 10, grounded neutral detection is accomplished by feeding the neutral coil with 120 Hz energy continuously and allowing some of the energy to couple into the sense transformer during conditions of neutral fault. rms to average conversion Transformers may be obtained from Magnetic Metals, Inc., 21st Street and Hayes Street, Camden, NJ 08101— (609) 964-7842. therefore: 0.4 1 1 æ 120 ---------ö ´ æ ---------------------ö ´ æ ------------ö ´ æ ---ö ´ ( 0.91 ) è 500ø è 1.6 + 0.4ø è 1000ø è 2ø C T = ------------------------------------------------------------------------------------------------------------------ ´ 0.008 17.5 C T = 0.01 mF (7) 7 LM1851 PRODUCT SPECIFICATION Application Circuits LM1851 7 1 CT 0.002 5 ISHUNT A 8 Timing Cap -In SCR Trigger +In 2 100K 0.047 µF 3 6 Op Amp Output RSET +VS GND 800 Hz 4 1K 300 mV 1.5M 31V 65-1851-10 Figure 9. Normal Fault Sensitivity Test Circuit Gnd/Neutral Coil Sense Coil 200:1 1000:1 Hot Load MOV Line Neutral High µ Coil Circuit Breaker 1.0 µF Tant 0.01/400V LM1851 7 Timing Cap –In SCR Trigger +In 5K/2W 0.0033 1 CT 0.015 SCR 0.01/400V 5 8 Op Amp Output RSET +VS GND 3 6 200 pF 4 0.01 10 µF Tant RSET* *Adjust RSET for desired sensitivity. Figure 10. 120 Hz Neutral Transformer Application 8 2 65-1851-11 PRODUCT SPECIFICATION LM1851 Schematic Diagram (3) (6) (5) (2) (8) R13 50K Q2 R9 100K R12 390 R10 110 Q31 .3X Q1 .5X Q44 R3 10K Q17 R2 40K Q28 .7X Q18 .5X .5X Q24 Q15 Q16 Q56 Q40 D1 Q26 R6 6K Q23 Q22 Q54 Q27 Q25 2.44X R5 320 R4 20K Q13 Q12 2.44X R8 2K Q14 R7 1.2K Q38 2X Q36 Q39 R15 5.6K Q50 Q48 R11 50K Q49 Q55 4.54X R16 17.33K (4) N+ Q11 (1) Q41 Q21 .5X Q20 .5X Q6 Q10 Q42 Q29 2.44X .3X Q5 Q37 .2X Q19 Q4 Q8 R17 100K Q46 Q45 R1 13.1K Q9 2.44X Q53 Q52 .8X Q3 Q7 Q54 3X Q47 .5X R14 5K Q30 Q33 .5X .5X C2 8 pF Q34 Q32 Q35 .5X (7) 65-1851-13 9 LM1851 PRODUCT SPECIFICATION Mechanical Dimensions 8-Lead Plastic DIP Package Inches Symbol A A1 A2 B B1 C D D1 E E1 e eB L Millimeters Min. Max. Min. Max. — .015 .115 .014 .045 .008 .348 .005 .300 .240 .210 — .195 .022 .070 .015 .430 — .325 .280 — .38 2.93 .36 1.14 .20 8.84 .13 7.62 6.10 5.33 — 4.95 .56 1.78 .38 10.92 — 8.26 7.11 .100 BSC — .430 .115 .160 2.54 BSC — 10.92 2.92 4.06 8¡ 8¡ N Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E1" do not include mold flashing. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. Terminal numbers are for reference only. 4. "C" dimension does not include solder finish thickness. 5. Symbol "N" is the maximum number of terminals. 4 2 2 5 D 4 1 5 8 E1 D1 E e A2 A A1 C L B1 10 B eB PRODUCT SPECIFICATION LM1851 Mechanical Dimensions (continued) 8-Lead Plastic SOIC Package Inches Symbol Min. A A1 B C D E e H h L N a ccc Millimeters Max. Min. Max. .053 .069 .004 .010 .013 .020 .008 .010 .189 .197 .150 .158 .050 BSC 1.35 1.75 0.10 0.25 0.33 0.51 0.20 0.25 4.80 5.00 3.81 4.01 1.27 BSC .228 .010 .016 5.79 0.25 0.40 .244 .020 .050 8 6.20 0.50 1.27 8 0¡ 8¡ 0¡ 8¡ — .004 — 0.10 8 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .010 inch (0.25mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5 2 2 5. "C" dimension does not include solder finish thickness. 6. Symbol "N" is the maximum number of terminals. 3 6 5 E 1 H 4 h x 45¡ D C A1 A SEATING PLANE e B –C– LEAD COPLANARITY a L ccc C 11 LM1851 PRODUCT SPECIFICATION Ordering Information Part Number Package Operating Temperature Range LM1851AN 8-lead Plastic DIP -40°C to +70°C RV4145M 8-lead Plastic SOIC -40°C to +70°C LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS30001851 Ó 1998 Fairchild Semiconductor Corporation