UTC LM1851 LINEAR INTEGRATED CIRCUIT GROUND FAULT INTERRUPTER DESCRIPTION The UTC LM1851 is designed to provide ground fault protection for AC power outlets in consumer and industrial environments. Ground fault currents greater than a presentable threshold value will trigger an external SCR-driven circuit breaker to interrupt the AC line and remove the fault condition. In addition to detection of conventional hot wire to ground faults, the neutral fault condition is also detected. DIP-8 Full advantage of the U.S. UL943 timing specification is taken to insure maximum immunity to false triggering due to line noise. Special features include circuitry that rapidly resets the timing capacitor in the event that noise pulses introduce unwanted charging currents and a memory circuit that allows firing of even a sluggish breaker on either half-cycle of the line voltage when external full-wave rectification is used. SOP-8 FEATURES * Internal power supply shunt regulator * Externally programmable fault current threshold * Externally programmable fault current integration time * Direct interface to SCR * Operates under line reversal; both load vs line and hot vs neutral * Detects neutral line faults PIN CONFIGURATION SCR Trigger 1 8 Vcc INVERTING INPUT 2 7 TIMING CAPACITOR NON-INVERTING INPUT 3 6 SENSE ITIVITY SET RESISTOR GND 4 5 SENSE AMPLIFIER OUTPUT UTC UNISONIC TECHNOLOGIES CO., LTD. 1 QW-R122-007,A UTC D21 Q29 Q25 6 R16 20k R3 12k D10 D9 D8 D7 D6 D5 R2 40k D22 Q26 D4 D3 UNISONIC TECHNOLOGIES CO., LTD. Q21 Q20 Q28 Q27 D23 Q23 R6 320 Q22 R4 6k Q24 R5 10k R14 1.2k D11 Q3 Q1 3 Q2 R15 2k Q5 Q4 D1 R1 D2 100k D12 Q6 Q9 Q7 Q12 R7 50k D14 Q18 Q11 C1 C2 Q19 D13 Q10 Q8 Q17 7 D20 D19 D18 D17 R9 50k R8 390 R13 110 Q13 Q14 Q16 D16 R10 5k 8 5 2 R12 Q30 12k R11 5k Q15 Q31 Q33 R17 100k Q32 Q35 4 Q34 1 Q36 UTC LM1851 LINEAR INTEGRATED CIRCUIT INTERNAL SCHEMATIC DIAGRAM 2 QW-R122-007,A UTC LM1851 LINEAR INTEGRATED CIRCUIT BLOCK DIAGRAM TIMING CAPACITOR Vcc 8 7 D3 I2 Q3 6 Q1 I1= - A1 + Vs Q5 Q4 D2 10V + - If 2 SCR TRIGGER ITH FOR If > 0 3ITH FOR If = 0 If D1 1 5 Q2 LATCH SENSE AMPLIFIER OUTPUT SENSITIVITY SET RESISTOR INVERTING INPUT 3 4 NON-INVERTING INPUT GND ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATINGS Supply Current Power Dissipation (Note 1) Operating Temperature Storage Temperature Lead Soldering Temperature DIP-8 (10 sec.) SOP-8 Vapor Phase (60 sec.) Infrared (15 sec.) Icc PD Topr Tstg 19 1250 -40 ~ +70 -55 ~ +150 UNIT mA mW °C °C 260 °C 215 220 °C °C TLED DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, Iss=5mA) PARAMETER Power Supply Shunt Regulator Voltage Latch Trigger Voltage Sensitivity Set Voltage Output Drive Current Output Saturation Voltage Output Saturation Resistance Output External Current Sinking Capability Noise Integration Sink Current Ratio UTC TEST CONDITIONS MIN TYP MAX UNIT Pin 8, Average Value 22 26 30 V Pin 7 Pin 8 to Pin 6 Pin 1, With Fault Pin 1, Without Fault Pin 1, Without Fault Pin 1, Without Fault Vpin 1 Held to 0.3V (Note 4) Pin 7, Ratio of Discharge Currents Between No Fault and Fault Conditions 15 6 0.5 17.5 7 1 100 100 20 8.2 2.4 240 V V mA mV Ω 2.0 5 2.0 2.8 mA 3.6 UNISONIC TECHNOLOGIES CO., LTD. μA/μA 3 QW-R122-007,A UTC LM1851 LINEAR INTEGRATED CIRCUIT AC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, Iss=5mA) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Normal Fault Current Sensitivity Figure 1 (Note 3) 3 5 7 mA 500Ω Fault, Figure 2 (Note 2) Normal Fault Trip Time 18 ms Normal Fault with Grounded Neutral 500Ω Normal Fault, 2Ω Neutral, 18 ms Fault Trip Time Figure 2 (Note 2) Note 1: For operation in ambient temperatures above 25℃, the device must be debated based on a 125℃ maximum junction temperature and a thermal resistance of 80℃/W junction to ambient for the DIP and 162/W for the SO Package. Note 2: Average of 10 trials. Note 3: Required UL sensitivity tolerance is such that external trimming of UTC LM1851 sensitivity will be necessary. Note 4: This externally applied current is in addition to the internal ''output drive current '' source. 7 TIMING CAP -IN 1 SCR TRIGGER +IN 5 Iss A + - 300mV Ct 0.002 1k 8 OP AMP OUTPUT RSET Vcc GND 2 100k 0.047μF 3 800Hz 6 4 1.5M 31V FIGURE 1.Normal Fault Sensitivity Test Circuit CIRCUIT DESCRIPTION (Refer to Block and Connection Diagram) The UTC LM1851 operates from 26V as set by an internal shunt regulator, D3. In the absence of a fault (If=0) the feedback path status signal (VS) is correspondingly zero. Under these conditions the capacitor discharge current, I1, sits quiescently at three times its threshold value, ITH, so that noise induced charge on the timing capacitor will be rapidly removed. When a fault current, If, is induced in the secondary of the external sense transformer, the operational amplifier, A1, uses feedback to force a virtual ground at the input as it extracts If. The presence of If during either half-cycle will cause VS to go high, which in turn changes I1 from 3ITH to ITH. Although ITH discharges the timing capacitor during both half-cycles of the line, If only charges the capacitor during the half-cycle in which If exits pin 2. Thus during one half-cycle If-ITH charges the timing capacitor, while during the other half-cycle ITH discharges it. When the capacitor voltage reaches 17.5V, the latch engages and turns off Q3 permitting I2 to drive the gate of an SCR. UTC UNISONIC TECHNOLOGIES CO., LTD. 4 QW-R122-007,A UTC LM1851 LINEAR INTEGRATED CIRCUIT APPLICATION CIRCUITS A typical ground fault interrupter circuit is shown in Figure 2. It is designed to operate on 120 VAC line voltage with 5 mA normal fault sensitivity. A full-wave rectifier bridge and a 15k/2W resistor are used to supply the DC power required by the IC. A 1μF capacitor at pin 8 used to filter the ripple of the supply voltage and is also connected across the SCR to allow firing of the SCR on either half-cycle. When a fault causes the SCR to trigger, the circuit breaker is energized and line voltage is removed from the load. At this time no fault current flows and the IC discharge current increases from ITH to 3ITH ( see Circuit Description and Block Diagram ). This quickly resets both the timing capacitor and the output latch. At this time the circuit breaker can be reset and the line voltage again supplied to the load, assuming the fault has been removed. A 1000:1 sense transformer is used to detect the normal fault. The fault current, which is basically the difference current between the hot and neutral lines, is stepped down by 1000 and fed into the input pins of the operational amplifier through a 10μF capacitor. The 0.0033μF capacitor between pin 2 and pin 3 and the 200 pF between pins 3 and 4 are added to obtain better noise immunity. The normal fault sensitivity is determined by the timing capacitor discharging current, ITH. ITH can be calculated by: ITH= 7V ÷2 RSET (1) At the decision point, the average fault current just equals the threshold current, ITH. ITH= If (rms) × 0.91 2 (2) Where If(rms) is the rms input fault current to the operational amp and the factor of 2 is due to the fact that If charges the timing capacitor only during one half-cycle, while ITH discharges the capacitor continuously. The factor 0.91 converts the rms value to an average value. Combining equations (1) and (2) we have RSET= 7V If (rms) × 0.91 (3) For example, to obtain 5mA (rms) sensitivity for the circuit in Figure 2 we have: RSET= 7V 5mA × 0.91 1000 =1.5MΩ (4) The correct value for RSET can also be determined from the characteristic curve that plots equation (3). Note that this is an approximate calculation; the exact value of RSET depends on the specific sense transformer used and UTC LM1851 tolerances. Inasmuch as UL943 specifies a sensitivity '' window '' of 4mA ~ 6mA, provision should be made to adjust RSET on a per-product basis. Independent of setting sensitivity, the desired integration time can be obtained through proper selection of the timing capacitor, Ct. Due to the large number of variables involved, proper selection of Ct is best done empirically. The following design example, then should only be used as a guideline. Assume the goal is to meet UL943 timing requirements. Also assume that worst-case timing occurs during GF1 Start-up (S1 closure) with both a heavy normal fault and a 2Ω grounded neutral fault present. This situation is shown diagrammatically below. UTC UNISONIC TECHNOLOGIES CO., LTD. 5 QW-R122-007,A UTC LM1851 LINEAR INTEGRATED CIRCUIT S1 HOT HOT LINE GFI NEUTRAL NEUTRAL RG 1.6 (0.8) I RN 0.4 (0.2) I RB 500 I UL943 specifies ≤25 ms average trip time under these conditions. Calculation of Ct based upon charging currents due to normal fault only is as follows: ≤25 ms Specification -3 ms GFI turn-on time (15k and 1μF) -8 ms Potential loss of one half-cycle due to fault current sense of half-cycles only -4 ms Time required to open a sluggish circuit breaker ≤10 ms Maximum integration time that could be allowed 8 ms Value of integration time that accommodates component tolerances and other variables 1× T V C t= (5) Where T=integration time V=threshold voltage I=average fault current into Ct 120VAC(rms) RB I= RN RG + RN × portion of fault current shunted around GFI heavy fault current generated (swamps ITH) × 1 turn 1000 turns current division of input sense transformer × 1 2 × Ct charging on halfcycles only 0.91 (6) rms to average conversion therefore: Ct = 120 500 Ct = 0.01μF UTC 0.4 × 1.6+0.4 × 1 1000 17.5 × 1 2 × 0.91 × 0.0008 (7) UNISONIC TECHNOLOGIES CO., LTD. 6 QW-R122-007,A UTC LM1851 LINEAR INTEGRATED CIRCUIT APPLICATION CIRCUITS In practice, the actual value of C1 will have to be modified to include the effects of the neutral loop upon the net charging current. The effect of neutral loop induced currents is difficult to quartile, but typically they sum with normal fault currents, thus allowing a larger value of C1. For UL943 requirements, 0.015μF has been found to be the best compromise between timing and noise. For those GFI standards not requiring grounded neutral detection, a still larger value capacitor can be used and better noise immunity obtained. The larger capacitor can be accommodated because RN and RG are not present, allowing the full fault current, I, to enter the GFI. In Figure 2, grounded neutral detection is accomplished by feeding the neutral coil with 120 Hz energy continuously and allowing some of the energy to couple into the sense transformer during conditions of neutral fault. TYPICAL APPLICATION GND/NEUTRAL COIL SENSE COIL HOT MOV LOAD LINE 200:1 NEUTRAL 1000:1 HIGH µ COIL CIRCUIT BREAKER 0.01/400V 15K/2W SCR 0.01/400V 10 μF + TANT 7 TIMING CAP 1 SCR TRIGGER 5 OP AMP Ct OUTPUT 0.015 8 VCC -IN +IN RSET GND 2 0.0033 3 6 200 pF 4 RSET* 0.01 + 1.0μF TANT * Adjust RSET for desired sensitivity FIGURE 2. 120Hz Neutral Transformer Approach UTC UNISONIC TECHNOLOGIES CO., LTD. 7 QW-R122-007,A UTC LM1851 LINEAR INTEGRATED CIRCUIT DEFINITION OF TERMS Normal Fault An unintentional electrical path , R B, between the load terminal of the hot line and the ground, as shown by the dashed lines HOT HOT GFI LINE Normal Fault plus Grounded Neutral fault: The combination of the normal fault and the grounded neutral fault, as shown by the dashed lines. RLOAD RB NEUTRAL HOT HOT GFI LINE RLOAD NEUTRAL NEUTRAL NEUTRAL RG RN RB RG Grounded Neutral Fault: An unintentional electrical path between the load terminal of the neutral line and the ground, as shown by the dashed lines. HOT HOT RLDAD LINE NEUTRAL GFI NEUTRAL RN RG UTC UNISONIC TECHNOLOGIES CO., LTD. 8 QW-R122-007,A UTC LM1851 LINEAR INTEGRATED CIRCUIT TYPICAL PERFORMANCE CHARACTERISTICS Average Trip Time vs Fault Current UL943 NORMAL FAULT 10 0.01 0.1 1.0 TRIP TIME (SECONDS) 1000 31V 800 5mA 8 600 400 1 1mA 200 A VPIN1 4 0 5 10 15 25 20 30 OUTPUT VOLTAGE@ VPIN1 (V) 7V If (rms)*×(0.91) SENSE TRANSF0RMER 1000:1 10 10 1200 35 Normal Fault Current Threshold vs RSET RSET= 1 100k 10 Output Drive Current vs Output Voltage 1400 0 100 FAULT CURRENT ON LINE (mA(rms)) 100 0 OUTPUT DRIVE CURRENT@PIN 1 ( μA) CIRCUIT OF FIGURE 2 PIN 1 SATURATION VOLTAGE (V) FAULT CURRENT (mA) 1000 1M RSET (Ω) 10M Pin 1 Saturation Voltage vs External Load Current, IL 1 5mA 31V 8 IL 0.1 1 1mA V 0.01 0.1 4 100 1 10 EXTERNAL LOAD CURRENT, LI (mA) UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UTC UNISONIC TECHNOLOGIES CO., LTD. 9 QW-R122-007,A