ETC PHASE

AN-SETS-7
PLL Configurations for ACS8530
ADVANCED COMMUNICATIONS
PRELIMINARY
APPLICATION
NOTE
Phase Lock Loop Configurations for the
Semtech ACS8530 SONET and SDH SETS Device
Overview
This Application Note describes some examples of the
ways in which the ACS8530 Phase Lock Loops (PLL) can be
configured for different frequency and output jitter options.
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PLL Configurations for ACS8530
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APPLICATION NOTE
Table of Contents
List of Sections
Page
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1 T0 DPLL Architecture and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.2 T4 DPLL Architecture and Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2.3 Default Configuration for Independent T4 and T0 Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.4 Alternative Configuration for Independent T0 and T4 Paths . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.5 Configuration for Low Jitter E3/DS3 and OC-N Clock Generation with No Independent T4
Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.6 Configuration for Low Jitter E3/DS3 and E1/DS1 with No Independent T4 Path . . . . . . . . . .12
2.7 T4 PLL Configured to Measure the Relative Phase Error between Inputs . . . . . . . . . . . . . . . .13
2.7.1 Examples of T4 PFD used for Phase Measurement . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.8 T4 Low Frequency Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Appendix 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
List of Figures
Figure 1 ACS8530 PLL Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 2 Basic T0 configuration for OC-N and n x E1/DS1 outputs (low and high jitter). . . . . . . . . . . . .6
Figure 3 Basic T4 configuration for independent BITS/SSU output. . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Figure 4 T4 configuration for low jitter independent BITS/SSU and OC-N clock outputs. . . . . . . . . . . .8
Figure 5 Default configuration of the T0 and T4 PLLs for simultaneous clock output.. . . . . . . . . . . . . .9
Figure 6 Alternative configuration for independent T0 and T4 outputs. . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 7 Configuration for low jitter E3/DS3 and OC-N clock generation with no independent T4
path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Figure 8 Configuration for low jitter E3/DS3 and E1/DS1 with no independent T4 path. . . . . . . . . . .12
Figure 9 T4 PFD configured to perform Phase Offset Measurement between selected T0 input and a
standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
List of Tables
Table 1
Table 2
Table 3
Phase measurement examples using T4 PFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
T0 DPLL Frequency Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
T4 DPLL Frequency Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
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PLL Configurations for ACS8530
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1
APPLICATION NOTE
Introduction
This Application Note describes some examples of the ways in which the ACS8530 Phase Lock Loops
(PLL) can be configured for different frequency and output jitter options. The ACS8530 has two
independent PLL "paths" on the same chip, one denoted the T0 path and the other the T4 path. The T0
path is a combination of a Digital PLL (DPLL) and an Analog PLL (APLL). The T4 path is also a combination
of a DPLL and an APLL, but the DPLL can be configured to function independently from the APLL. The T0
path is a high quality, highly configurable path designed to provide features necessary for node timing
synchronization within a SONET/SDH network. The T4 path is a simpler and less configurable path
designed to give a totally independent path for internal equipment synchronization. The device supports
use of either or both paths, either locked together or independent. The basic PLL architecture of the
ACS8530 is shown in Figure 1.
2
General
A DPLL gives a stable and consistent level of performance that can be easily programmed for different
dynamic behaviour or operating range. Digital synthesis is used to generate all required SONET/SDH
output frequencies. The digital logic operates at 204.8 MHz that is multiplied up from the external 12.8
MHz oscillator module. Hence the best resolution of the output signals from the DPLL is one 204.8 MHz
cycle or 4.9 ns. Additional resolution and lower final output jitter is provided by a de-jittering APLL that
reduces the 4.9 ns pk-pk jitter from the digital down to 350 ps pk-pk and 50-60 ps RMS as typical final
outputs measured broadband (from 10 Hz to 1 GHz). This arrangement combines the advantages of the
flexibility and repeatability of a DPLL with the low jitter of an APLL.
Figure 1
T4
Reference
Input
ACS8530 PLL Architecture
Lock_T4_to_T0
Sts_Current_Phase
Control
T4_DPLL_Frequency
T4_APLL_for_T0
0
Forward
DFS
PFD and
Loop Filter
0
T4_Dig_Feedback
T0_DPLL_Freq
1
1
1
T4
Output
Dividers
T4
Output
APLL
TO1 to TO7
0
T4 DPLL
Locking
Frequency
Feedback
DFS
T4_Op_From_TO
0
0
1
TO8 /TO9
8 kHz
T0_DPLL_Frequency
Control
0
77M
Output
DFS
Sts_Current_Phase
T0
Reference
Input
PFD and
Loop Filter
PBO
Phase
Offset
1
LF
Output
DFS
0
T0_DPLL_Frequency
Control
77M
Forward
DFS
1
1
T0
Output
APLL
T0
Output
Dividers
TO1 to TO7
TO1 to TO7
TO10/TO11
T0
Feedback
APLL
1
Locking
Frequency
Feedback
DFS
0
T0 DPLL
Analog
F8530D_017BLOCKDIA_04
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PLL Configurations for ACS8530
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APPLICATION NOTE
The DPLLs in the ACS8530 are uniquely very programmable for all PLL parameters of bandwidth (from
0.5 mHz up to 70 Hz), damping factor (from 1.2 to 20), frequency acceptance and output range (from 0
to 80 ppm, typically 9.2 ppm), input frequency (12 common SONET/SDH spot frequencies) and input-tooutput phase offset (in 6 ps steps up to 200 ns).
There is no requirement to understand the loop filter equations or detailed gain parameters since all
high level factors such as overall bandwidth can be set directly via registers in the microprocessor
interface.
The T0 path DPLL by default always produces an output at 77.76 MHz to feed the APLL, regardless of
the frequency selected at the output pins. The T4 path can be operated at a number of frequencies. This
is to enable the generation of extra output frequencies, which cannot be easily related to 77.76 MHz.
When the T4 path is selected to lock to the T0 path, the T4 DPLL locks to the 8 kHz from the T0 DPLL.
This is because all of the frequencies of operation of the T4 path can be divided to 8 kHz and this will
ensure synchronization of all the frequencies within the two paths. Both the DPLL's outputs are
connected to multiplying and filtering APLLs. The outputs of these APLLs are divided making a number
of frequencies simultaneously available for selection at the output clock ports. The various combinations
of DPLL, APLL and divider configurations allow for generation of a comprehensive set of frequencies, as
listed in ACS8530 datasheet. To synchronize the lower output frequencies when the T0 PLL is locked to
a high frequency reference input, an additional input is provided. The SYNC2K pin (pin 45) is used to
reset the dividers that generate the 2 kHz and 8 kHz outputs such that the output 2/8 kHz clocks are
precisely aligned with the input 2 kHz.
The T4 DPLL is similar in structure to the T0 DPLL, but since the T4 is only providing a clock synthesis
and input to output frequency translation function, with no defined requirement for jitter attenuation or
input phase jump absorption, then its bandwidth is limited to the high end and the T4 does not
incorporate any of the Phase Build-out and adjustment facilities of the T0 DPLL.
The T0 and T4 PLL paths support the following common features:
z
Automatic source selection according to input priorities and quality level.
z
Different quality levels (activity alarm thresholds) for each input.
z
Variable bandwidth, lock range and damping factor.
z
Direct PLL locking to common SONET/SDH input frequencies or any multiple of 8 kHz.
z
Automatic mode switching between Free run, Locked and Holdover states.
z
Fast detection on input failure and entry into Holdover mode (holds at the last good frequency
value).
z
Frequency translation between input and output rates via direct digital synthesis.
z
Multi-cycle phase detection and locking, programmable up to +/-8192 UI for improved jitter
tolerance in direct lock mode.
z
Multiple n x E1/DS1 outputs supported.
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PLL Configurations for ACS8530
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2.1
APPLICATION NOTE
T0 DPLL Architecture and Features
The main features of the T0 DPLL are:
z
Programmable DPLL bandwidth in 18 steps from 0.5 mHz to 70 Hz.
z
Programmable damping factor for optional faster locking and peaking control. Factors = 1.2, 2.5, 5,
10 or 20.
z
Multiple phase lock detectors.
z
Phase Build-out on source switch (hitless source switching, +/- 2.5 ns).
z
Input to output Phase offset adjustment (Master/Slave), +/- 200 ns range, 6ps resolution step size.
z
Phase Build-out phase offset adjustment (source switch), +/- 3 ns range, 5ps resolution step size.
z
Detection of phase jump on the current locked to source: programmable limit from 1 - 3.5 us in 100
ms.
z
Optional automatic Phase Build-out event on a detected input phase jump.
z
Holdover frequency averaging with a choice of average times, 3rd Order anti-aliasing filter, read-out
of filtered value.
z
Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs.
z
Revertive and non-revertive mode.
The control of the T0 DPLL is either via software or an internal state machine control. The basic
configuration for the T0 PLL is shown in Figure 2. The T0 DPLL always produces 77.76 MHz regardless
of either the reference frequency (frequency at the input pin of the device) or the locking frequency
(frequency at the input of the DPLL Phase and Frequency Detector- PFD). The input reference is either
passed directly to the PFD or via a pre-divider (not shown) to produce the reference input. The feedback
77.76 MHz is either divided or synthesized to generate the locking frequency. Digital Frequency
Synthesis (DFS) is a technique for generating an output frequency using a higher frequency system
clock. However, the edges of the output clock are not ideally placed in time, since all edges of the output
clock will be aligned to the active edge of the 204.8 MHz system clock. This will mean that the generated
clock will inherently have jitter on it equivalent to one period of the 204.8 MHz system clock.
The T0 77.76 MHz forward DFS block uses DFS clocked by the 204.8 MHz system clock to synthesize
the 77.76 MHz and, therefore, has an inherent 4.9 ns of pk-pk jitter. There is an option to use an APLL,
the T0 feedback APLL, to filter out this jitter before the 77.76 MHz is used to generate the feedback
locking frequency in the T0 feedback DFS block. This analog feedback option allows a lower jitter (<1 ns)
feedback signal to give maximum performance. The digital feedback option is present so that when the
output path is switched to digital feedback the two paths remain synchronized. The T0 77.76 MHz
forward DFS block is also the block that handles Phase Build-out and any phase offset programmed into
the device. Hence, the T0 77.76 MHz forward DFS and the T0 77.76 MHz output DFS blocks are locked
in frequency but may be offset in phase. The T0 77.76 MHz output DFS block also uses the 204.8 MHz
system clock and always generates 77.76 MHz for the output clocks (with inherent 4.9 ns of jitter). This
is fed to another DFS block and to the T0 output APLL.
The low frequency T0 LF output DFS block is used to produce three frequencies; two of them, Digital1
and Digital2, are available for selection to be produced at outputs TO1-TO7, and the third frequency can
produce multiple E1/DS1 rates via the filtering APLLs. The input clock to the T0 LF output DFS block is
either 77.76 MHz from the T0 output APLL (post jitter filtering) or 77.76 MHz direct from the T0
77.76 MHz output DFS. Utilizing the clock from the output of the APLL will result in lower jitter outputs
from the T0 LF output DFS block. However, when the input to the APLL is taken from the T0 LF output
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PLL Configurations for ACS8530
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APPLICATION NOTE
DFS block, the input to that block comes directly from the T0 77.76 MHz output DFS block so that a
"loop" is not created.
The T0 output APLL is for multiplying and filtering. The input to the T0 output APLL can be either
77.76 MHz from the T0 77.7 6MHz output DFS block or an alternative frequency from the T0 LF output
DFS block (offering 77.76 MHz, 12 x E1, 16 x E1, 16 x DS1 or 24 x DS1). The frequency from the T0
output APLL is 4 times it's input frequency i.e. 311.04 MHz when used with a 77.76 MHz input. The T0
output APLL is subsequently divided by 1, 2, 4, 6, 8, 12, 16 or 48, and these are available at the TO1TO7 outputs.
Figure 2
Basic T0 configuration for OC-N and n x E1/DS1 outputs (low and high jitter).
path 7
2.2
T4 DPLL Architecture and Features
The main features of the T4 DPLL are:
z
Programmable DPLL bandwidth in 3 steps from 18, 35 and 70 Hz.
z
Programmable damping factor: For optional faster locking and peaking control. Factors = 1.2, 2.5, 5,
10 or 20.
z
Multiple phase lock detectors.
z
Multi-cycle phase detection and locking, programmable up to +/-8192 UI - improves jitter tolerance
in direct lock mode.
z
N x E1/DS1 including 12 x E1, 16 x E1, 16 x DS1 and 24 x DS1 supported.
z
E3/DS3 (44.736 MHz/34.368 MHz) support.
z
Low jitter N x E1/DS1 options.
z
Low jitter MFrSync (2 kHz) and FrSync (8 kHz) outputs.
z
Can use the T4 DPLL as an Independent FrSync DPLL.
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APPLICATION NOTE
The T4 path is much simpler than the T0 path - see Figure 3. This path offers no Phase Build-out or phase
offset. The T4 input can be used to either lock to a reference clock input independent of the T0 path, or
lock to the T0 path. Unlike the T0 path, the T4 forward DFS block does not always generate 77.76 MHz.
The possible frequencies are listed in Appendix description for Register 64. Similarly to the T0 path, the
output of the T4 forward DFS block is generated using DFS clocked by the 204.8 MHz system clock and
will have an inherent jitter of 4.9 ns. The T4 feedback DFS also has the facility to be able to use the post
APLL (jitter-filtered) clock to generate the feedback locking frequency. Again, this will give the maximum
performance by using a low jitter feedback, see Figure 4. The T4 output APLL block is also for multiplying
and filtering. The input to the T4 output APLL can come either from the T4 forward DFS block or from the
T0 path. These configurations are described in more detail in later sections.
Figure 3
Basic T4 configuration for independent BITS/SSU output.
path8
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Figure 4
APPLICATION NOTE
T4 configuration for low jitter independent BITS/SSU and OC-N clock outputs.
path1
The input to the T4 output APLL can be programmed to be one of the following:
z
Output from the T4 forward DFS block
z
12 x E1 from T0
z
16 x E1 from T0
z
16 x DS1 from T0
z
24 x DS1 from T0
The T4 path can be operated at a number of frequencies. This is to enable the generation of extra output
frequencies, which cannot be easily related to 77.76 MHz. When the T4 path is selected to lock to the
T0 path, the T4 DPLL locks to the 8 kHz from the T0 DPLL. This is because all of the frequencies of
operation of the T4 path can be divided to 8 kHz and this will ensure synchronization of all the
frequencies within the two paths.
The frequency generated from the T4 output APLL block is four times its input frequency i.e. 311.04 MHz
when used with a 77.76 MHz input. The T4 output APLL is subsequently divided by 2, 4, 8, 12, 16, 48
and 64 and these are available at the TO1-TO7 outputs.
The TO8 and TO9 outputs are driven from either the T4 or the T0 path.
The TO10 and TO11 outputs are always generated from the T0 path. Reg.7A Bit 7 selects whether the
source of the 2 kHz and 8 kHz outputs available from TO1-TO7 is derived from either the T0 or the T4
paths.
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2.3
APPLICATION NOTE
Default Configuration for Independent T4 and T0 Paths
The default configuration for the ACS8530 for the T0 and T4 paths to produce simultaneous
independent clock outputs is shown in Figure 5.
This configuration will yield high jitter BITS/AMI clocks from the T4 path. In addition, the T4 APLL will yield
low jitter
OC-N clocks. The T0 path will yield low jitter OC-N, clocks and high jitter n x E1/DS1 simultaneously.
Figure 5
Default configuration of the T0 and T4 PLLs for simultaneous clock output.
Must use
LOCK8K
The register settings for the default configuration are as follows:
Reg 35 bit 7 = 0
Reg 35 bit 6 = 1
Reg 35 bit 4 = 0
Reg 64 bit (2:0) = 001, see Table 3
Reg 65 bit 7 = 0
Reg 65 bit 6 = 0
Reg 65 bit (5:4) = 00
Reg 65 bit (2:0) = 000, see Table 2
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2.4
APPLICATION NOTE
Alternative Configuration for Independent T0 and T4 Paths
An alternative configuration for the ACS8530 for independent T0 and T4 paths to produce simultaneous
clock outputs is shown in Figure 6.
This configuration will yield high jitter BITS/AMI outputs from the T4 path. The T0 path will yield low jitter
OC-N and high jitter n x E1/DS1 plus a low jitter version of the n x E1/DS1 from the T4 APLL.
Figure 6
Alternative configuration for independent T0 and T4 outputs.
Configure for 16E1 or 16DS1 mode for lower jitter BITS/AMI
path2
The register settings for the configuration described are as follows:
Reg 35 bit 7 = 0
Reg 35 bit 6 = 1
Reg 35 bit 4 = 0
Reg 64 bit (2:0) = 12 E1 (010), 16 E1 (011), 16 DS1 (101) or 24 DS1 (100), see Table 3
Reg 65 bit 7 = 0
Reg 65 bit 6 = 1
Reg 65 bit (5:4) = 12 E1 (00), 16 E1 (01), 16 DS1 (11) or 24 DS1 (10), see Table 2
Reg 65 bit (2:0) = 000
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2.5
APPLICATION NOTE
Configuration for Low Jitter E3/DS3 and OC-N Clock Generation with No
Independent T4 Path
The configuration for the ACS8530 for E3/DS3 generation, where the T0 and T4 paths are locked to the
T0, is shown in Figure 7.
This configuration will yield low jitter E3/DS3 outputs from the T4 path. The T0 path will yield low jitter
OC-N and high jitter n x E1/DS1.
Figure 7
Configuration for low jitter E3/DS3 and OC-N clock generation with no independent T4 path.
Configure for E3/DS3 mode as required
path4
The register settings for the configuration described are as follows:
Reg 35 bit 7 = 1
Reg 35 bit 6 = 0
Reg 35 bit 4 = x
Reg 64 bit (2:0) = E3 (110) or DS3 (111), see Table 3
Reg 65 bit 7 = 0
Reg 65 bit 6 = 0
Reg 65 bit (5:4) = xx
Reg 65 bit (2:0) = 000, see Table 2
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2.6
APPLICATION NOTE
Configuration for Low Jitter E3/DS3 and E1/DS1 with No Independent T4 Path
The configuration for the ACS8530 where the T0 and T4 paths are locked to the T0 is shown in Figure 8.
This configuration will yield low jitter E3/DS3 outputs from the T4 path. The T0 path will yield low jitter
n x E1/DS1.
Figure 8
Configuration for low jitter E3/DS3 and E1/DS1 with no independent T4 path.
Configure for E3/DS3 mode as required
path 5
Note... Digital feedback is required to match digital output,
for synchronization reasons
The register settings for the configuration described are as follows:
Reg 35 bit 7 = 1
Reg 35 bit 6 = 0
Reg 35 bit 4 = x
Reg 64 bit (2:0) = E3 (110) or DS3 (111), see Table 3
Reg 65 bit 7 = 0
Reg 65 bit 6 = 0
Reg 65 bit (5:4) = xx
Reg 65 bit (2:0) = 12 E1 (010), 16 E1 (011), 16 DS1 (101) or 24 DS1 (100), see Table 2
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PLL Configurations for ACS8530
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2.7
APPLICATION NOTE
T4 PLL Configured to Measure the Relative Phase Error between Inputs
The T4 DPLL PFD can be configured to measure the phase difference of the currently locked to input on
the T0 DPLL with respect to any other valid input.
The T4 DPLL PFD compares two inputs (usually the feedback and reference input) with each other and
performs some filtering. This filtering has a bandwidth of approx. 100 Hz. This will result in a digital
number representing the filtered phase difference between these two signals being available (normally
used for the digital synthesis).
The phase difference is reported in units of 0.707 degrees of the actual locking frequency. When direct
locking to high frequency input, the actual time is then scaled down and will give resolution down to e.g.
110 ps at 19.44 MHz in direct locking mode compared with 245 ns with Lock8K mode enabled with the
same 19.44 MHz input. The two inputs to the PFD have to be very close in frequency to give an accurate
phase measurement.
The phase difference measurement is held in the 16 bit register, sts_current_phase. The register is
updated on a 204.8 MHz cycle.
Under normal circumstances the frequency of the inputs to the PFD are determined by the input
frequency selection and the pre-divider mode settings such as Lock8K and DivN. The appropriate
feedback frequency is automatically selected from the supported spot frequencies to match the input
reference frequency (post division if necessary).
The feature to use the T4 PFD to measure the relative phase error between the selected T0 input and
the selected T4 input will require the user to ensure that the settings and frequency are the same for the
two inputs to be measured. Enabling the feature simply replaces the T4 DPLL feedback signal to the T4
PFD with the T0 PFD input reference signal. Reading the current phase register from the T4 path will yield
the filtered phase difference between the two inputs. If there is jitter or wander present on either or both
inputs, then this will have an effect on the measured phase. The extent of this effect will depend on the
frequency of the jitter/wander compared to the 100 Hz bandwidth of the filter.
The T4 PFD configuration is shown in Figure 9.
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PLL Configurations for ACS8530
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Figure 9
APPLICATION NOTE
T4 PFD configured to perform Phase Offset Measurement between selected T0 input and a
standby.
Select stand-by source
path6
The register settings for the configuration described are as follows:
Reg 35 bit 7 = 0
Reg 35 bit 6 = x
Reg 35 bit 4 = x
Reg 64 bit (2:0) = xxx
Reg 65 bit 7 = 1
Reg 65 bit 6 = 1 (if required)
Reg 65 bit (5:4) = 12 E1 (00), 16 E1 (01), 16 DS1 (11) or 24 DS1 (10) - see Table 1
Reg 65 bit (2:0) = 000
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2.7.1
APPLICATION NOTE
Examples of T4 PFD used for Phase Measurement
Table 1 gives examples of possible outcomes when T4 PFD used to measure phase between two valid
input reference sources, where the ACS8530 has following valid inputs:
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
inactive
inactive
19.44 MHz, direct locking
19.44 MHz, direct locking
77.76 MHz, Lock8K enabled
77.76 MHz, Lock8K enabled
2.048 MHz, direct locking
2.048 MHz, direct locking
10 MHz, DivN to 8 kHz enabled
10 MHz, DivN to 8 kHz enabled
inactive
inactive
inactive
inactive
Table 1 Phase measurement examples using T4 PFD
Example T0 Path Input Selection
Case 1
I3
Case 2
I5
Case 3
Case 4
2.8
I3
I3
T4 Input Selection
I4
Result/Problems
Meaningful result
Any other input
Result not meaningful
I6
Can measure result, but phase error in 245 ns resolution
due to locking at 8 kHz (period of 77.76 MHz is 13 ns)
Any other input
Result not meaningful
I8
Meaningful result
Any other input
Result not meaningful
I10
Can measure result, but phase error in 245 ns resolution
due to locking at 8 kHz (period of 10 MHz is 100 ns)
Any other input
Result not meaningful
T4 Low Frequency Outputs
The TO8 output is an AMI composite clock output. This always produces a 64 kHz/8 kHz composite
clock. TO9 always produces an E1/DS1 frequency output for a BITS/SSU application. Both TO8 and TO9
are generated by DFS within either the T0 or T4 path, as controlled by Register 35 Bit 4. The frequencies
generated from TO8 and TO9 are independent of the mode (frequency) of either the T4 or the T0 paths.
The amount of jitter generated on the TO8 and TO9 outputs will be related to the clock period of the
source DFS block added to any jitter present on that clock. This is detailed in the following text. As can
be seen in the block diagram in Figure 1, the DFS blocks used to generate these outputs are the T4
feedback DFS block in the case of the T4 path and the T0 LF output DFS block for the T0 path. The T4
feedback DFS block is clocked by the T4 forward DFS, or its APLL. The frequency of the T4 forward DFS
block can be determined by referring to the ACS8530 data sheet, Table 13 (T4 APLL frequencies). This
is in the region of 65 MHz to 89 MHz and can be approximated to have a period of between 11 ns and
15 ns. The output of the T4 forward DFS block will have an inherent pk-pk jitter of approximately 4.9 ns.
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APPLICATION NOTE
The clock to the T4 feedback DFS block will have <1 ns of jitter when the T4 path is in analog feedback
mode (Reg. 35 Bit 6 = 0). However, it will have 4.9 ns when in digital feedback mode.
The TO8 output, being 64 kHz/8 kHz, can be directly divided from the clock to the T4 feedback DFS
block; therefore, it will have a similar amount of jitter on it, i.e. <1 ns when using analog feedback, and
4.9 ns when using digital feedback.
The TO9 output will have more jitter because it is synthesized from the clock to the T4 feedback DFS
block. The jitter, in addition to that present on the clock to the T4 feedback DFS block, will be equivalent
to a period of that clock, i.e. between 11 ns and 15 ns.
The jitter present on the TO9 output will range from 11 ns (when the T4 path is in DS3 mode - 89 MHz
combined with analog feedback) to 20 ns (when in 16 x E1 mode - 65 MHz combined with digital
feedback).
Appendix 1
Register definitions for configuration of the T0 and T4 paths used in the text, the default is in BOLD.
Register 35 - cnfg_T4_Path
Bit 7
Lock_T4_to_T0
Bit selects either the T4 direct inputs, or T0 DPLL as the input of the T4 path. This allows the T4
DPLL to be used to produce different sets of frequencies to the T0 DPLL but still maintain lock.
Bit 6
0
T4 path locks independently from the T0 path.
1
T4 DPLL locks to the output of the T0 DPLL.
T4_dig_feedback
Bit to select digital feedback mode for the T4 DPLL.
0
T4 DPLL in analog feedback mode.
1
T4 DPLL in digital feedback mode.
Bit 5
Not used.
Bit 4
T4_op_from_T0
0
T08 and T09 will be generated from T4 DPLL.
1
T08 and T09 will be generated from T0 DPLL.
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PLL Configurations for ACS8530
ADVANCED COMMUNICATIONS
APPLICATION NOTE
Register 64 - cnfg_T4_PLL_Freq
Bits [2:0] T4_DPLL_frequency
Register to configure the frequency of operation of the DPLL in the T4 path. The frequency of the
DPLL will also affect the frequency of the T4 APLL which, in turn, affects the frequencies
available at outputs TO1 - TO7. It is also possible to not use the T4 DPLL at all, but use the T4
APLL to run directly from the T0 DPLL output, see Register 65 (cnfg_T0_DPLL_frequency).
000
T4 DPLL squelched (clock off).
001
77.76 MHz (OC-N rates), T4 APLL frequency = 311.04 MHz.
010
12E1, T4 APLL frequency = 98.304 MHz.
011
16E1, T4 APLL frequency = 131.072 MHz.
100
24DS1, T4 APLL frequency = 148.224 MHz.
101
16DS1, T4 APLL frequency = 98.816 MHz.
110
E3, T4 APLL frequency = 274.944 MHz.
111
DS3, T4 APLL frequency = 178.944 MHz.
Register 65 - cnfg_T0_DPLL_Frequency
Bit 7
T4_meas_T0_ph
Register bit to control the feature to use the T4 path to measure phase offset from the T0 path.
When enabled the T4 path is disabled and the phase detector is used to measure the phase
between the input to the T0 DPLL and the selected T4 input.
Bit 6
0
Normal - T4 Path normal operation.
1
T4 DPLL disabled, T4 phase detector used to measure phase between selected T0 input
and selectedT4 input.
T4_APLL_for_T0
Register bit to select whether the T4 APLL takes its input from the T4 DPLL or the T0 DPLL. If the
T0 DPLL is selected then the frequency is controlled by Bits [5:4], T0_freq_to_T4_APLL.
0
T4 APLL takes its input from the T4 DPLL.
1
T4 APLL takes its input from the T0 DPLL.
Bits [5:4] T0_freq_to_T4_APLL
Register to select the T0 frequency driven to the T4 APLL when selected by Bit 6,
T4_APLL_for_T0.
00
12E1, T4 APLL frequency = 98.304 MHz.
01
16E1, T4 APLL frequency = 131.072 MHz.
10
24DS1, T4 APLL frequency = 148.224 MHz.
11
16DS1, T4 APLL frequency = 98.816 MHz.
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Bit 3
APPLICATION NOTE
Not used
Bits [2:0] T0_DPLL_frequency
Register to configure the frequency of operation of the DPLL/APLL in the T0 path. This register
affects the frequencies available at outputs TO1 - TO7, see Reg. 60 - Reg. 63.
000
77.76 MHz, digital feedback, T0 APLL frequency = 311.04 MHz.
001
77.76 MHz, analog feedback, T0 APLL frequency = 311.04 MHz.
010
12E1, T0 APLL frequency = 98.304 MHz.
011
16E1, T0 APLL frequency = 131.072 MHz.
100
24DS1, T0 APLL frequency = 148.224 MHz.
101
16DS1, T0 APLL frequency = 98.816 MHz.
110
Not used.
111
Not used.
Table 2 T0 DPLL Frequency Configurations
T0 DPLL
Mode
OC-N
Frequencies available for selection at the outputs TO1-TO7 (MHz)
311.04
155.52
77.76
51.84
38.88
25.92
19.44
6.144
6.48
12E1
98.304
49.152
24.576
16.384
12.288
8.192
16E1
131.072
65.536
32.768
21.84533
16.384
10.922667 8.192
2.7306667
24DS1
148.224
74.112
37.056
24.704
18.528
12.352
3.088
16DS1
98.816
49.408
24.704
16.46933
12.352
8.2346667 6.176
9.264
2.048
2.0586667
Table 3 T4 DPLL Frequency Configurations
T4 DPLL Mode
Frequencies available for selection at the outputs TO1-TO7(MHz)
OC-N
155.52
77.76
38.88
19.44
6.48
4.86
12E1
49.152
24.576
12.288
6.144
2.048
1.536
16E1
65.536
32.768
16.384
8.192
2.7306667
2.048
24DS1
74.112
37.056
18.528
9.264
3.088
2.316
16DS1
49.408
24.704
12.352
6.176
2.0586667
1.544
E3
137.472
68.736
34.368
17.184
5.728
4.296
DS3
89.472
44.736
22.368
11.184
3.728
2.796
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PLL Configurations for ACS8530
ADVANCED COMMUNICATIONS
APPLICATION NOTE
Notes
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PLL Configurations for ACS8530
ADVANCED COMMUNICATIONS
APPLICATION NOTE
Revision History
Revision
Date
Reference
Description of changes
1.0
11/Apr/2002
All pages
First draft
1.01
16/Apr/2002
All Pages
2.1 bullets 4 & 5
New format
phase offset adjustment- resolution steps updated
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