ETC PI74LPT543AQ

PI74LPT543
3.3V
8-BIT
LATCHED
TRANSCEIVER
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PI74LPT543
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Fast CMOS 3.3V 8-Bit
Latched Transceiver
Product Features
Product Description
• Compatible with LCX™ and LVT™ families of products
• Supports 5V tolerant mixed signal mode operation
– Input can be 3V or 5V
– Output can be 3V or connected to 5V bus
• Advanced low power CMOS operation
• Excellent output drive capability:
Balanced drives (24 mA sink and source)
• Low ground bounce outputs
• Hysteresis on all inputs
• Industrial operating temperature range: –40°C to +85°C
• Packages available:
– 24-pin 173-mil wide plastic TSSOP (L)
– 24-pin 150-mil wide plastic QSOP (Q)
– 24-pin 150-mil wide plastic TQSOP (R)
– 24-pin 300-mil wide plastic SOIC (S)
Pericom Semiconductor’s PI74LPT series of logic circuits are produced in the Company’s advanced 0.6 micron CMOS technology,
achieving industry leading speed grades.
The PI74LPT543 is an 8-bit wide non-inverting transceiver designed
with two sets of eight D-type latches with separate input and output
controls for each set. For data flow from A to B, for example, the
A-to-B Enable (CEAB) input must be LOW in order to enter data
from A0–A7 or to take data from B0–B7, as indicated in the Truth
Table. With CEAB LOW, a LOW signal makes the A-to-B latches
transparent; a subsequent LOW-to-HIGH transition of the LEAB
signal puts the A latches in the storage mode and their outputs no
longer change the A inputs. With CEAB and OEAB both LOW, the
3-state B output buffers are active and reflect the data present at the
output of the A latches. Control of data from B to A is similar, but
uses the CEAB, LEAB, and OEAB inputs.
The PI74LPT543 can be driven from either 3.3V or 5.0V devices
allowing this device to be used as a translator in a mixed
3.3/5.0V system.
Logic Block Diagram
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PS2062A 01/15/97
PI74LPT543
3.3V
8-BIT
LATCHED
TRANSCEIVER
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Product Pin Configuration
LEBA
OEBA
A0
A1
A2
A3
A4
A5
A6
A7
CEAB
GND
Product Pin Description
1
24
2
23
3
22
4 24-PIN 21
L24
5
20
Q24
6
19
R24
7
18
S24
8
17
9
16
10
15
11
14
12
13
Pin Name
OEAB
OEBA
CEAB
CEBA
LEAB
LEBA
A0-A7
B0-B7
GND
VCC
VCC
CEBA
B0
B1
B2
B3
B4
B5
B6
B7
LEAB
OEAB
Description
A-to-B Output Enable Input (Active LOW)
B-to-A Output Enable Input (Active LOW)
A-to-B Enable Input (Active LOW)
B-to-A Enable Input (Active LOW)
A-to-B Latch Enable Input (Active LOW)
B-to-A Latch Enable Input (Active LOW)
A-to-B Data Inputs or B-to-A 3-State Outputs
B-to-A Data Inputs or A-to-B 3-State Outputs
Ground
Power
Truth Table (Non-Inverting)(1,2)
For A-to-B (Symmetric with B-to-A)
OEAB
Latch
Status
A-to-B
Output
Buffers
B0–B7
X
X
Storing
High-Z
X
H
X
Storing
X
X
X
H
X
High Z
L
L
L
Transparent
Current A Inputs
L
H
L
Storing
Previous* A Inputs
CEAB
Inputs
LEAB
H
Notes:
1. *Before LEAB LOW-to-HIGH Transition
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care or Irrevelant
2. A-to-B data flow shown; B-to-A flow control is the same,
except using CEBA, LEBA, and OEBA.
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PS2062A 01/15/97
PI74LPT543
3.3V
8-BIT
LATCHED
TRANSCEIVER
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ............................................................. –55°C to +125°C
Ambient Temperature with Power Applied ............................ –40°C to +85°C
Supply Voltage to Ground Potential (Inputs & Vcc Only) ...... –0.5V to +7.0V
Supply Voltage to Ground Potential (Outputs & D/O Only) .. –0.5V to +7.0V
DC Input Voltage .................................................................... –0.5V to +7.0V
DC Output Current .............................................................................. 120 mA
Power Dissipation .................................................................................... 1.0W
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC Electrical Characteristics (Over the Operating Range, TA = –40°C to +85°C, VCC = 2.7V to 3.6V)
Parameters
Description
IOZH
IOZL
VIK
IODH
IODL
VOH
Input HIGH Voltage (Input pins)
Input HIGH Voltage (I/O pins)
Input LOW Voltage
(Input and I/O pins)
Input HIGH Current (Input pins)
Input HIGH Current (I/O pins)
Input LOW Current (Input pins)
Input LOW Current (I/O pins)
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
Output HIGH Current
Output LOW Current
Output HIGH Voltage
VOL
Output LOW Voltage
IOS
IOFF
VH
Short Circuit Current(4)
Power Down Disable
Input Hysteresis
VIH
VIL
IIH
IIL
Test Conditions(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
Min.
Typ(2)
Max.
Units
2.2
2.0
–0.5
—
—
—
5.5
5.5
0.8
V
V
V
—
—
—
—
—
—
–0.7
–60
90
—
3.0
3.0
—
—
0.2
0.3
–85
—
150
±1
±1
±1
±1
±1
±1
–1.2
–110
200
—
—
—
—
0.2
0.4
0.5
–240
±100
—
µA
µA
µA
µA
µA
µA
V
mA
mA
V
V
V
VCC = Max.
VIN = 5.5V
—
VCC = Max.
VIN = VCC
—
VCC = Max.
VIN = GND
—
VCC = Max.
VIN = GND
—
VCC = Max.
VOUT = 5.5V
—
VCC = Max.
VOUT = GND
—
VCC = Min., IIN = –18 mA
—
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
–36
VCC = 3.3V, VIN = VIH or VIL, VO = 1.5V(3)
50
VCC = Min.
IOH = –0.1 mA Vcc-0.2
VIN = VIH or VIL
IOH = –3 mA
2.4
VCC = 3.0V,
IOH = –8 mA
2.4(5)
VIN = VIH or VIL
IOH = –24 mA
2.0
VCC = Min.
IOL = 0.1 mA
—
VIN = VIH or VIL
IOL = 16 mA
—
IOL = 24 mA
—
VCC = Max.(3), VOUT = GND
–60
VCC = 0V, VIN or VOUT ≤ 4.5V
—
—
V
V
V
mA
µA
mV
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at Vcc = 3.3V, +25°C ambient and maximum loading.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. This parameter is guaranteed but not tested.
5. VOH = VCC – 0.6V at rated current.
Capacitance (TA = 25°C, f = 1 MHz)
Parameters(1)
CIN
COUT
Description
Test Conditions
Input Capacitance
Output Capacitance
VIN = 0V
VOUT = 0V
Typ.
Max.
Units
4.5
5.5
6
8
pF
pF
Note:
1. This parameter is determined by device characterization but is not production tested.
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PS2062A 01/15/97
PI74LPT543
3.3V
8-BIT
LATCHED
TRANSCEIVER
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Power Supply Characteristics
Parameters Description
Test Conditions(1)
Min.
Typ(2)
Max.
Units
ICC
Quiescent Power Supply Current
VCC = Max.
VIN = GND or VCC
0.1
10
µA
∆ICC
Quiescent Power Supply Current
TTL Inputs HIGH
VCC = Max.
VIN = VCC – 0.6V(3)
2.0
30
µA
ICCD
Dynamic Power Supply(4)
VCC = Max.,
Outputs Open
CEAB and
OEAB = GND
CEBA = VCC
One Bit Toggling
50% Duty Cycle
VIN = VCC
VIN = GND
50
75
µA/
MHz
IC
Total Power Supply
Current(6)
VCC = Max.,
Outputs Open
fI = 10 MHZ
50% Duty Cycle
CEAB and
OEAB = GND
CEBA = VCC
One Bit Toggling
VIN = VCC – 0.6V
VIN = GND
0.6
2.3
mA
VCC = Max.,
Outputs Open
fI = 2.5 MHZ
50% Duty Cycle
CEAB and
OEAB = GND
CEBA = VCC
8 Bits Toggling
VIN = VCC – 0.6V
VIN = GND
2.1
4.7(5)
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at Vcc = 3.3V, +25°C ambient.
3. Per TTL driven input; all other inputs at Vcc or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the Icc formula. These limits are guaranteed but not tested.
6. IC =IQUIESCENT + IINPUTS + IDYNAMIC
IC = ICC + ∆ICC DHNT + ICCD (fCP/2 + fINI)
ICC = Quiescent Current (ICCL, ICCH and ICCZ)
∆ICC = Power Supply Current for a TTL High Input
DH = Duty Cycle for TTL Inputs High
NT = Number of TTL Inputs at DH
ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices)
NCP = Number of Clock Inputs at fCP
fI = Input Frequency
NI = Number of Inputs at fI
All currents are in milliamps and all frequencies are in megahertz.
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PS2062A 01/15/97
PI74LPT543
3.3V
8-BIT
LATCHED
TRANSCEIVER
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Switching Characteristics over Operating Range(1)
Parameters
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tSU
tH
tW
Description
Conditions(2)
Propagation Delay Transparent
CL = 50 pF
Mode AN to BN or BN to AN
RL = 500Ω
Propagation Delay
LEBA to AN, LEAB to BN
Output Enable Time
OEBA or OEAB to AN or BN
CEBA or CEAB to AN or BN
Output Disable Time(3)
OEBA or OEAB to AN or BN
CEBA or CEAB to AN or BN
Setup Time, HIGH or LOW
AN or BN to LEBA or LEAB
Hold Time, HIGH or LOW
AN or BN to LEBA or LEAB
LEBA or LEAB Pulse Width LOW(3)
LPT543
Com.
(3)
Min.
Max.
LPT543A
Com.
(3)
Min.
Max.
LPT543C
Com.
(3)
Min.
Max. Units
2.5
8.5
2.5
6.5
2.5
5.3
ns
2.5
12.5
2.5
8.0
2.5
7.0
ns
2.0
12.0
2.0
9.0
2.0
8.0
ns
2.0
9.0
2.0
7.5
2.0
6.5
ns
3.0
—
2.0
—
2.0
—
ns
2.0
—
2.0
—
2.0
—
ns
5.0
—
5.0
—
5.0
—
ns
Notes:
1. Propagation Delays and Enable/Disable times are with Vcc = 3.3V ±0.3V, normal range. For Vcc = 2.7V, extended range, all
Propagation Delays and Enable/Disable times should be degraded by 20%.
2. See test circuit and wave forms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4. This parameter is guaranteed but not production tested.
5. Skew between any two outputs, of the same package, switching in the same direction. This parameter is guaranteed by design.
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
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PS2062A 01/15/97