FEATURES Multiple pins/software programmable input ranges: ±10V, ±5V, 10V, 5V iCMOS™ process technology Pins or serial SPI input ranges/mode selection Throughput: 670kSPS (AD7634) 250kSPS (AD7631) INL: ± 1.75 LSB (7± ppm of full scale) DNL: +2/-1 LSB 18-bit resolution with no missing codes Dynamic range: 102.5 dB typical SNR: 101 dB typical THD: -122 dB typical 5V internal reference: typical drift 7ppm/°C; TEMP output No pipeline delay (SAR architecture) Parallel (18, 16- or 8-bit bus) and serial 5 V/3.3 V interface SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible Power dissipation: 190 mW @ 670kSPS 75 mW @ 250kSPS Pb-free 48-lead LQFP and LFCSP (7x7mm) packages Pin compatible with other PulSAR ADCs APPLICATIONS Process control High speed data acquisition Digital signal processing Spectrum analysis Instrumentation Communications GENERAL DESCRIPTION The AD7631/AD7634 is an18-bit, charge redistribution successive approximation register (SAR) architecture analog-todigital converter (ADC) with programmable input ranges and mode selection via a dedicated write only serial interface (or by hardware pin-strapping). The device is fabricated on ADI’s patented iCMOS high voltage process. The device contains a high speed 18-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), and both serial and parallel system interface ports. Power consumption is automatically scaled with throughput (AD7634 in Impulse mode), making it ideal for battery-powered applications. It is available in Pb-free, 48-lead packages with operation specified from −40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM TEMP REFBUFIN REF REFGND VCC VEE DVDD DGND OVDD AD7631/ AD7634 AGND AVDD SERIAL PROGRAMMABLE PORT REF AMP IN+ SWITCHED CAP DAC IN- PDREF SPPCLK SPPDATA HW/SW SERIAL DATA PORT 18 D[17:0] BUSY CLOCK PARALLEL INTERFACE PDBUF PD OGND SPPEN REF CONTROL LOGIC AND CALIBRATION CIRCUITRY RD CS RESET D0/OB/2C CNVST WARP IMPULSE MODE0 -001 Preliminary Technical Data 18-Bit 250/670 kSPS PulSAR® Bipolar Programmable Inputs ADC AD7631/AD7634 MODE1 Figure 1. Table 1. PulSAR® Selection Type/kSPS Pseudo Differential True Bipolar True Differential 18-Bit Multichannel/ Simultaneous 100 to 250 AD7651, AD7660 AD7661 AD7610, AD7663 AD7675 AD7631 AD7678 500 to 570 AD7650 AD7652 AD7664 AD7666 AD7665 AD7676 AD7679 650 to 1000 AD7653 AD7667 AD7612, AD7671 AD7677 AD7634 AD7674 >1000 AD7621 AD7622 AD7623 AD7641 AD7643 AD7654 AD7655 PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Programmable input range and mode selection. Dedicated write only serial port used for selecting input range and mode select (mode select AD7634 only). Fast throughput The AD7634 is 670kSPS and the AD7631 is 250kSPS. Superior Linearity. No missing 18-bit code. +/- 1.75 LSB typical INL Internal Reference. 5 V internal reference with a typical drift of ±7 ppm/°C and on-chip TEMP sensor. Serial or Parallel Interface. Versatile parallel (18, 16- or 8-bit bus) or 2-wire serial interface arrangement compatible with 3.3 V, or 5 V logic. Rev. PrC Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD7631/AD7634 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................8 Applications....................................................................................... 1 ESD Caution...................................................................................8 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................9 Functional Block Diagram .............................................................. 1 Terminology .................................................................................... 13 Product Highlights ........................................................................... 1 Outline Dimensions ....................................................................... 14 Revision History ............................................................................... 2 Ordering Guide .......................................................................... 14 Specifications..................................................................................... 3 Timing Specifications....................................................................... 6 REVISION HISTORY Rev. PrC | Page 2 of 14 Preliminary Technical Data AD7631/AD7634 SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15V; VEE = -15V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter RESOLUTION ANALOG INPUT 1 Differential Voltage Range 0 to 5V 0 to 10V ±5V ±10V Operating Input Voltage Range 0 to 5V 0 to 10V ±5V ±10V Common Mode Voltage range 0 to 5V 0 to 10V Bipolar ranges Analog Input CMRR Input Current Input Current Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate Time between Conversions Complete Cycle Throughput Rate Complete Cycle Throughput Rate Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error 2 No Missing Codes Differential Linearity Error Transition Noise Bipolar Offset Error Bipolar Offset Error Temperature Drift Bipolar Full-Scale Error Bipolar Full-Scale Error Temperature Drift Power Supply Sensitivity Conditions Min 18 Typ Max VIN+ - VIN− VIN+ - VIN− VIN+ - VIN− VIN+ - VIN− -VREF -2VREF -2VREF -4VREF VREF 2VREF 2VREF 4VREF (VIN+, VIN−) to AGND (VIN+, VIN−) to AGND (VIN+, VIN−) to AGND (VIN+, VIN−) to AGND -0.1V -0.1V -VREF – 0.1V -2VREF – 0.1V VREF + 0.1V 2VREF + 0.1V VREF + 0.1V 2VREF + 0.1V VIN+, VIN− VIN+, VIN− VIN+, VIN− fIN = 100 kHz @ 670 kSPS throughput @ 250 kSPS throughput VREF/2 – 0.1V VREF – 0.2V –0.1V Unit Bits T AD7634 in Warp mode AD7634 in Warp mode AD7634 in Warp mode AD7634 in Normal mode AD7634 in Normal mode AD7634 in Impulse AD7634 in Impulse mode AD7631 AD7631 VREF/2 VREF 0 TBD TBD TBD 0 0 0 ±1.75 18 −1 AVDD = 5 V ± 5% Rev. PrC | Page 3 of 14 dB μA μA 1.49 670 1 1.75 570 2.22 450 4 250 1 VREF = 5V, PDREF = PDBUF = High VREF/2 + 0.1V VREF + 0.2V 0.1V +2 0.75 10 TBD ±60 TBD TBD μs kSPS ms μs kSPS μs kSPS μs kSPS LSB 3 Bits LSB LSB LSB ppm/°C LSB ppm/°C LSB AD7631/AD7634 Parameter AC ACCURACY Dynamic Range Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) –3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response INTERNAL REFERENCE Output Voltage Temperature Drift Line Regulation Turn-On Settling Time REFERENCE BUFFER REFBUFIN Input Voltage Range EXTERNAL REFERENCE Voltage Range Current Drain Current Drain TEMPERATURE PIN Voltage Output Temperature Sensitivity Output Resistance DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format 5 Pipeline Delay 6 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD VCC VEE Preliminary Technical Data Conditions VIN = ±5V, VIN = ±5V, VIN = ±5V, VIN = ±5V, VIN = ±5V, Min fIN = 2 kHz, -60dB fIN = 2 kHz fIN = 2 kHz fIN = 2 kHz fIN = 2 kHz Full-scale step PDREF = PDBUF = low REF @ 25°C –40°C to +85°C AVDD = 5 V ± 5% CREF = 10 μF PDREF = high Typ Max 102.5 101 122 -106 100 12 dB 4 dB dB dB dB MHz 1 5 ns ps rms ns 115 4.985 5.000 ±7 ±15 5 5.015 2.5 PDREF = PDBUF = high REF AD7634 @ 670 kSPS throughput AD7631 @ 250 kSPS throughput 5 TBD TBD TEMP @ 25°C –0.3 2.1 –1 –1 AVDD+0.1 5 5 15 -15 Rev. PrC | Page 4 of 14 V μA μA mV mV/°C kΩ +0.6 OVDD+0.3 +1 +1 V V μA μA 0.4 V V 5.25 5.25 5.25 V V V V V OVDD − 0.6 4.75 4.75 2.7 V ppm/°C ppm/V ms V TBD 1 4 ISINK = 500 μA ISOURCE = −500 μA Unit Preliminary Technical Data Parameter Operating Current 7 AVDD 8 DVDD OVDD VCC VEE VCC VEE Power Dissipation With Internal Reference7 With Internal Reference7 Without Internal Reference Without Internal Reference7 In Power-Down Mode 9 TEMPERATURE RANGE 10 Specified Performance AD7631/AD7634 Conditions PDREF = PDBUF = low AD7631 @ 250kSPS throughput AD7634 @ 670kSPS throughput AD7631 @ 250kSPS throughput AD7634 @ 670kSPS throughput AD7631 @ 250kSPS throughput AD7634 @ 670kSPS throughput AD7631 @ 250kSPS throughput AD7631 @ 250kSPS throughput AD7634 @ 670kSPS throughput AD7634 @ 670kSPS throughput Min AD7631 @ 250kSPS throughput AD7634 @ 670kSPS throughput AD7631 @ 250kSPS throughput AD7634 @ 670kSPS throughput PD = high TMIN to TMAX −40 1 Typ Max 8.5 21 3.5 7 0.1 0.2 1 0.6 2.8 2 mA mA mA mA mA mA mA mA mA mA 75 190 62 160 2 mW mW mW μW +85 The inputs are differential anti-phase. Refer to the Error! Reference source not found. section. Linearity is tested using endnotes, not best fit. LSB means least significant bit. With the 0 to 5V input range, 1 LSB 38.15μV. 4 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified. 5 Parallel or serial 18-bit. 6 Conversion results are available immediately after completed conversion. 7 Tested in parallel reading mode. 8 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high. 9 With all digital inputs forced to OVDD. 10 Consult sales for extended temperature range. 2 3 Rev. PrC | Page 5 of 14 Unit °C AD7631/AD7634 Preliminary Technical Data TIMING SPECIFICATIONS AVDD = DVDD = 5 V; OVDD = 2.7 V to 5.5 V; VCC = 15V; VEE = -15V; VREF = 5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter CONVERSION AND RESET Convert Pulse Width Time Between Conversions (Warp Mode/Normal Mode 1 ) AD7631 AD7634 (Warp Mode/Normal Mode/Impulse Mode) 2 CNVST Low to BUSY High Delay BUSY High All Modes (Except Master Serial Read After Convert) AD7631 AD7634 (Warp Mode/Normal Mode/Impulse Mode) Aperture Delay End of Conversion to BUSY Low Delay Conversion Time AD7631 AD7634 (Warp Mode/Normal Mode/Impulse Mode) Acquisition Time AD7631 AD7634 (Warp Mode/Normal Mode/Impulse Mode) RESET Pulse Width Symbol Min Typ t1 t2 10 ns ns 4 1.49/1.75/2.22 μs μs ns 35 t3 t4 t5 t6 t7 Max Unit TBD TBD μs μs ns ns TBD TBD μs μs 2 10 t8 t9 250 250 10 ns ns ns PARALLEL INTERFACE MODES CNVST Low to DATA Valid Delay AD7631 AD7634 (Warp Mode/Normal Mode/Impulse Mode) DATA Valid to BUSY Low Delay Bus Access Request to DATA Valid Bus Relinquish Time t10 1.5 1/1.25/1.5 t11 t12 t13 45 15 μs μs ns ns ns 10 10 10 ns ns ns 12 5 MASTER SERIAL INTERFACE MODES 3 CS Low to SYNC Valid Delay CS Low to Internal SCLK Valid Delay CS Low to SDOUT Delay CNVST Low to SYNC Delay AD7631 AD7634 (Warp Mode/Normal Mode/Impulse Mode) SYNC Asserted to SCLK First Edge Delay Internal SCLK Period 4 Internal SCLK High4 Internal SCLK Low4 SDOUT Valid Setup Time4 SDOUT Valid Hold Time4 SCLK Last Edge to SYNC Delay4 CS High to SYNC HI-Z CS High to Internal SCLK HI-Z CS High to SDOUT HI-Z t14 t15 t16 t17 525 25/275/525 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 Rev. PrC | Page 6 of 14 3 25 12 7 4 2 3 40 10 10 10 ns ns ns ns ns ns ns ns ns ns ns ns Preliminary Technical Data AD7631/AD7634 Parameter Symbol Min Typ Max Unit See 4 BUSY High in Master Serial Read after Convert CNVST Low to SYNC Asserted Delay (all Modes) AD7631 AD7634 (Warp Mode/Normal Mode/Impulse Mode) SYNC Deasserted to BUSY Low Delay Table 4 t28 t29 t30 SLAVE SERIAL INTERFACE MODES External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK High External SCLK Low ns ns ns ns TBD TBD 25 t31 t32 t33 t34 t35 t36 t37 5 1 5 5 12.5 5 5 8 ns ns ns ns ns ns ns 1 In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time. 3 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. 4 In serial master read during convert mode. See Error! Reference source not found. for serial master read after convert mode timing specifications. 2 Table 4. Serial Clock Timings in Master Read After Convert Mode DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK High Minimum Internal SCLK Low Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum BUSY High Width Maximum (Warp mode) BUSY High Width Maximum (Normal mode) BUSY High Width Maximum (Impulse mode) Symbol t18 t19 t19 t20 t21 t22 t23 t24 t28 t28 t28 Rev. PrC | Page 7 of 14 0 0 3 25 40 12 7 4 2 3 1.75 2 2.25 0 1 17 60 80 22 21 18 4 60 2.5 2.75 3 1 0 17 120 160 50 49 18 30 140 4 4.25 4.5 1 1 17 240 320 100 99 18 89 300 7 7.25 7.5 Unit ns ns ns ns ns ns ns ns μs μs μs AD7631/AD7634 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Analog Inputs/Outputs IN+, IN−, REF, REFBUFIN, TEMP, INGND, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD OVDD AVDD to DVDD AVDD, DVDD to OVDD Digital Inputs PDREF, PDBUF Internal Power Dissipation1 Internal Power Dissipation2 Junction Temperature Storage Temperature Range Rating AVDD + 0.3 V to AGND − 0.3 V ±0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −0.3 V to +2.7 V −0.3 V to +3.8 V ±2.8 V −3.8 V to +2.8 V −0.3 V to +5.5 V ±20 mA 700 mW 2.5 W 125°C –65°C to +125°C 1. Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W, θJC = 30°C/W. 2. Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. 500µA TO OUTPUT PIN IOL 1.4V CL 50pF 2V 0.8V tDELAY tDELAY 2V 0.8V 2V 0.8V Figure 3. Voltage Reference Levels for Timing Figure 2. Load Circuit for Digital Interface Timing, SDOUT, SYNC, and SCLK Outputs, CL = 10 pF Rev. PrC | Page 8 of 14 04761-003 IOH 04761-002 500µA NOTE IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMING ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. Preliminary Technical Data AD7631/AD7634 REFGND REF IN– VCC VEE IN+ AGND AVDD PDBUF PDREF REFBUFIN TEMP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 48 47 46 45 44 43 42 41 40 39 38 37 36 BIPOLAR PIN 1 IDENTIFIER 35 CNVST MODE0 3 MODE1 4 D0/OB/2C 5 WARP 6 34 PD 33 RESET 32 CS AD7631/AD7634 31 RD TOP VIEW (Not to Scale) IMPULSE 7 30 TEN D1/A0 8 D2/A1 9 29 BUSY 28 D17/SPPEN D3 10 27 D16/SPPCLK D4DIVSCLK[0] 11 D5/DIVSCLK[1] 12 25 D14/HW/SW D13/RDERROR D11/SCLK D12/SYNC DVDD DGND D10/SDOUT OVDD D9/RDC/SDIN OGND 13 14 15 16 17 18 19 20 21 22 23 24 D6/EXT/INT D7/INVSYNC D8/INVSCLK NC = NO CONNECT 26 D15/SPPDATA -004 AGND 1 AVDD 2 Figure 4. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1, 42 2, 44 3, 4 Mnemonic AGND AVDD MODE[0:1] Type 1 P P DI 5 D0/OB/2C DI/O 6 WARP DI 7 IMPULSE DI 8 D1/A0 DI/O 9 D2/A1 DI/O 10 D3 D0 Description Analog Power Ground Pin. Input Analog Power Pins. Nominally 5 V. Data Output Interface Mode Selection. Interface MODE# MODE1 MODE0 Description 0 0 0 18-bit interface 1 0 1 16-bit interface 2 1 0 8-bit (byte) interface 3 1 1 Serial interface When MODE[1:0] = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows the choice of straight binary/twos complement. When OB/2C is high, the digital output is straight binary; when low, the MSB is inverted resulting in a twos complement output from its internal shift register. AD7634: Conversion Mode Selection. When WARP = high and IMPULSE = low, this selects warp mode. In this mode, the maximum throughput is achievable, and a minimum conversion rate must be applied to guarantee full specified accuracy. When WARP = low and IMPULSE = low, this selects normal mode where full accuracy is maintained independent of the minimum conversion rate. AD7631: Connect to DGND. AD7634: Conversion Mode Selection. When IMPULSE = high and WARP = low, this input selects impulse mode, a reduced power mode. In this mode, the power dissipation is approximately scaled proportional to the sampling rate. AD7631: Connect to DGND. When MODE[1:0] = 0, this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output as shown in Table 7. When MODE[1:0] = 0, this pin is Bit 2 of the parallel port data output bus. When MODE[1:0] = 1 or 2, this input pin controls the form in which data is output as shown in Table 7. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. Rev. PrC | Page 9 of 14 AD7631/AD7634 Pin No. 11, 12 Preliminary Technical Data Mnemonic D[4:5] or DIVSCLK[0:1] Type 1 DI/O 13 D6 or EXT/INT DI/O 14 D7 or INVSYNC DI/O 15 D8 or INVSCLK DI/O 16 D9 or RDC DI/O or SDIN 17 18 OGND OVDD P P 19 20 21 DVDD DGND D10 or SDOUT P P DO 22 D11 or SCLK DI/O 23 D12 or SYNC DO Description When MODE[1:0] = 0, 1, or 2, these pins are Bit 4 and Bit 5 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), serial clock division selection. When using serial master read after convert mode (EXT/INT = low, RDC/SDIN = low), these inputs can be used to slow down the internally generated serial clock that clocks the data output. In other serial modes, these pins are high impedance outputs. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 6 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), serial clock source select. This input is used to select the internally generated (master) or external (slave) serial data clock. When EXT/INT = low, master mode. The internal serial clock is selected on SCLK output. When EXT/INT = high, slave mode. The output data is synchronized to an external clock signal, gated by CS, connected to the SCLK input. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 7 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), invert sync select. In serial master mode (EXT/INT = low), this input is used to select the active state of the SYNC signal. When INVSYNC = low, SYNC is active high. When INVSYNC = high, SYNC is active low. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 8 of the parallel port data output bus. When MODE[1:0] = 3, invert SCLK select. In all serial modes, this input is used to invert the SCLK signal. When MODE[1:0] = 0, 1, or 2, this output is used as bit 9 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), read during convert. When using serial master mode (EXT/INT = low), RDC is used to select the read mode. When RDC = high, the previous conversion result is output on SDOUT during conversion and the period of SCLK changes. When RDC = low (read after convert), the current result can be output on SDOUT only when the conversion is complete. When MODE[1:0] = 3 (serial mode), serial data in. When using serial slave mode, (EXT/INT = high), SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after the initiation of the read sequence. Input/Output Interface Digital Power Ground. Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface (2.7 V to 5V). Digital Power. Nominally at 5 V. Digital Power Ground. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 10 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), serial data output. In serial mode, this pin is used as the serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The ADC provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In master mode, EXT/INT = low. SDOUT is valid on both edges of SCLK. In slave mode, EXT/INT = high: When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge. When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 11 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), serial clock. In all serial modes, this pin is used as the serial data clock input or output, depending upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends on the logic state of the INVSCLK pin. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 12 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), frame synchronization. In serial master mode (EXT/INT= low), this output is used as a digital output frame synchronization for use with the internal data clock. Rev. PrC | Page 10 of 14 Preliminary Technical Data Pin No. Mnemonic Type 1 24 D13 or RDERROR DO 25 D14 or HW/SW DI/O 26 D15 or SPPDATA DI/O 27 D16 or SPPCLK DI/O 28 D17 or SPPEN DI/O 29 BUSY DO 30 TEN DI 31 RD DI 32 CS DI 33 RESET DI 34 PD DI 35 CNVST DI 36 BIP DI 37 REF AI/O AD7631/AD7634 Description When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while SDOUT output is valid. When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while SDOUT output is valid. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 13 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), read error. In serial slave mode (EXT/INT = high), this output is used as an incomplete read error flag. If a data read is started and not completed when the current conversion is complete, the current data is lost and RDERROR is pulsed high. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 14 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode) hardware/software select. This input, part of the serial programmable port, is used to select hardware or software input ranges and mode selection. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 15 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), serial programmable port data. This input is used to write in the serial programmable port data when HW/SW = low. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 16 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), serial programmable port clock. This input is used to clock in the data on SPPDATA. The active edge where the data SPPDATA is updated depends on the logic state of the INVSCLK pin. When MODE[1:0] = 0, 1, or 2, this output is used as Bit 17 of the parallel port data output bus. When MODE[1:0] = 3 (serial mode), serial programmable port enable. Asserting this input enables the serial programmable port. Busy Output. Transitions high when a conversion is started and remains high until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used as a data-ready clock signal. 10 Volt Input Range. Refer to Table 8. When MODE[1:0] = 0, 1, or 2, this input is used to select the 10V input range. When MODE[1:0] = 3 (serial mode), and HW/SW = high, driving TEN high selects the 10 Volt input range. HW/SW = low, the input range is programmed with the serial programmable port and this pin is a don’t care. Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled. Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock in slave serial mode. Reset Input. When high, resets the ADC. Current conversion, if any, is aborted. Falling edge of RESET enables the calibration mode indicated by pulsing BUSY high. If not used, this pin can be tied to DGND. Power-Down Input. When high, power downs the ADC. Power consumption is reduced and conversions are inhibited after the current one is completed. Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a conversion. Bipolar Input Range. Refer to Table 8. When MODE[1:0] = 0, 1, or 2, this input is used to select the bipolar input range. When MODE[1:0] = 3 (serial mode), and HW/SW = high, driving BIP high selects the bipolar input range. HW/SW = low, the input range is programmed with the serial programmable port and this pin is a don’t care. Reference Output/Input. When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 5 V on this pin. When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal reference and buffer. Rev. PrC | Page 11 of 14 AD7631/AD7634 Preliminary Technical Data Pin No. 38 39 40 41 43 45 46 Mnemonic REFGND IN− VCC VEE IN+ TEMP REFBUFIN Type 1 AI AI P P AI AO AI/O 47 PDREF DI 48 PDBUF DI 1 Description Reference Input Analog Ground. Differential Negative Analog Input; referenced to IN+. High Voltage Positive Supply. High Voltage Negative Supply. Differential Positive Analog Input; referenced to IN-. Temperature Sensor Analog Output. Reference Buffer Input. When using an external reference with the internal buffer (PDBUF = low, PDREF = high), applying 2.5V on this pin produces 5V on the REF pin. When using the internal reference (PDBUF = PDREF = low), this pin should not be connected. Internal Reference Power-Down Input. When low, the internal reference is enabled (PDBUF also needs to be low). When high, the internal reference is powered down and an external reference must been used. Internal Reference Buffer Power-Down Input. When low, the buffer is enabled (PDREF also needs to be low). When high, the buffer is powered-down and an external reference must be used. AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power. Table 7. Data Bus Interface Definition MODE MODE1 MODE0 0 1 0 0 0 1 1 0 1 2 1 0 2 1 0 2 1 0 2 1 0 3 1 1 D0/OB/2C R[0] OB/2C D1/A0 D2/A1 D[3] D[4:9] D[10:11] D[12:15] D[16:17] Description R[1] A0 = 0 R[2] R[2] R[3] R[3] R[4:9] R[4:9] R[10:11] R[10:11] R[12:15] R[12:15] R[16:17] R[16:17] 18-Bit Parallel 16-Bit High Word OB/2C OB/2C A0 = 1 R[0] R[1] A0 = 0 A1 = 0 All Hi-Z R[10:11] R[12:15] R[16:17] 8-Bit High Byte OB/2C OB/2C A0 = 0 A1 = 1 All Hi-Z R[2:3] R[4:7] R[8:9] 8-Bit Mid Byte A0 = 1 A1 = 0 All Hi-Z R[0:1] OB/2C OB/2C A0 = 1 A1 = 1 All Hi-Z All Hi-Z Table 8. Input Range Selection. Parallel Mode and Serial Hardware Mode 1 Range BIP TEN 0 - 5V 0 - 10V ±5V ±10V All Ranges 1 Low Low High High X Low High Low High X HW/SW (serial mode) High High High High Low In serial mode (MODE[1:0] = 3) when HW/SW = low, the input ranges are defined by registers. Rev. PrC | Page 12 of 14 All Zeros 16-Bit Low Word All Zeros All Zeros Serial Interface R[0:1] 8-Bit Low Byte 8-Bit Low Byte Serial Interface Preliminary Technical Data AD7631/AD7634 TERMINOLOGY Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Gain Error The first transition (from 000…00 to 000…01) should occur for an analog voltage ½ LSB above the nominal negative full scale (19.073486 V for the 0 to 5V range). The last transition (from 111…10 to 111…11) should occur for an analog voltage 1½ LSB below the nominal full scale (+4.999943 V for the 0 to 5V V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. Signal to (Noise + Distortion) Ratio (SINAD) SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD and is expressed in bits by ENOB = [(SINADdB − 1.76)/6.02] Aperture Delay Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Zero Error The zero error is the difference between the ideal midscale input voltage (0 V) and the actual voltage producing the midscale output code. Transient Response The time required for the AD7641 to achieve its rated accuracy after a full-scale step function is applied to its input. Dynamic Range It is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. It is derived from the typical shift of output voltage at 25°C on a sample of parts maximum and minimum reference output voltage (VREF) measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C using Reference Voltage Temperature Coefficient Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. TCVREF (ppm/°C ) = VREF ( Max ) − VREF ( Min) × 106 VREF (25°C ) × (TMAX − TMIN ) where: VREF (Max) = Maximum VREF at TMIN, T(25°C), or TMAX VREF (Min) = Minimum VREF at TMIN, T(25°C), or TMAX VREF (25°C) = VREF at 25°C TMAX = +85°C TMIN = –40°C Rev. PrC | Page 13 of 14 AD7631/AD7634 Preliminary Technical Data OUTLINE DIMENSIONS 0.75 0.60 0.45 9.00 BSC SQ 1.60 MAX 37 48 36 1 PIN 1 7.00 BSC SQ TOP VIEW 1.45 1.40 1.35 0.15 0.05 (PINS DOWN) 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY SEATING PLANE 25 12 13 24 0.27 0.22 0.17 VIEW A 0.50 BSC LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BBC Figure 5. 48-Lead Low Profile Quad Flat Package [LQFP] (ST-48) Dimensions shown in millimeters 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR TOP VIEW 12° MAX PIN 1 INDICATOR 48 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 25 24 13 12 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE 1 EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 0.30 0.23 0.18 0.20 REF PADDLE CONNECTED TO AGND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES. COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 6. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model AD7641BCPZ 1 AD7641BCPZRL1 AD7641BSTZ1 AD7641BSTZRL1 EVAL-AD7641CB 2 EVAL-CONTROLBRD3 3 1 2 3 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 48-Lead Low Profile Quad Flat Package (LQFP) 48-Lead Low Profile Quad Flat Package (LQFP) Evaluation Board Controller Board Package Option CP-48-1 CP-48-1 ST-48 ST-48 Z = Pb-free part. This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes. This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06004-0-6/06(PrC) T T Rev. PrC | Page 14 of 14