87C196CA 18 MHz Advanced 16-Bit CHMOS Microcontroller Automotive Datasheet Product Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ –40°C to +125 °C Ambient High Performance CHMOS 16-Bit CPU 32 Kbytes of On-Chip EPROM 1.0 Kbytes of On-Chip Register RAM 256 Bytes of Additional RAM (Code RAM) Register-Register Architecture SixChannel/10-Bit A/D with Sample/Hold Up to 37 Prioritized Interrupt Sources 38 I/O Ports Full Duplex Serial I/O Port Dedicated Baud Rate Generator Interprocessor Communication Slave Port ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High Speed Peripheral Transaction Server (PTS) Two 16-Bit Software Timers Six High Speed Capture/Compare (EPA) Full Duplex Synchronous Serial I/O Port (SSIO) Two Flexible 16-Bit Timer/Counters Quadrature Counting Inputs Flexible 8-/16-Bit External Bus Programmable Bus (HLD/HLDA) 1.75 µs 16 x 16 Multiply 3 µs 32/16 Divide 68-Pin PLCC Package Supports CAN (Controller Area Network) Specification 2.0 Order Number: 273187-001 June, 1998 Information in this document is provided in connection with Intel products. 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Datasheet Automotive — 87C196CA 18 MHz Microcontroller Contents 1.0 Introduction .................................................................................................................. 1 2.0 Architecture .................................................................................................................. 2 2.1 2.2 2.3 2.4 CPU Features........................................................................................................ 2 Peripheral Features............................................................................................... 2 New Instructions.................................................................................................... 2 2.3.1 XCH/XCHB ............................................................................................... 2 2.3.2 BMOVi ...................................................................................................... 2 2.3.3 TIJMP ....................................................................................................... 3 2.3.4 EPTS/DPTS ............................................................................................. 3 SFR Operation ...................................................................................................... 3 3.0 Packaging Information ............................................................................................. 5 4.0 Electrical Characteristics ........................................................................................ 8 4.1 4.2 4.3 4.4 5.0 Design Considerations ..........................................................................................23 5.1 6.0 Datasheet Absolute Maximum Ratings................................................................................... 8 Operating Conditions............................................................................................. 8 DC Characteristics ................................................................................................ 9 AC Characteristics...............................................................................................11 4.4.1 Explanation of AC Symbols....................................................................16 4.4.2 EPROM Specifications ...........................................................................16 4.4.3 A to D Converter Specifications .............................................................18 4.4.4 AC Characteristics—Slave Port .............................................................20 4.4.5 AC Characteristics—Serial Port— Shift Register Mode .........................22 4.4.6 Waveform—Serial Port—Shift Register Mode 0 ....................................22 87C196CA Design Considerations......................................................................23 Revision History .......................................................................................................25 3 87C196CA 18 MHz Microcontroller — Automotive Figures 1 2 3 4 5 6 7 8 9 10 11 13 14 15 Block Diagram....................................................................................................... 3 87C196CA Nomenclature ..................................................................................... 4 87C196CA 68-Pin PLCC Package Diagram ......................................................... 5 87C196CA ICC vs. Frequency ............................................................................. 10 System Bus Timing ............................................................................................. 13 READY Timing .................................................................................................... 14 External Clock Drive Waveforms ........................................................................ 14 AC Testing Input, Output Waveforms ................................................................. 15 Float Waveforms ................................................................................................. 15 Slave Programming Mode Data Program Mode with Single Program Pulse ...... 17 Slave Programming Mode in Word Dump or Data Verify Mode with Auto Increment ............................................................................................ 17 Slave Programming Mode Timing in Data Program Mode with Repeated PROG Pulse and Auto Increment ............................................... 18 Slave Port Waveform (SLPL = 0) ........................................................................ 20 Slave Port Waveform (SLPL = 1) ........................................................................ 21 Serial Port Waveform—Shift Register Mode ....................................................... 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 87C196Kx and Jx Features Summary .................................................................. 1 Pin Descriptions .................................................................................................... 6 Absolute Maximum Ratings .................................................................................. 8 Operating Conditions ............................................................................................ 8 DC Characteristics ................................................................................................ 9 AC Characteristics .............................................................................................. 11 External Clock Drive............................................................................................ 14 Thermal Characteristics ...................................................................................... 15 AC EPROM Programming Characteristics.......................................................... 16 DC EPROM Programming Characteristics ......................................................... 17 A/D Operating Conditions ................................................................................... 18 A/D Operating Parameter Values........................................................................ 19 Slave Port Timing–(SLPL = 0)............................................................................. 20 Slave Port Timing–(SLPL = 1)............................................................................. 21 Serial Port Timing—Shift Register Mode ............................................................ 22 12 Tables 4 Datasheet Automotive — 87C196CA 18 MHz Microcontroller 1.0 Introduction The MCS 96 microcontroller family members are all high performance microcontrollers with a 16-bit CPU. The 87C196CA family members are composed of the high-speed (18 MHz) core as well as the following peripherals: • 32 Kbytes of Programmable EPROM • 1.0 Kbytes of register RAM and 512 bytes of code RAM (16-bit addressing modes) with the ability to execute from this RAM space • Six–10-Bit/ ± 3 LSB analog to digital converter with programmable S/H times with conversion times < 5 µs at 16 MHz • An asynchronous/synchronous serial I/O port (8096 compatible) with a dedicated 16-bit baud rate generator • • • • Interprocessor communication slave port Synchronous serial I/O port with full duplex master/slave transceivers A flexible timer/counter structure with prescaler, cascading, and quadrature capabilities Six modularized multiplexed high speed I/O for capture and compare (called Event Processor Array) with 250 ns resolution and double buffered inputs • A sophisticated prioritized interrupt structure with programmable Peripheral Transaction Server (PTS). The PTS has several channel modes, including single/burst block transfers from any memory location to any memory location, a PWM and PWM toggle mode to be used in conjunction with the EPA, and an A/D scan mode. • Serial communications protocol CAN 2.0 with 15 message objects of 8 bytes data length The 87C196CA device is a member of the fourth generation of MCS® 96 microcontroller products implemented on Intel’s advanced 1 micron process technology. This product is based on the 80C196KB device with improvements for automotive applications. The instruction set is a true super set of 80C196KB. The 87C196CA device is a memory scalar of the 87C196KR in a 68-pin package with 32 Kbytes of on-chip EPROM, 1.0 Kbytes of register RAM, and 256 bytes of code RAM. In addition, the 87C196CA contains an extra peripheral for serial communications protocol CAN 2.0. Table 1 summarizes the features of the 87C196CA device. Table 1. 87C196Kx and Jx Features Summary Device 87C196CA Datasheet Pins/Package 68-Pin PLCC EPROM Reg RAM Code RAM I/O EPA SIO SSIO A/D 32 K 1.0 K 256 38 6 Y Y 6 1 87C196CA 18 MHz Microcontroller — Automotive 2.0 Architecture The 87C196CA is a member of the MCS 96 microcontroller family, has the same architecture and use the same instruction set as the 80C196KB/KC. Many new features have been added including: 2.1 CPU Features • • • • • • • • • • 2.2 Powerdown and Idle Modes 18 MHz Operating Frequency A High Performance Peripheral Transaction Server (PTS) Up to 37 Interrupt Vectors 256 Bytes of Code RAM 1.0 Kbytes of Register RAM “Windowing” Allows 8-Bit Addressing to Some 16-Bit Addresses 1.75 µs 16 x 16 Multiply 3 µs 32/16 Divide Oscillator Fail Detect Peripheral Features • • • • • • Programmable A/D Conversion and S/H Times Six Capture/Compare I/O with 2 Flexible Timers Synchronous Serial I/O Port for Full Duplex Serial I/O Total Utilization of ALL Available Pins (I/O Mux’d with Control) Two 16-Bit Timers with Prescale, Cascading and Quadrature Counting Capabilities Up to 12 Externally Triggered Interrupts 2.3 New Instructions 2.3.1 XCH/XCHB Exchange the contents of two locations, either Word or Byte is supported. 2.3.2 BMOVi Interruptable Block Move Instruction, allows the user to be interrupted during long executing Block Moves. 2 Datasheet Automotive — 87C196CA 18 MHz Microcontroller 2.3.3 TIJMP Table Indirect JUMP. This instruction incorporates a way to do complex CASE level branches through one instruction. An example of such code savings: several interrupt sources and only one interrupt vector. The TIJMP instruction will sort through the sources and branch to the appropriate sub-code level in one instruction. This instruction was added especially for the EPA structure, but has other code saving advantages. 2.3.4 EPTS/DPTS Enable and Disable PTS Interrupts (Works like EI and DI). 2.4 SFR Operation The 87C196CA device contains 512 bytes of SFR registers to support the wide range of on-chip peripherals. The memory space 1F00-1FFFh has the ability to be addressed as direct 8-bit addresses through the “windowing” technique. The memory space 1E00-1EFFh is reserved for CAN functions. Figure 1. Block Diagram XTAL1 XTAL2 Clock Generator On-chip EPROM (optional) Code RAM Peripheral Register Transaction RAM Server (PTS) 16 ALU Power and GND Memory Controller with Prefetch Queue VCC VSS VSS VSS Control Signals ADDR/ Data Bus 16 Programmable Interrupt Controller I/O Ports Timer 1 & 2 PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 SC0 SC1 SD0 SD1 TXD RXD ACH0 - 7 Serial I/O (UART & SSIO) Event Processor Array (EPA) EPA0 - 9 ANGND A/D Converter (10-Bit) [8 Channels] T1CLK T1DIR T2CLK T2DIR VREF A4643-01 Datasheet 3 87C196CA 18 MHz Microcontroller — Automotive Figure 2. 87C196CA Nomenclature A N 8 7 C 1 9 6 CA 1 8 Frequency Designation Product Designation Product Family CHMOS Technology Program Memory Options: 7 = EPROM, OTP, QROM Package Type Options: N = PLCC (plastic leaded chip carrier) Temperature and Burn-in Options: A = -40˚C to +125˚C ambient with Intel Standard Burn-in A4704-01 4 Datasheet Automotive — 87C196CA 18 MHz Microcontroller 3.0 Packaging Information 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 WR# / P5.2 WRH# / P5.5 RD# / P5.3 VPP VSS ALE / P5.0 READY / P5.6 P5.4 VSS1 XTAL1 XTAL2 RXCAN TXCAN SD1 / P6.7 SC1 / P6.6 SD0 / P6.5 SC0 / P6.4 Figure 3. 87C196CA 68-Pin PLCC Package Diagram 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 87C196CA18 68 – ld PLCC View of component as mounted on PC board 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 NC NC VCC EPA9 / P6.1 EPA8 / P6.0 EPA0 / P1.0 / T2CLK EPA1 / P1.1 EPA2 / P1.2 / T2DIR EPA3 / P1.3 NC VREF ANGND ACH7 / P0.7 ACH6 / P0.6 ACH5 / P0.5 ACH4 / P0.4 NC P3.1 / AD1 P3.0 / AD0 RESET# NMI EA# VSS1 VCC VSS TXD / P2.0 RXD / P2.1 EXTINT / P2.2 P2.4 P2.6 CLKOUT / P2.7 ACH2 / P0.2 ACH3 / P0.3 NC 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 NC AD15 / P4.7 AD14 / P4.6 AD13 / P4.5 AD12 / P4.4 AD11 / P4.3 AD10 / P4.2 AD9 / P4.1 AD8 / P4.0 AD7 / P3.7 AD6 / P3.6 AD5 / P3.5 AD4 / P3.4 AD3 / P3.3 AD2 / P3.2 NC NC A5926-01 Datasheet 5 87C196CA 18 MHz Microcontroller — Automotive Table 2. Pin Descriptions (Sheet 1 of 2) Symbol 6 Name and Function VCC Main supply voltage (+5 V). VSS Digital circuit ground (0 V). There are three VSS pins, all of which MUST be connected to a single ground plane. VREF Reference for the A/D converter (+5 V). VREF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. VPP Programming voltage for the EPROM parts. It should be +12.5 V for programming. It is also the timing pin for the return from powerdown circuit. Connect this pin with a 1 µF capacitor to VSS and a 1 MΩ resistor to VCC. If this function is not used, VPP may be tied to VCC. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. XTAL1 Input of the oscillator inverter and the internal clock generator. XTAL2 Output of the oscillator inverter. P2.7/CLKOUT Output of the internal clock generator. The frequency is ½ the oscillator frequency. It has a 50% duty cycle. Also LSIO pin when not used as CLKOUT. RESET# Reset input to the chip. Input low for at least 16 state times will reset the chip. The subsequent low to high transition resynchronizes CLKOUT and commences a 10state time sequence in which the PSW is cleared, bytes are read from 2018H and 201AH loading the CCBs, and a jump to location 2080H is executed. Input high for normal operation. RESET# has an internal pullup. NMI A positive transition causes a non-maskable interrupt vector through memory location 203EH. EA# Input for memory select (External Access). EA# equal to a high causes memory accesses within the [EP]ROM address space to be directed to on-chip EPROM/ ROM. EA# equal to a low causes accesses to these locations to be directed to offchip memory. EA# = +12.5 V causes execution to begin in the Programming Mode. EA# latched at reset. P5.0/ALE/ADV# Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a latch to demultiplex the address from the address/data bus. When the pin is ADV#, it goes inactive (high) at the end of the bus cycle. ADV# can be used as a chip select for external memory. ALE/ADV# is active only during external memory accesses. Also LSIO when not used as ALE. P5.3/RD# Read signal output to external memory. RD# is active only during external memory reads. LSIO when not used as RD#. P5.2/WR#/WRL# Write and Write Low output to external memory, as selected by the CCR, WR# will go low for every external write, while WRL# will go low only for external writes where an even byte is being written. WR#/WRL# is active during external memory writes. Also an LSIO pin when not used as WR#/WRL#. P5.5/BHE#/WRH# Byte High Enable or Write High output, as selected by the CCR. BHE# = 0 selects the bank of memory that is connected to the high byte of the data bus. A0 = 0 selects that bank of memory that is connected to the low byte. Thus accesses to a 16-bit wide memory can be to the low byte only (A0 = 0, BHE# =1), to the high byte only (A0 = 1, BHE# = 0) or both bytes (A0 = 0, BHE# = 0). If the WRH# function is selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE#/WRH# is only valid during 16-bit external memory write cycles. Also an LSIO pin when not BHE#/WRH#. Datasheet Automotive — 87C196CA 18 MHz Microcontroller Table 2. Pin Descriptions (Sheet 2 of 2) Symbol Datasheet Name and Function P5.6/READY Ready input to lengthen external memory cycles, for interfacing with slow or dynamic memory, or for bus sharing. If the pin is high, CPU operation continues in a normal manner. If the pin is low prior to the falling edge of CLKOUT, the memory controller goes into a wait state mode until the next positive transition in CLKOUT occurs with READY high. When external memory is not used, READY has no effect. The max number of wait states inserted into the bus cycle is controlled by the CCR/CCR1. Also an LSIO pin when READY is not selected. P5.4/SLPINT Dual functional I/O pin. As a bidirectional port pin (LSIO) or as a system function. The system function is a Slave Port Interrupt Output Pin. P6.2/T1CLK Dual function I/O pin. Primary function is that of a bidirectional I/O pin (LSIO); however it may also be used as a TIMER1 Clock input. The TIMER1 will increment or decrement on both positive and negative edges of this pin. P6.3/T1DIR Dual function I/O pin. Primary function is that of a bidirectional I/O pin (LSIO); however it may also be used as a TIMER1 Direction input. The TIMER1 will increment when this pin is high and decrements when this pin is low. PORT1/EPA0–3 P6.0–6.1/EPA8–9 Dual function I/O port pins. Primary function is that of bidirectional I/O (LSIO). System function is that of High Speed capture and compare. EPA0 and EPA2 have yet another function of T2CLK and T2DIR of the TIMER2 timer/counter. PORT 0/ACH2–7 6-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. These pins are also used as inputs to EPROM parts to select the Programming Mode. P6.4–6.7/SSIO Dual function I/O ports that have a system function as Synchronous Serial I/O. Two pins are clocks and two pins are data, providing full duplex capability. PORT 2 6-bit multi-functional port. All of its pins are shared with other functions. PORT 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus which has strong internal pullups. TXCAN Push-pull output to the CAN bus line. RXCAN High-impedance input-only from the CAN bus line. 7 87C196CA 18 MHz Microcontroller — Automotive 4.0 Electrical Characteristics Note: This document contains information on products in production. The specifications are subject to change without notice. 4.1 Absolute Maximum Ratings Table 3. Absolute Maximum Ratings Parameter Storage Temperature –60°C to +150°C Voltage from VPP or EA# to VSS or ANGND –0.5 V to +13.0 V Voltage from any other pin to VSS or ANGND –0.5 V to +7.0 V Power Dissipation Warning: Maximum Rating 0.5 W Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. 4.2 Operating Conditions Table 4. Operating Conditions Parameter TA (Ambient Temperature Under Bias) Values –40°C to +125°C VCC (Digital Supply Voltage) 4.75 V to 5.25 V VREF (Analog Supply Voltage) (Notes 1, 2) 4.75 V to 5.25 V FOSC (Oscillator Frequency): 4 MHz to 18 MHz(2) NOTE: 1. ANGND and V SS should be nominally at the same potential. 2. Device is static and should operate below 1 Hz, but only tested down to 4 MHz. Warning: 8 Operation beyond the “Operating Conditions” is not recommended and extended exposure beyond the “Operating Conditions” may affect device reliability. Datasheet Automotive — 87C196CA 18 MHz Microcontroller 4.3 DC Characteristics Table 5. DC Characteristics (Sheet 1 of 2) Symbol Parameter Min Typical Max Units 90 mA Test Conditions ICC V CC supply current (–40°C to +125°C ambient) 50 ICC1 Active mode supply current (typical) 50 IREF A/D reference supply current 2 5 mA IIDLE Idle mode current 15 40 mA XTAL1 = 18 MHz, VCC = VPP = VREF = 5.25 V IPD Powerdown mode current 50 µA VCC = VPP = VREF = 5.25 V (Note 4) VIL Input low voltage (all pins) VIH Input high voltage (all pins) VOL Output low voltage (outputs configured as push/pull) VOH Output high voltage (outputs configured as complementary) ILI Input leakage current (standard inputs) ILI1 mA XTAL1 = 18 MHz, VCC = VPP = VREF = 5.25 V (While device is in reset) –0.5 V 0.3 VCC V 0.7 VCC VCC + 0.5 V (Note 5) 0.3 0.45 1.5 V IOL = 200 µA (Note 3) IOL = 3.2 mA IOL = 7.0 mA V IOH = – 200 µA (Note 3) IOH = – 3.2 mA IOH = – 7.0 mA ±10 µA VSS ≤ VIN ≤ VCC (Note 2) Input leakage current (Port 0—A/D inputs) ±1.5 µA VSS ≤ VIN ≤ VCC IIH Input high current (NMI pin) +175 µA VSS ≤ VIN ≤ VCC V OH1 SLPINT (P5.4) and HLDA (P2.6) Output high voltage in RESET 2.0 V IOH = 0.8 mA (Note 8) VOH2 Output high voltage in RESET VCC – 1 V V IOH = – 15 µA (Notes 1, 6) IOH2 Output High Current in RESET –30 –75 –90 V CC – 0.3 V CC – 0.7 V CC – 1.5 –120 –240 –280 µA VOH2 = VCC – 1.0 V VOH2 = VCC – 2.5 V VOH2 = VCC – 4.0 V NOTES: 1. All BD (bidirectional) pins except P5.5/INST and P2.7/CLKOUT which are excluded due to their not being weakly pulled high in reset. BD pins include Port1, Port 2, Port3, Port4, Port5, and Port6. 2. Standard Input pins include XTAL1, EA#, RESET#, and Ports 1,2,3,4,5,6 when configured as inputs. 3. All bidirectional I/O pins when configured as outputs (push/pull). 4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and VREF = VCC = 5.0 V. 5. V IH max for Port0 is VREF + 0.5 V. 6. Refer to “VOH2/IOH2 Specification” errata #1 in errata section of this datasheet. 7. This specification is not tested in production and is based upon theoretical estimates and/or product characterization. 8. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6). Datasheet 9 87C196CA 18 MHz Microcontroller — Automotive Table 5. DC Characteristics (Sheet 2 of 2) Symbol RRST Parameter Reset pullup resistor Min Typical 6K Max Units 65 K Ω V IOL3 = 4 mA (Note 7) IOL3 = 6 mA IOL3 = 10 mA pF FTEST = 1.0 MHz Ω (Note 4) VOL3 Output low voltage in reset (RESET pin only) 0.3 0.5 0.8 CS Pin Capacitance (any pin to VSS) 10 RWPU Weak pullup resistance (approx.) 150 K Test Conditions NOTES: 1. All BD (bidirectional) pins except P5.5/INST and P2.7/CLKOUT which are excluded due to their not being weakly pulled high in reset. BD pins include Port1, Port 2, Port3, Port4, Port5, and Port6. 2. Standard Input pins include XTAL1, EA#, RESET#, and Ports 1,2,3,4,5,6 when configured as inputs. 3. All bidirectional I/O pins when configured as outputs (push/pull). 4. Typicals are based on limited number of samples and are not guaranteed. The values listed are at room temperature and VREF = VCC = 5.0 V. 5. VIH max for Port0 is VREF + 0.5 V. 6. Refer to “VOH2/IOH2 Specification” errata #1 in errata section of this datasheet. 7. This specification is not tested in production and is based upon theoretical estimates and/or product characterization. 8. Violating these specifications in reset may cause the device to enter test modes (P5.4 and P2.6). Figure 4. 87C196CA ICC vs. Frequency Active ICC Max = 90 mA 90 80 Active ICC = 75 mA 70 60 50 ICC (mA) Idle Max = 40 mA 40 Idle ICC = 32 mA 30 20 10 0 2 8 14 20 A5862-01 10 Datasheet Automotive — 87C196CA 18 MHz Microcontroller 4.4 AC Characteristics Table 6. AC Characteristics (Sheet 1 of 2) (over specified operating conditions); Test conditions: capacitance load on all pins = 100 pF, Rise and fall times = 10 ns, FOSC = 18 MHz Symbol Parameter Min Max Units The system must meet these specifications to work with the 87C196CA Microcontroller. TAVYV Address Valid to READY Setup TLLYV ALE Low to READY Setup TYLYH Non Ready Time TCLYX READY Hold after CLKOUT Low TLLYX READY Hold after ALE Low TAVDV Address Valid to Input Data Valid TRLDV 2 TOSC – 75 ns TOSC – 70 ns No Upper Limit ns 0 TOSC – 30 ns(1) TOSC – 15 2 TOSC – 40 ns(1) 3 TOSC – 55 ns RD# Active to Input Data Valid TOSC – 22 ns TCLDV CLKOUT Low to Input Data Valid TOSC – 50 ns TRHDZ End of RD# to Input Data Float TOSC ns TRXDX Data Hold after RD# Inactive 0 ns The 87C196CA Microcontroller meets these specifications. 4 18 MHz(2) FXTAL Oscillator Frequency TOSC Oscillator Period (1/FXTAL) 55 250 ns TXHCH XTAL1 High to CLKOUT High or Low 20 110 ns(3) TOFD Clock Failure to Reset Pulled Low 4 40 µS(7) TCLCL CLKOUT Period 2 TOSC ns TCHCL CLKOUT High Period TOSC – 10 TOSC + 15 ns TCLLH CLKOUT Falling Edge to ALE Rising –15 10 ns TLLCH ALE/ADV# Falling Edge to CLKOUT Rising –20 15 ns TLHLH ALE/ADV# Cycle Time 4 TOSC ns TLHLL ALE/ADV# High Period TOSC – 10 TAVLL Address Setup to ALE/ADV# Falling Edge T OSC – 15 ns TLLAX Address Hold after ALE/ADV# Falling Edge TOSC – 40 ns TLLRL ALE/ADV# Falling Edge to RD# Falling Edge T OSC – 30 ns TRLCL RD# Low to CLKOUT Falling Edge TRLRH RD# Low Period 4 TOSC – 10 TOSC + 10 30 ns ns ns NOTES: 1. If max is exceeded, additional wait states will occur. 2. Testing performed at 4 MHz; however, the device is static by design and will typically operate below 1 Hz. 3. Typical specifications, not guaranteed. 4. Assuming back-to-back bus cycles. 5. 8-bit bus only. 6. TRLAZ (max) = 5 ns by design. 7. TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. Datasheet 11 87C196CA 18 MHz Microcontroller — Automotive Table 6. AC Characteristics (Sheet 2 of 2) (over specified operating conditions); Test conditions: capacitance load on all pins = 100 pF, Rise and fall times = 10 ns, FOSC = 18 MHz Symbol Parameter Min Max Units TOSC TOSC + 25 ns(4) 5 ns(6) TRHLH RD# Rising Edge to ALE/ADV# Rising Edge TRLAZ RD# Low to Address Float TLLWL ALE/ADV# Falling Edge to WR# Falling Edge TCLWL CLKOUT Low to WR# Falling Edge TQVWH Data Stable to WR# Rising Edge TCHWH CLKOUT High to WR# Rising Edge TWLWH WR# Low Period TOSC – 20 ns TWHQX Data Hold after WR# Rising Edge TOSC – 25 ns TWHLH WR# Rising Edge to ALE/ADV# Rising Edge TOSC – 10 TWHBX BHE# Hold after WR# Rising Edge TOSC – 10 ns TWHAX AD[15:8] Hold after WR# Rising Edge TOSC – 30 ns(5) TRHBX BHE# Hold after RD# Rising Edge TOSC – 10 ns TRHAX AD[15:8] Hold after RD# Rising Edge TOSC – 30 ns(5) TOSC – 10 –5 ns 25 ns 15 ns TOSC – 23 –10 ns TOSC + 15 ns(4) NOTES: 1. If max is exceeded, additional wait states will occur. 2. Testing performed at 4 MHz; however, the device is static by design and will typically operate below 1 Hz. 3. Typical specifications, not guaranteed. 4. Assuming back-to-back bus cycles. 5. 8-bit bus only. 6. TRLAZ (max) = 5 ns by design. 7. TOFD is the time for the oscillator fail detect circuit (OFD) to react to a clock failure. 12 Datasheet Automotive — 87C196CA 18 MHz Microcontroller Figure 5. System Bus Timing TOSC XTAL1 TCLCL TCHCL TXHCH CLKOUT TCLCH TLLCH TLHLH ALE TLHLL TLLRL TAVLL TRLAZ TRLRH TRHLH RD# BUS TRHDZ TRLDV TLLAX Address Out TAVDV Data In TLLWL TWLWH TWHLH WR# TQVWH BUS Address Out Data Out TWHQX Address Out TWHBX, TRHBX BHE# Valid TWHAX, TRHAX AD15:8 Address Out A5927-01 Datasheet 13 87C196CA 18 MHz Microcontroller — Automotive Figure 6. READY Timing TOSC XTAL1 TCLCL TCHCL TXHCH CLKOUT TLLYX TCLLH ALE RD# BUS Address Out TLLYV Data TCLYX READY TAVYV A5928-01 Table 7. External Clock Drive Symbol Parameter Min Max Units Oscillator Frequency 4 18 MHz TXLXL Oscillator Period (TOSC) 55 250 ns TXHXX High Time 0.35 TOSC 0.65 TOSC ns TXLXX Low Time 0.35 TOSC 0.65 TOSC ns TXLXH Rise Time 10 ns TXHXL Fall Time 10 ns 1/TXLXL Figure 7. External Clock Drive Waveforms TXHXX 0.7 VCC + 0.5 V 0.7 VCC + 0.5 V TXHXL TXLXH TXLXX 0.3 VCC – 0.5 V 0.7 VCC + 0.5 V 0.3 VCC – 0.5 V TXLXL A5842-01 14 Datasheet Automotive — 87C196CA 18 MHz Microcontroller Figure 8. AC Testing Input, Output Waveforms OUTPUTS INPUTS 3.5 V 2.0 V Test Points 0.45 V 0.8 V Note: AC testing inputs are driven at 3.5 V for a logic “ 1” and 0.45 V for a logic “ 0” . Timing measurements are made at 2.0 V for a logic “ 1” and 0.8 V for a logic “ 0”. A4651-01 Figure 9. Float Waveforms VOH – 0.15 V VLOAD + 0.15 V VLOAD Timing Reference Points VLOAD – 0.15 V VOL + 0.15 V Note: For timing purposes, a port pin is no longer floating when a 150 mV change from load voltage occurs and begins to float when a 150 mV change from the loading VOH/VOL level occurs with IOL/IOH ≤ 15 mA. A5844-01 Table 8. Thermal Characteristics Device and Package AN87C196CA (68-Lead PLCC) θJA θJC 36.5°C/W 10°C/W NOTES: 1. θJA = Thermal resistance between junction and the surrounding environment (ambient). Measurements are taken 1 ft. away from case in air flow environment. θJC = Thermal resistance between junction and package surface (case). 2. All values of θJA and θJC may fluctuate depending on the environment (with or without airflow, and how much airflow) and device power dissipation at temperature of operation. Typical variations are ±2°C/W. 3. Values listed are at a maximum power dissipation of 0.50 W. Datasheet 15 87C196CA 18 MHz Microcontroller — Automotive 4.4.1 Explanation of AC Symbols Each symbol is two pairs of letters prefixed by “t” for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions Signals H–High A–Address HA–HLDA# L–Low B–BHE# L–ALE/ADV# V–Valid C–CLKOUT R–RD# X–No Longer Valid D–DATA W–WR#/WRH#/WRI# Z–Floating G–Buswidth X–XTAL1 H–HOLD# Y–READY 4.4.2 EPROM Specifications Table 9. AC EPROM Programming Characteristics Operating Conditions: Load Capacitance = 150 pF; TC = 25°C ± 5°C; VREF = 5.0 V ± 0.25 V; VSS, ANGND = 0 V; VPP = 12.5 V ± 0.25 V; EA# = 12.5 V ± 0.25 V; FOSC = 5.0 MHz Symbol Parameter Min Max Units TAVLL Address Setup Time 0 TOSC TLLAX Address Hold Time 100 TOSC TDVPL Data Setup Time 0 TOSC TPLDX Data Hold Time 400 TOSC TLLLH PALE# Pulse Width 50 TOSC TPLPH PROG# Pulse Width(3) 50 TOSC TLHPL PALE# High to PROG# Low 220 TOSC TPHLL PROG# High to Next PALE# Low 220 TOSC TPHDX Word Dump Hold Time TPHPL PROG# High to Next PROG# Low TPLDV PROG# Low to Word Dump Valid TSHLL RESET# High to First PALE# Low TPHIL PROG# High to AINC# Low TILIH AINC# Pulse Width TILVH PVER Hold after AINC# Low 50 TOSC TILPL AINC# Low to PROG# Low 170 TOSC TPHVL PROG# High to PVER# Valid 50 220 TOSC TOSC 50 TOSC 1100 TOSC 0 TOSC 240 TOSC 220 TOSC NOTES: 1. Run-time programming is done with FOSC = 6.0 MHz to 10.0 MHz, VCC, VPD, VREF = 5 V ± 0.25 V, TC = 25 °C ± 5 °C and VPP = 12.5 V ± 0.25 V. For run-time programming over a full operating range, contact factory. 2. Programming specifications are not tested, but guaranteed by design. 3. This specification is for the word dump mode. For programming pulses, use 300 TOSC + 100 µS. 16 Datasheet Automotive — 87C196CA 18 MHz Microcontroller Table 10. DC EPROM Programming Characteristics Symbol IPP Parameter Min VPP Programming Supply Current Max Units 200 mA NOTE: VPP must be within 1 V of VCC while VCC < 4.5 V. VPP must not have a low impedance path to ground or VSS while VCC > 4.5 V. Figure 10. Slave Programming Mode Data Program Mode with Single Program Pulse RESET# TDVPL TAVLL PORTS 3/4 Address/Command TSHLL PALE# P2.1 Data TPHDX TLLAX TLHPL TLLLH Address/Command TPLPH TPHLL PROG# P2.2 TPHVL AINC# P2.0 Valid TLLVH A5838-01 Figure 11. Slave Programming Mode in Word Dump or Data Verify Mode with Auto Increment RESET# ADDR PORTS 3/4 Address/Command TSHLL TPLDV ADDR + 2 Ver Bits/WD Dump Ver Bits/WD Dump TPHDX TPLDV TPHDX PALE# P2.1 PROG# P2.2 TILPL TPHPL PVER# P2.0 A5839-01 Datasheet 17 87C196CA 18 MHz Microcontroller — Automotive Figure 12. Slave Programming Mode Timing in Data Program Mode with Repeated PROG Pulse and Auto Increment RESET# PORTS 3/4 Address/Command PALE# P2.1 Data Data TPHPL PROG# P2.2 TILPL P1 P2 TILVH PVER# P2.0 Valid For P1 Valid For P2 TILIH AINC# P2.4 TPHIL A5840-01 4.4.3 A to D Converter Specifications The speed of the A/D converter in the 10-bit or 8-bit modes can be adjusted by setting the AD_TIME special function register to the appropriate value. The AD_TIME register only programs the speed at which the conversions are performed, not the speed at which it can convert correctly. The converter is ratiometric, so absolute accuracy is dependent on the accuracy and stability of VREF. VREF must not exceed VCC by more than 0.5 V since it supplies both the resistor ladder and the digital portion of the converter and input port pins. For testing purposes, after a conversion is started, the device is placed in the IDLE mode until the conversion is complete. Testing is performed at VREF = 5.12 V and 18 MHz operating frequency. There is an AD_TEST register that allows for conversion on ANGND and VREF as well as zero offset adjustment. The absolute error listed is without doing any adjustments. Table 11. A/D Operating Conditions Symbol Min Max Units Automotive Ambient Temperature –40 +125 °C VCC Digital Supply Voltage 4.75 5.25 V V REF Analog Supply Voltage 4.75 5.25 TSAM Sample Time 2.0 Conversion Time 15 18 µS Oscillator Frequency 4 18 MHz TA TCONV FOSC Description V µS NOTES: 1. ANGND and VSS should nominally be at the same potential. 2. VREF must not exceed VCC by more than +0.5 V. 3. Testing is performed at VREF = 5.12 V. 4. The value of AD_TIME must be selected to meet these specifications. 18 Datasheet Automotive — 87C196CA 18 MHz Microcontroller Table 12. A/D Operating Parameter Values Parameter Typical(†,1) Resolution Absolute Error Min Max Units†† 1024 10 1024 10 Level Bits 0 –3 +3 LSBs Full Scale Error ±2 LSBs Zero Offset Error ±2 LSBs Non-linearity Differential Non-linearity Channel-to-Channel Matching Repeatability ±0.25 Temperature Coefficients: Offset Fullscale Differential Non-linearity 0.009 0.009 0.009 Off Isolation ±3 LSBs > –0.5 +0.5 LSBs 0 ±1 LSBs LSBs(1) 0 LSB/C(1) dB(1)(2)(3) –60 Feedthrough –60 dB (1)(2) VCC Power Supply Rejection –60 dB(1)(2) Input Resistance DC Input Leakage 750 1.2 K Ω(1) 0 ±3 µA NOTES: † These values are expected for most parts at 25 °C but are not tested or guaranteed. †† An “LSB,” as used here, has a value of approximately 5 mV. (See Automotive Handbook for A/D glossary of terms.) 1. These values are not tested in production and are based on theoretical estimates and/or laboratory test. 2. DC to 100 KHz. 3. Multiplexer break-before-make guaranteed. Datasheet 19 87C196CA 18 MHz Microcontroller — Automotive 4.4.4 AC Characteristics—Slave Port Figure 13. Slave Port Waveform (SLPL = 0) CS# TSRHAV ALE / A1 TSRLRH RD# TSRLDV TSRHDZ P3 TSDVWH TSAVWL TSWLWH TSWHQX WR# A5847-01 Table 13. Slave Port Timing–(SLPL = 0) (See notes 1, 2, 3) Symbol Parameter Min Max Units TSAVWL Address Valid to WR# Low 50 ns TSRHAV RD# High to Address Valid 60 ns TSRLRH RD# Low Period TOSC ns TSWLWH WR# Low Period TOSC ns TSRLDV RD# Low to Output Data Valid TSDVWH Input Data Setup to WR# High 20 ns TSWHQX WR# High to Data Invalid 30 ns TSRHDZ RD# High to Data Float 15 ns 60 ns NOTES: 1. Test conditions: FOSC = 18 MHz, TOSC = 60 ns, Rise/Fall Time = 10 ns. Capacitive Pin Load = 100 pF. 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. Specifications above are advanced information and are subject to change. 20 Datasheet Automotive — 87C196CA 18 MHz Microcontroller Figure 14. Slave Port Waveform (SLPL = 1) TSRHEH TSELLL CS# ALE TSLLRL TSRLRH RD# TSRLDV TSRHDZ P3 TSAVLL TSLLAX TSWHQX TSDVWH TSWLWH WR# A5884-01 Table 14. Slave Port Timing–(SLPL = 1) (See notes 1, 2, 3) Symbol Parameter Min Max Units TSELLL CS# Low to ALE Low 20 ns TSRHEH RD# or WR# High to CS# High 60 ns TSLLRL ALE Low to RD# Low TOSC ns TSRLRH RD# Low Period TOSC ns TSWLWH WR# Low Period TOSC ns ns TSAVLL Address Valid to ALE Low 20 20 TSLLAX ALE Low to Address Invalid TSRLDV RD# Low to Output Data Valid TSDVWH Input Data Setup to WR# High 20 ns TSWHQX WR# High to Data Invalid 30 ns TSRHDZ RD# High to Data Float 15 ns ns 60 ns NOTES: 1. Test conditions: FOSC = 18 MHz, TOSC = 60 ns, Rise/Fall Time = 10 ns. Capacitive Pin Load = 100 pF. 2. These values are not tested in production, and are based upon theoretical estimates and/or laboratory tests. 3. Specifications above are advanced information and are subject to change. Datasheet 21 87C196CA 18 MHz Microcontroller — Automotive 4.4.5 AC Characteristics—Serial Port— Shift Register Mode Table 15. Serial Port Timing—Shift Register Mode Test Conditions: TA = –40°C to +125°C; VCC = 5.0 V ± 5%; VSS = 0.0 V; Load Capacitance = 100 pF Symbol Parameter Min TXLXL Serial Port Clock Period TXLXH Serial Port Clock Falling Edge to Rising Edge TQVXH Output Data Setup to Clock Rising Edge TXHQX Output Data Hold after Clock Rising Edge TXHQV Next Output Data Valid after Clock Rising Edge TDVXH Input Data Setup to Clock Rising Edge TXHDX(1) TXHQZ (1) Max Units 4 TOSC + 50 ns 8 TOSC ns 4 TOSC – 50 3 TOSC ns 2 TOSC – 50 ns 2 TOSC + 50 ns 2 TOSC + 200 ns 0 ns Input Data Hold after Clock Rising Edge Last Clock Rising to Output Float 5 TOSC ns NOTES: 1. Parameter not tested. 4.4.6 Waveform—Serial Port—Shift Register Mode 0 Figure 15. Serial Port Waveform—Shift Register Mode TXLXL TXDx TQVXH RXDx (Out) TXLXH 0 1 2 Valid TXHQZ TXHQX 4 3 TDVXH RXDx (In) TXHQV 7 6 5 TXHDX Valid Valid Valid Valid Valid Valid Valid A5841-01 22 Datasheet Automotive — 87C196CA 18 MHz Microcontroller 5.0 Design Considerations 5.1 87C196CA Design Considerations 1. EPA Timer RESET/Write Conflict If the user writes to the EPA timer at the same time that the timer is reset, it is indeterminate which will take precedence. Users should not write to a timer if using EPA signals to reset it. 2. Valid Time Matches The timer must increment/decrement to the compare value for a match to occur. A match does not occur if the timer is loaded with a value equal to an EPA compare value. Matches also do not occur if a timer is reset and 0 is the EPA compare value. 3. P6 PIN.4-.7 Not Updated Immediately Values written to P6 REG are temporarily held in a buffer. If P6 MODE is cleared, the buffer is loaded into P6 REG.x. If P6 MODE is set, the value stays in the buffer and is loaded into P6 REG.x when P6 MODE.x is cleared. Since reading P6 REG returns the current value in P6. REG and not the buffer, changes to P6 REG cannot be read until/unless P6 MODE.x is cleared. 4. Write Cycle during Reset If RESET occurs during a write cycle, the contents of the external memory device may be corrupted. 5. Indirect Shift Instruction The upper 3 bits of the byte register holding the shift count are not masked completely. If the shift count register has the value 32 x n, where n = 1, 3, 5, or 7, the operand will be shifted 32 times. This should have resulted in no shift taking place. 6. P2.7 (CLKOUT) P2.7 (CLKOUT) does not operate in open drain mode. 7. CLKOUT The CLKOUT signal is active on P2.7 during RESET. 8. EPA Overruns EPA “lock-up” can occur if overruns are not handled correctly, refer to Intel Techbit #DB0459 “Understanding EPA Capture Overruns”, dated 12-9-93. Applies to EPA channels with interrupts and overruns enabled (ON/RT bit in EPA_CONTROL register set to “1”). 9. Indirect Addressing with Auto-Increment For the special case of a pointer pointing to itself using auto-increment, an incorrect access of the incremented pointer address will occur instead of an access to the original pointer address. All other indirect auto-increment accesses will note be affected. Please refer to Techbit #MC0593. Incorrect sequence: ld ax,#ax ; ldb bx,[ax]+ ; Results in ax being incremented by 1 and the contents of the address pointed to by ax+1 to be loaded into bx. Correct sequence: Datasheet ld ax,#bx ; ldb cx,[ax]+ ; where ax ≠ bx. Results in the contents of the address pointed to by ax to be loaded into bx and ax incremented by 1. 23 87C196CA 18 MHz Microcontroller — Automotive 196KR Features Unsupported on the 196CA: • • • • Analog Channels 0 and 1 INST Pin Functionality SLPINT and SLPCS Pin Support HLD/HLDA Functionality • • • • External Clocking/Direction of Timer1 Quadrature Clocking Timer 1 Dynamic Buswidth EPA Capture Channels 4–7 1. External Memory Removal of the Buswidth pin means the bus cannot dynamically switch from 8- to 16-bit bus mode or vice versa. The programmer must define the bus mode by setting the associated bits in the CCB. 2. Auto-Programming Mode The 87C196CA device will ONLY support the 16-bit zero wait state bus during auto-programming. 3. EPA4 through EPA7 Since the CA device is based on the KR design, these functions are in the device, however there are no associated pins. A programmer can use these as compare only channels or for other functions like software timer, start an A/D conversion, or reset timers. 4. Slave Port Support The Slave port can not be used on the 196CA due to a function change for P5.4/SLPINT and P5.1/SLPCS not being bonded-out. 5. Port Functions Some port pins have been removed. P5.1, P6.2, P6.3, P1.4 through P1.7, P2.3, P2.5, P0.0 and P0.1. The PxREG, PxSSEL, and PxIO registers can still be updated and read. The programmer should not use the corresponding bits associated with the removed port pins to conditionally branch in software. Treat these bits as RESERVED. Additionally, these port pins should be setup internally by software as follows: a. Written to PxREG as ‘‘1’’ or ‘‘0’’. b. Configured as Push/Pull, PxIO as ‘‘0’’. c. Configured as LSIO. This configuration will effectively strap the pin either high or low. DO NOT Configure as Open Drain output ‘’1’’, or as an Input pin. This device is CMOS. 6. EPA Timer RESET/Write Conflict If the user writes to the EPA timer at the same time that the timer is reset, it is indeterminate which will take precedence. Users should not write to a timer if using EPA signals to reset it. 7. Valid Time Matches The timer must increase/decrease to the compare value for a match to occur. A match does not occur if the timer is loaded with a value equal to an EPA compare value. Matches also do not occur if a timer is reset and 0 is the EPA compare value. 8. Write Cycle during Reset If RESET occurs during a write cycle, contents of the external memory device may be corrupted. 9. Indirect Shift Instruction The upper 3 bits of the byte register holding the shift count are not masked completely. If the shift count register has the value 32 c n, where n e 1, 3, 5, or 7, the operand will be shifted 32 times. This should have resulted in no shift taking place. 10. P2.7 (CLKOUT) P2.7 (CLKOUT) does not operate in open drain mode. 24 Datasheet Automotive — 87C196CA 18 MHz Microcontroller 6.0 Datasheet Revision History Revision Date 001 06/98 Description Initial release. 25