87C196KC 16-BIT HIGH-PERFORMANCE CHMOS MICROCONTROLLER Automotive Y b 40§ C to a 125§ C Y Full Duplex Serial Port Y 16 Kbytes of On-Chip EPROM Y High-Speed I/O Subsystem Y 232 Byte Register File Y 16-Bit Timer Y 256 Bytes of Additional RAM Y 16-Bit Up/Down Counter with Capture Y Register-to-Register Architecture Y 3 Pulse-Width-Modulated Outputs Y 28 Interrupt Sources/16 Vectors Y Four 16-Bit Software Timers Y Peripheral Transaction Server Y Y 1.75 ms 16 x 16 Multiply (16 MHz) 8- or 10-Bit 8-Channel A/D Converter with Sample/Hold 3.0 ms 32/16 Divide (16 MHz) Y Y HOLD/HLDA Bus Protocol Y Powerdown and Idle Modes Y Y Five 8-Bit I/O Ports OTP One-Time Programmable and QROM Versions Y Y 16-Bit Watchdog Timer Available in 12 MHz and 16 MHz Versions Y Dynamically Configurable 8-Bit or 16-Bit Buswidth Y 16 MHz Operation The 87C196KC 16-bit microcontroller is a high-performance member of the MCSÉ 96 microcontroller family. The 87C196KC is an enhanced 8XC196KB device with 488 bytes RAM, 16 MHz operation and 16 Kbytes of on-chip EPROM. Intel’s CHMOS process provides a high performance processor along with low power consumption. Four high-speed capture inputs are provided to record times when events occur. Six high-speed outputs are available for pulse or waveform generation. The high-speed output can also generate four software timers or start an A/D conversion. Events can be based on the timer or up/down counter. NOTICE: This datasheet contains information on products in full production. Specifications within this datasheet are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. *Other brands and names are the property of their respective owners. Information in this document is provided in connection with Intel products. Intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Intel retains the right to make changes to these specifications at any time, without notice. Microcomputer Products may have minor variations to this specification known as errata. COPYRIGHT © INTEL CORPORATION, 1995 January 1995 Order Number: 270846-004 AUTOMOTIVE 87C196KC 270846 – 1 Figure 1. 87C196KC Block Diagram 270846 – 33 Figure 2. The 87C196KC Family Nomenclature 87C196KC Enhanced Feature Set over the 87C196KB 1. The 87C196KC has twice the RAM and twice the EPROM of the 87C196KB. Also, a Vertical Register Windowing Scheme allows the extra 256 bytes of RAM to be used as registers. This greatly reduces the context switching time. 2. Peripheral Transaction Server (PTS). The PTS is an alternative way to service an interrupt, reducing latency and overhead. Each interrupt can be mapped to its PTS channel, which acts like a DMA channel. Each interrupt can now do a single or block transfer, without executing an Interrupt service routine. Special PTS modes exist for the A/D converter, HSI, and HSO. 3. Two extra Pulse Width Modulated outputs. The 87C196KC has added 2 PWM outputs that are functionally compatible to the 87C196KB PWM. 4. Timer2 Internal Clocking. Timer2 can now be clocked with an internal source, every 1 or 8 state times. 5. The A/D can now perform an 8- as well as a 10-bit conversion. 8-bit conversion allows for a faster conversion time. 6. Additional On-chip Memory Security. Two UPROM (Uneraseable Programmable Read Only Memory) bits can be programmed to disable the bus controller for external code and data fetches. Once programmed, a UPROM bit cannot be erased. By shutting off the bus controller for external fetches, no one can try and gain access to your code by executing from external memory. 7. New Instructions. The 87C196KC has 5 new instructions. An exchange (XCHB/XCHW) instruction swaps two memory locations, an Interruptable Block Move Instruction (BMOVI), a Table Indirect Jump (TIJMP) instruction, and two instructions for enabling and disabling the PTS (EPTS/DPTS). 2 AUTOMOTIVE 87C196KC PACKAGING PLCC Description PLCC Description PLCC Description 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 ACH7/P0.7 ACH6/P0.6 ACH2/P0.2 ACH0/P0.0 ACH1/P0.1 ACH3/P0.3 NMI EA VCC VSS XTAL1 XTAL2 CLKOUT BUSWIDTH INST ALE/ADV RD AD0/P3.0 AD1/P3.1 AD2/P3.2 AD3/P3.3 AD4/P3.4 AD5/P3.5 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 AD6/P3.6 AD7/P3.7 AD8/P4.0 AD9/P4.1 AD10/P4.2 AD11/P4.3 AD12/P4.4 AD13/P4.5 AD14/P4.6 AD15/P4.7 T2CLK/P2.3 READY T2RST/P2.4 BHE/WRH WR/WRL PWM0/P2.5 P2.7/T2CAPTURE VPP VSS HSO.3 HSO.2 P2.6/T2UP-DN P1.7/HOLD 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 P1.6/HLDA P1.5/BREQ HSO.1 HSO.0 HSO.5/HSI.3 HSO.4/HSI.2 HSI.1 HSI.0 P1.4/PWM2 P1.3/PWM1 P1.2 P1.1 P1.0 TXD/P2.0 RXD/P2.1 RESET EXTINT/P2.2 VSS VREF ANGND ACH4/P.04 ACH5/P.05 Figure 3. 68-Pin PLCC Functional Pin-out 3 AUTOMOTIVE 87C196KC 270846 – 2 Figure 4. 68-Pin PLCC Package Table 1. Prefix Identification PLCC 87C196KC *OTP Version 4 AN87C196KC* AUTOMOTIVE 87C196KC PIN DESCRIPTIONS Symbol Name and Function VCC Main supply voltage (5V). VSS Digital circuit ground (0V). There are three VSS pins, all of which must be connected. VREF Reference voltage for the A/D converter (5V). VREF is also the supply voltage to the analog portion of the A/D converter and the logic used to read Port 0. Must be connected for A/D and Port 0 to function. ANGND Reference ground for the A/D converter. Must be held at nominally the same potential as VSS. VPP Timing pin for the return from powerdown circuit. Connect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC. If this function is not used VPP may be tied to VCC. This pin is the programming voltage on the EPROM device. XTAL1 Input of the oscillator inverter and of the internal clock generator. XTAL2 Output of the oscillator inverter. CLKOUT Output of the internal clock generator. The frequency of CLKOUT is (/2 the oscillator frequency. RESET Reset input to the chip. BUSWIDTH Input for buswidth selection. If CCR bit 1 is a one, this pin selects the bus width for the bus cycle in progress. If BUSWIDTH is a 1, a 16-bit bus cycle occurs. If BUSWIDTH is a 0 an 8-bit cycle occurs. If CCR bit 1 is a 0, the bus is always an 8-bit bus. NMI A positive transition causes a vector through 203EH. INST Output high during an external memory read indicates the read is an instruction fetch. INST is valid throughout the bus cycle. INST is activated only during external memory accesses and output low for a data fetch. EA Input for memory select (External Access). EA equal to a TTL-high causes memory accesses to locations 2000H through 5FFFH to be directed to on-chip ROM/EPROM. EA equal to a TTL-low causes accesses to those locations to be directed to off-chip memory. ALE/ADV Address Latch Enable or Address Valid output, as selected by CCR. Both pin options provide a signal to demultiplex the address from the address/data bus. When the pin is ADV, it goes inactive high at the end of the bus cycle. ALE/ADV is activated only during external memory accesses. RD Read signal output to external memory. RD is activated only during external memory reads. WR/WRL Write and Write Low output to external memory, as selected by the CCR. WR will go low for every external write, while WRL will go low only for external writes where an even byte is being written. WR/WRL is activated only during external memory writes. BHE/WRH Bus High Enable or Write High output to external memory, as selected by the CCR. BHE e 0 selects the bank of memory that is connected to the high byte of the data bus. A0 e 0 selects the bank of memory that is connected to the low byte of the data bus. Thus accesses to a 16-bit wide memory can be to the low byte only (A0 e 0, BHE e 1), to the high byte only (A0 e 1, BHE e 0), or both bytes (A0 e 0, BHE e 0). If the WRH function is selected, the pin will go low if the bus cycle is writing to an odd memory location. BHE/WRH is valid only during 16-bit external memory write cycles. 5 AUTOMOTIVE 87C196KC PIN DESCRIPTIONS (Continued) Symbol 6 Name and Function READY Ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. When the external memory is not being used, READY has no effect. HSI Inputs to High Speed Input Unit. Four HSI pins are available: HSI.0, HSI.1, HSI.2 and HSI.3. Two of them (HSI.2 and HSI.3) are shared with the HSO Unit. HSO Outputs from High Speed Output Unit. Six HSO pins are available: HSO.0, HSO.1, HSO.2, HSI.3, HSO.4 and HSO.5. Two of them (HSO.4 and HSO.5) are shared with the HSI Unit. Port 0 8-bit high impedance input-only port. These pins can be used as digital inputs and/or as analog inputs to the on-chip A/D converter. Port 1 8-bit quasi-bidirectional I/O port. Port 2 8-bit multi-functional port. All of its pins are shared with other functions in the 87C196KC. Ports 3 and 4 8-bit bidirectional I/O ports with open drain outputs. These pins are shared with the multiplexed address/data bus. HOLD Bus Hold input requesting control of the bus. HLDA Bus Hold acknowledge output indicating release of the bus. BREQ Bus Request output activated when the bus controller has a pending external memory cycle. AUTOMOTIVE 87C196KC ELECTRICAL CHARACTERISTICS NOTICE: This is a production data sheet. The specifications are subject to change without notice. *WARNING: Stressing the device beyond the ‘‘Absolute Maximum Ratings’’ may cause permanent damage. These are stress ratings only. Operation beyond the ‘‘Operating Conditions’’ is not recommended and extended exposure beyond the ‘‘Operating Conditions’’ may affect device reliability. Absolute Maximum Ratings* Ambient Temperature Under Bias ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ b 40§ C to a 125§ C Storage Temperature ÀÀÀÀÀÀÀÀÀÀ b 65§ C to a 150§ C Voltage On Any Pin to VSS ÀÀÀÀÀÀÀÀ b 0.5V to a 7.0V Power Dissipation ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ0.43W OPERATING CONDITIONS Description Min Max Units TA Symbol Ambient Temperature Under Bias b 40 a 125 §C VCC Digital Supply Voltage 4.50 5.50 V VREF Analog Supply Voltage 4.50 5.50 V FOSC Oscillator Frequency 4 16 MHz NOTE: ANGND and VSS should be nominally at the same potential. DC CHARACTERISTICS Symbol (Over Specified Operating Conditions) Description VIL Input Low Voltage VIH Input High Voltage (Note 1) VIH1 Input High Voltage on XTAL 1, EA Min Max Units b 0.5 0.8 V 0.2 VCC a 1.0 VCC a 0.5 V 0.7 VCC VCC a 0.5 V 2.2 VCC a 0.5 V Test Conditions VIH2 Input High Voltage on RESET VOL Output Low Voltage 0.3 0.45 1.5 V V V IOL e 200 mA IOL e 2.8 mA IOL e 7 mA VOL1 Output Low Voltage in RESET on P2.5 (Note 2) 0.8 V IOL e a 0.2 mA VOH Output High Voltage (Standard Outputs) VCC b 0.3 VCC b 0.7 VCC b 1.5 V V V IOH e b 200 mA IOH e b 3.2 mA IOH e b 7 mA VOH1 Output High Voltage (Quasi-bidirectional Outputs) VCC b 0.3 VCC b 0.7 VCC b 1.5 V V V IOH e b 10 mA IOH e b 30 mA IOH e b 60 mA VOH2 Output High Voltage in RESET on P2.0 (Note 2) 2.0 V IOH e b 0.6 mA NOTES: 1. All pins except RESET, XTAL1 and EA. 2. Violating these specifications in Reset may cause the part to enter test modes. 7 AUTOMOTIVE 87C196KC DC CHARACTERISTICS Symbol (Over Specified Operating Conditions) Description Min Typ ILI Input Leakage Current (Std. Inputs) ILI1 Input Leakage Current (Port 0) ITL 1 to 0 Transition Current (QBD Pins) IIL Logical 0 Input Current (QBD Pins) ICC Active Mode Current in Reset 50 IREF A/D Converter Reference Current 2 IIDLE Idle Mode Current IPD Powerdown Mode Current RRST Reset Pullup Resistor CS Pin Capacitance (Any Pin to VSS) 6K Max Units Test Conditions g 10 mA 0 k VIN k VCC b 0.3V g3 mA 0 k VIN k VREF b 650 mA VIN e 2.0V b 70 mA VIN e 0.45V 70 mA 5 mA XTAL1 e 16 MHz VCC e VPP e VREF e 5.5V 15 30 mA 50 T.B.D. mA VCC e VPP e VREF e 5.5V 65K X VCC e 5.0V, VIN e 4.0V 10 pF NOTES: (Notes apply to all specifications) 1. QBD (Quasi-bidirectional) pins include Port 1, P2.6 and P2.7. 2. Standard Outputs include AD0–15, RD, WR, ALE, BHE, INST, HSO pins, PWM/P2.5, CLKOUT, RESET, Ports 3 and 4, TXD/P2.0 and RXD (in serial mode 0). The VOH specification is not valid for RESET. Ports 3 and 4 are open-drain outputs. 3. Standard Inputs include HSI pins, READY, BUSWIDTH, NMI, RXD/P2.1, EXTINT/P2.2, T2CLK/P2.3 and T2RST/P2.4. 4. Maximum current per pin must be externally limited to the following values if VOL is held above 0.45V or VOH is held below VCC b 0.7V: IOL on Output pins: 10 mA IOH on quasi-bidirectional pins: self limiting IOH on Standard Output pins: 10 mA 5. Maximum current per bus pin (data and control) during normal operation is g 3.2 mA. 6. During normal (non-transient) conditions the following total current limits apply: IOH is self limiting Port 1, P2.6 IOL: 29 mA IOH: 26 mA HSO, P2.0, RXD, RESET IOL: 29 mA IOL: 13 mA IOH: 11 mA P2.5, P2.7, WR, BHE IOH: 52 mA AD0 – AD15 IOL: 52 mA IOH: 13 mA RD, ALE, INST–CLKOUT IOL: 13 mA 8 AUTOMOTIVE 87C196KC 270846 – 21 ICC MAX e 3.88 c Freq a 8.43 IIDLE MAX e 1.65 c Freq a 2.2 Figure 5. ICC and IIDLE vs Frequency AC CHARACTERISTICS For use over specified operating conditions. Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz The system must meet these specifications to work with the 87C196KC: Symbol Description TAVYV Address Valid to READY Setup TLLYV ALE Low to READY Setup TYLYH Non READY Time TCLYX READY Hold after CLKOUT Low TLLYX READY Hold after ALE Low TAVGV Address Valid to Buswidth Setup TLLGV ALE Low to Buswidth Setup TCLGX Buswidth Hold after CLKOUT Low TAVDV Address Valid to Input Data Valid TRLDV TCLDV TRHDZ End of RD to Input Data Float TRXDX Data Hold after RD Inactive Min Max Units 2 TOSC b 75 ns TOSC b 70 No upper limit Notes ns ns 0 TOSC b 30 ns (Note 1) TOSC b 15 2 TOSC b 40 ns (Note 1) 2 TOSC b 75 ns TOSC b 60 ns 0 ns 3 TOSC b 55 ns (Note 2) RD Active to Input Data Valid TOSC b 30 ns (Note 2) CLKOUT Low to Input Data Valid TOSC b 50 ns TOSC 0 ns ns NOTES: 1. If max is exceeded, additional wait states will occur. 2. If wait states are used, add 2 TOSC * N, where N e number of wait states. 9 AUTOMOTIVE 87C196KC AC CHARACTERISTICS (Continued) For use over specified operating conditions. Test Conditions: Capacitive load on all pins e 100 pF, Rise and fall times e 10 ns, FOSC e 16 MHz The 87C196KC will meet these specifications: Symbol Description Min Max Units Notes (Note 1) FXTAL Frequency on XTAL1 4.0 16 MHz TOSC I/FXTAL 62.5 250 ns TXHCH XTAL1 High to CLKOUT High or Low 110 ns TCLCL CLKOUT Cycle Time TCHCL CLKOUT High Period TOSC b 10 TOSC a 15 ns TCLLH CLKOUT Falling Edge to ALE Rising b5 15 ns TLLCH ALE Falling Edge to CLKOUT Rising b 20 a 15 ns TLHLH ALE Cycle Time 20 2 TOSC ns 4 TOSC ns TLHLL ALE High Period TOSC b 10 TAVLL Address Setup to ALE Falling Edge TOSC b 15 TLLAX Address Hold after ALE Falling Edge TOSC b 40 ns TLLRL ALE Falling Edge to RD Falling Edge TOSC b 30 ns TRLCL RD Low to CLKOUT Falling Edge TRLRH RD Low Period TRHLH RD Rising Edge to ALE Rising Edge TRLAZ RD Low to Address Float TLLWL ALE Falling Edge to WR Falling Edge TCLWL CLKOUT Low to WR Falling Edge 0 TOSC a 10 35 TOSC b 5 TOSC ns ns ns (Note 4) TOSC a 25 ns (Note 2) 5 ns TOSC b 10 0 ns 25 ns 15 ns TOSC b 30 TQVWH Data Stable to WR Rising Edge TCHWH CLKOUT High to WR Rising Edge TWLWH WR Low Period TOSC b 30 ns TWHQX Data Hold after WR Rising Edge TOSC b 25 ns TWHLH WR Rising Edge to ALE Rising Edge TOSC b 10 TWHBX BHE, INST after WR Rising Edge TOSC b 10 ns TWHAX AD8–15 HOLD after WR Rising TOSC b 30 ns TRHBX BHE, INST after RD Rising Edge TOSC b 10 ns TRHAX AD8–15 HOLD after RD Rising TOSC b 30 ns b 10 (Note 4) TOSC a 15 ns NOTES: 1. Testing performed at 4.0 MHz. However, the device is static by design and will typically operate below 1 Hz. 2. Assuming back-to-back bus cycles. 3. 8-Bit bus only. 4. If wait states are used, add 2 TOSC * N, where N e number of wait states. 10 (Note 4) (Note 4) (Note 2) (Note 3) (Note 3) AUTOMOTIVE 87C196KC System Bus Timings 270846 – 22 11 AUTOMOTIVE 87C196KC READY Timings (One Waitstate) 270846 – 23 Buswidth Timings 270846 – 24 12 AUTOMOTIVE 87C196KC HOLD/HLDA Timings Symbol Description Min Max THVCH HOLD Setup TCLHAL CLKOUT Low to HLDA Low b 15 55 TCLBRL CLKOUT Low to BREQ Low b 15 TAZHAL HLDA Low to Address Float TBZHAL HLDA Low to BHE, INST, RD, WR Weakly Driven TCLHAH CLKOUT Low to HLDA High b 15 TCLBRH CLKOUT Low to BREQ High b 15 15 THAHAX HLDA High to Address No Longer Float b 15 THAHBV HLDA High to BHE, INST, RD, WR Valid b 10 TCLLH CLKOUT Low to ALE High b5 15 Units Notes ns (Note 1) ns 15 ns 15 ns 15 ns 15 ns ns ns ns 15 ns NOTE: 1. To guarantee recognition at next clock. DC SPECIFICATIONS IN HOLD Weak Pullups on ADV, RD, WR, WRL, BHE Weak Pulldowns on ALE, INST Min Max Units 50K 250K VCC e 5.5V, VIN e 0.45V 10K 50K VCC e 5.5V, VIN e 2.4 270846 – 25 13 AUTOMOTIVE 87C196KC EXTERNAL CLOCK DRIVE Symbol Parameter Min Max Units 1/TXLXL TXLXL Oscillator Frequency 4.0 16.0 MHz Oscillator Frequency 62.5 250 ns TXHXX High Time 22 ns TXLXX Low Time 22 ns TXLXH Rise Time 10 ns TXHXL Fall Time 10 ns EXTERNAL CLOCK DRIVE WAVEFORMS 270846 – 26 An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts-up. This is due to interaction between the amplifier and its feedback capacitance. Once the external signal meets the VIL and VIH specifications, the capacitance will not exceed 20 pF. AC TESTING INPUT, OUTPUT WAVEFORMS 270846 – 27 AC Testing inputs are driven at 2.4V for a Logic ‘‘1’’ and 0.45V for a Logic ‘‘0’’ Timing measurements are made at 2.0V for a Logic ‘‘1’’ and 0.8V for a Logic ‘‘0’’. FLOAT WAVEFORMS 270846 – 28 For Timing Purposes a Port Pin is no Longer Floating when a 100 mV change from Load Voltage Occurs and Begins to Float when a 100 mV change from the Loaded VOH/VOL Level occurs IOL/IOH e g 15 mA. EXPLANATION OF AC SYMBOLS Each symbol is two pairs of letters prefixed by ‘‘T’’ for time. The characters in a pair indicate a signal and its condition, respectively. Symbols represent the time between the two signal/condition points. Conditions: HÐ High LÐ Low VÐ Valid XÐ No Longer Valid ZÐ Floating Signals: AÐ Address BÐ BHE CÐ DÐ GÐ HÐ CLKOUT DATA Buswidth HOLD HAÐ HLDA 14 LÐ BRÐ RÐ WÐ ALE/ADV BREQ RD WR/WRH/WRL XÐ XTAL1 YÐ READY QÐ Data Out AUTOMOTIVE 87C196KC AC CHARACTERISTICSÐSERIAL PORTÐSHIFT REGISTER MODE SERIAL PORT TIMINGÐSHIFT REGISTER MODE Symbol Parameter Min TXLXL Serial Port Clock Period (BRR t 8002H) TXLXH Serial Port Clock Falling Edge to Rising Edge (BRR t 8002H) TXLXL Serial Port Clock Period (BRR e 8001H) TXLXH Serial Port Clock Falling Edge to Rising Edge (BRR e 8001H) 2 TOSC b 50 TQVXH Output Data Setup to Clock Rising Edge 2 TOSC b 50 TXHQX Output Data Hold after Clock Rising Edge 2 TOSC b 50 TXHQV Next Output Data Valid after Clock Rising Edge TDVXH Input Data Setup to Clock Rising Edge TXHDX Input Data Hold after Clock Rising Edge TXHQZ Last Clock Rising to Output Float Max 6 TOSC 4 TOSC b 50 Units ns 4 TOSC a 50 ns 2 TOSC a 50 ns 4 TOSC ns ns ns 2 TOSC a 50 ns TOSC a 50 ns 0 ns 1 TOSC ns WAVEFORMÐSERIAL PORTÐSHIFT REGISTER MODE SERIAL PORT WAVEFORMÐSHIFT REGISTER MODE 270846 – 29 15 AUTOMOTIVE 87C196KC EPROM SPECIFICATIONS AC EPROM Programming Characteristics Operating Conditions: Load Capacitance e 150 pF, TA e a 25§ C g 5§ C, VCC, VREF e 5V, VSS, ANGND e 0V, VPP e 12.50V g 0.25V, EA e 12.50V g 0.25V Symbol Description Min Max Units TSHLL Reset High to First PALE Low TLLLH PALE Pulse Width 1100 TOSC 50 TOSC TAVLL TLLAX Address Setup Time 0 TOSC Address Hold Time 100 TOSC TPLDV PROG Low to Word Dump Valid 50 TOSC TPHDX Word Dump Data Hold 50 TOSC TDVPL Data Setup Time 0 TOSC TPLDX Data Hold Time 400 TOSC TPLPH(2) PROG Pulse Width 50 TOSC TPHLL PROG High to Next PALE Low 220 TOSC TLHPL PALE High to PROG Low 220 TOSC TPHPL PROG High to Next PROG Low 220 TOSC TPHIL PROG High to AINC Low 0 TOSC TILIH AINC Pulse Width 240 TOSC TILVH PVER Hold after AINC Low 50 TOSC TILPL AINC Low to PROG Low 170 TPHVL PROG High to PVER Valid TOSC 220 TOSC NOTES: 1. Run Time Programming is done with FOSC e 6.0 MHz to 12.0 MHz, VREF e 5V g 0.50V. TA e a 25§ C to g 5§ C and VPP e 12.50V. For run-time programming over a full operating range, contact the factory. 2. This specification is for the Word Dump Mode. For programming pulses, use 300 TOSC a 100 ms. DC EPROM Programming Characteristics Symbol IPP Description VPP Supply Current (When Programming) Min Max Units 100 mA NOTE: VPP must be within 1V of VCC while VCC k 4.5V. VPP must not have a low impedance path to ground of VSS while VCC l 4.5V. 16 AUTOMOTIVE 87C196KC EPROM PROGRAMMING WAVEFORMS SLAVE PROGRAMMING MODE DATA PROGRAM MODE WITH SINGLE PROGRAM PULSE 270846 – 30 SLAVE PROGRAMMING MODE IN WORD DUMP WITH AUTO INCREMENT 270846 – 31 17 AUTOMOTIVE 87C196KC SLAVE PROGRAMMING MODE TIMING IN DATA PROGRAM WITH REPEATED PROG PULSE AND AUTO INCREMENT 270846 – 32 18 AUTOMOTIVE 87C196KC 10-BIT A/D CHARACTERISTICS The speed of the A/D converter in the 10-bit mode can be adjusted by setting a clock prescaler on or off. At high frequencies more time is needed for the comparator to settle. The maximum frequency with the clock prescaler disabled is 6 MHz. The conversion times with the prescaler turned on or off is shown in the table below. The ADÐTIME register has not been characterized for the 10-bit mode. of VREF. VREF must be close to VCC since it supplies both the resistor ladder and the digital section of the converter. A/D CONVERTER SPECIFICATIONS The specifications given below assume adherence to the Operating Conditions section of this data sheet. Testing is performed with VREF e 5.12V. The converter is ratiometric, so the absolute accuracy is dependent on the accuracy and stability Clock Prescaler On IOC2.4 e 0 Clock Prescaler Off IOC2.4 e 1 156.5 States 19.5 ms @ 16 MHz 89.5 States 29.8 ms @ 6 MHz Parameter Typical (3) Resolution Absolute Error Minimum Maximum Units* 1024 10 1024 10 Levels Bits 0 g4 LSBs Full Scale Error g3 LSBs Zero Offset Error g3 LSBs Non-Linearity Differential Non-Linearity Error Channel-to-Channel Matching 0 g4 LSBs l b1 a2 LSBs 0 g1 LSBs Repeatability g 0.25 LSBs Temperature Coefficients: Offset Full Scale Differential Non-Linearity 0.009 0.009 0.009 LSB/§ C LSB/§ C LSB/§ C Off Isolation b 60 Notes dB 1, 2 Feedthrough b 60 dB 1 VCC Power Supply Rejection b 60 dB 1 Input Resistance 750 1.2K X DC Input Leakage 0 3.0 mA Sample Time: Prescaler On Prescaler Off 16 8 States States Input Capacitance 3 pF NOTES: *An ‘‘LSB’’, as used here, has a value of approximately 5 mV. 1. DC to 100 KHz. 2. Multiplexer Break-Before-Make Guaranteed. 3. Typical values are expected for most devices at 25§ C. 19 AUTOMOTIVE 87C196KC 8-BIT MODE A/D CHARACTERISTICS Sample Time 20 States The 8-bit mode trades off resolution for a faster conversion time. The ADÐTIME register must be used when performing an 8-bit conversion. Convert Time 56 States A6H in ADÐTIME 9.8 ms @ 16 MHz The following specifications are tested @ 16 MHz with OA6H in ADÐTIME. The actual ADÐTIME register is tested with all possible values, to ensure functionality, but the accuracy of the A/D converter is not. Parameter Typical Minimum Maximum Units* 256 8 256 8 Levels Bits 0 g2 Resolution Absolute Error Full Scale Error g1 Zero Offset Error g2 LSBs LSBs LSBs Non-Linearity Differential Non-Linearity Error Notes 0 g2 LSBs l b1 a1 LSBs g1 LSBs Channel-to-Channel Matching Repeatability g 0.25 LSBs Temperature Coefficients: Offset Full Scale Differential Non-Linearity 0.003 0.003 0.003 LSB/§ C LSB/§ C LSB/§ C NOTES: *An ‘‘LSB’’, as used here, has a value of approximately 20 mV. 1. Typical values are expected for most devices at 25§ C. 8XC196KB TO 87C196KC DESIGN CONSIDERATIONS 1. Memory Map. The 87C196KC has 512 bytes of RAM/SFRs and 16K of ROM/EPROM. The extra 256 bytes of RAM will reside in locations 100H – 1FFH and the extra 8K of EPROM will reside in locations 4000H–5FFFH. These locations are external memory on the 87C196KB. 2. The CDE pin on the KB has become a VSS pin on the KC to support 16 MHz operation. 3. EPROM programming. The 87C196KC has a different programming algorithm to support 16K of on-board memory. When performing Run-Time Programming, use the section of code on page 99 of the 80C196KC User’s Guide, Order Number 270704. 20 4. ONCE Mode Entry. The ONCE mode is entered on the 87C196KC by driving the TXD pin low on the rising edge of RESET. The TXD pin is held high by a pullup that is specified at 1.4 mA and remain at 2.0V. This Pullup must not be overridden or the 87C196KC will enter the ONCE mode. 5. During the bus HOLD state, the 87C196KC weakly holds RD, WR, ALE, BHE and INST in their inactive states. The 87C196KB only holds ALE in its inactive state. 6. A RESET pulse from the 87C196KC is 16 states rather than 4 states as on the 87C196KB (i.e., a watchdog timer overflow). This provides a longer RESET pulse for other devices in the system. AUTOMOTIVE 87C196KC 87C196KC B-3 STEP ERRATA 1. NMI during PTS skips an address: When an NMI interrupts a PTS routine, the first byte of the instruction following completion of the PTS cycle is lost. This results in incorrect code execution. Workaround: NMI must be disabled using external hardware during any PTS activity. 2. QBD port glitch. There is a strong negative glitch on all QBD Port pins (P1.x and P2.6, P2.7) synchronous with the first falling edge of CLKOUT. This glitch lasts about 10 ns, and only occurs one time following the initial application of VCC. The time for the pin to return to VCC may be several microseconds, depending on pin loading capacitance. Workaround: External systems and devices should be disabled from responding to this glitch until after the first CLKOUT falling edge has occurred. 3. Divide error during HOLD or READY. The result of a signed divide instruction may be off by one if executed while the device is held off the bus by HOLD or READY and the queue is empty. Specific timings of HOLD or READY going active or inactive must be met. Workaround for HOLD: disable HOLD during signed divide operations (using hardware or software). Workaround for READY: problem will only occur if unlimited wait state mode is selected, and 14 or more wait states are inserted. 4. The HSI unit has two errata: one dealing with resolution and the other with first entries into the FIFO. The HSI resolution is 9 states instead of 8 states. Events on the same line may be lost if they occur faster than once every 9 state times. There is a mismatch between the 9 state time HSI resolution and the 8 state time timer. This causes one time value to be unused every 9 timer counts. Events may receive a time-tag on one count later than expected because of this ‘‘skipped’’ time value. If the first two events into an empty FIFO (not including the Holding Register) occur in the same internal phase, both are recorded with one timetag. Otherwise, if the second event occurs within 9 states after the first, its time-tag is one count later than the first time tag. If this is the ‘‘skipped’’ time value, the second event’s time-tag is 2 counts later than the first’s. If the FIFO and Holding Register are empty, the first event will transfer into the Holding Register after 8 state times, leaving the FIFO empty again. If the second event occurs after this time, it will act as a new first event into an empty FIFO. DATASHEET REVISION HISTORY The following are the key differences between this datasheet and the -003 version: 1. The ‘‘advanced information’’ status was dropped and replaced with production status (no label). 2. Trademarks were updated. 21