ETC AOP-12D

AOP-12D
Multi-Function
Analogue Output Card
User Manual
AOP-12d
User Manual
Document Part N°
Document Reference
Document Issue Level
0127-0146
AOP-12d\..\0127-0146.doc
2.0
Manual covers PCBs identified
KFA12o Rev. B
All rights reserved. No part of this publication may be reproduced, stored in any retrieval system, or
transmitted, in any form or by any means, electronic, mechanical, photocopied, recorded or otherwise,
without the prior permission, in writing, from the publisher. For permission in the UK contact Blue Chip
Technology.
Information offered in this manual is correct at the time of printing. Blue Chip Technology accepts no
responsibility for any inaccuracies. This information is subject to change without notice.
All trademarks and registered names acknowledged.
Blue Chip Technology Ltd.
Chowley Oak, Tattenhall,
Chester, Cheshire, CH35 9EX.
Telephone : (01829) 772000 Facsimile : (01829) 772001.
Amendment History
Issue
Level
1.0
2.0
Issue
Date
9/8/95
20/12/95
Author
SH
EGW
Amendment Details
First approved issue, new front sheet.
Addition of EMC information to Technical Section.
Errors corrected. References to current outputs
removed. Added layout diagram. Earlier part no.
was 127-038. Filename was ...\Userg.doc
Contents
OUTLINE DESCRIPTION
1
SPECIFICATION
Analogue Outputs
Digital Input/Outputs
Timers
Board Connectors
Electromagnetic Compatibility (EMC)
2
2
3
4
4
5
QUICK INSTALLATION
Base Address
Interrupts
DMA Settings
Fitting the Card
7
7
7
8
8
USING THE CARD
External Input/Output Connections
Analogue Connections
Analogue Voltage Outputs
Digital Connections
9
9
9
10
11
OPERATION OF THE CARD
Programmable Digital Input/Outputs
Control Codes
Timers
Timer Initialisation
DAC Section
Auto Channel Scanning
12
12
13
14
16
17
18
MAPS AND REGISTERS
Card Address Map
DAC Control Register
Channel Enable Registers
19
19
19
20
SAMPLE PROGRAM DESCRIPTIONS
QBASIC and C Examples
22
22
Blue Chip Technology Ltd.
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Contents
DETAILED CARD INSTALLATION
Base Address
Interrupts
DMA Settings
Card Layout Diagram
23
23
25
26
27
APPENDIX A - NUMBERING SYSTEMS
Binary and Hexadecimal Numbers
Base Address Selection
28
28
31
APPENDIX B - PC MAPS
PC XT/AT I/O Address Map
PC XT Interrupt Map
PC AT Interrupt Map
DMA Channels
32
32
33
34
34
APPENDIX C - USING DMA
The DMA Controller
The DMA Controller Registers
Addressing
DMA Limitations
Programming Example
35
35
37
40
41
42
Outline Description
Page 1
OUTLINE DESCRIPTION
The AOP-12d is a PC-compatible short card which provides digital inputs and
outputs, and analogue outputs.
There are 24 TTL compatible programmable digital input/outputs available
externally. There are also three programmable timers. One of the timer outputs
is available externally to the user.
There are 12 analogue outputs available as ±10 Volts. Output resolution is
12 bits.
DMA data transfer is available on the analogue output channels.
Blue Chip Technology Ltd.
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Page 1
Page 2
Specification
SPECIFICATION
Analogue Outputs
Analogue Outputs
12 channels
Resolution
12 Bit Monotonic
Voltage Outputs
±10 Volts @ 10mA maximum one O/P,
or 5mA each from all O/Ps
Output Error Volts
0.5% of Span
Output Settling Time
3µS to ±1 LSB
Data Transfer
I/O Port or DMA
DMA Channels Supported
1,2 and 3
Fastest DMA Transfer Rate
Channel Selection
12µS per Transfer
Any or all channels may be selected to
be updated
DMA Transfer Initialisation
Software Start Signal
Maximum Time Skew
Channel 1 To Channel 12
Between Channels
144µS
12µS
DMA Timing Source
On-board Programmable Timer
Page 2
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Blue Chip Technology Ltd.
Specification
Page 3
Digital Input/Outputs
Number of Channels
24
Digital Inputs
High Level Input
Current
2.2 Volts minimum
10µA sink
Low Level Input
Current
0.8 Volts maximum
10µA source
Digital Outputs
Logic High Voltage
Current
3.5 Volt minimum
400µA source
Logic Low Voltage
Current
0.4 Volt
2.5mA sink
Blue Chip Technology Ltd.
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Page 3
Page 4
Specification
Timers
Number Of Timer Channels
3
Timer Usage
Timer 0
Timer 1
Timer 2
Pre-Scalar for timer 1
Timer for DMA transfer
Uncommitted (output available)
Timer 0
Resolution
Minimum Time
Maximum Time
1µS
2µS
130mS
Timer 1
Resolution
Minimum Time
Maximum Time
timer 0 output value
4µS
2.3 hours
Timer 2
Resolution
Minimum Time
Maximum Time
1µS
2µS
130mS
Board Connectors
PC ISA 8-bit card
Analogue Signals
Digital Signals
Page 4
50 Way Male `D' Type
50 Way IDC Male Box Header
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Blue Chip Technology Ltd.
Specification
Page 5
ELECTROMAGNETIC COMPATIBILITY (EMC)
This product meets the requirements of the European EMC Directive
(89/336/EEC) and is eligible to bear the CE mark.
It has been assessed operating in a Blue Chip Technology Icon industrial PC.
However, because the board can be installed in a variety of computers, certain
conditions have to be applied to ensure that the compatibility is maintained. It
meets the requirements for an industrial environment ( Class A product) subject
to those conditions.
• The board must be installed in a computer system which provides screening
suitable for the industrial environment.
• Any recommendations made by the computer system manufacturer/supplier
must be complied with regarding earthing and the installation of boards.
• The board must be installed with the backplate securely screwed to the
chassis of the computer to ensure good metal-to-metal (i.e. earth) contact.
• Most EMC problems are caused by the external cabling to boards. With
analogue boards particular attention must be paid to this aspect. It is
imperative that any external cabling to the board is totally screened, and that
the screen of the cable connects to the metal end bracket of the board and
hence to earth. It is recommended that round screened cables with a braided
wire screen are used in preference to those with a foil screen and drain wire.
Use metal connector shells which connect around the full circumference of
the screen; they are far superior to those which earth the screen by a simple
“pig-tail”. Standard ribbon cable will not be adequate unless it is contained
wholly within the cabinetry housing the industrial PC.
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Page 5
Page 6
Specification
• If difficulty with interference is experienced the cable should also be fitted
with a ferrite clamp as close possible to the connector. The preferred type is
the Chomerics clip-on style, type H8FE-1004-AS.
• It is recommended that cables are kept as short as possible, particularly
when dealing with low level signals.
• Ensure that the screen of the external cable is bonded to a good RF earth at
the remote end of the cable.
Failure to observe these recommendations may invalidate the EMC compliance.
Warning
This is a Class A product. In a domestic environment this product
may cause radio interference in which case the user may be required
to take adequate measures.
EMC Specification
A Blue Chip Technology Icon industrial PC fitted with this card meets the
following specification:
Emissions
EN 55022:1995
Radiated
Class A
Conducted
Class A & B
Immunity
EN 50082-1:1992 incorporating:
Electrostatic Discharge
Performance Criteria B
Radio Frequency Susceptibility
Performance Criteria A
Fast Burst Transients
Performance Criteria B
Page 6
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IEC 801-2:1984
IEC 801-3:1984
IEC 801-4:1988
Blue Chip Technology Ltd.
Quick Installation
Page 7
QUICK INSTALLATION
Before installing the card into your computer system, there are a number of
links which must be set.
The settings of these links will depend upon the computer system into which the
card is being fitted. Users unfamiliar with the settings of links should refer to
the section “Detailed Card Installation”. For those unfamiliar with Binary and
Hexadecimal numbers, a brief explanation is included in the Appendices.
Base Address
Select an unused I/O address range for the card. The card requires a block of
16 contiguous addresses.
The base address is set on jumper block JP3. Fitting a link is equivalent to a
logic “0”. Leaving the link open is equivalent to a logic “1”. The card is
shipped with the default address setting of 300 Hex. This is suitable for most
small installations.
Interrupts
The DAC generates interrupts at the end of a DMA transfer. Interrupts IRQ2 to
IRQ7 are provided. The PIO and the Timer cannot generate interrupts.
The interrupt setting is selected by a link on jumper block JP1. If interrupt
operation is not required leave the link off.
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Page 7
Page 8
Quick Installation
DMA Settings
The card can transfer data from memory to the analogue outputs using DMA.
The settings are controlled by links on jumper blocks JP2 and JP4. DMA
channels 1 and 3 are provided.
JP4 controls the setting of the DMA Request channels for the DAC. JP2
controls the setting of the DMA Acknowledge channels. The settings must be
the same on both JP2 and JP4. If DMA operation is not required, the links may
left open to allow the unused channels to be used by other cards.
The appendix contains a section explaining the use of DMA
Fitting the Card
Once all the links have been set, the card can be installed into the host
computer.
Observe all safety precautions and anti-static precautions. If possible try and
locate the card away from 'noisy' cards such as hard disc controllers, network
cards and processor cards.
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Using the Card
Page 9
USING THE CARD
External Input/Output Connections
The AOP-12d has two connectors for external circuitry.
The analogue output signals are available at a standard 50 pin D-type connector
which protrudes through the end bracket of the printed circuit board.
The digital input output signals are presented on a 50 way IDC header at the
inner end of the printed circuit board. These signals may be brought to a
connector on a second bracket the rear cover of the PC using a 50 way ribbon
extension cable. Filtered connectors are recommended for EMC.
Analogue Connections
The following table shows the pin out of the D-type analogue connector CON1.
The pins are arranged in three rows.
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
USAGE
V output 1
No connect
No connect
V output 2
No connect
No connect
V output 3
No connect
No connect
V output 4
No connect
No connect
V output 5
No connect
No connect
V output 6
No connect
Blue Chip Technology Ltd.
PIN
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
USAGE
No connect
V output 7
No connect
No connect
V output 8
No connect
No connect
V output 9
No connect
No connect
V output 10
No connect
No connect
V output 11
No connect
No connect
01270146.doc
PIN
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
USAGE
V output 12
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
No connect
Analogue ground
No connect
Page 9
Page 10
Using the Card
Analogue Voltage Outputs
The analogue output signals from the AOP-12d are available as voltages only,
with the ability to supply a limited current.
Each of the 12 output signals (Voutput-1 to Voutput-12) has a corresponding
analogue ground or 0 Volt connection. The voltage outputs are referenced to
these connections. Measuring output voltages with reference to other ground
points (particularly the digital ground) will give electrically noisy results.
The voltage output has a span from +10 Volts to -10 Volts with an output drive
of 10mA maximum for any single output and 5mA maximum each for all
outputs simultaneously.
If large capacitive loads are to be connected to the voltage output, it is
recommended that a series resistance of approximately 100 ohms is placed in
series with the output voltage to avoid oscillations occurring at the output.
Page 10
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Blue Chip Technology Ltd.
Using the Card
Page 11
Digital Connections
The following table shows the pin out of the IDC digital signal connector
CON2. The pins are arranged in two rows.
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
SIGNAL
DIO port A, bit 0
DIO port A, bit 2
DIO port A, bit 4
DIO port A, bit 6
DIO port B, bit 0
DIO port B, bit 2
DIO port B, bit 4
DIO port B, bit 6
DIO port C, bit 0
DIO port C, bit 2
DIO port C, bit 4
DIO port C, bit 6
Digital ground
Digital ground
Digital ground
Timer2 Output
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
SIGNAL
DIO port A, bit 1
DIO port A, bit 3
DIO port A, bit 5
DIO port A, bit 7
DIO port B, bit 1
DIO port B, bit 3
DIO port B, bit 5
DIO port B, bit 7
DIO port C, bit 1
DIO port C, bit 3
DIO port C, bit 5
DIO port C, bit 7
Digital ground
Digital ground
Digital ground
Timer 0 Output
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
Digital ground
DIO - Digital input/output.
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Page 11
Page 12
Operation of the Card
OPERATION OF THE CARD
Programmable Digital Input/Outputs
The AOP-12d includes an NEC µPD71055 device which is equivalent to an
Intel 8255 PIO.
This device provides 24 programmable digital I/O channels. It is suitable for
sensing the presence of, or driving TTL connections only. These connections
should be kept as short as possible, less than 2 metres is recommended.
The digital I/O appears to the PC as four ports. The first three can be set as
input or output by writing suitable codes to the fourth Control Port.
These four ports are mapped into the AOP-12d address map as follows:
BASE
+4
+5
+6
+7
Programmable Digital I/O Port A (read/write);
Programmable Digital I/O Port B (read/write);
Programmable Digital I/O Port C (read/write);
Control Port (write only).
A summary of the codes required to change the operation of the ports are given
later. A typical sequence of events to use this feature would be :
• Decide on the input/output mix and write the appropriate code to
BASE + 7.
• Read from the selected output port or write to the selected output port.
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Operation of The Card
Page 13
Control Codes
The µPD71055 can operate in one of 3 modes.
The first (Mode 0) provides for simple inputs and outputs for three, 8 bit ports.
Data is written to or read from a specified port (A, B, or C) without the use of
handshaking.
The following table gives a summary of the most commonly used ‘Control
Words’ which must be written to the control port to configure the µPD71055
I/O ports in Mode 0.
CONTROL
WORD
(hex)
80
81
82
83
88
89
8A
8B
90
91
92
93
98
99
9A
9B
CONTROL
WORD
(decimal)
128
129
130
131
136
137
138
139
144
145
146
147
152
153
154
155
SET ALL
of PORT
A as
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
SET ALL
of PORT
B as
Output
Output
Input
Input
Output
Output
Input
Input
Output
Output
Input
Input
Output
Output
Input
Input
SET HIGH
4 BITS of
C as
Output
Output
Output
Output
Input
Input
Input
Input
Output
Output
Output
Output
Input
Input
Input
Input
SET LOW
4 BITS of
C as
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Output
Input
Mode 1 enables the transfer of data to or from a specified 8 bit port (A or B) in
conjunction with strobes or handshaking signals on port C.
In Mode 2, data is transferred via one bi-directional 8 bit port (A) with
handshaking (port C).
Refer to the µPD71055 or i8255 data sheet for full details of the settings and use
of Modes 1 and 2.
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Page 14
Operation of the Card
Timers
The AOP-12d includes an NEC µPD71054 timer chip which is equivalent to an
Intel 8254.
The timer chip contains three independent 16 bit counters which may be
operated in different modes. There are five basic modes of operation with each
mode providing a different output signal from the three output pins of the
device.
IMPORTANT
Timers 0 and 1 are crucial to the operation of the board. The DAC
section is controlled by the output of these timers so for all operating
modes of the DAC, these timers must be configured to run. See the
section on TIMER INITIALISATION for code examples to configure
these timers.
The reference clock for timers 0 and 2 is 1Mhz. Timer 1 is in series with the
output of timer 0.
Timer 0 is committed as the first divider for DMA in the AOP-12d and its
output is also available on the external connector.
Timer 2 is uncommitted in the AOP-12d and its output is available on the
external connector.
In DMA mode, timers 0 and 1 set the rate at which data is DMA’d. To set a
particular DMA rate, use the following equation:
Note that the 1 MHz clock is divided by 8 by the circuitry giving
a reference of 125 KHz
DMA RATE (in Hz) = 1250000 / divider
where “divider” = (65536 * TIMER 1 value) + (TIMER 0 value)
Page 14
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Blue Chip Technology Ltd.
1 MHz
Clock
Timer 0 Output
Timer 0
Connection
Timer 1
DMA Transfer
Control Circuit
Operation of The Card
Page 15
Timer 2 Output
Timer 2
Connection
Block Diagram of
Timer Connections
The timer circuit appears to the PC as four ports. These four ports are mapped
into the AOP-12d address map as follows:
BASE
+8
+9
+ 10
+ 11
Timer/Counter 0 (read/write).
Timer/Counter 1 (read/write).
Timer/Counter 2 (read/write).
Control register, (write only).
Bits 6 and 7 in the control register enable and disable Timer 0 and 1, and
Timer 2.
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Page 15
Page 16
Operation of the Card
Timer Initialisation
Before the DAC section can be operated IN ANY MODE Timers 0 and 1 must
be configured. To do this, follow this sequence of writing to the timer registers
Output hex 0 to control register (base + 0). This disables timers 0 and 1.
Read base + 0. This resets the internal state machine logic.
Output hex 34 to the timer control register (base + 11). This sets timer
0 into mode 2.
Output 3 to timer 0 count register (base + 8). This writes 3 into the
LOW 8 bits of the 16 bit counter register.
Output 0 to timer 0 count register (base + 8). This writes 0 into the
HIGH 8 bits of the 16 bit counter register.
Output hex 78 to the timer control register (base + 11). This sets timer
1 into mode 4.
Output hex 1 to timer 1 count register (base + 9). This writes 1 into
the LOW 8 bits of the 16 bit counter register.
Output hex 0 to time 1 count register (base + 9).
Output hex 40 to control register 1 (base + 0).
In BASIC the initialisation sequence would look like this:
10 out (BASEADD + 0,&h0)
20 dummy% = inp(BASEADD)
30 out (BASEADD + 11,&h34)
40 out (BASEAAD + 8,&h03)
50 out (BASEAAD + 8,&h00)
60 out (BASEADD + 11,&h78)
70 out (BASEADD + 9,&h03)
80 out (BASEADD + 9,&h00)
90 out(BASEADD,&h40)
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Blue Chip Technology Ltd.
Operation of The Card
Page 17
DAC Section
The Digital to Analogue converter is accessed as 4 ports. These ports are
mapped into the PC at the following addresses.
BASE
+0
+1
+2
+3
DAC Control register
Channel enable register 1
Channel enable register 3
DAC output register
The DAC is 12 bits wide, therefore two write operations are required to the
DAC output register to load the required value. The low 8 bits are sent first
followed by the high 4 bits.
Output Value
0
2048
4095
Output Voltage
-10 V
0V
+10 V
The DAC section operates in one of two basic modes, I/O or DMA.
To send data to the DAC in I/O mode use the following sequence:
Initialise the timer (see Timer Initialisation above).
Write 0 to BASE + 1 and BASE + 2, this enables all the channels.
Read BASE + 0 , this resets the internal state machine.
Write the low 8 bits of the DAC data into BASE + 3.
Write the high 4 bits of the DAC data into BASE + 3.
Write the channel number to update (1 to 12) to BASE + 0.
Write 0 to BASE + 0.
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Page 17
Page 18
Operation of the Card
To operate in DMA mode updating a single channel use the following sequence:
Initialise the timer, as above.
Program timers 0 and 1 for the required output rate.
Write 0 to BASE + 1 and BASE + 2, this enables all the channels.
Program the DMA controller.
Write the channel number (1 to 12) + 240 to BASE + 0.
Start the DMA operation by reading BASE + 0.
Auto Channel Scanning
In DMA mode it is possible to output to all 12 channels by setting the AUTO
CHANNEL SCANNING bit in channel enable register 2.
When this bit is set, after each DMA transfer the channel number will be
incremented so the next DMA transfer will take place on the next channel.
When the channel reaches 12, it will continue to increment as if channels 13-16
were present, before resetting to channel 1.
To use this mode, the software must set-up a multi-dimensional array to store
the data for 16 channels (12 real + 4 phantom channels).
In BASIC:
DIM dataarray%(numsamples,16)
in C:
int dataarray[numsamples][16]
Software example 4 demonstrates the use of channel scanning.
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Blue Chip Technology Ltd.
Maps and Registers
Page 19
MAPS AND REGISTERS
Card Address Map
BASE
+n
0
0
1
2
3
4
5
6
7
8
9
10
11
R/W
SECTION
FUNCTION
W
R
W
W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DAC
DAC
DAC
DAC
DAC
PIO
PIO
PIO
PIO
Timer
Timer
Timer
Timer
DAC Control register
Initiate DMA transfer / reset state machine logic
Channel Enable register 1
Channel Enable register 2
DAC output data
PIO PORT A data
PIO PORT B data
PIO PORT C data
PIO Control register
Timer 0 count register
Timer 1 count register
Timer 2 count register
Timer control register
DAC Control Register
(Base + 0)
DATA BIT
0
1
2
3
4
5
6
7
*1
FUNCTION
DAC Channel Select / update Bit 0
DAC Channel Select / update Bit 1
DAC Channel Select / update Bit 2
DAC Channel Select / update Bit 3
0 = Disable DMA Request
1 = Enable DMA Request
0 = I/O Mode
1 = DMA Mode
0 = Disable DAC control timers (timers 0 and 1)
1 = Enable DAC control timers (timers 0 and 1)
0 = Disable uncommitted timer 2
1 = Enable uncommitted timer 2
*1
*1
*1
*1
writing 0 into all four bits updates the previously selected DAC output
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Page 19
Page 20
Maps and Registers
Channel Enable Registers
Register 1
DATA BIT
0
1
2
3
4
5
6
7
Page 20
(Base + 1)
FUNCTION
0 = Enable channel 1 output
1 = Disable channel 1 output
0 = Enable channel 2 output
1 = Disable channel 2 output
0 = Enable channel 3 output
1 = Disable channel 3 output
0 = Enable channel 4 output
1 = Disable channel 4 output
0 = Enable channel 5 output
1 = Disable channel 5 output
0 = Enable channel 6 output
1 = Disable channel 6 output
0 = Enable channel 7 output
1 = Disable channel 7 output
0 = Enable channel 8 output
1 = Disable channel 8 output
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Blue Chip Technology Ltd.
Maps and Registers
Register 2
DATA BIT
0
(Base + 2)
6
FUNCTION
0 = Enable channel 9 output
1 = Disable channel 9 output
0 = Enable channel 10 output
1 = Disable channel 10 output
0 = Enable channel 11 output
1 = Disable channel 11 output
0 = Enable channel 12 output
1 = Disable channel 12 output
0 = Disable AUTOMATIC channel scanning
1 = Enable AUTOMATIC channel scanning
0 = Enable DMA Cycle mode
1 = Disable DMA Cycle mode
Not Used, always write 0
7
Not Used, always write 0
1
2
3
4
5
Page 21
*1
*2
*1
When this bit is 1 the selected DAC channel will increment after each DAC update
(DMA MODE ONLY)
*2
When this bit is 1 the AUTO-INITIALISE function of the DMA control is disabled
(See USING DMA for a description of AUTO-INITIALISE)
Blue Chip Technology Ltd.
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Page 21
Page 22
Sample Program Descriptions
SAMPLE PROGRAM DESCRIPTIONS
The disk supplied with the card contains several example programs to
demonstrate the various operating modes.
QBASIC and C Examples
EXAMPLE1.BAS
EXAMPLE1.C
These demonstrate the simple I/O mode to output a single value to one analogue
output channel.
EXAMPLE2.BAS
EXAMPLE2.C
These demonstrate reading and writing to the digital I/O.
EXAMPLE3.BAS
EXAMPLE3.C
These demonstrate the DMA mode to output a sine wave to a single analogue
output channel
EXAMPLE4.BAS
EXAMPLE4.C
These demonstrate the DMA mode to output a sine wave to all twelve analogue
output channels.
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Blue Chip Technology Ltd.
Detailed Card Installation
Page 23
DETAILED CARD INSTALLATION
Before installing the card into your computer system, there are a number of
links which must be set. The settings of these links will depend upon the
computer system into which the card is being fitted.
The positions of these links are shown on the card layout diagram towards the
end of this manual
Base Address
The card may be located in any 62 pin slot in the PC motherboard but must be
set up to appear at a specified address in the I/O port map. Available positions
are shown in the IBM-PC Technical Reference Guide. However, for those who
do not possess a copy of this document, a good place is the location normally
allocated to the prototyping card as supplied by IBM. This address is 300 Hex
which is the factory default setting.
However, no two devices should be used while set to the same address since
contention will occur and neither card will work. If your machine contains a
card with a conflicting address then another reasonably safe address to use is
200 to 21F Hex.
A set of links are provided on the card to set the base address within the IBMPC I/O port map. The address is in binary with the presence of a link
representing a 0 and the absence of a link representing a 1.
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Detailed Card Installation
To set the base address to 300 Hex, locate the jumper block JP3 labelled Base
Address. Set the following pattern on the links as indicated below with
Connector CON2 on right hand side and the gold fingers to the lower edge.:-
Other examples are:
Address hex 200
Address hex 240
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Detailed Card Installation
Page 25
Interrupts
The DAC generates an interrupt signal at the end of a DMA transfer.
The interrupt is selected on jumper block JP1.
The diagram below shows the DAC set to produce an interrupt request on IRQ3.
The second example shows the setting if the DAC generates interrupt request
IRQ6.
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Detailed Card Installation
DMA Settings
The DMA selection is set on two sets of jumper blocks, JP2 and JP4.
JP4 controls which channel the DAC uses to request Direct Memory Access.
Only channels 1,2 and 3 are available. Jumper JP2 sets the channel on which
the DMA controller acknowledges the request. It is essential that the pattern of
links on the two jumper blocks correspond.
The example below shows the link settings for the DAC to generate DRQ1 and
receive DACK1.
1
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2
3
1
2
3
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Detailed Card Installation
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KFA12o
Card Layout Diagram
Card Layout showing Selector Link Positions
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Appendix A
APPENDIX A - NUMBERING SYSTEMS
Binary and Hexadecimal Numbers
The normal numbering system is termed DECIMAL because there are ten
possible digits (0 to 9) in any single column of numbers. Decimal numbers are
also referred to as numbers having a Base 10. When counting, the numbers
increment in the units column from 0 up to 9. The next increment resets the
units column to 0 and carries over 1 into the next column. This 1 indicates that
there has been a full ten (the base number) counts in the units column. The
second column is therefore termed the “tens” column.
It is more convenient when programming to use a number system that provides
a clearer picture of the hardware at an operational or register level. The two
most common number systems used are BINARY and HEXADECIMAL.
These two systems provide an alternative representation to decimal numbers.
For a binary number there are only 2 possible values (0 or 1) and as a result
binary numbering is often known as Base 2. When counting in binary numbers,
the number increments the units column from 0 to 1. At the next increment the
units column is reset to 0 and 1 is carried over to the next column. This column
indicates that a full two counts have occurred in the units column. Now the
second column is termed the “twos” column.
Hexadecimal numbers may have 16 values (0 to 9 followed by the letters A to
F). It is also known as a system with the Base 16. With this counting system
the units increment from 0 to 9 as with the decimal system, but at the next count
the units column increments from 9 to A and then B, C and so on up to F. After
F the units column resets to 0 and the next column increments from 0 to 1.
This 1 indicates that sixteen counts have occurred in the units column. The
second column is termed the “sixteen’s” column.
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Appendix A
Page 29
The following table shows how the three systems indicate successive numbers
Decimal
Base 10
0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
Binary
Base 2
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
1 0 1
1 0 1
1 1 0
1 1 0
1 1 1
1 1 1
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Hexadecimal
Base 16
0
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
8
0
9
0
A
0
B
0
C
0
D
0
E
0
F
1
0
1
1
1
2
1
3
1
4
Notice how the next higher column does not increment until the lesser one to its
right has overflowed.
Binary representation is ideally suited where a visual representation of a
computer register or data is needed. Each column is termed a BIT (from Binary
digIT). Only five Bits are shown in the above table. With larger numbers,
more Bits are required. Normally Bits are arranged in groups of eight termed
BYTES. By definition there are 8 BITS per BYTE. Each Bit (or column) has a
value. In the binary table above the rightmost or least significant column each
digit has a value of 1. Each digit in the next column has a value of 2, the next
4, then 8 and so on.
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Appendix A
The following diagram illustrates this.
BIT No
DECIMAL VALUE
7
128
6
64
5
32
4
16
3
8
2
4
1
2
0
1
To determine the decimal value of a binary pattern, add up the decimal number
of each column containing a binary “1”.
BIT No
DECIMAL VALUE
BINARY NUMBER
7
128
1
6
64
1
5
32
0
4
16
0
3
8
0
2
4
1
1
2
1
0
1
0
The above example shows the binary pattern that is equivalent to 198 Decimal.
The binary string defining a Byte can be unwieldy. To make it less error prone,
the 8 bits forming a byte are divided into two groups of 4 bits, known as
NIBBLES. With four bits there are 16 possible numeric combinations
(including zero). A convenient method of representing each nibble is to use the
hexadecimal base 16 system.
When converting binary to hex, the byte is divided into nibbles each represented
by a single hex digit. This technique is applied to the selection of the base
address for the circuit board. The following diagram illustrates the construction
of a hex number.
BIT No
NIBBLE VALUE
BINARY NUMBER
7
8
1
6
4
1
5
2
0
4
1
0
3
8
0
2
4
1
1
2
1
0
1
0
ÀÄÄÄ-ÄÂÄÄÄÄÄÄÄÙÀÄÄÄÄÄÂÄÄÄÄÄÄÙ
HEXADECIMAL:
C
6
Hexadecimal upper nibble = (1 x 8) + (1 x 4) + (0 x 2) + (0 x 1) = 12
lower nibble = (0 x 8) + (1 x 4) + (1 x 2) + (0 x 1) = 6
The resulting value is C6 Hex, since 12 Decimal is C Hex.
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Appendix A
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Base Address Selection
Each column can be physically represented on the board by a pair of pins. In
practice, the boards cover a range of addresses (usually 16 Decimal). Therefore
the low order four bits are not included, but two higher order bits are added.
This gives an address range of 0 to 3F0 Hex . The following diagram shows a
typical set of pins.
Here a link is fitted to denote a binary or logic “0”, or left open to indicate a
binary or logic “1”. The example shows a base address setting of 300 Hex.
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Appendix B
APPENDIX B - PC MAPS
PC XT/AT I/O Address Map
Address
Allocated to:
000-01F
020-03F
040-05F
060-06F
070-07F
080-09F
0A0-0BF
0F0
0F1
0F8-0FF
1F0-1F8
200-207
278-27F
2F8-2FF
300-31F
360-36F
378-37F
380-38F
3A0-3AF
3B0-3BF
3C0-3CF
3D0-3DF
3F0-3F7
3F8-3FF
DMA Controller 1 (8237A-5)
Interrupt Controller 1 (8259A)
Timer (8254)
Keyboard Controller (8742) Control Port B
RTC and CMOS RAM, NMI Mask (Write)
DMA Page Register (Memory Mapper)
Interrupt Controller 2 (8259)
Clear NPX (80287) Busy
Reset NPX (80287)
Numeric Processor Extension (80287)
Hard Disk Drive Controller
Reserved
Reserved for Parallel Printer Port 2
Reserved for Serial Port 2
Reserved
Reserved
Parallel Printer Port 1
Reserved for SDLC Communications, Bisync 2
Reserved for Bisync 1
Reserved
Reserved
Display Controller
Diskette Drive Controller
Serial Port 1
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Appendix B
Page 33
PC XT Interrupt Map
Number
Allocated to:
NMI
0
1
2
3
Parity
Timer
Keyboard
Reserved
Asynchronous Communications (Secondary)
SDLC Communications
Asynchronous Communications (Primary)
SDLC Communications
Fixed Disk
Diskette
Parallel Printer
4
5
6
7
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Appendix B
PC AT Interrupt Map
Level
Allocated to:
CPU NMI
Ctlr 1
Parity or I/O Channel Check
Ctlr 2
IRQ 0
IRQ 1
IRQ 2
IRQ 8
IRQ 9
IRQ 10
IRQ 11
IRQ 12
IRQ 13
IRQ 14
IRQ 15
IRQ 3
IRQ 4
IRQ 5
IRQ 6
IRQ 7
(Interrupt Controllers)
Timer Output 0
Keyboard (Output Buffer Full)
Interrupt from CTLR 2
Real-time Clock Interrupt
S/w Redirected to INT 0AH (IRQ 2)
Reserved
Reserved
Reserved
Co.-processor
Fixed Disk Controller
Reserved
Serial Port 2
Serial Port 1
Parallel Port 2
Diskette Controller
Parallel Port 1
DMA Channels
0
1
2
3
Page 34
Memory Refresh
Spare
Floppy Disk Drive
Spare
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Appendix C
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APPENDIX C - USING DMA
Direct Memory Access or DMA is a process by which data can be transferred
directly from the memory of the PC into an I/O card or directly from the I/O
card into the PC memory with no intervention from the processor. This can
greatly increase the throughput of data and at the same time, reduce the
overhead of processor time.
The DMA Controller
DMA is controlled by the PC using one of two DMA Controllers. The DMA
Controllers are INTEL 8237 or compatible devices, each containing four
channels. The first one is used for byte transfers in the bottom 1 MB of system
memory, the second can transfer words into the bottom 16 MB.
Blue Chip Technology boards only allow DMA channels 1 or 3 on the first
controller to be used. Normally channel 0 is reserved for memory refresh
control and channel 2 is used by the floppy disk drives.
In order to begin a DMA transfer, first the I/O board must be configured to
enable DMA operation - consult the relevant section of the manual on how to do
this. Secondly, the DMA controller must be programmed to begin the transfer.
The DMA controller is programmed by writing to I/O ports in much the same
way as the card is programmed.
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Appendix C
These port locations are fixed for all PCs as follows:-
Page 36
I/O
ADDRESS
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000CH
000DH
000EH
000FH
READ/
WRITE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0081H
0082H
0083H
R/W
R/W
R/W
DESCRIPTION
DMA Channel 0 Current Address
DMA Channel 0 Current Word Count
DMA Channel 1 Current Address
DMA Channel 1 Current Word Count
DMA Channel 2 Current Address
DMA Channel 2 Current Word Count
DMA Channel 3 Current Address
DMA Channel 3 Current Word Count
Command/Status Register
DMA Request Register
DMA Single Bit Mask Register
DMA Mode Register
DMA Clear Byte Pointer
DMA Master Clear
Clear Mask Register
DMA Write All Mask Register Bit
Page Register DMA Channel 2
Page Register DMA Channel 3
Page Register DMA Channel 1
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Appendix C
Page 37
The DMA Controller Registers
In order to begin a DMA transfer there are several registers within the DMA
controller which need to be configured. The relevant registers are described
below:Mode Register
7
MODE
Bit 1
6
MODE
Bit 0
Port 0BH
5
AUTO
INC/
DEC
4
AUTO
INIT.
3
TRANS
MODE
Bit 1
2
TRANS
MODE
Bit 0
1
CHAN
SEL
Bit 1
0
CHAN
SEL
Bit 0
Mode Bits
Bit1
0
0
1
1
Bit 0
0
1
0
1
FUNCTION
Demand Mode
Single Mode
Block Mode
Not Used
The mode bits set the particular mode for the channel, normally this will be set
for SINGLE mode.
Auto INC/DEC
0
1
Increment Address
Decrement Address
When a DMA transfer takes place, the transfer address can either be
incremented or decremented after each transfer selected by this bit.
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Appendix C
Auto Initialise
0
1
Disabled
Enabled
If set to AUTO INITIALISE, when the DMA transfer reaches the end of a
block, the DMA controller will reload all its initial values and repeat the
transfer. This is useful on ANALOGUE OUT boards for outputting continuous
wave forms.
Transfer Mode
Bit 1
0
0
1
1
Bit 0
0
1
0
1
FUNCTION
Verify Transfer
Write Transfer
Read Transfer
Not Used
Use WRITE TRANSFER if the I/O board is generating a value to be written
into memory (Analogue in), use read transfer when values are written from
memory into the board (Analogue out).
Channel Select
Bit 1
0
0
1
1
Page 38
Bit0
0
1
0
1
FUNCTION
DMA Channel 0 select
DMA Channel 1 select
DMA Channel 2 select
DMA Channel 3 select
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Appendix C
Mask Register
7
NOT
USED
Page 39
Port 0AH
6
NOT
USED
5
NOT
USED
4
NOT
USED
3
NOT
USED
2
CLR/SET
MASK
1
MASK
Bit 1
0
MASK
Bit 0
CLR/SET Mask
0
1
Clear Mask Bit
Set Mask Bit
Mask
Bit 1
0
0
1
1
Bit 0
0
1
0
1
FUNCTION
Channel 0 select
Channel 1 select
Channel 2 select
Channel 3 select
Setting a mask bit for a particular channel disables the DMA operation on that
channel.
Status Register
7
CHAN
3
DMA
RQ
6
CHAN
2
DMA
RQ
Port 0BH READ
5
CHAN
1
DMA
RQ
4
CHAN
0
DMA
RQ
3
CHAN
3
at
TC
2
CHAN
2
at
TC
1
CHAN
1
at
TC
DMA RQ
1 = DMA Request made on channel N
AT TC
1 = Channel N has reached Terminal Count (TC)
0
CHAN
0
at
TC
The status register indicates which channels have made a DMA request and
which channels have reached Terminal Count. Terminal count is set when the
number of bytes specified by the TRANSFER LENGTH register have been
transferred.
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Appendix C
Clear Byte Pointer Flip Flop
Port 0CH
Any write to this port resets the byte pointer flip flop. This ensures that the first
write to the Start Address or Transfer Length registers will go into the LSB of
that register.
DMA Transfer Start Address Ports 00H, 02H, 04H, 06H
Sets the 16 bit start address for the DMA transfer, send LS Byte first.
Transfer Length
Ports 01H, 03H, 05H, 07H
Sets the 16 bit length of the DMA transfer, send LS Byte first.
Page Register
Ports 83H, 81H, 82H
Sets the upper eight bits of the physical memory address of the DMA transfer.
Addressing
In order for DMA to operate correctly the page register and start address
register should be set-up to inform the DMA controller where in memory the
transfer is to take place.
The INTEL x86 family of microprocessors address memory using 2 address
pointers called SEGMENT and OFFSET, this is called a LOGICAL address.
The microprocessor combines the SEGMENT and OFFSET to produce a
PHYSICAL address which it uses to access the memory.
If we consider a PC which has 1Mbyte of memory, each memory location will
have a PHYSICAL address of 0 to 1048575 (or 0 to FFFFFHex).
It has a LOGICAL range of 0000:0000 to F000:FFFF. The colon is commonly
used to separate the SEGMENT address from the OFFSET address
(Segment:Offset)
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Appendix C
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To convert from a LOGICAL address to a PHYSICAL address use the following
formula:
PHYSICAL ADDRESS = (SEGMENT * 16) + OFFSET
Most programming languages allow access to the SEGMENT and OFFSET
addresses of variables in memory. For example, in QUICK BASIC the
following commands can be used:
DIM dat%(1000)
seg = VARSEG(dat%)
offs = VARPTR(dat%)
In this example, the variables “seg” and “offs” would contain the SEGMENT
and OFFSET addresses of the array “dat%”. In order to pass this address to the
DMA controller the segment and offset values need to be converted into
DMAPAGE and DMAOFFSET addresses as follows:
PhyAdd = (seg * 16) + offs
DMAPAGE = (PhyAdd / 65536) AND 15
DMAOFFSET = PhyAdd AND 65535
DMA Limitations
The DMA controller is only capable of incrementing or decrementing the
DMAOFFSET address, the DMAPAGE value is fixed throughout the transfer.
This means that a maximum of 64K bytes can be transferred in one operation.
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Appendix C
Programming Example
To set-up a DMA transfer the following program sequence is required:
Define an area of memory for the transfer
Set-up the I/O board for DMA operation
Disable the DMA channel being used.
Load the start address into PAGE register. This is the START address
register for the DMA channel being used.
Load the length count into the TRANSFER LENGTH register. Note
that the DMA controller only transfers 8 bits at a time, each value
written to an ANALOGUE OUT board or read from an ANALOGUE
IN board is 2 bytes long so the transfer length will be twice the number
of samples to be taken.
Load the mode for the selected DMA channel.
Enable the DMA channel.
The following extract from a QUICK BASIC program demonstrates how to
program the DMA controller for a WRITE transfer.
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Appendix C
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2000 REM PROGRAM THE DMA CONTROLLER
2005 REM FIRST EXTRACT THE SEGMENT AND OFFSET
ADDRESS OF OUR DATA
2010 seg = VARSEG(DAT%(0))
2020 offs = VARPTR(DAT%(0))
2025 REM Transfer the Logical SEGMENT:OFFSET address
2027 REM into a physical PAGE:OFFSET address
2030 PAGE& = seg1% AND &HF000
2040 PAGE& = PAGE& / 4096
2050 PAGE& = PAGE& AND 15
2060 OFFSET& = seg
2070 OFFSET& = OFFSET& * 16
2080 OFFSET& = OFFSET& + offs
2090 OFFSET& = OFFSET& AND 65535
2100 REM Setup the DMA registers.
2105 OUT (&HA),7: REM DISABLE DMA CHANNEL 3
2110 OUT (&HC), 0: REM RESET BYTE SELECT FF
2120 OUT (&HB), &H47: REM AUTO INC ON CH3,WRITE
TRANSFER, SINGLE MODE
2130 OUT (&H82), PAGE&: REM SET PAGE FOR DMA CH3
2150 OUT (&H6), (OFFSET& AND 255): REM SET UP START
FOR LS 8 BITS
2160 OUT (&H6), (OFFSET& AND &HFF00) / 256: REM SET
UP START FOR MS 8 BITS
2170 OUT (&H7), length% AND 255: REM BYTE COUNT LS 8
BITS
2180 OUT (&H7), length% / 256: REM BYTE COUNT MS
BITS
2190 OUT (&HA), 3: REM ENABLE DMA TXFER
2200 RETURN
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