BR24C32 / BR24C32F / BR24C64 / BR24C64F Memory ICs I2C BUS compatible serial EEPROM BR24C32 / BR24C32F / BR24C64 / BR24C64F The BR24C32 and BR24C64 series are 2-wire (I2C BUS type) serial EEPROMs which are electrically programmable. ∗ I2C BUS is a registered trademark of Philips. zFeatures 1) 4k x 8 bits (32k) serial EEPROM. (BR24C32 / F) 8k x 8 bits (64k) serial EEPROM. (BR24C64 / F) 2) Two wire serial interface. (2Byte Address: BR24E16) 3) Operating voltage range: 2.7V ∼ 5.5V 4) Low current consumption Active (at 5V) : 2.0mA (Typ.) Standby (at 5V) : 1.0µA (Typ.) 5) Auto erase and auto complete functions can be used during write operations. 6) Page write function. BR24C32 / F: 32 bytes BR24C64 / F: 64 bytes 7) DATA security Write protect feature Inhibit to WRITE at low Vcc 8) Noise filters at SCL and SDA pins. 9) Address can be incremented automatically during read operations. 10) Compact packages. 11) Rewriting possible up to 100,000 times. 12) Data can be stored for ten years without corruption. zAbsolute maximum ratings (Ta=25°C) Parameter Symbol Limits −0.3~+6.5 VCC Supply voltage Pd Power dissipation Unit V 450(SOP8) ∗1 800(DIP8) ∗2 mW Storage temperature range Tstg −65~+125 °C Operating temperature range Topr −40~+85 °C − −0.3~VCC+0.3 V Terminal voltage ∗1 Reduced by 4.5mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 8.0mW for each increase in Ta of 1°C over 25°C. zRecommended operating conditions (Ta=25°C) Symbol Limits Supply voltage Parameter VCC 2.7~5.5 Unit V Input voltage VIN 0~VCC V BR24C32 / BR24C32F / BR24C64 / BR24C64F Memory ICs zBlock diagram BR24C32 / F A0 1 A1 2 A2 3 GND 4 A0 1 32kbits EEPROM ARRAY 8 VCC 7 WP 6 SCL 5 SDA 8 VCC 7 WP 6 SCL 5 SDA 8bits 12bits ADDRESS SLAVE·WORD 12bits DECODER ADDRESS REGISTER START DATA REGISTER STOP CONTROL LOGIC ACK HIGH VOLTAGE GEN. Vcc LEVEL DETECT BR24C64 / F 64kbits EEPROM ARRAY 8bits 13bits A1 2 A2 3 ADDRESS SLAVE·WORD 13bits DECODER ADDRESS REGISTER START DATA REGISTER STOP CONTROL LOGIC ACK GND 4 HIGH VOLTAGE GEN. Vcc LEVEL DETECT zPin descriptions Pin name I/O VCC − Power supply Function GND − Ground (0V) A0, A1, A2 I Slave address set SCL I Serial clock input SDA I/O WP I Slave and word address, serial data input, serial data output Write protect input ∗An open drainn output requires a pull-up resistor. ∗ BR24C32 / BR24C32F / BR24C64 / BR24C64F Memory ICs zElectrical characteristics DC characteristics (Unless otherwise noted, Ta=−40∼85°C, VCC=2.7∼5.5V) Parameter Symbol Min. Typ. Max. Unit Conditions VIH 0.7VCC − − V − "LOW" Input voltage VIL − − 0.3VCC V "LOW" Output voltage VOL − − 0.4 V IOL=3.0mA(SDA) Input leakage current ILI −1.0 − 1.0 µA VIN=0V~VCC Output leakage current ILO −1.0 − 1.0 µA VOUT=0V~VCC Operating current ICC − − 3.0 mA VCC=5.5V, fSCL=400kHz Standby current ISB − − 3.0 µA VCC=5.5V, SDA SCL=VCC A0, A1, A2=GND, WP=GND "HIGH" Input voltage − This product is not designed for protection against radioactive rays. Operating timing characteristics (Unless otherwise noted, Ta=−40∼85°C, VCC=2.7∼5.5V) Vcc=5V±10% Parameter Symbol Vcc=3V±10% Min. Typ. Max. Min. Typ. Max. Unit Clock frequency fSCL − − 400 − − 100 kHz Data clock "HIGH" period tHIGH 0.6 − − 4.0 − − µs Data clock "LOW" period tLOW 1.2 − − 4.7 − − µs SDA and SCL rise time tR − − 0.3 − − 1.0 µs SDA and SCL fall time tF − − 0.3 − − 0.3 µs tHD : STA 0.6 − − 4.0 − − µs Start condition setup time tSU : STA 0.6 − − 4.7 − − µs Input data hold time tHD : DAT 0 − − 0 − − ns Input data setup time tSU : DAT 100 − − 250 − − ns Output data delay time tPD 0.1 − 0.9 0.2 − 3.5 µs Output data hold time tDH 0.1 − − 0.2 − − µs µs Start condition hold time tSU : STO 0.6 − − 4.7 − − Bus free time tBUF 1.2 − − 4.7 − − µs Write cycle time tWR − − 10 − − 10 ms tI − − 0.05 − − 0.1 µs Stop condition setup time Noise spike width (SDA and SCL) BR24C32 / BR24C32F / BR24C64 / BR24C64F Memory ICs zTiming charts tR tF tHIGH SCL tHD : STA tSU : DAT tLOW tHD : DAT SDA (IN) tBUF tPD tDH SDA (OUT) SCL tSU : STA tHD : STA tSU : STO SDA START bit STOP bit Data is read on the rising edge of SCL. Data is output in synchronization with the falling edge of SCL. Fig.1 Synchronized data input / output timing SCL SDA D0 ACK Write data (n) tWR Stop condition Start condition Fig.2 Write cycle timing zCircuit operation (1) Start condition (recognition of start bit) Before executing any command, when SCL is HIGH, a start condition (start bit) is required to cause SDA to fall from HIGH and LOW. This IC is designed to constantly detect whether there is a start condition (start bit) for the SDA and SCL line, and no commands will be executed unless this condition is satisfied. (See Fig.1 for the synchronized data input / output timing.) (2) Stop condition (recognition of stop bit) To stop any command, a stop condition (stop bit) is required. A stop condition is achieved when SDA goes from LOW to HIGH while SCL is HIGH. This enables commands to be completed. (See Fig.1 for the synchronized data input / output timing.) BR24C32 / BR24C32F / BR24C64 / BR24C64F Memory ICs (3) Precautions concerning write commands In the WRITE mode, the transferred data is not written to the memory unless the stop bit is executed. (4) Device addressing 1) Make sure the slave address is output from the master immediately after the start condition. 2) The upper 4 bits of the slave address are used to determine the device type. The device code for this IC is fixed at “1010”. 3) The next 3 bits of the slave address (A2, A1, A0 … device address) are used to select the device. This IC can address up to eight devices on the same bus. 4) The lowermost bit of the slave address (R / W … READ / WRITE) is used to set the write or read mode as follows. R / W set to 0 … Write (Random read word address setting is also 0) R / W set to 1 … Read 1010 A2 A1 A0 R/W (5) Write protect functions (WP) When WP pin set to Vcc (High level), write protect is set by all address. When WP pin set to GND (Low level), enable to write to all address. Either control this pin or connect to GND (or Vcc). It is inhibited from being left unconnected. (6) ACK signal The acknowledge signal (ACK signal) is determined by software and is used to indicate whether or not a data transfer is proceeding normally. The transmitting device, whether the master or slave, opens the bus after an 8 bits data output (µ-COM when a write or read command of the slave address input; this IC when reading data). For the receiving device during the ninth clock cycle, SDA is set to LOW and an acknowledge signal (ACK signal) is sent to indicate that it received the 8 bits data (this IC when a write command or a read command of the slave address input, µ -COM when a read command data output). The ICs output a LOW acknowledge signal (ACK signal) after recognizing the start condition and slave address (8 bits). When data is being write to the ICs a LOW acknowledge signal (ACK signal ) is output after the receipt of each 8 bits of data (word address and write data). When data is being read from the IC, 8 bits of data (read data) are output and the IC waits for a returned LOW acknowledge signal (ACK signal). When an acknowledge signal (ACK signal) is detected and a stop condition is not sent from the master (µ-COM) side, the IC continues to output data. If an acknowledge signal (ACK signal) is not detected, the IC interrupts the data transfer and ceases reading operations after recognizing the stop condition (stop bit). The IC then enters the waiting or standby state. (See Fig.3 for acknowledge signal (ACK signal) response.) Start condition (Start bit) SCL (From µ−COM) 1 8 9 SDA (µ-COM Output data) SDA (IC output data) Acknowledge signal (ACK signal) Fig.3 Acknowledge (ACK signal) response (during write and read slave address input) BR24C32 / BR24C32F / BR24C64 / BR24C64F Memory ICs (7) Byte write cycle BR24C32 / F S T A R T SDA LINE SLAVE ADDRESS W R I T E 1st WORD ADDRESS ∗ ∗ ∗ ∗ 1 0 1 0 A2 A1 A0 2nd WORD ADDRESS WA 11 R A / C W K S T O P DATA WA 0 A C K D7 D0 A C K A C K WP Fig.4 BR24C64 / F S T A R T SDA LINE SLAVE ADDRESS W R I T E 1st WORD ADDRESS ∗ ∗ ∗ 1 0 1 0 A2 A1 A0 R A / C W K 2nd WORD ADDRESS WA 12 DATA WA 0 A C K S T O P D7 A C K WP Fig.5 $Data is written to the address designed by the word address (n address). $After 8 bits of data are input, the data is written to the memory cell by issuing the stop bit. D0 A C K BR24C32 / BR24C32F / BR24C64 / BR24C64F Memory ICs (8) Page write cycle BR24C32 / F S T A R T SDA LINE SLAVE ADDRESS W R I T E 1st WORD ADDRESS(n) 2nd WORD ADDRESS(n) ∗ ∗ ∗ ∗ WA 11 1 0 1 0 A2 A1 A0 A C K R A / C W K DATA(n+31) DATA(n) WA 0 D7 S T O P D0 D0 A C K A C K A C K WP Fig.6 BR24C64 / F S T A R T SDA LINE SLAVE ADDRESS W R I T E 1st WORD ADDRESS(n) ∗ ∗ ∗ 1 0 1 0 A2 A1 A0 2nd WORD ADDRESS(n) WA 12 A C K R A / C W K DATA(n+31) DATA(n) WA 0 D7 S T O P D0 D0 A C K A C K A C K WP Fig.7 $A 32 bytes write is possible using this command. $The page write command arbitrarily sets the upper 7 bits (WA11 to WA5) of the word address. The lower 5 bits (WA4 and WA0) can write up to 32 bytes of data with the address being incremented internally. (9) Current read cycle S T A R T SDA LINE SLAVE ADDRESS 1 0 1 R E A D S T O P DATA 0 A2 A1 A0 D7 R A / C W K Fig.8 D0 A C K BR24C32 / BR24C32F / BR24C64 / BR24C64F Memory ICs $In case the previous operation is random or current read (which includes sequential read respectively), the internal address counter is increased by one from the last accessed address (n). Thus current read outputs the data of the next word address (n+1). If the last command is byte or page write, the internal address counter stays at the last address (n). Thus current read outputs the data of the word address (n). If the master does not transfer the acknowledge but does generate a stop condition, the current address read operation only provides single byte of data. At this point, this IC discontinues transmission. $When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. (See Fig.8 for the sequential read cycles.) $This command is ended by inputting HIGH to the ACK signal after D0 and raising the SDA signal (stop condition) by setting SCL to HIGH. (10) Random read cycle BR24C32 / F S T A R T SDA LINE SLAVE ADDRESS W R I T E 1st WORD ADDRESS(n) 2nd WORD ADDRESS(n) ∗ ∗ ∗ ∗ WA 11 1 0 1 0 A2 A1 A0 R A / C W K S T A R T WA 0 SLAVE ADDRESS 1 0 1 0 A2 A1A0 S T O P DATA(n) D7 D0 A C K R A / C W K A C K A C K R E A D Fig.9 BR24C64 / F S T A R T SDA LINE SLAVE ADDRESS W R I T E 1st WORD ADDRESS(n) ∗ ∗ ∗ 1 0 1 0 A2 A1 A0 R A / C W K S T A R T 2nd WORD ADDRESS(n) WA 12 WA 0 1 0 1 0 A2 A1A0 A C K A C K SLAVE ADDRESS R E A D DATA(n) D7 R A / C W K S T O P D0 A C K Fig.10 $This command can read the designated word address data. $When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. (See Fig.8 for the sequential lead cycles.) $This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) by raising SCL to HIGH. BR24C32 / BR24C32F / BR24C64 / BR24C64F Memory ICs (11) Sequential read cycle S T A R T SDA LINE SLAVE ADDRESS R E A D DATA(n) 1 0 1 0 A2 A1 A0 D7 DATA(n+x) D0 R A / C W K S T O P D7 A C K D0 A C K A C K Fig.11 $When an ACK signal LOW is detected after D0 and a stop condition is not sent from the master (µ-COM), the next word address data can be read. $This command is ended by inputting a HIGH signal to the ACK signal after D0 and raising the SDA signal (stop condition) by using the SCL and HIGH. $Sequential reading can also be done with a random read. zExternal dimension (Units : mm) BR24C32 BR24C64 BR24C32F BR24C64F 9.3 ± 0.3 5 5.0 ± 0.2 0.11 5 1 4 1.27 0.4 ± 0.1 0.15 ± 0.1 7.62 1.5 ± 0.1 8 4.4 ± 0.2 4 0.51Min. 3.2 ± 0.2 3.4 ± 0.3 1 6.2 ± 0.3 6.5 ± 0.3 8 0.3Min. 0.3 ± 0.1 2.54 0.5 ± 0.1 DIP8 0.15 0° ~ 15° SOP8