Memory ICs BR93LC46-W / BR93LC46F-W / BR93LC46RF-W / BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W 64×16bits serial EEPROM BR93LC46-W / BR93LC46F-W / BR93LC46RF-W / BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W The BR93LC46-W series are CMOS serial input / output-type memory circuits (EEPROMs) that can be programmed electrically. Each is configured of 64 words × 16 bits (1,024 bits), and each word can be accessed individually and data read from it and written to it. Operation control is performed using five types of commands. The commands, addresses, and data are input through the DI pin under the control of the CS and SK pins. In a write operation, the internal status signal (READY or BUSY) can be output from the DO pin. zApplications VCRs, TVs, printers, car stereos, cordless telephones, short wave radios, programmable DIP switches, and other battery-powered equipment requiring low voltage and low current zFeatures 1) 64 words × 16 bits EEPROM 2) Operating voltage range When reading : 2.0 to 5.5V When writing : 2.7 to 5.5V 3) Low current consumption Operating (at 5V) : 3mA (Max.) Standby (at 5V) : 5µA (Max.) 4) Address can be incremented automatically during read operations. 5) Auto erase and auto complete functions can be used during write operations. 6) A write instruction inhibit function allows : - write protection when power supply voltage is low. - write disable state at power up. - writing using command codes. 7) Compact packages 8) Display of READY / BUSY status 9) TTL-compatible input / output 10) Rewriting possible up to 100,000 times 11) Data can be stored for ten years without corruption. zBlock diagram Power supply CS voltage detector Command decode Control Clock generation SK Address Command DI Write High voltage disable generator 6bits Address buffer decoder Data R/W 6bits register 1,024bits 16bits register DO Dummy bits amplifier EEPROM array 16bits BR93LC46-W / BR93LC46F-W / BR93LC46RF-W / BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W Memory ICs zPin descriptions CS 1 SK 2 DI 3 DO 4 BR93LC46-W BR93LC46RF-W BR93LC46RFJ-W 8 VCC N.C. 1 7 N.C. VCC 2 6 N.C. CS 3 5 GND SK 4 Fig.1 BR93LC46F-W BR93LC46FJ-W BR93LC46FV-W 8 N.C. 7 GND 6 DO 5 DI Fig.2 Pin No. BR93LC46-W BR93LC46RF-W BR93LC46RFJ-W BR93LC46F-W BR93LC46FJ-W BR93LC46FV-W Pin name 1 3 CS 2 4 SK Serial clock input 3 5 DI Start bit, operating code, address, and seria data input 4 6 DO Serial data output, READY / BUSY internal status display output 5 7 GND Ground 6 8 N.C. Not connected 7 1 N.C. Not connected 8 2 VCC Power supply Function Chip select input zAbsolute maximum ratings (Ta = 25°C) Parameter Applied voltage Symbol Limits VCC −0.3~+6.5 BR93LC46-W Power dissipation BR93LC46F-W / RF-W / FJ-W / RFJ-W BR93LC46FV-W Pd Unit 500 ∗1 350 ∗2 300 V mW ∗3 Storage temperature Tstg −65~+125 °C Operating temperature Topr −40~+85 °C − −0.3~VCC+0.3 V Terminal voltage ∗1 Reduced by 5.0mW for each increase in Ta of 1°C over 25°C. ∗2 Reduced by 3.5mW for each increase in Ta of 1°C over 25°C. ∗3 Reduced by 3.0mW for each increase in Ta of 1°C over 25°C. zRecommended operating conditions (Ta = 25°C) Parameter Power supply voltage Input voltage Symbol Writing Reading VCC VIN Min. Typ. Max. Unit 2.7 − 5.5 V 2.0 − 5.5 V 0 − VCC V Memory ICs BR93LC46-W / BR93LC46F-W / BR93LC46RF-W / BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W zElectrical characteristics For 5V operation (unless otherwise noted, Ta = −40 to + 85°C, VCC = 5.0V ± 10%) Parameter Symbol Min. Typ. Max. Unit Conditions Measurement circuit Input low level voltage VIL −0.3 − 0.8 V − − Input high level voltage VIH 2.0 − VCC+0.3 V − Output low level voltage 1 VOL1 − − 0.4 V Output high level voltage 1 VOH1 2.4 − − Output low level voltage 2 VOL2 − − 0.2 Output high level voltage 2 VOH2 VCC−0.4 − − Input leakage current ILI −1.0 − Output leakage current ILO −1.0 − − IOL=2.1mA Fig.3 V IOH=−0.4mA Fig.4 V IOL=10µA Fig.3 V IOH=−10µA Fig.4 1.0 µA VIN=0V~VCC Fig.5 1.0 µA VOUT=0V~VCC, CS=GND Fig.6 Operating current dissipation 1 ICC1 − 1.5 3.0 mA Operating current dissipation 2 ICC2 − 0.7 1.5 mA Standby current ISB − 1.0 5.0 µA VIN=VIH / VIL, DO=OPEN, f=1MHz, WRITE VIN=VIH / VIL, DO=OPEN, f=1MHz, READ CS=SK=DI=GND, DO=OPEN Fig.7 Fig.7 Fig.8 For 3V operation (unless otherwise noted, Ta = −40 to + 85°C, VCC = 3.0V ± 10%) Parameter Symbol Min. Typ. Max. Unit Conditions Measurement circuit VIL −0.3 − 0.15×VCC V − − Input high level voltage VIH 0.7×VCC − VCC+0.3 V Output low level voltage VOL − − 0.2 V IOL=10µA Fig.3 Output high level voltage Input low level voltage − − VOH VCC−0.4 − − V IOH=−10µA Fig.4 Input leakage current ILI −1.0 − 1.0 µA VIN=0V~VCC Fig.5 Output leakage current ILO −1.0 − 1.0 µA VOUT=0V~VCC, CS=GND Fig.6 Operating current dissipation 1 ICC1 − 0.5 2.0 mA Operating current dissipation 2 ICC2 − 0.2 1.0 mA Standby current ISB − 0.4 3.0 µA VIN=VIH / VIL, DO=OPEN f=250kHz, WRITE VIN=VIH / VIL, DO=OPEN f=250kHz, READ CS=SK=DI=GND, DO=OPEN Fig.7 Fig.7 Fig.8 For 2V operation (unless otherwise noted, Ta = −40 to + 85°C, VCC = 2.0V) Symbol Min. Typ. Max. Unit Conditions Measurement circuit VIL −0.3 − 0.15×VCC V − − Input high level voltage VIH 0.7×VCC − VCC+0.3 V Output low level voltage VOL − − 0.2 V IOL=10µA Fig.3 Output high level voltage Parameter Input low level voltage − − VOH VCC−0.4 − − V IOH=−10µA Fig.4 Input leakage current ILI −1.0 − 1.0 µA VIN=0V~VCC Fig.5 Output leakage current ILO −1.0 − 1.0 µA VOUT=0V~VCC, CS=GND Fig.6 Operating current dissipation 2 ICC2 − 0.2 1.0 mA Standby current ISB − 0.4 3.0 µA VIN=VIH / VIL, DO=OPEN f=200kHz, READ CS=SK=DI=GND, DO=OPEN Fig.7 Fig.8 BR93LC46-W / BR93LC46F-W / BR93LC46RF-W / BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W Memory ICs zMeasurement circuits VCC VCC VCC VCC IOL IOH DO DO GND V GND VOL V Control output to "LOW" Control output to "HIGH" Fig.3 "LOW" output voltage circuit Fig.4 "HIGH" output voltage circuit VCC VCC VCC VCC ILO ILI CS,SK,DI A CS VIN=0~VCC DO GND VIN=VIH / VIL Vcc ICC A VCC CS VO=0~VCC Fig.6 Output leak current circuit VCC A SK ISB Vcc CS DO OPEN WRITE / READ INPUT SK DI A GND Fig.5 Input leak current circuit fSK=1MHz / 250kHz / 200kHz VOH DO OPEN GND DI GND Fig.7 Supply current circuit Fig.8 Standby current circuit zCircuit operation (1) Command mode With these ICs, commands are not recognized or acted upon until the start bit is received. The start bit is taken as the first “1” that is received after the CS pin rises. Command Start bit Operating Address code Data Read (READ) ∗1 1 10 A5~A0 Write enabled (WEN) 1 00 11XXXX − Write (WRITE) ∗2 1 01 A5~A0 D15~D0 Write all addresses (WRAL) ∗2 1 00 01XXXX D15~D0 Write disabled (WDS) 1 00 00XXXX − Erase (ERASE) ∗3 1 11 A5~A0 − Chip erase (ERAL) ∗3 1 00 10XXXX − − X: Either VIH or VIL ∗1 After setting of the read command and input of the SK clock, data corresponding to the specified address is output, with data corresponding to upper addresses then output in se-quence. (Auto increment function) ∗2 When the write or write all addresses command is executed, all data in the selected memory cell is erased autematically, and the input data is writen to the cell. ∗3 These modes are optinal modes. Please contact Rohm for information on operation timing. Memory ICs BR93LC46-W / BR93LC46F-W / BR93LC46RF-W / BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W (2) Operation timing characteristics For 5V operation (unless otherwise noted, Ta = −40 to + 85°C, VCC = 5.0V ± 10%) Symbol Min. Typ. Max. Unit SK clock frequency fSK − − 1 MHz SK "HIGH" time tSKH 450 − − ns SK "LOW" time tSKL 450 − − ns CS "LOW" time tCS 450 − − ns CS setup time tCSS 50 − − ns DI setup time tDIS 100 − − ns CS hold time tCSH 0 − − ns DI hold time tDIH 100 − − ns Data "1" output delay time tPD1 − − 500 ns Data "0" output delay time tPD0 − − 500 ns Time from CS to output confirmation tSV − − 500 ns Time from CS to output High impedance tDF − − 100 ns tE / W − − 10 ms Parameter Write cycle time For low voltage operation (unless otherwise noted, Ta = −40 to + 85°C, VCC = 3.0V ± 10%) Symbol Min. Typ. Max. Unit SK clock frequency Parameter fSK − − 250 kHz SK "HIGH" time tSKH 1 − − µs SK "LOW" time tSKL 1 − − µs CS "LOW" time tCS 1 − − µs CS setup time tCSS 200 − − ns DI setup time tDIS 400 − − ns CS hold time tCSH 0 − − ns DI hold time tDIH 400 − − ns Data "1" output delay time tPD1 − − 2 µs Data "0" output delay time tPD0 − − 2 µs Time from CS to output confirmation tSV − − 2 µs Time from CS to output High impedance tDF − − 400 ns tE / W − − 25 ms Write cycle time When reading at low voltage (unless otherwise noted, Ta = −40 to + 85°C, VCC = 2.0V) Symbol Min. Typ. Max. Unit SK clock frequency Parameter fSK − − 200 kHz SK "HIGH" time tSKH 2 − − µs SK "LOW" time tSKL 2 − − µs CS "LOW" time tCS 2 − − µs CS setup time tCSS 400 − − ns DI setup time tDIS 800 − − ns CS hold time tCSH 0 − − ns DI hold time tDIH 800 − − ns Data "1" output delay time tPD1 − − 4 µs Data "0" output delay time tPD0 − − 4 µs Time from CS to output High impedance tDF − − 800 ns Not designed for radiative rays. BR93LC46-W / BR93LC46F-W / BR93LC46RF-W / BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W Memory ICs (3) Timing chart CS tCSS tSKH tDIS tDIH tCSH tSKL SK DI tPD0 tPD1 tDF DO (READ) tDF STATUS VALID DO (WRITE) · Data is acquired from DI in synchronization with the SK rise. · During a reading operation, data is output from DO in synchronization with the SK rise. · During a writing operation, a Status Valid (READY or BUSY) is valid from the time CS is HIGH until time tCS after CS falls following the input of a write command and before the output of the next command start bit. Also, DO must be in a HIGH-Z state when CS is LOW. · After the completion of each mode, make sure that CS is set to LOW, to reset the internal circuit, before changing modes. Fig.9 Synchronized data timing (4) Reading (Fig.10) When the read command is acknowledged, the data (16 bits) for the input address is output serially. The data is synchronized with the SK rise during A0 acquisition and a “0” (dummy bit) is output. All further data is output in synchronization with the SK pulse rises. CS (∗1) SK DI 1 2 1 1 4 0 A5 9 A4 A1 10 25 26 A0 (∗2) 0 DO D15 D14 D1 D0 D15 D14 High Z (∗1) If the first data input following the rise of the start bit CS is "1", the start bit is acknowledged. Also, if a "1" is input following several zeroes in succession, the "1" is recognized as the start bit, and subsequent operation commences. This applies also to all commands described subsequently. (∗2) Address auto increment function: These ICs are equipped with an address auto increment function which is effective only during reading operations. With this function, if the SK clock is input following execution of one of the above reading commands, data is read from upper addresses in succession. CS is held in HIGH state during automatic incrementing. Fig.10 Read cycle timing (READ) BR93LC46-W / BR93LC46F-W / BR93LC46RF-W / BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W Memory ICs (5) Write enable (Fig.11) These ICs are set to the write disabled state by the internal reset circuit when the power is turned on. Therefore, before performing a write command, the write enable command must be executed. When this command is executed, it remains valid until a write disable command is issued or the power supply is cut off. However, read commands can be used in either the write enable or write disable state. CS SK DI 1 0 0 1 1 DO High Z Fig.11 Write enable cycle timing (6) Write (Fig.12) This command writes the input 16 bits data (D15 to D0) to the specified address (A5 to A0). Actual writing of the data begins after CS falls (following the 25th clock pulse after the start bit input), and D0 is in the Acquire state. STATUS is not detected if CS = LOW after the time tE / W. When STATUS is detected (CS = HIGH), no commands are accepted while DO is LOW (BUSY). Therefore, no commands should be input during this period. CS SK tCS 1 2 4 9 10 A0 D15 STATUS 25 DI 1 0 1 A5 A4 A1 D14 D1 D0 tSV DO BUSY READY High Z tE / W Fig.12 Write cycle timing (WRITE) (STATUS) After time tCS following the fall of CS, after input of the write command), if CS is set to HIGH, the write execute = BUSY (LOW) and the command wait status READY (HIGH) are output. If in the command wait status (STATUS = READY), the next command can be performed within the time tE / W. Thus, if data is input via SK and DI with CS = HIGH in the tE / W period, erroneous operations may be performed. To avoid this, make sure that DI = LOW when CS = HIGH. (Caution is especially important when common input ports are used.) This applies to all of the write commands. BR93LC46-W / BR93LC46F-W / BR93LC46RF-W / BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W Memory ICs (7) All address write (Fig.13) With this command, the input 16 bits data is written simultaneously to all of the addresses (64 words). Rather than writing one word at a time, in succession, data is written all at one time, enabling a write time of tE / W. tSV CS STATUS 1 SK 2 5 10 1 D15 25 DI 1 0 0 0 D14 D1 D0 tCS DO BUSY READY High Z tE / W Fig.13 Write all address cycle timing. (WRAL) (8) Write disable (Fig.14) When the power supply is turned on, the IC enters the write disable status. Similarly, when the write disable command is issued, the IC enters the same status. When in this status, all write commands are ignored, but read commands may be executed. In the write enable status, writing begins even if a write command is entered accidentally. To prevent errors of this type, we recommend executing a write disable command after writing has been completed. CS SK DI 1 0 0 0 0 DO High Z Fig.14 Write disable cycle timing (WDS) zOperation notes (1) Cancelling modes 〈READ〉 Start bit 1 bit Operating code 2 bits Address Data 6 bits 16 bits Cancel can be performed for the entire read mode space Cancellation method: CS LOW 〈WRITE, WRAL〉 Start bit 1 bit Operating code 2 bits Address Data 6 bits 16 bits a ∗ a: Canceled by setting CS LOW or VCC OFF ( ) b: Cannot be canceled by any method. If VCC is set to OFF during this time, the data in the designated address is not secured. VCC OFF (VCC is turned off after CS is set to LOW) ∗ Fig.15 tE / W b BR93LC46-W / BR93LC46F-W / BR93LC46RF-W / BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W Memory ICs (2) Timing in the standby mode As shown in Fig.16, during standby, if CS rises when SK is HIGH, the DI state may be read on the rising edge. If this happens, and DI is HIGH, this is taken to be the start bit, causing a bit error (see point “a” in Fig.16). Make sure all inputs are LOW during standby or when turning the power supply on or off (see Fig.17). Point a: Start bit position during erroneous operation Point b: Timing during normal operation SK SK CS CS 0 DI 1 0 DI a b 1 b Fig. 17 Normal operation timing Fig. 16 Erroneous operation timing (3) Precautions when turning power on and off When turning the power supply on and off, make sure CS is set to LOW (see Fig.18). When CS is HIGH, the EEPROM enters the active state. To avoid this, make sure CS is set to LOW (disable mode) when turning on the power supply. (When CS is LOW, all input is cancelled.) When the power supply is turned off, the low power state can continue for a long time because of the capacity of the power supply line. Erroneous operations and erroneous writing can occur at such times for the same reasons as described above. To avoid this, make sure CS is set to LOW before turning off the power supply. To prevent erroneous writing, these ICs are equipped with a POR (Power On Reset) circuit, but in order to achieve operation at a low power supply, VCC is set to operate at approximately 1.3V. After the POR has been activated, writing is disabled, but if CS is set to HIGH, writing may be enabled because of noise or other factors. However, the POR circuit is effective only when the power supply is on, and will not operate when the power is off. Also, to prevent erroneous writing at low voltages, these ICs are equipped with a built-in circuit (VCC-lockout circuit) which resets the write command if VCC drops to approximately 2V or lower (typ.) (∗). + 5V VCC GND + 5V CS GND Bad example (Bad example) (Good example) Good example Here, the CS pin is pulled up to VCC. In this case, CS is HIGH (active state). Please be aware that the EEPROM may perform erroneous operations or write erroneous data because of noise or other factors. Please be aware that this can occur even if the CS input is HIGH-Z. In this case, CS is LOW when the power supply is turned on or off. Fig. 18 (4) Clock (SK) rise conditions If the clock pin (SK) signal of the BR93LC46-W has a long rise time (tr) and if noise on the signal line exceeds a certain level, erroneous operation can occur due to erroneous counts in the clock. To prevent this, a Schmitt trigger is built into the SK input of the BR93LC46-W. The hysteresis amplitude of this circuit is set to approximately 0.2V, so if the noise exceeds the SK input, the noise amplitude should be set to 0.2VP-P or lower. Furthermore, rises and falls in the clock input should be accelerated as much as possible. Memory ICs BR93LC46-W / BR93LC46F-W / BR93LC46RF-W / BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W (5) Power supply noise The BR93LC46-W discharge high volumes of high voltage when a write is completed. The power supply may fluctuate at such times. Therefore, make sure a capacitor of 1000pF or greater is connected between VCC (Pin 8) and GND (Pin 5). (6) Connecting DI and DO directly The BR93LC46-W have an independent input pin (DI) and output pin (DO). These are treated as individual signals on the timing chart but can be controlled through one control line. Control can be initiated on a single control line by inserting a resistor R. BR93LC46 µCOM IO port DI R DO Fig. 19 Common connections for the DI and DO control line 1) Data collision between the µ-COM output and the DO output Within the input and output timing of the BR93LC46-W the drive from the µ-COM output to the DI input and a signal output from the DO output can be emitted at the same time. This happens only for the 1 clock cycle (a dummy bit “0” is output to the DO pin) which acquires the A0 address data during a read cycle. When the address data A0 = 1, the µ-COM output becomes a direct current source for the DO pin. The resistor R is the only resistance which limits this current. Therefore, a resistor with a value which satisfies the µ-COM and the BR93LC46-W current capacity is required. When using a single control line, when a dummy bit “0” is output to the DO, the µ-COM I / O address data A0 is also output. Therefore, the dummy bit cannot be detected. 2) Feedback to the DI input from the DO output Data is output from the DO pin and then feeds back into the DI input through the resistor R. This happens when: DO data is output during a read operation A READY / BUSY signal is output during WRITE or WRAL operation Such feedback does not cause problems in the basic operation of the BR93LC46-W. The µ-COM input level must be adequately maintained for the voltage drop at R which is caused by the total input leakage current for the µ-COM and the BR93LC46-W. In the state in which SK is input, when the READY / BUSY function is used, make sure that CS is dropped to LOW within four clock pulses of the output of the READY signal HIGH and the standby mode is restored. For input after the fifth clock pulse, the READY HIGH will be taken as the start bit and WDS or some other mode will be activated, depending on the DI state. • • BR93LC46-W / BR93LC46F-W / BR93LC46RF-W / BR93LC46FJ-W / BR93LC46RFJ-W / BR93LC46FV-W Memory ICs zExternal dimensions (Units : mm) BR93LC46-W BR93LC46F-W / RF-W 9.3 ± 0.3 5 5.0 ± 0.2 0.11 1.5 ± 0.1 0.51Min. 7.62 1 4 1.27 0.4 ± 0.1 2.54 0.5 ± 0.1 0.15 0°~15° DIP8 SOP8 BR93LC46FJ-W / RFJ-W BR93LC46FV-W 4.9 ± 0.2 3.0 ± 0.2 0.42 ± 0.1 5 1 4 0.22 ± 0.1 (0.52) 0.15 ± 0.1 0.1 1.15 ± 0.1 6.4 ± 0.3 0.2 ± 0.1 0.45Min. 1.27 8 4.4 ± 0.2 3.9 ± 0.2 1 2 3 4 0.175 6.0 ± 0.3 8 7 6 5 1.375 ±0.1 0.3Min. 0.3 ± 0.1 3.2± 0.2 3.4 ± 0.3 5 0.15 ± 0.1 4 8 4.4 ± 0.2 1 6.2 ± 0.3 6.5 ± 0.3 8 0.3Min. 0.65 0.1 0.1 SOP-J8 SSOP-B8