CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 D D D D D D D D D D Generates Clocks for Pentium III Class Microprocessors Supports a Single Pentium III Microprocessor Uses a 14.318 MHz Crystal Input to Generate Multiple Output Frequencies Includes Spread Spectrum Clocking (SSC), 0.34% Downspread for Reduced EMI Performance Power Management Control Terminals Low Output Skew and Jitter for Clock Distribution Operates from Dual 2.5-V and 3.3-V Supplies Generates the Following Clocks: – 3 CPU (2.5 V, 100/133 MHz) – 10 PCI (3.3 V, 33.3 MHz) – 1 CPU/2 (2.5 V, 50/66 MHz) – 1 APIC (2.5 V, 16.67 MHz) – 3 3V66 (3.3 V, 66 MHz) – 2 REF (3.3 V, 14.318 MHz) – 1 48MHz (3.3 V, 48 MHz) Packaged in 48-Pin SSOP Package Designed for Use with TI’s Direct Rambus Clock Generators (CDCR81, CDCR82, CDCR83) DL PACKAGE (TOP VIEW) REF0 REF1 VDD3.3V XIN XOUT GND PCI0 PCI1 VDD3.3V PCI2 PCI3 PCI4 PCI5 GND PCI6 PCI7 VDD3.3V PCI8 PCI9 GND 3V66(0) 3V66(1) 3V66(2) VDD3.3V 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 GND VDD2.5V APIC GND VDD2.5V CPU_DIV2 GND VDD2.5V CPU2 GND VDD2.5V CPU1 CPU0 GND VDD3.3V GND PWR_DWN SPREAD SEL1 SEL0 VDD3.3V 48MHz GND SEL133/100 description The CDC922 is a clock synthesizer/driver that generates CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF system clock signals to support computer systems with a single Pentium III class microprocessor. All output frequencies are generated from a 14.318-MHz crystal input. Instead of a crystal, a reference clock input can be provided at the XIN input. Two phase-locked loops (PLLs) are used to generate the host frequencies and the 48-MHz clock frequency. On-chip loop filters and internal feedback eliminate the need for external components. The host and PCI clock outputs provide low-skew and low-jitter clock signals for reliable clock operation. All outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100. The 48MHz clock can be independently disabled via the control inputs SEL0, SEL1, and SEL133/100. In this state, the 48-MHz PLL is disabled and the 48MHz clock is driven to high impedance to reduce component jitter. The outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely with the outputs in a low-level output state. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Intel and Pentium III are trademarks of Intel Corporation. Direct Rambus and Rambus are trademarks of Rambus Inc. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 1 CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 description (continued) The CPU bus can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding setting for SEL133/100 control input. The PCI bus frequency is fixed to 33 MHz. Since the CDC922 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required after power up or after changes to the SEL inputs are made. With use of an external reference clock, this signal must be fixed-frequency and fixed-phase before the stabilization time starts. Function Tables SELECT FUNCTIONS INPUTS OUTPUTS FUNCTION SEL133/ 100 SEL1 SEL0 CPU CPU_DIV2 3V66 PCI 48MHz REF APIC L L L Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z L L H N/A N/A N/A N/A N/A N/A N/A Reserved L H L 100 MHz 50 MHz 66 MHz 33 MHz Hi-Z 14.318 MHz 16.67 MHz 48-MHz PLL off L H H 100 MHz 50 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 48-MHz PLL on H L L TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK TCLK/16 Test H L H N/A N/A N/A N/A N/A N/A N/A Reserved H H L 133 MHz 66 MHz 66 MHz 33 MHz Hi-Z 14.318 MHz 16.67 MHz 48-MHz PLL off H H H 133 MHz 66 MHz 66 MHz 33 MHz 48 MHz 14.318 MHz 16.67 MHz 48-MHz PLL on 3-state ENABLE FUNCTIONS OUTPUTS INPUTS INTERNAL PWR_DWN CPU CPU_DIV2 APIC 3V66 PCI REF, 48MHz L L L L L L L Off Off H On On On On On On On On CRYSTAL VCOs OUTPUT BUFFER SPECIFICATIONS BUFFER NAME VDD RANGE (V) IMPEDANCE (Ω) BUFFER TYPE CPU, CPU_DIV2, APIC 2.375 – 2.625 13.5 – 45 TYPE 1 48MHz, REF 3.135 – 3.465 20 – 60 TYPE 3 PCI, 3V66 3.135 – 3.465 12 – 55 TYPE 5 2 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 Terminal Functions TERMINAL NAME 3V66 [0–2] NO. I/O DESCRIPTION 21–23 O 3.3 V, Type 5, 66-MHz clock outputs 48MHz 27 O 3.3 V, Type 3, 48-MHz clock output APIC 46 O 2.5 V, Type 2, APIC clock output at 16.67 MHz 36, 37, 40 O 2.5 V, Type 1, CPU clock outputs 43 O 2.5 V, Type 1, CPU_DIV2 clock output CPU [0–2] CPU_DIV2 GND 6, 14, 20, 26, 33, 35, 39, 42, 45, 48 PCI [0–9] 7, 8, 10–13, 15, 16, 18, 19 Ground for PCI, 3V66, 48MHz, CPU, CPU_DIV2, APIC, REF [0–1] outputs and CORE O 3.3 V, Type 5, 33-MHz PCI clock outputs PWR_DWN 32 I Power down for complete device with outputs forced low REF0, REF1 1, 2 O 3.3 V, Type 3, 14.318-MHz reference clock outputs SEL0, SEL1 29, 30 I LVTTL level logic select terminals for function selection SEL133/100 25 I LVTTL level logic select terminal for enabling 100/133 MHz SPREAD 31 I Disables SSC function VDD2.5V VDD3.3V 38, 41, 44, 47 Power for CPU, CPU_DIV2, and APIC outputs 3, 9, 17, 24, 28, 34 Power for the REF, PCI, 3V66, 48MHz outputs and CORE XIN 4 I Crystal input – 14.318 MHz XOUT 5 O Crystal output – 14.318 MHz POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 3 CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 spread spectrum clock (SSC) implementation for CDC922 Simultaneously switching at fixed frequency generates a significant power peak at the selected frequency, which in turn will cause EMI disturbance to the environment. The purpose of the internal frequency modulation of the CPU–PLL allows to distribute the energy to many different frequencies which reduces the power peak. A typical characteristic for a single frequency spectrum and a frequency modulated spectrum is shown in Figure 1. Highest Peak ∆ Non-SSC SSC δ of fnom fnom Figure 1. Frequency Power Spectrum With and Without the Use of SSC The modulated spectrum has its distribution left hand to the single frequency spectrum which indicates a “down-spread modulation”. The peak reduction depends on the modulation scheme and modulation profile. System performance and timing requirements are the limiting factors for actual design implementations. The implementation was driven to keep the average clock frequency closed to its upper specification limit. The modulation amount was set to approximately –0.34% (compared to – 0.5% on the CDC921). Period of Output Frequency – ns In order to allow a downstream PLL to follow the frequency modulated signal, the bandwidth of the modulation signal is limited in order to minimize SSC induced tracking skew jitter. The ideal modulation profile used for CDC922 is shown in Figure 2. 10.03 10.02 10.01 10 9.99 9.98 9.97 5 10 15 20 25 30 35 Period of Modulation Signal – µs Figure 2. SSC Modulation Profile 4 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 40 45 CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 functional block diagram SEL133/100 25 SEL0 29 SEL1 3-State Control Logic 48-MHz Inactive Test SEL 133/100 30 2*REF 14.318 MHz (1,2) XIN XOUT 4 5 1*48MHz 48 MHz (27) 48 MHz PLL Xtal Oscillator SPREAD 31 Spread Logic CPU PLL /2 /2 /3 /4 /2 /3 /4 PWR_DWN Sync Logic & Power Down Logic 3*CPU 100/133 MHz (36,37,40) 1*CPU_DIV2 50/66 MHz (43) 10*PCI 33 MHz (7,8,10,11,12, 13,15,16,18,19) 1*APIC 16.67 MHz (46) 3*AGP (3V66) 66 MHz (21,22,23) 32 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 5 CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V Voltage range applied to any output in the high-impedance state or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VDD + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 × IOL Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATNG DERATING FACTOR† ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING DL 1315.7 mW 10.53 mW/°C 842.1 mW 684.2 mW † This is the inverse of the traditional junction-to-case thermal resistance (RθJA) and uses a board-mounted device at 95°C/W. recommended operating conditions (see Note 2) MIN Supply voltage voltage, VDD NOM† 3.465 2.5 V 2.375 2.625 2 VDD + 0.3 V V GND – 0.3 V 0.8 V VDD –12 V Low-level input voltage, VIL Input voltage, VI 0 CPUx, CPU_DIV2 Low level output current Low-level current, IOL APIC –12 48MHz, REFx –14 PCIx, PCI_F, 3V66x –18 CPUx, CPU_DIV2 12 APIC 12 48MHz, REFx 9 PCIx, PCI_F, 3V66x Reference frequency, f(XTAL)‡ Crystal frequency, f(XTAL)§ UNIT 3.135 High-level input voltage, VIH High level output current, High-level current IOH MAX 3.3 V Normal mode mA mA 12 Test mode Operating free-air temperature, TA V 130 13.8 0 14.318 MHz 14.8 85 MHz °C NOTE 2: Unused inputs must be held high or low to prevent them from floating. † All nominal values are measured at their respective nominal VDD values. ‡ Reference frequency is a test clock driven on the XIN input during the device test mode and normal mode. In test mode, XIN can be driven externally up to f(XTAL) = 130 MHz. If XIN is driven externally, XOUT is floating. § This is a series fundamental crystal with fO = 14.31818 MHz. 6 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK RI IIH TEST CONDITIONS Input clamp voltage Input resistance High-level g input current XIN, XOUT VDD = 3.135 V, VDD = 3.465 V, II = –18 mA VI = VDD –0.5 V XOUT VDD = 3.135 V, VI = VDD –0.5 V SEL0, SEL1, SPREAD VDD = 3.465 V, Low-level input current kΩ VI = VDD <10 10 µA VI = VDD VI = VDD <10 10 µA SEL133/100 VDD = 3.465 V, VDD = 3.465 V, <10 10 µA XOUT VDD = 3.135 V, VI = 0 V –2 –5 mA SEL0, SEL1, SPREAD VDD = 3.465 V, VI = GND <10 –10 µA VDD = 3.465 V, VDD = 3.465 V, VI = GND VI = GND <10 –10 µA <10 –10 µA |VDD| = max, VO = VDD or GND All outputs = low, ±10 µA <20 100 µA <20 100 µA <50 200 µA 37 mA VDD = 2.625 V, PWR_DWN = low IDD(Z) Supply current High-impedance-state g supply y current Dynamic IDD CI V mA SEL133/100 IDD UNIT –1.2 50 High-impedance-state output current Input capacitance Crystal terminal capacitance VDD = 2.625 V, VDD = 3.465 V, PWR_DWN = low All outputs = high VDD = 3.465 V, VDD = 2.625 V All outputs = high 80 MAX 350 PWR_DWN IOZ TYP† 20 PWR_DWN IIL MIN All outputs = low, 12 1.4 VDD = 3.465 V 30 CL = 20 pF, CPU = 133 MHz VDD = 3.465 V VDD = 2.625 V VDD = 3.3 V, VDD = 3.3 V, VI = VDD or GND VI = 0.3 V 114 156 44 60 5.8 pF 18.5 22.5 pF 3.3 18 mA mA † All typical values are measured at their respective nominal VDD values. POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 7 CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) CPUx, CPU_DIV2, APIC (Type 1) PARAMETER VOH g g High-level output voltage VOL Low level output voltage Low-level IOH High-level output current IOL Low-level output current CO Output capacitance ZO TEST CONDITIONS Output impedance High state VDD = min to max, IOH = – 1 mA VDD = 2.375 V, VDD = min to max, IOH = –12 mA IOL = 1 mA VDD = 2.375 V, VDD = 2.375 V, IOL = 12 mA VO = 1 V VDD = 2.5 V, VDD = 2.625 V, VO = 1.25 V VO = 2.375 V VDD = 2.375 V, VDD = 2.5 V, VDD = 2.625 V, VO = 1.2 V VO = 1.25 V VDD = 3.3 V, VO = 0.5 VDD, Low state VO = 0.5 VDD, † All typical values are measured at their respective nominal VDD values. VO = 0.3 V VO = VDD or GND VO/IOH VO/IOL MIN TYP† MAX VDD – 0.1 V UNIT V 2 0.1 0.18 –26 0.4 –42 mA –46 –16 27 V –27 57 mA 63 23 5.8 43 8.5 13.5 27 45 13.5 20 45 MIN TYP† MAX pF Ω 48MHz, REFx (Type 3) PARAMETER VOH VOL IOH IOL CO ZO TEST CONDITIONS High-level g output voltage g Low level output voltage Low-level High-level output current Low-level output current Output capacitance Output impedance High state VDD = min to max, IOH = – 1 mA VDD = 3.135 V, VDD = min to max, IOH = –14 mA IOL = 1 mA VDD = 3.135 V, VDD = 3.135 V, IOL = 9 mA VO = 1 V VDD = 3.3 V, VDD = 3.465 V, VO = 1.65 V VO = 3.135 V VDD = 3.135 V, VDD = 3.3 V, VDD = 3.465 V, VO = 1.95 V VO = 1.65 V VDD = 3.3 V, VO = 0.5 VDD, Low state VO = 0.5 VDD, † All typical values are measured at their respective nominal VDD values. 8 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 VO = 0.4 V VO = VDD or GND VO/IOH VO/IOL • DALLAS, TEXAS 75265 VDD – 0.1 V UNIT V 2.4 0.1 0.18 –27 0.4 –41 mA –41 –12 29 V –23 50 mA 53 20 37 20 40 60 20 31 60 4.5 7 pF Ω CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) PCIx, 3V66x (Type 5) PARAMETER VOH g g High-level output voltage VOL Low level output voltage Low-level IOH High-level output current IOL Low-level output current CO Output capacitance ZO TEST CONDITIONS Output impedance High state MIN VDD = min to max, IOH = – 1 mA VDD = 3.135 V, VDD = min to max, IOH = –18 mA IOL = 1 mA VDD = 3.135 V, VDD = 3.135 V, IOL = 12 mA VO = 1 V VDD = 3.3 V, VDD = 3.465 V, VO = 1.65 V VO = 3.135 V VDD = 3.135 V, VDD = 3.3 V, VDD = 3.465 V, VO = 1.95 V VO = 1.65 V VDD = 3.3 V, VO = 0.5 VDD, Low state VO = 0.5 VDD, † All typical values are measured at their respective nominal VDD values. TYP† MAX VDD – 0.1 V UNIT V 2.4 0.1 0.15 –33 0.4 –53 mA –53 –16 30 –33 67 mA 70 VO = 0.4 V VO = VDD or GND VO/IOH VO/IOL V 27 49 4.5 7.5 12 31 55 12 24 55 pF Ω switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C PARAMETER TEST CONDITIONS Overshoot/undershoot tdis3 Disable time, PWR_DWN to PCIx Stabilization time, PWR_DWN to CPUx tdis4 Disable time, PWR_DWN to CPUx Stabilization time† TYP GND – 0.7 V Ring back Stabilization time, PWR_DWN to PCIx MIN VIL – 0.1 V f(CPU) = 133 MHz f(CPU) = 133 MHz 0.05 f(CPU) = 133 MHz f(CPU) = 133 MHz 0.03 MAX UNIT VDD + 0.7 V VIH + 0.1 V V 3 ms 3 ms 50 V ns 50 ns After SEL1, SEL0 3 After power up 3 ms † Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics tables are not applicable. Stabilization time is defined as the time from when VDD achieves its nominal operating level until the output frequency is stable and operating within specification. POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 9 CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 switching characteristics, VDD = 2.375 V to 2.625 V, TA = 0°C to 85°C (continued) CPUx FROM (INPUT) PARAMETER ten1 tdis1 tc TO (OUTPUT) Output enable time SEL133/100 CPUx Output disable time SEL133/100 CPUx TEST CONDITIONS Cycle to cycle jitter f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz Duty cycle TYP MAX 6 10 ns 8 10 ns 10 10.04 10.2 ns 7.5 7.53 f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz f(CPU) = 100 MHz f(CPU) = 133 MHz CPU clock period† MIN 45 f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz 7.7 ns 250 ps 55 % 175 ps 2.2 ns tsk(o) tsk(p) CPU bus skew CPUx CPUx CPU pulse skew CPUn CPUn t(off) t(off) CPU clock to APIC clock offset, rising edge 1.5 2.8 4 ns CPU clock to 3V66 clock offset, rising edge 0 0.75 1.5 ns 2.6 4.3 1.4 3.7 2.8 4.3 1.7 4 0.4 1.5 2.2 ns 0.4 1.4 2 ns MIN TYP MAX 6 10 ns 8 10 ns 20 20.08 20.4 ns 15 15.06 15.3 ns 250 ps tw1 1 Pulse duration width, width high f(CPU) = 100 MHz f(CPU) = 133 MHz tw2 2 Pulse duration width width, low f(CPU) = 100 MHz f(CPU) = 133 MHz tr Rise time VO = 0.4 V to 2.0 V tf Fall time VO = 0.4 V to 2.0 V † The average over any 1-µs period of time is greater than the minimum specified period. 50 UNIT ns ns CPU_DIV2 FROM (INPUT) TO (OUTPUT) Output enable time SEL133/100 CPU_DIV2 Output disable time SEL133/100 CPU_DIV2 PARAMETER ten1 tdis1 tc CPU DIV2 clock period† CPU_DIV2 Cycle to cycle jitter Duty cycle tsk(p) CPU_DIV2 pulse skew tw1 1 Pulse duration width, width high tw2 2 Pulse duration width width, low TEST CONDITIONS f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz f(CPU) = 100 MHz f(CPU) = 133 MHz f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz f(CPU) = 100 or 133MHz f(CPU) = 100 MHz f(CPU) = 133 MHz f(CPU) = 100 MHz f(CPU) = 133 MHz VO = 0.4 V to 2.0 V tr Rise time tf Fall time VO = 0.4 V to 2.0 V † The average over any 1-µs period of time is greater than the minimum specified period. 10 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 45 UNIT 55 % 1.6 ns 7.1 ns 4.7 7.3 8.9 5 6.6 0.4 1.4 2 ns 0.4 1.3 1.8 ns ns CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 switching characteristics, VDD = 2.375 V to 2.625 V, TA = 0°C to 85°C (continued) APIC PARAMETER ten1 tdis1 tc FROM (INPUT) TO (OUTPUT) Output enable time SEL133/100 APIC Output disable time APIC clock period† SEL133/100 APIC Duty cycle APIC pulse skew t(off) APIC clock to CPU clock offset, rising edge tw1 tw2 APIC MIN f(APIC) = 16.67 MHz f(APIC) = 16.67 MHz Cycle to cycle jitter tsk(p) TEST CONDITIONS f(APIC) = 16.67 MHz f(CPU) = 100 or 133 MHz 60 f(APIC) = 16.67 MHz f(APIC) = 16.67 MHz 45 CPUx Pulse duration width, high MAX 6 10 ns 8 10 ns 60.24 60.6 ns 400 ps 55 % 3 ns –4 ns –1.5 f(APIC) = 16.67 MHz f(APIC) = 16.67 MHz Pulse duration width, low TYP tr Rise time VO = 0.4 V to 2 V tf Fall time VO = 0.4 V to 2 V † The average over any 1-µs period of time is greater than the minimum specified period. UNIT 25.5 28 ns 25.3 29.2 0.4 1.6 2.1 ns 0.4 1.2 1.7 ns MIN TYP MAX 6 10 ns 8 10 ns 15.06 15.3 ns 400 ps 55 % 150 ps 2.6 ns ns switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C 3V66 PARAMETER ten1 tdis1 tc FROM (INPUT) TO (OUTPUT) Output enable time SEL133/100 3V66x Output disable time 3V66 clock period† SEL133/100 3V66x Cycle to cycle jitter Duty cycle TEST CONDITIONS f(3V66) = 66 MHz f(3V66) = 66 MHz f(3V66) = 66 MHz f(CPU) = 100 or 133 MHz 15 45 tsk(o) tsk(p) 3V66 bus skew 3V66x 3V66x f(3V66) = 66 MHz f(3V66) = 66 MHz 3V66 pulse skew 3V66n 3V66n f(3V66) = 66 MHz t(off) t(off) 3V66 clock to CPU clock offset 3V66x CPUx tw1 tw2 Pulse duration width, high 3V66 clock to PCI clock offset, rising edge 50 UNIT 0 –0.75 –1.5 ns 1.2 2.1 3 ns f(3V66) = 66 MHz f(3V66) = 66 MHz 5.2 tr Rise time VO = 0.4 V to 2 V tf Fall time VO = 0.4 V to 2 V † The average over any 1-µs period of time is greater than the minimum specified period. 0.5 1.5 2 ns 0.5 1.5 2 ns Pulse duration width, low POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 ns 5 ns 11 CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued) 48MHz PARAMETER FROM (INPUT) TO (OUTPUT) ten1 tdis1 Output enable time SEL133/100 48MHz Output disable time SEL133/100 48MHz tc 48MHz clock period† Duty cycle 48MHz pulse skew tw2 tr Pulse duration width, low 48MHz 48MHz Pulse duration width, high MIN f(48MHz) = 48 MHz f(48MHz) = 48 MHz f(48MHz) = 48 MHz f(CPU) = 100 or 133 MHz Cycle to cycle jitter tsk(p) tw1 TEST CONDITIONS 20.5 TYP MAX UNIT 6 10 ns 8 10 ns 20.83 21.1 ns 500 ps 55 % 3 ns f(48MHz) = 48 MHz f(48MHz) = 48 MHz 45 f(48MHz) = 48 MHz f(48MHz) = 48 MHz 7.8 ns 7.8 ns Rise time VO = 0.4 V to 2 V tf Fall time VO = 0.4 V to 2 V † The average over any 1-µs period of time is greater than the minimum specified period. 1 2.1 2.8 ns 1 1.9 2.8 ns MIN TYP MAX 6 10 ns 8 10 ns REF PARAMETER ten1 tdis1 tc FROM (INPUT) TO (OUTPUT) Output enable time SEL133/100 REFx Output disable time REF clock period† SEL133/100 REFx TEST CONDITIONS f(REF) = 14.318 MHz f(REF) = 14.318 MHz f(REF) = 14.318 MHz f(CPU) = 100 or 133 MHz Cycle to cycle jitter Duty cycle tsk(o) tsk(p) REF bus skew REFx REFx REF pulse skew REFn REFn tw1 tw2 Pulse duration width, high f(REF) = 14.318 MHz f(REF) = 14.318 MHz f(REF) = 14.318 MHz f(REF) = 14.318 MHz Pulse duration width, low f(REF) = 14.318 MHz tr Rise time VO = 0.4 V to 2 V tf Fall time VO = 0.4 V to 2 V † The average over any 1-µs period of time is greater than the minimum specified period. 12 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 69.84 ns 700 45 150 UNIT ps 55 % 250 ps 2 ns 26.2 32.7 ns 26.2 31.2 1 2 2.8 ns 1 1.9 2.8 ns ns CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 switching characteristics, VDD = 3.135 V to 3.465 V, TA = 0°C to 85°C (continued) PCI PARAMETER ten1 tdis1 tc FROM (INPUT) TO (OUTPUT) Output enable time SEL133/100 PCIx Output disable time PCIx clock period† SEL133/100 PCIx Cycle to cycle jitter Duty cycle TEST CONDITIONS f(PCI) = 33 MHz f(PCI) = 33 MHz f(PCI) = 33 MHz f(CPU) = 100 or 133 MHz 30 45 tsk(o) tsk(p) PCIx bus skew PCIx PCIx f(PCI) = 33 MHz f(PCI) = 33 MHz PCIx pulse skew PCIn PCIn f(PCI) = 33 MHz t(off) tw1 PCIx clock to 3V66 clock offset tw2 tr Pulse duration width, low TYP MAX 6 10 ns 8 10 ns 30.12 30.5 ns 300 ps 55 % 300 ps 4 ns –3 ns 70 –1.2 Pulse duration width, high Rise time POST OFFICE BOX 655303 UNIT f(PCI) = 33 MHz f(PCI) = 33 MHz 12 VO = 0.4 V to 2 V VO = 0.4 V to 2 V 0.5 1.6 2 ns 0.5 1.5 2 ns tf Fall time † The average over any 1-µs period of time is greater than the minimum specified period. Powered by ICminer.com Electronic-Library Service CopyRight 2003 MIN • DALLAS, TEXAS 75265 ns 12 ns 13 CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 PARAMETER MEASUREMENT INFORMATION RL = 500 Ω From Output Under Test CL (see Note A) VO_REF OPEN GND S1 RL = 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VO_REF GND LOAD CIRCUIT for tpd and tsk ÎÎ tw From Output Under Test Test Point 3V VIH_REF VT_REF 0V VIL_REF Input CL (see Note A) VOLTAGE WAVEFORMS LOAD CIRCUIT FOR tr and tf 3V Input VT_REF VT_REF 0V tPLH Output Enable (high-level enabling) VDD VT_REF 0V tPZL tPHL tPLZ VOH VIH_REF Output VT_REF VIL_REF VOL tf tr VT_REF ≈3 V Output Waveform 1 S1 at 6 V (see Note B) VT_REF tPZH tw_low VOL tPHZ Output Waveform 2 S1 at GND (see Note B) tw_high VOL + 0.3 V VOH – 0.3 V VOH VT_REF ≈0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. CL = 20 pF (CPUx, APIC, 48MHz, REF), CL = 30 pF (PCIx) B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 14.318 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. v PARAMETER 3.3-V INTERFACE 2.5-V INTERFACE UNIT VIH_REF High-level reference voltage 2.4 2 V VIL_REF Low-level reference voltage 0.4 0.4 V VT_REF Input Threshold reference voltage 1.5 1.25 V VO_REF Off-state reference voltage 6 4.6 V Figure 3. Load Circuit and Voltage Waveforms 14 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 PARAMETER MEASUREMENT INFORMATION VT_REF CPUx or PCIx Clock tc VT_REF CPUx or PCIx Clock tsk(o) t sk(p) + Ť t –t t(low) Ť PLH PHL t(high) Duty Cycle + t (low) tc 100 3V66 or CPUx VT_REF VT_REF 3V66, PCIx, or APIC t(off) [3V66 to PCIx] t(off) [CPUx to APIC] t(off) [CPUx to 3V66] Figure 4. Waveforms for Calculation of Skew, Offset, and Jitter CPU (internal) PCI (internal) PWR_DWN CPU (external) PCI (external) ÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇ VCO CRYSTAL ÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇ ÇÇÇÇÇÇÇÇÇÇÇÇ NOTE A: Shaded sections on the VCO and Crystal waveforms indicate that the VCO and crystal oscillators are active and there is a valid clock. Figure 5. Power-Down Timing POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 15 CDC922 133-MHz CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS WITH 3-STATE OUTPUTS SCAS634 –JULY 28, 1999 MECHANICAL DATA DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48-PIN SHOWN 0.025 (0,635) 0.012 (0,305) 0.008 (0,203) 48 0.005 (0,13) M 25 0.006 (0,15) NOM 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°– 8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / D 08/97 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 16 POST OFFICE BOX 655303 Powered by ICminer.com Electronic-Library Service CopyRight 2003 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated Powered by ICminer.com Electronic-Library Service CopyRight 2003