ETC COP888CL

COP888CL
8-Bit Microcontroller
General Description
I/O Features
The following part numbers are pin count and temperature variations of the COP888CL: COP688CL,
COP684CL, COP884CL, COP988CL, COP984CL.
The COP888 family of microcontrollers uses an 8-bit single
chip core architecture fabricated with National Semiconductor’s M2CMOS™ process technology. The COP888CL is a
member of this expandable 8-bit core processor family of
microcontrollers.
It is a fully static part, fabricated using double-metal silicon
gate microCMOS technology. Features include an 8-bit
memory mapped architecture, MICROWIRE/PLUS serial
I/O, two 16-bit timer/counters supporting three modes (Processor Independent PWM generation, External Event
counter, and Input Capture mode capabilities), and two
power savings modes (HALT and IDLE), both with a multisourced wakeup/interrupt capability. This multi-sourced interrupt capability may also be used independent of the HALT
or IDLE modes. Each I/O pin has software selectable configurations. The device operates over a voltage range of
2.5V to 6V. High throughput is achieved with an efficient,
regular instruction set operating at a maximum of 1 µs per
instruction rate.
n Memory mapped I/O
n Software selectable I/O options ( TRI-STATE Output,
Push-Pull Output, Weak Pull-Up Input, High Impedance
Input)
n High current outputs
n Schmitt trigger inputs on port G
n Packages:
— 44 PLCC with 40 I/O pins
— 40 DIP with 36 I/O pins
— 28 DIP with 24 I/O pins
— 28 SO with 24 I/O pins
Key Features
n Two 16-bit timers, each with two 16-bit registers
supporting:
— Processor Independent PWM mode
— External Event counter mode
— Input Capture mode
n 4 kbytes of on-chip ROM
n 128 bytes of on-chip RAM
Additional Peripheral Features
n
n
n
n
Idle Timer
Multi-input Wake Up (MIWU) with optional interrupts (8)
WATCHDOG and Clock Monitor logic
MICROWIRE/PLUS™ serial I/O
CPU/Instruction Set Feature
n 1 µs instruction cycle time
n Ten multi-source vectored interrupts servicing
— External Interrupt with selectable edge
— Idle Timer T0
— Timers (Each with 2 interrupts)
— MICROWIRE/PLUS
— Multi-Input Wake Up
— Software Trap
— Default VIS (default interrupt)
n Versatile and easy to use instruction set
n 8-bit Stack Pointer (SP) — stack in RAM
n Two 8-bit Register Indirect Data Memory Pointers (B, X)
Fully Static CMOS
n Low current drain (typically < 1 µA)
n Single supply operation: 2.5V to 6.0V
n Temperature ranges: 0˚C to +70˚C, −40˚C to +85˚C,
−55˚C to +125˚C
Development Support
n Emulation and OTP devices
n Real time emulation and full program debug offered by
MetaLink Development System
MICROWIRE/PLUS™, M2CMOS™, COPS™ microcontrollers, and MICROWIRE™ are trademarks of National Semiconductor Corporation.
iceMASTER™ is a trademark of MetaLink Corporation.
© 2001 National Semiconductor Corporation
DS009766
www.national.com
COP888CL
8-Bit Microcontroller
September 2000
COP888CL
Block Diagram
DS009766-1
FIGURE 1. Block Diagram
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2
COP888CL
Connection Diagrams
Plastic Chip Carrier
Dual-In-Line Package
DS009766-2
Top View
Order Number COP688CL-XXX/V, COP888CL-XXX/V,
COP988CL-XXX/V or COP988CLH-XXX/V
See NS Plastic Chip Package Number V44A
DS009766-4
Top View
Order Number COP688CL-XXX/N, COP888CL-XXX/N,
COP988CL-XXX/N or COP988CLH-XXX/N
See NS Molded Package Number N40A
Dual-In-Line Package
DS009766-5
Top View
Order Number COP688CL-XXX/N, COP884CL-XXX/N, COP984CL-XXX/N or COP984CLH-XXX/N
See NS Molded Package Number N28B
Order Number COP684CL-XXX/WM,
COP884CL-XXX/WM, COP984CL-XXX/WM,
or COP984CLHXXX/WM
See NS Surface Mount Package Number M28B
FIGURE 2. Connection Diagrams
3
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COP888CL
Connection Diagrams
(Continued)
Pinouts for 28-, 40- and 44-Pin Packages
28-Pin
40-Pin
44-Pin
L0
Port
I/O
Type
MIWU
Alt. Fun
Alt. Fun
11
17
17
L1
I/O
MIWU
12
18
18
L2
I/O
MIWU
13
19
19
L3
I/O
MIWU
14
20
20
L4
I/O
MIWU
T2A
15
21
25
L5
I/O
MIWU
T2B
16
22
26
L6
I/O
MIWU
17
23
27
L7
I/O
MIWU
18
24
28
G0
I/O
INT
25
35
39
G1
WDOUT
26
36
40
G2
I/O
T1B
27
37
41
G3
I/O
T1A
28
38
42
G4
I/O
SO
1
3
3
G5
I/O
SK
2
4
4
G6
I
SI
3
5
5
G7
I/CKO
HALT
4
6
6
D0
O
19
25
29
D1
O
20
26
30
D2
O
21
27
31
D3
O
22
28
32
I0
I
7
9
9
I1
I
8
10
10
I2
I
11
11
I3
I
12
12
I4
I
9
13
13
I5
I
10
14
I6
I
RESTART
14
15
I7
I
D4
O
29
16
33
D5
O
30
34
D6
O
31
35
D7
O
32
36
C0
I/O
39
43
C1
I/O
40
44
C2
I/O
1
1
C3
I/O
2
C4
I/O
21
C5
I/O
22
C6
I/O
23
C7
I/O
2
24
Unused (Note 1)
16
Unused (Note 1)
15
VCC
6
8
8
GND
23
33
37
CKI
5
7
7
RESET
24
34
38
Note 1: On the 40-pin package Pins 15 and 16 must be connected to GND.
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4
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
Voltage at Any Pin
100 mA
110 mA
−65˚C to +140˚C
Note 2: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
7V
−0.3V to VCC + 0.3V
DC Electrical Characteristics
COP98XCL: 0˚C ≤ TA ≤ + 70˚C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
Operating Voltage
COP98XCL
2.5
4.0
V
COP98XCLH
4.0
6.0
V
0.1 VCC
V
12.5
mA
2.5
mA
8
µA
5
µA
3.5
mA
Power Supply Ripple (Note 3)
Peak-to-Peak
Supply Current (Note 4)
CKI = 10 MHz
VCC = 6V, tc = 1 µs
CKI = 4 MHz
VCC = 4V, tc = 2.5 µs
HALT Current (Note 5)
< 0.7
< 0.4
VCC = 6V, CKI = 0 MHz
VCC = 4V, CKI = 0 MHz
IDLE Current
CKI = 10 MHz
VCC = 6V, tc = 1 µs
Input Levels
RESET
Logic High
0.8 VCC
Logic Low
V
0.2 VCC
V
CKI (External and Crystal Osc. Modes)
Logic High
0.7 VCC
Logic Low
V
0.2 VCC
V
All Other Inputs
Logic High
0.7 VCC
Logic Low
V
0.2 VCC
V
Hi-Z Input Leakage
VCC = 6V
−1
+1
µA
Input Pullup Current
VCC = 6V, VIN = 0V
−40
−250
µA
0.35 VCC
V
G and L Port Input Hysteresis
Output Current Levels
D Outputs
Source
Sink
VCC = 4V, VOH = 3.3V
−0.4
VCC = 2.5V, VOH = 1.8V
mA
−0.2
mA
VCC = 4V, VOL = 1V
10
mA
VCC = 2.5V, VOL = 0.4V
2.0
mA
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
VCC = 4V, VOH = 2.7V
−10
−100
VCC = 2.5V, VOH = 1.8V
−2.5
−33
VCC = 4V, VOH = 3.3V
−0.4
VCC = 2.5V, VOH = 1.8V
−0.2
mA
VCC = 4V, VOL = 0.4V
1.6
mA
VCC = 2.5V, VOL = 0.4V
0.7
mA
VCC = 6.0V
−1
µA
µA
mA
+1
µA
D Outputs (Sink)
15
mA
All others
3
mA
Allowable Sink/Source
Current per Pin
5
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COP888CL
Absolute Maximum Ratings (Note 2)
COP888CL
DC Electrical Characteristics
(Continued)
COP98XCL: 0˚C ≤ TA ≤ + 70˚C unless otherwise specified.
Parameter
Maximum Input Current
Conditions
Min
Typ
TA = 25˚C
Max
Units
± 100
mA
without Latchup (Note 6)
RAM Retention Voltage, Vr
500 ns Rise
2
V
and Fall Time (Min)
Input Capacitance
Load Capacitance on D2
7
pF
1000
pF
Note 3: Rate of voltage change must be less then 0.5 V/ms.
Note 4: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 5: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G0–G5 configured as
outputs and set high. The D port set to zero. The clock monitor is disabled.
AC Electrical Characteristics
0˚C ≤ TA ≤ + 70˚C unless otherwise specified.
Parameter
Conditions
Min
Typ
Max
Units
µs
Instruction Cycle Time (tc)
Crystal or Resonator
4V ≤ VCC ≤ 6V
2.5V ≤ VCC < 4V
R/C Oscillator
4V ≤ VCC ≤ 6V
2.5V ≤ VCC < 4V
1
DC
2.5
DC
µs
3
DC
µs
7.5
DC
µs
Inputs
tSETUP
tHOLD
Output Propagation Delay (Note 7)
4V ≤ VCC ≤ 6V
200
ns
2.5V ≤ VCC < 4V
500
ns
4V ≤ VCC ≤ 6V
60
ns
2.5V ≤ VCC < 4V
150
ns
RL = 2.2k, CL = 100 pF
tPD1, tPD0
SO, SK
All Others
4V ≤ VCC ≤ 6V
0.7
µs
2.5V ≤ VCC < 4V
1.75
µs
1
µs
4V ≤ VCC ≤ 6V
2.5V ≤ VCC < 4V
2.5
µs
MICROWIRE™ Setup Time (tUWS)
20
ns
MICROWIRE Hold Time (tUWH)
56
ns
MICROWIRE Output Propagation Delay (tUPD)
220
ns
Input Pulse Width
Interrupt Input High Time
1
tc
Interrupt Input Low Time
1
tc
Timer Input High Time
1
tc
Timer Input Low Time
1
tc
1
µs
Reset Pulse Width
Note 6: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCCwhen biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 7: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
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6
Total Current into VCC Pin (Source)
Total Current out of GND Pin (Sink)
Storage Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
Voltage at Any Pin
100 mA
110 mA
−65˚C to +140˚C
Note 8: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
7V
−0.3V to VCC + 0.3V
DC Electrical Characteristics
COP88XCL: −40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Conditions
Operating Voltage
Power Supply Ripple (Note 9)
Min
Typ
2.5
Peak-to-Peak
Max
Units
6
V
0.1 VCC
V
Supply Current (Note 10)
CKI = 10 MHz
VCC = 6V, tc = 1 µs
12.5
mA
CKI = 4 MHz
VCC = 4V, tc = 2.5 µs
2.5
mA
10
µA
3.5
mA
HALT Current (Note 11)
<1
VCC = 6V, CKI = 0 MHz
IDLE Current
CKI = 10 MHz
VCC = 6V, tc = 1 µs
Input Levels
RESET
Logic High
0.8 VCC
Logic Low
V
0.2 VCC
V
CKI (External and Crystal Osc. Modes)
Logic High
0.7 VCC
Logic Low
V
0.2 VCC
V
All Other Inputs
Logic High
0.7 VCC
Logic Low
V
0.2 VCC
V
Hi-Z Input Leakage
VCC = 6V
−1
+1
µA
Input Pullup Current
VCC = 6V, VIN = 0V
−40
−250
µA
0.35 VCC
V
G and L Port Input Hysteresis
Output Current Levels
D Outputs
Source
Sink
VCC = 4V, VOH = 3.3V
−0.4
mA
VCC = 2.5V, VOH = 1.8V
−0.2
mA
VCC = 4V, VOL = 1V
10
mA
VCC = 2.5V, VOL = 0.4V
2.0
mA
All Others
Source (Weak Pull-Up Mode)
Source (Push-Pull Mode)
Sink (Push-Pull Mode)
TRI-STATE Leakage
VCC = 4V, VOH = 2.7V
−10
−100
µA
VCC = 2.5V, VOH = 1.8V
−2.5
−33
µA
VCC = 4V, VOH = 3.3V
−0.4
mA
VCC = 2.5V, VOH = 1.8V
−0.2
mA
VCC = 4V, VOL = 0.4V
1.6
mA
VCC = 2.5V, VOL = 0.4V
0.7
mA
VCC = 6.0V
−2
+2
µA
D Outputs (Sink)
15
mA
All others
3
mA
± 100
mA
Allowable Sink/Source
Current per Pin
Maximum Input Current
TA = 25˚C
without Latchup (Note 12)
7
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COP888CL
Absolute Maximum Ratings (Note 8)
COP888CL
DC Electrical Characteristics
(Continued)
COP88XCL: −40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
RAM Retention Voltage, Vr
Conditions
500 ns Rise
Min
Typ
Max
2
Units
V
and Fall Time (Min)
Input Capacitance
Load Capacitance on D2
7
pF
1000
pF
Note 9: Rate of voltage change must be less then 0.5 V/ms.
Note 10: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 11: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G0–G5 configured
as outputs and set high. The D port set to zero. The clock monitor is disabled.
AC Electrical Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (tc)
Crystal or Resonator
4V ≤ VCC ≤ 6V
2.5V ≤ VCC < 4V
R/C Oscillator
4V ≤ VCC ≤ 6V
2.5V ≤ VCC < 4V
1
DC
µs
2.5
DC
µs
3
DC
µs
7.5
DC
µs
Inputs
tSETUP
tHOLD
Output Propagation Delay (Note 13)
4V ≤ VCC ≤ 6V
200
ns
2.5V ≤ VCC < 4V
500
ns
4V ≤ VCC ≤ 6V
60
ns
2.5V ≤ VCC < 4V
150
ns
RL = 2.2k, CL = 100 pF
tPD1, tPD0
SO, SK
All Others
4V ≤ VCC ≤ 6V
0.7
µs
2.5V ≤ VCC
1.75
µs
1
µs
< 4V
4V ≤ VCC ≤ 6V
2.5V ≤ VCC < 4V
2.5
MICROWIRE Setup Time (tUWS)
20
MICROWIRE Hold Time (tUWH)
56
MICROWIRE Output Propagation Delay (tUPD)
µs
ns
ns
220
ns
Input Pulse Width
Interrupt Input High Time
1
tc
Interrupt Input Low Time
1
tc
Timer Input High Time
1
tc
Timer Input Low Time
1
tc
1
µs
Reset Pulse Width
Note 12: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCC when biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 13: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
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8
Note 14: Absolute maximum ratings indicate limits beyond which damage to
the device may occur. DC and AC electrical specifications are not ensured
when operating the device at absolute maximum ratings.
DC ELECTRICAL SPECIFICATIONS
COP688CL Absolute Specifications
Supply Voltage (VCC)
Voltage at Any Pin
7V
−0.3V to VCC + 0.3V
Total Current into VCC Pin
(Source)
90 mA
Total Current out of GND Pin
(Sink)
100 mA
Storage Temperature Range
−65˚C to +150˚C
DC Electrical Characteristics
COP68XCL: −55˚C ≤ TA ≤ +125˚C unless otherwise specified
Parameter
Conditions
Operating Voltage
Power Supply Ripple (Note 15)
Min
Typ
4.5
Peak-to-Peak
Max
Units
5.5
V
0.1 VCC
V
Supply Current (Note 16)
CKI = 10 MHz
VCC = 5.5V, tc = 1 µs
12.5
mA
CKI = 4 MHz
VCC = 5.5V, tc = 2.5 µs
5.5
mA
30
µA
HALT Current (Note 17)
< 10
VCC = 5.5V, CKI = 0 MHz
IDLE Current
CKI = 10 MHz
VCC = 5.5V, tc = 1 µs
3.5
mA
CKI = 4 MHz
VCC = 5.5V, tc = 2.5 µs
2.5
mA
Input Levels
RESET
Logic High
0.8 VCC
Logic Low
V
0.2 VCC
V
CKI (External and Crystal Osc. Modes)
Logic High
0.7 VCC
Logic Low
V
0.2 VCC
V
All Other Inputs
Logic High
0.7 VCC
Logic Low
Hi-Z Input Leakage
VCC = 5.5V
−5
Input Pullup Current
VCC = 5.5V, VIN = 0V
−35
G and L Port Input Hysteresis
V
0.2 VCC
V
+5
µA
−400
µA
0.35 VCC
V
Output Current Levels
D Outputs
Source
VCC = 4.5V, VOH = 3.8V
−0.4
mA
Sink
VCC = 4.5V, VOL = 1.0V
9
mA
Source (Weak Pull-Up Mode)
VCC = 4.5V, VOH = 3.8V
−9.0
Source (Push-Pull Mode)
VCC = 4.5V, VOH = 3.8V
−0.4
All Others
Sink (Push-Pull Mode)
VCC = 4.5V, VOL = 0.4V
1.4
TRI-STATE Leakage
VCC = 5.5V
−5.0
−140
µA
mA
mA
+5.0
µA
Note 15: Rate of voltage change must be less then 0.5 V/ms.
Note 16: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 17: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G0–G5 configured
as outputs and set high. The D port set to zero. The clock monitor is disabled.
9
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COP888CL
Electrical Specifications
COP888CL
DC Electrical Characteristics
−55˚C ≤ TA ≤ +25˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
D Outputs (Sink)
12
mA
All others
2.5
mA
150
mA
Allowable Sink/Source
Current per Pin
Maximum Input Current
without Latchup (Note 21)
RAM Retention Voltage, Vr
500 ns Rise
2.0
V
and Fall Time (Min)
Input Capacitance
Load Capacitance on D2
7
pF
1000
pF
Note 18: Rate of voltage change must be less then 0.5 V/ms.
Note 19: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 20: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to VCC, L and G ports in the
TRI-STATE mode and tied to ground, all outputs low and tied to ground. The Clock Monitor and the comparators are disabled.
AC Specifications for COP688CL
AC Electrical Characteristics
−55˚C ≤ TA ≤ +125˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (tc)
VCC ≥ 4.5V
1
DC
µs
VCC ≥ 4.5V
3
DC
µs
tSETUP
VCC ≥ 4.5V
200
ns
tHOLD
VCC ≥ 4.5V
60
ns
Crystal, Resonator, or
External Oscillator
R/C Oscillator (div-by 10)
Inputs
Output Propagation Delay (Note 22)
RL = 2.2k, CL = 100 pF
tPD1, tPD0
SO, SK
VCC ≥ 4.5V
All Others
VCC ≥ 4.5V
0.7
1
MICROWIRE Setup Time (tUWS)
20
MICROWIRE Hold Time(tUWH)
56
MICROWIRE Output Propagation Delay (tUPD)
µs
µs
ns
ns
220
ns
Input Pulse Width
Interrupt Input High Time
1
tc
Interrupt Input Low Time
1
tc
Timer Input High Time
1
tc
Timer Input Low Time
1
tc
1
µs
Reset Pulse Width
Note 21: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than VCC and the pins will
have sink current to VCCwhen biased at voltages greater than VCC (the pins do not have source current when biased at a voltage below VCC). The effective
resistance to VCC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 22: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
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10
COP888CL
AC Electrical Characteristics
(Continued)
DS009766-26
FIGURE 3. MICROWIRE/PLUS Timing
Typical Performance Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified
Halt — IDD
Idle — IDD(Crystal Clock Option)
DS009766-27
Dynamic — IDD vs VCC
(Crystal Clock Option)
DS009766-28
Port L/C/G Weak Pull-Up
Source Current
DS009766-29
DS009766-30
11
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COP888CL
Typical Performance Characteristics
−40˚C ≤ TA ≤ +85˚C unless otherwise specified (Continued)
Port L/C/G Push-Pull Source Current
Port L/C/G Push-Pull Sink Current
DS009766-31
Port D Source Current
DS009766-32
Port D Sink Current
DS009766-33
DS009766-34
Pin Descriptions
CONFIGURATION
VCC and GND are the power supply pins.
CKI is the clock input. This can come from an R/C generated
oscillator, or a crystal oscillator (in conjunction with CKO).
See Oscillator Description section.
RESET is the master reset input. See Reset Description
section.
The device contains three bidirectional 8-bit I/O ports (C, G
and L), where each individual bit may be independently
configured as an input (Schmitt trigger inputs on ports G and
L), output or TRI-STATE under program control. Three data
memory address locations are allocated for each of these
I/O ports. Each I/O port has two associated 8-bit memory
mapped registers, the CONFIGURATION register and the
output DATA register. A memory mapped address is also
reserved for the input pins of each I/O port. (See the memory
map for the various addresses associated with the I/O ports.)
Figure 4 shows the I/O port configurations. The DATA and
CONFIGURATION registers allow for each port bit to be
individually configured under software control as shown below:
DATA
Register
Port Set-Up
Register
0
0
Hi-Z Input
(TRI-STATE Output)
0
1
Input with Weak Pull-Up
1
0
Push-Pull Zero Output
1
1
Push-Pull One Output
DS009766-6
FIGURE 4. I/O Port Configurations
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12
PORT L is an 8-bit I/O port. All L-pins have Schmitt triggers
on the inputs.
Port C is an 8-bit I/O port. The 40-pin device does not have
a full complement of Port C pins. The unavailable pins are
not terminated. A read operation for these unterminated pins
will return unpredictable values.
Port L supports Multi-Input Wakeup (MIWU) on all eight pins.
L4 and L5 are used for the timer input functions T2A and
T2B.
Port I is an 8-bit Hi-Z input port. The 40-pin device does not
have a full complement of Port I pins. Pins 15 and 16 on this
package must be connected to GND.
Port L has the following alternate features:
L0
MIWU
L1
MIWU
L2
MIWU
L3
MIWU
L4
MIWU or T2A
L5
MIWU or T2B
L6
MIWU
L7
MIWU
Port G is an 8-bit port with 5 I/O pins (G0, G2–G5), an input
pin (G6), and two dedicated output pins (G1 and G7). Pins
G0 and G2–G6 all have Schmitt Triggers on their inputs. Pin
G1 serves as the dedicated WDOUT WATCHDOG output,
while pin G7 is either input or output depending on the
oscillator mask option selected. With the crystal oscillator
option selected, G7 serves as the dedicated output pin for
the CKO clock output. With the single-pin R/C oscillator
mask option selected, G7 serves as a general purpose input
pin, but is also used to bring the device out of HALT mode
with a low to high transition. There are two registers associated with the G Port, a data register and a configuration
register. Therefore, each of the 5 I/O bits (G0, G2–G5) can
be individually configured under software control.
Since G6 is an input only pin and G7 is the dedicated CKO
clock output pin or general purpose input (R/C clock configuration), the associated bits in the data and configuration
registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will
return zeros.
Note that the chip will be placed in the HALT mode by writing
a “1” to bit 7 of the Port G Data Register. Similarly the chip
will be placed in the IDLE mode by writing a “1” to bit 6 of the
Port G Data Register.
Writing a “1” to bit 6 of the Port G Configuration Register
enables the MICROWIRE/PLUS to operate with the alternate phase of the SK clock. The G7 configuration bit, if set
high, enables the clock start up delay after HALT when the
R/C clock configuration is used.
The 28-pin device has four I pins (I0, I1, I4, I5). The user
should pay attention when reading port I to the fact that I4
and I5 are in bit positions 4 and 5 rather than 2 and 3.
The unavailable pins (I4–I7) are not terminated i.e., they are
floating. A read operation for these unterminated pins will
return unpredictable values. The user must ensure that the
software takes into account by either masking or restricting
the accesses to bit operations. The unterminated port I pins
will draw power only when addressed.
Port D is an 8-bit output port that is preset high when RESET
goes low. The user can tie two or more D port outputs
(except D2) together in order to get a higher drive.
(Continued)
Config Reg.
Note: Care must be exercised with the D2 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay
above 0.8 VCC to prevent the chip from entering special modes. Also
keep the external loading on D2 to less than 1000 pF.
Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store
memory (RAM). Both ROM and RAM have their own separate addressing space with separate address buses. The
architecture, though based on Harvard architecture, permits
transfer of data from ROM to RAM.
CPU REGISTERS
The CPU can do an 8-bit addition, subtraction, logical or shift
operation in one instruction (tc) cycle time.
There are five CPU registers:
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer, which can be optionally
post auto incremented or decremented.
X is an 8-bit alternate RAM address pointer, which can be
optionally post auto incremented or decremented.
SP is the 8-bit stack pointer, which points to the subroutine/
interrupt stack (in RAM). The SP is initialized to RAM address 06F with reset.
All the CPU registers are memory mapped with the exception of the Accumulator (A) and the Program Counter (PC).
Data Reg.
G7
CLKDLY
HALT
G6
Alternate SK
IDLE
Port G has the following alternate features:
G0 INTR (External Interrupt Input)
G2 T1B (Timer T1 Capture Input)
G3 T1A (Timer T1 I/O)
G4 SO (MICROWIRE Serial Data Output)
G5 SK (MICROWIRE Serial Clock)
G6 SI (MICROWIRE Serial Data Input)
Port G has the following dedicated functions:
G1 WDOUT WATCHDOG and/or Clock Monitor dedicated output
G7 CKO Oscillator dedicated output or general purpose
input
PROGRAM MEMORY
Program memory consists of 4096 bytes of ROM. These
bytes may hold program instructions or constant data (data
tables for the LAID instruction, jump vectors for the JID
instruction, and interrupt vectors for the VIS instruction). The
program memory is addressed by the 15-bit program
counter (PC). All interrupts vector to program memory location 0FF Hex.
13
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COP888CL
Pin Descriptions
COP888CL
Functional Description
(Continued)
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers, the I/O registers (Configuration, Data and
Pin), the control registers, the MICROWIRE/PLUS SIO shift
register, and the various registers, and counters associated
with the timers (with the exception of the IDLE timer). Data
memory is addressed directly by the instruction or indirectly
by the B, X and SP pointers.
The device has 128 bytes of RAM. Sixteen bytes of RAM are
mapped as “registers” at addresses 0F0 to 0FF Hex. These
registers can be loaded immediately, and also decremented
and tested with the DRSZ (decrement register and skip if
zero) instruction. The memory pointer registers X, SP, and B
are memory mapped into this space at address locations
0FC to 0FE Hex respectively, with the other registers (other
than reserved register 0FF) being available for general usage.
The instruction set permits any bit in memory to be set, reset
or tested. All I/O and registers (except A and PC) are
memory mapped; therefore, I/O bits and register bits can be
directly and individually set, reset and tested. The accumulator (A) bits can also be directly and individually tested.
DS009766-7
RC
> 5 x Power Supply Rise Time
FIGURE 5. Recommended Reset Circuit
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin
which can be between DC and 10 MHz. The CKO output
clock is on pin G7 (crystal configuration). The CKI input
frequency is divided down by 10 to produce the instruction
cycle clock (1/tc).
Figure 6 shows the Crystal and R/C diagrams.
CRYSTAL OSCILLATOR
CKI and CKO can be connected to make a closed loop
crystal (or resonator) controlled oscillator.
Note: RAM contents are undefined upon power-up.
Reset
Table 1 shows the component values required for various
standard crystal values.
The RESET input when pulled low initializes the microcontroller. Initialization will occur whenever the RESET input is
pulled low. Upon initialization, the data and configuration
registers for Ports L, G, and C are cleared, resulting in these
Ports being initialized to the TRI-STATE mode. Pin G1 of the
G Port is an exception (as noted below) since pin G1 is
dedicated as the WATCHDOG and/or Clock Monitor error
output pin. Port D is initialized high with RESET . The PC,
PSW, CNTRL, ICNTRL, and T2CNTRL control registers are
cleared. The Multi-Input Wakeup registers WKEN, WKEDG,
and WKPND are cleared. The Stack Pointer, SP, is initialized
to 06F Hex.
The device comes out of reset with both the WATCHDOG
logic and the Clock Monitor detector armed, and with both
the WATCHDOG service window bits set and the Clock
Monitor bit set. The WATCHDOG and Clock Monitor detector
circuits are inhibited during reset. The WATCHDOG service
window bits are initialized to the maximum WATCHDOG
service window of 64k tc clock cycles. The Clock Monitor bit
is initialized high, and will cause a Clock Monitor error following reset if the clock has not reached the minimum specified frequency at the termination of reset. A Clock Monitor
error will cause an active low error output on pin G1. This
error output will continue until 16–32 tc clock cycles following
the clock frequency reaching the minimum specified value,
at which time the G1 output will enter the TRI-STATE mode.
The external RC network shown in should be used to ensure
that the RESET pin is held low until the power supply to the
chip stabilizes.
R/C OSCILLATOR
By selecting CKI as a single pin oscillator input, a single pin
R/C oscillator circuit can be connected to it. CKO is available
as a general purpose input, and/or HALT restart pin.
Table 2 shows the variation in the oscillator frequencies as
functions of the component (R and C) values.
DS009766-8
DS009766-9
FIGURE 6. Crystal and R/C Oscillator Diagrams
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14
TABLE 2. RC Oscillator Configuration, TA = 25˚C
(Continued)
TABLE 1. Crystal Oscillator Configuration, TA = 25˚C
R1
R2
C1
C2
CKI
Freq
Conditions
(kΩ)
(MΩ)
(pF)
(pF)
(MHz)
0
1
30
30–36
10
VCC = 5V
0
1
30
30–36
4
VCC = 5.0V
0
1
200
100–150
0.455
VCC = 5V
R
C
CKI Freq
Instr. Cycle
(kΩ)
(pF)
(MHz)
(µs)
Conditions
3.3
82
2.2 to 2.7
3.7 to 4.6
5.6
100
1.1 to 1.3
7.4 to 9.0
VCC = 5V
6.8
100
0.9 to 1.1
8.8 to 10.8
VCC = 5V
VCC = 5V
Note 23: 3k ≤ R ≤ 200k, 50 pF ≤ C ≤ 200 pF
Control Registers
CNTRL Register (Address X'00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
by (00 = 2, 01 = 4, 1x = 8)
IEDG
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
MSEL
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
T1C0 Timer T1 Start/Stop control in timer
modes 1 and 2
Timer T1 Underflow Interrupt Pending Flag in timer
mode 3
T1C1 Timer T1 mode control bit
T1C2 Timer T1 mode control bit
T1C3 Timer T1 mode control bit
T1C3 T1C2 T1C1 T1C0 MSEL IEDG
SL1
Bit 7
ICNTRL Register (Address X'00E8)
The ICNTRL register contains the following bits:
T1ENB
Timer T1 Interrupt Enable for T1B Input capture
edge
T1PNDB Timer T1 Interrupt Pending Flag for T1B capture edge
µWEN
Enable MICROWIRE/PLUS interrupt
µWPND MICROWIRE/PLUS interrupt pending
T0EN
T0PND
LPEN
Unused LPENT0PND T0EN µWPND µWENT1PNDB T1ENB
Bit 7
HC
Bit 0
C T1PNDA T1ENA EXPND BUSY EXEN
Bit 0
T2CNTRL Register (Address X'00C6)
The T2CNTRL register contains the following bits:
T2ENB
Timer T2 Interrupt Enable for T2B Input capture
edge
T2PNDB Timer T2 Interrupt Pending Flag for T2B capture edge
T2ENA
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)
SL0
PSW Register (Address X'00EF)
The PSW register contains the following select bits:
GIE
Global interrupt enable (enables interrupts)
EXEN
Enable external interrupt
BUSY
MICROWIRE/PLUS busy shifting flag
EXPND External interrupt pending
T1ENA
Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload
RA in mode 1, T1 Underflow in Mode 2, T1A
capture edge in mode 3)
C
Carry Flag
HC
Half Carry Flag
Bit 7
Timer T0 Interrupt Enable (Bit 12 toggle)
Timer T0 Interrupt pending
L Port Interrupt Enable (Multi-Input Wakeup/
Interrupt)
Bit 7 could be used as a flag
T2C0
T2C1
T2C2
T2C3
GIE
Timer T2 Start/Stop control in timer modes 1
and 2 Timer T2 Underflow Interrupt Pending
Flag in timer mode 3
Timer T2 mode control bit
Timer T2 mode control bit
Timer T2 mode control bit
T2C3 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB
Bit
0
Bit
7
The Half-Carry bit is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and RC (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and RC instructions, ADC, SUBC,
RRC and RLC instructions affect the carry and Half Carry
flags.
15
Bit 0
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COP888CL
Oscillator Circuits
COP888CL
Figure 7 shows a block diagram for the timers.
Timers
The device contains a very versatile set of timers (T0, T1,
T2). All timers and associated autoreload/capture registers
power up containing random data.
DS009766-11
FIGURE 7. Timers
TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE timer T0, which is a
16-bit timer. The Timer T0 runs continuously at the fixed rate
of the instruction cycle clock, tc. The user cannot read or
write to the IDLE Timer T0, which is a count down timer.
The Timer T0 supports the following functions:
Exit out of the Idle Mode (See Idle Mode description)
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
The IDLE Timer T0 can generate an interrupt when the
thirteenth bit toggles. This toggle is latched into the T0PND
pending flag, and will occur every 4 ms at the maximum
clock frequency (tc = 1 µs). A control flag T0EN allows the
interrupt from the thirteenth bit of Timer T0 to be enabled or
disabled. Setting T0EN will enable the interrupt, while resetting it will disable the interrupt.
and TxB. The pin TxA supports I/O required by the timer
block, while the pin TxB is an input to the timer block. The
powerful and flexible timer block allows the device to easily
perform all timer functions with minimal software overhead.
The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and
Input Capture mode.
The control bits TxC3, TxC2, and TxC1 allow selection of the
different modes of operation.
Mode 1. Processor Independent PWM Mode
As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention.
The user only has to define the parameters of the PWM
signal (ON time and OFF time). Once begun, the timer block
will continuously generate the PWM signal completely independent of the microcontroller. The user software services
the timer block only when the PWM parameters require
updating.
In this mode the timer Tx counts down at a fixed rate of tc.
Upon every underflow the timer is alternately reloaded with
the contents of supporting registers, RxA and RxB. The very
first underflow of the timer causes the timer to reload from
the register RxA. Subsequent underflows cause the timer to
be reloaded from the registers alternately beginning with the
register RxB.
The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the
timer for PWM mode operation.
TIMER T1 AND TIMER T2
The device has a set of two powerful timer/counter blocks,
T1 and T2. The associated features and functioning of a
timer block are described by referring to the timer block Tx.
Since the two timer blocks, T1 and T2, are identical, all
comments are equally applicable to either timer block.
Each timer block consists of a 16-bit timer, Tx, and two
supporting 16-bit autoreload/capture registers, RxA and
RxB. Each timer block has two pins associated with it, TxA
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16
Figure 8 shows a block diagram of the timer in PWM mode.
(Continued)
DS009766-13
FIGURE 8. Timer in PWM Mode
Mode 2. External Event Counter Mode
This mode is quite similar to the processor independent
PWM mode described above. The main difference is that the
timer, Tx, is clocked by the input signal from the TxA pin. The
Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to
be clocked either on a positive or negative edge from the
TxA pin. Underflows from the timer are latched into the
TxPNDA pending flag. Setting the TxENA control flag will
cause an interrupt when the timer underflows.
In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
The underflows can be programmed to toggle the TxA output
pin. The underflows can also be programmed to generate
interrupts.
Underflows from the timer are alternately latched into two
pending flags, TxPNDA and TxPNDB. The user must reset
these pending flags under software control. Two control
enable flags, TxENA and TxENB, allow the interrupts from
the timer underflow to be enabled or disabled. Setting the
timer enable flag TxENA will cause an interrupt when a timer
underflow causes the RxA register to be reloaded into the
timer. Setting the timer enable flag TxENB will cause an
interrupt when a timer underflow causes the RxB register to
be reloaded into the timer. Resetting the timer enable flags
will disable the associated interrupts.
Either or both of the timer underflow interrupts may be
enabled. This gives the user the flexibility of interrupting
once per PWM period on either the rising or falling edge of
the PWM output. Alternatively, the user may choose to interrupt on both edges of the PWM output.
Figure 9 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is being
used as the counter input clock.
DS009766-14
FIGURE 9. Timer in External Event Counter Mode
In this mode, the timer Tx is constantly running at the fixed tc
rate. The two registers, RxA and RxB, act as capture regis-
Mode 3. Input Capture Mode
The device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode.
17
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COP888CL
Timers
COP888CL
Timers
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
(Continued)
ters. Each register acts in conjunction with a pin. The register
RxA acts in conjunction with the TxA pin and the register RxB
acts in conjunction with the TxB pin.
Figure 10 shows a block diagram of the timer in Input Capture mode.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger
condition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag TxENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.
Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
TIMER CONTROL FLAGS
The timers T1 and T2 have indentical control structures. The
control bits and their functions are summarized below.
TxC0
Timer Start/Stop control in Modes 1 and 2 (Processor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in
Mode 3 (Input Capture)
TxPNDA Timer Interrupt Pending Flag
TxPNDB Timer Interrupt Pending Flag
TxENA
Timer Interrupt Enable Flag
TxENB
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
TxC3
Timer mode control
TxC2
Timer mode control
TxC1
Timer mode control
DS009766-15
FIGURE 10. Timer in Input Capture Mode
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18
COP888CL
Timers
(Continued)
The timer mode control bits (TxC3, TxC2 and TxC1) are detailed below:
TxC3
0
TxC2
0
TxC1
0
0
0
1
1
0
1
1
0
0
0
1
0
1
0
1
1
1
1
0
1
1
Timer Mode
Interrupt A
Interrupt B
Timer
Source
Source
Counts On
MODE 2 (External
Timer
Pos. TxB
TxA
Event Counter)
Underflow
Edge
Pos. Edge
MODE 2 (External
Timer
Pos. TxB
TxA
Event Counter)
Underflow
Edge
Neg. Edge
MODE 1 (PWM)
Autoreload
Autoreload
tc
TxA Toggle
RA
RB
MODE 1 (PWM)
Autoreload
Autoreload
No TxA Toggle
RA
RB
MODE 3 (Capture)
Pos. TxA
Pos. TxB
Captures:
Edge or
Edge
TxA Pos. Edge
Timer
TxB Pos. Edge
Underflow
MODE 3 (Capture)
Pos. TxA
Neg. TxB
Captures:
Edge or
Edge
TxA Pos. Edge
Timer
TxB Neg. Edge
Underflow
MODE 3 (Capture)
Neg. TxB
Pos. TxB
Captures:
Edge or
Edge
TxA Neg. Edge
Timer
TxB Pos. Edge
Underflow
MODE 3 (Capture)
Neg. TxA
Neg. TxB
Captures:
Edge or
Edge
TxA Neg. Edge
Timer
TxB Neg. Edge
Underflow
tc
tc
tc
tc
tc
Power Save Modes
The device offers the user two power save modes of operation: HALT and IDLE. In the HALT mode, all microcontroller
activities are stopped. In the IDLE mode, the on-board oscillator circuitry and timer T0 are active but all other microcontroller activities are stopped. In either mode, all on-board
RAM, registers, I/O states, and timers (with the exception of
T0) are unaltered.
This method precludes the use of the crystal clock configuration (since CKO becomes a dedicated output), and so may
be used with an RC clock configuration. The third method of
exiting the HALT mode is by pulling the RESET pin low.
Since a crystal or ceramic resonator may be selected as the
oscillator, the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full amplitude and frequency stability. The IDLE timer is used to
generate a fixed delay to ensure that the oscillator has
indeed stabilized before allowing instruction execution. In
this case, upon detecting a valid Wakeup signal, only the
oscillator circuitry is enabled. The IDLE timer is loaded with
a value of 256 and is clocked with the tc instruction cycle
clock. The tc clock is derived by dividing the oscillator clock
down by a factor of 10. The Schmitt trigger following the CKI
inverter on the chip ensures that the IDLE timer is clocked
only when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications. This Schmitt trigger
is not part of the oscillator closed loop. The startup timeout
from the IDLE timer enables the clock signals to be routed to
the rest of the chip.
If an RC clock option is being used, the fixed delay is
introduced optionally. A control bit, CLKDLY, mapped as
configuration bit G7, controls whether the delay is to be
HALT MODE
The device is placed in the HALT mode by writing a “1” to the
HALT flag (G7 data bit). All microcontroller activities, including the clock, timers, are stopped. The WATCHDOG logic is
disabled during the HALT mode. However, the clock monitor
circuitry, if enabled, remains active and will cause the
WATCHDOG output pin (WDOUT) to go low. If the HALT
mode is used and the user does not want to activate the
WDOUT pin, the Clock Monitor should be disabled after the
device comes out of reset (resetting the Clock Monitor control bit with the first write to the WDSVR register). In the
HALT mode, the power requirements of the device are minimal and the applied voltage (VCC) may be decreased to Vr
(Vr = 2.0V) without altering the state of the machine.
The device supports three different ways of exiting the HALT
mode. The first method of exiting the HALT mode is with the
Multi-Input Wakeup feature on the L port. The second
method is with a low to high transition on the CKO (G7) pin.
19
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COP888CL
Power Save Modes
Figure 11 shows the Multi-Input Wakeup logic.
The Multi-Input Wakeup feature utilizes the L Port. The user
selects which particular L port bit (or combination of L Port
bits) will cause the device to exit the HALT or IDLE modes.
The selection is done through the Reg: WKEN. The Reg:
WKEN is an 8-bit read/write register, which contains a control bit for every L port bit. Setting a particular WKEN bit
enables a Wakeup from the associated L port pin.
The user can select whether the trigger condition on the
selected L Port pin is going to be either a positive edge (low
to high transition) or a negative edge (high to low transition).
This selection is made via the Reg: WKEDG, which is an
8-bit control register with a bit assigned to each L Port pin.
Setting the control bit will select the trigger condition to be a
negative edge on that particular L Port pin. Resetting the bit
selects the trigger condition to be a positive edge. Changing
an edge select entails several steps in order to avoid a
pseudo Wakeup condition as a result of the edge change.
First, the associated WKEN bit should be reset, followed by
the edge select change in WKEDG. Next, the associated
WKPND bit should be cleared, followed by the associated
WKEN bit being re-enabled.
An example may serve to clarify this procedure. Suppose we
wish to change the edge select from positive (low going high)
to negative (high going low) for L Port bit 5, where bit 5 has
previously been enabled for an input interrupt. The program
would be as follows:
RBIT 5, WKEN
SBIT 5, WKEDG
RBIT 5, WKPND
SBIT 5, WKEN
If the L port bits have been used as outputs and then
changed to inputs with Multi-Input Wakeup/Interrupt, a safety
procedure should also be followed to avoid inherited pseudo
wakeup conditions. After the selected L port bits have been
changed from output to input but before the associated
WKEN bits are enabled, the associated edge select bits in
WKEDG should be set or reset for the desired edge selects,
followed by the associated WKPND bits being cleared.
This same procedure should be used following reset, since
the L port inputs are left floating as a result of reset.
The occurrence of the selected trigger condition for
Multi-Input Wakeup is latched into a pending register called
WKPND. The respective bits of the WKPND register will be
set on the occurrence of the selected trigger edge on the
corresponding Port L pin. The user has the responsibility of
clearing these pending flags. Since WKPND is a pending
register for the occurrence of selected wakeup conditions,
the device will not enter the HALT mode if any Wakeup bit is
both enabled and pending. Consequently, the user has the
responsibility of clearing the pending flags before attempting
to enter the HALT mode.
The WKEN, WKPND and WKEDG are all read/write registers, and are cleared at reset.
(Continued)
introduced or not. The delay is included if CLKDLY is set,
and excluded if CLKDLY is reset. The CLKDLY bit is cleared
on reset.
The device has two mask options associated with the HALT
mode. The first mask option enables the HALT mode feature,
while the second mask option disables the HALT mode. With
the HALT mode enable mask option, the device will enter
and exit the HALT mode as described above. With the HALT
disable mask option, the device cannot be placed in the
HALT mode (writing a “1” to the HALT flag will have no
effect).
The WATCHDOG detector circuit is inhibited during the
HALT mode. However, the clock monitor circuit, if enabled,
remains active during HALT mode in order to ensure a clock
monitor error if the device inadvertently enters the HALT
mode as a result of a runaway program or power glitch.
IDLE MODE
The device is placed in the IDLE mode by writing a “1” to the
IDLE flag (G6 data bit). In this mode, all activity, except the
associated on-board oscillator circuitry, the WATCHDOG
logic, the clock monitor and the IDLE Timer T0, is stopped.
As with the HALT mode, the device can be returned to
normal operation with a reset, or with a Multi-Input Wake-up
from the L Port. Alternately, the microcontroller resumes
normal operation from the IDLE mode when the thirteenth bit
(representing 4.096 ms at internal clock frequency of 1 MHz,
tc = 1 µs) of the IDLE Timer toggles.
This toggle condition of the thirteenth bit of the IDLE Timer
T0 is latched into the T0PND pending flag.
The user has the option of being interrupted with a transition
on the thirteenth bit of the IDLE Timer T0. The interrupt can
be enabled or disabled via the T0EN control bit. Setting the
T0EN flag enables the interrupt and vice versa.
The user can enter the IDLE mode with the Timer T0 interrupt enabled. In this case, when the T0PND bit gets set, the
device will first execute the Timer T0 interrupt service routine
and then return to the instruction following the “Enter Idle
Mode” instruction.
Alternatively, the user can enter the IDLE mode with the
IDLE Timer T0 interrupt disabled. In this case, the device will
resume normal operation with the instruction immediately
following the “Enter IDLE Mode” instruction.
Note: It is necessary to program two NOP instructions following both the set
HALT mode and set IDLE mode instructions. These NOP instructions
are necessary to allow clock resynchronization following the HALT or
IDLE modes.
Multi-Input Wakeup
The Multi-Input Wakeup feature is used to return (wakeup)
the device from either the HALT or IDLE modes. Alternately
Multi-Input Wakeup/Interrupt feature may also be used to
generate up to 8 edge selectable external interrupts.
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20
COP888CL
Multi-Input Wakeup
(Continued)
DS009766-16
FIGURE 11. Multi-Input Wake Up Logic
PORT L INTERRUPTS
Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into the
same service subroutine.
The interrupt from Port L shares logic with the wake up
circuitry. The register WKEN allows interrupts from Port L to
be individually enabled or disabled. The register WKEDG
specifies the trigger condition to be either a positive or a
negative edge. Finally, the register WKPND latches in the
pending trigger conditions.
The GIE (Global Interrupt Enable) bit enables the interrupt
function.
A control flag, LPEN, functions as a global interrupt enable
for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not
needed since the register WKPND is adequate.
Since Port L is also used for waking the device out of the
HALT or IDLE modes, the user can elect to exit the HALT or
IDLE modes either with or without the interrupt enabled. If he
elects to disable the interrupt, then the device will restart
execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE
modes. In the other case, the device will first execute the
interrupt service routine and then revert to normal operation.
The Wakeup signal will not start the chip running immediately since crystal oscillators or ceramic resonators have a
finite start up time. The IDLE Timer (T0) generates a fixed
delay to ensure that the oscillator has indeed stabilized
before allowing the device to execute instructions. In this
case, upon detecting a valid Wakeup signal, only the oscillator circuitry and the IDLE Timer T0 are enabled. The IDLE
Timer is loaded with a value of 256 and is clocked from the
tc instruction cycle clock. The tc clock is derived by dividing
down the oscillator clock by a factor of 10. A Schmitt trigger
following the CKI on-chip inverter ensures that the IDLE
timer is clocked only when the oscillator has a sufficiently
large amplitude to meet the Schmitt trigger specifications.
This Schmitt trigger is not part of the oscillator closed loop.
The startup timeout from the IDLE timer enables the clock
signals to be routed to the rest of the chip. If the RC clock
option is used, the fixed delay is under software control. A
control flag, CLKDLY, in the G7 configuration bit allows the
clock start up delay to be optionally inserted. Setting
CLKDLY flag high will cause clock start up delay to be
inserted and resetting it will exclude the clock start up delay.
The CLKDLY flag is cleared during reset, so the clock start
up delay is not present following reset with the RC clock
options.
Interrupts
The device supports a vectored interrupt scheme. It supports
a total of ten interrupt sources. The following table lists all the
possible interrupt sources, their arbitration ranking and the
memory locations reserved for the interrupt vector for each
source.
Two bytes of program memory space are reserved for each
interrupt source. All interrupt sources except the software
interrupt are maskable. Each of the maskable interrupts
have an Enable bit and a Pending bit. A maskable interrupt is
active if its associated enable and pending bits are set. If
GIE = 1 and an interrupt is active, then the processor will be
interrupted as soon as it is ready to start executing an
instruction except if the above conditions happen during the
Software Trap service routine. This exception is described in
the Software Trap sub-section.
The interruption process is accomplished with the INTR
instruction (opcode 00), which is jammed inside the Instruction Register and replaces the opcode about to be executed.
The following steps are performed for every interrupt:
1. The GIE (Global Interrupt Enable) bit is reset.
2. The address of the instruction about to be executed is
pushed into the stack.
3. The PC (Program Counter) branches to address 00FF.
This procedure takes 7 tc cycles to execute.
21
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COP888CL
Interrupts
(Continued)
Arbitration
Ranking
Vector
Source
Description
Address
Hi-Low Byte
(1) Highest
Software
INTR Instruction
0yFE–0yFF
Reserved
for Future Use
0yFC–0yFD
(2)
External
Pin G0 Edge
0yFA–0yFB
(3)
Timer T0
Underflow
0yF8–0yF9
(4)
Timer T1
T1A/Underflow
0yF6–0yF7
(5)
Timer T1
T1B
0yF4–0yF5
(6)
MICROWIRE/PLUS
BUSY Goes Low
0yF2–0yF3
Reserved
for Future Use
0yF0–0yF1
Reserved
for UART
0yEE–0yEF
Reserved
for UART
0yEC–0yED
(7)
Timer T2
T2A/Underflow
0yEA–0yEB
(8)
Timer T2
T2B
0yE8–0yE9
Reserved
for Future Use
0yE6–0yE7
Reserved
for Future Use
0yE4–0yE5
(9)
Port L/Wakeup
Port L Edge
0yE2–0yE3
(10) Lowest
Default
VIS Instr. Execution
0yE0–0yE1
without Any Interrupts
y is VIS page, y ≠ 0.
VIS and the vector table must be located in the same
256-byte block (0y00 to 0yFF) except if VIS is located at the
last address of a block. In this case, the table must be in the
next block. The vector table cannot be inserted in the first
256-byte block.
The vector of the maskable interrupt with the lowest rank is
located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte)
and so forth in increasing rank number. The vector of the
maskable interrupt with the highest rank is located at 0yFA
(Hi-Order byte) and 0yFB (Lo-Order byte).
The Software Trap has the highest rank and its vector is
located at 0yFE and 0yFF.
If, by accident, a VIS gets executed and no interrupt is
active, then the PC (Program Counter) will branch to a vector
located at 0yE0–0yE1.
At this time, since GIE = 0, other maskable interrupts are
disabled. The user is now free to do whatever context
switching is required by saving the context of the machine in
the stack with PUSH instructions. The user would then program a VIS (Vector Interrupt Select) instruction in order to
branch to the interrupt service routine of the highest priority
interrupt enabled and pending at the time of the VIS. Note
that this is not necessarily the interrupt that caused the
branch to address location 00FF Hex prior to the context
switching.
Thus, if an interrupt with a higher rank than the one which
caused the interruption becomes active before the decision
of which interrupt to service is made by the VIS, then the
interrupt with the higher rank will override any lower ones
and will be acknowledged. The lower priority interrupt(s) are
still pending, however, and will cause another interrupt immediately following the completion of the interrupt service
routine associated with the higher priority interrupt just serviced. This lower priority interrupt will occur immediately
following the RETI (Return from Interrupt) instruction at the
end of the interrupt service routine just completed.
Inside the interrupt service routine, the associated pending
bit has to be cleared by software. The RETI (Return from
Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit, allowing the
processor to be interrupted again if another interrupt is active
and pending.
The VIS instruction looks at all the active interrupts at the
time it is executed and performs an indirect jump to the
beginning of the service routine of the one with the highest
rank.
The addresses of the different interrupt service routines,
called vectors, are chosen by the user and stored in ROM in
a table starting at 01E0 (assuming that VIS is located between 00FF and 01DF). The vectors are 15-bit wide and
therefore occupy 2 ROM locations.
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WARNING
A Default VIS interrupt handle routine must be present. As a
minimum, this handler should confirm that the GIE bit is
cleared (this indicates that the interrupt sequence has been
taken), take care of any required housekeeping, restore
context and return. Some sort of Warm Restart procedure
should be implemented. These events can occur without any
error on the part of the system designer or programmer.
Note: There is always the possibility of an interrupt occurring during an
instruction which is attempting to reset the GIE bit or any other interrupt enable bit. If this occurs when a single cycle instruction is being
used to reset the interrupt enable bit, the interrupt enable bit will be
reset but an interrupt may still occur. This is because interrupt processing is started at the same time as the interrupt bit is being reset. To
avoid this scenario, the user should always use a two, three, or four
cycle instruction to reset interrupt enable bits.
Figure 12 shows the Interrupt block diagram.
22
COP888CL
Interrupts
(Continued)
DS009766-18
FIGURE 12. Interrupt Block Diagram
SOFTWARE TRAP
The Software Trap (ST) is a special kind of non-maskable
interrupt which occurs when the INTR instruction (used to
acknowledge interrupts) is fetched from ROM and placed
inside the instruction register. This may happen when the PC
is pointing beyond the available ROM address space or
when the stack is over-popped.
When an ST occurs, the user can re-initialize the stack
pointer and do a recovery procedure (similar to reset, but not
necessarily containing all of the same initialization procedures) before restarting.
The occurrence of an ST is latched into the ST pending bit.
The GIE bit is not affected and the ST pending bit (not
accessible by the user) is used to inhibit other interrupts
and to direct the program to the ST service routine with the
VIS instruction. The RPND instruction is used to clear the
software interrupt pending bit. This pending bit is also
cleared on reset.
The ST has the highest rank among all interrupts.
Nothing (except another ST) can interrupt an ST being
serviced.
The lower limit of the service window is fixed at 2048 instruction cycles. Bits 7 and 6 of the WDSVR register allow the
user to pick an upper limit of the service window.
Table 4 shows the four possible combinations of lower and
upper limits for the WATCHDOG service window. This flexibility in choosing the WATCHDOG service window prevents
any undue burden on the user software.
Bits 5, 4, 3, 2 and 1 of the WDSVR register represent the
5-bit Key Data field. The key data is fixed at 01100. Bit 0 of
the WDSVR Register is the Clock Monitor Select bit.
TABLE 3. WATCHDOG Service Register (WDSVR)
Window
Key Data
Clock
Select
Monitor
X
X
0
1
1
0
0
Y
7
6
5
4
3
2
1
0
TABLE 4. WATCHDOG Service Window Select
WATCHDOG
The device contains a WATCHDOG and clock monitor. The
WATCHDOG is designed to detect the user program getting
stuck in infinite loops resulting in loss of program control or
“runaway” programs. The Clock Monitor is used to detect the
absence of a clock or a very slow clock below a specified
rate on the CKI pin.
The WATCHDOG consists of two independent logic blocks:
WD UPPER and WD LOWER. WD UPPER establishes the
upper limit on the service window and WD LOWER defines
the lower limit of the service window.
Servicing the WATCHDOG consists of writing a specific
value to a WATCHDOG Service Register named WDSVR
which is memory mapped in the RAM. This value is composed of three fields, consisting of a 2-bit Window Select, a
5-bit Key Data field, and the 1-bit Clock Monitor Select field.
Table 3 shows the WDSVR register.
WDSVR
WDSVR
Service Window
Bit 7
Bit 6
(Lower-Upper Limits)
0
0
2k-8k tc Cycles
0
1
2k-16k tc Cycles
1
0
2k-32k tc Cycles
1
1
2k-64k tc Cycles
Clock Monitor
The Clock Monitor aboard the device can be selected or
deselected under program control. The Clock Monitor is
guaranteed not to reject the clock if the instruction cycle
clock (1/tc) is greater or equal to 10 kHz. This equates to a
clock input rate on CKI of greater or equal to 100 kHz.
WATCHDOG Operation
The WATCHDOG and Clock Monitor are disabled during
reset. The device comes out of reset with the WATCHDOG
armed, the WATCHDOG Window Select bits (bits 6, 7 of the
WDSVR Register) set, and the Clock Monitor bit (bit 0 of the
23
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COP888CL
WATCHDOG Operation
limit of the service window. The user may service the
WATCHDOG as many times as wished in the time period
between the lower and upper limits of the service window.
The first write to the WDSVR Register is also counted as a
WATCHDOG service.
(Continued)
WDSVR Register) enabled. Thus, a Clock Monitor error will
occur after coming out of reset, if the instruction cycle clock
frequency has not reached a minimum specified value, including the case where the oscillator fails to start.
The WATCHDOG has an output pin associated with it. This
is the WDOUT pin, on pin 1 of the port G. WDOUT is active
low. The WDOUT pin is in the high impedance state in the
inactive state. Upon triggering the WATCHDOG, the logic
will pull the WDOUT (G1) pin low for an additional 16 tc–32
tc cycles after the signal level on WDOUT pin goes below the
lower Schmitt trigger threshold. After this delay, the device
will stop forcing the WDOUT output low.
The WATCHDOG service window will restart when the
WDOUT pin goes high It is recommended that the user tie
the WDOUT pin back to VCC through a resistor in order to
pull WDOUT high.
A WATCHDOG service while the WDOUT signal is active will
be ignored. The state of the WDOUT pin is not guaranteed
on reset, but if it powers up low then the WATCHDOG will
time out and WDOUT will enter high impedance state.
The WDSVR register can be written to only once after reset
and the key data (bits 5 through 1 of the WDSVR Register)
must match to be a valid write. This write to the WDSVR
register involves two irrevocable choices: (i) the selection of
the WATCHDOG service window (ii) enabling or disabling of
the Clock Monitor. Hence, the first write to WDSVR Register
involves selecting or deselecting the Clock Monitor, select
the WATCHDOG service window and match the WATCHDOG key data. Subsequent writes to the WDSVR register
will compare the value being written by the user to the
WATCHDOG service window value and the key data (bits 7
through 1) in the WDSVR Register. Table 5 shows the sequence of events that can occur.
The user must service the WATCHDOG at least once before
the upper limit of the serivce window expires. The WATCHDOG may not be serviced more than once in every lower
TABLE 5. WATCHDOG Service Actions
Key
Window
Clock
Data
Data
Monitor
Action
Match
Match
Match
Don’t Care
Mismatch
Don’t Care
Valid Service: Restart Service Window
Error: Generate WATCHDOG Output
Mismatch
Don’t Care
Don’t Care
Error: Generate WATCHDOG Output
Don’t Care
Don’t Care
Mismatch
Error: Generate WATCHDOG Output
TABLE 6. MICROWIRE/PLUS
Master Mode Clock Select
SL1
SL0
0
0
2 x tc
SK
0
1
4 x tc
1
x
8 x tc
Where tc is the instruction cycle clock
The Clock Monitor forces the G1 pin low upon detecting a
clock frequency error. The Clock Monitor error will continue
until the clock frequency has reached the minimum specified
value, after which the G1 output will enter the high impedance TRI-STATE mode following 16 tc–32 tc clock cycles.
The Clock Monitor generates a continual Clock Monitor error
if the oscillator fails to start, or fails to reach the minimum
specified frequency. The specification for the Clock Monitor
is as follows:
1/tc > 10 kHz — No clock rejection.
•
The initial WATCHDOG service must match the key data
value in the WATCHDOG Service register WDSVR in
order to avoid a WATCHDOG error.
•
Subsequent WATCHDOG services must match all three
data fields in WDSVR in order to avoid WATCHDOG
errors.
•
The correct key data value cannot be read from the
WATCHDOG Service register WDSVR. Any attempt to
read this key data value of 01100 from WDSVR will read
as key data value of all 0’s.
1/tc < 10 Hz — Guaranteed clock rejection.
•
The WATCHDOG detector circuit is inhibited during both
the HALT and IDLE modes.
•
The Clock Monitor detector circuit is active during both
the HALT and IDLE modes. Consequently, the device
inadvertently entering the HALT mode will be detected as
a Clock Monitor error (provided that the Clock Monitor
enable option has been selected by the program).
•
With the single-pin R/C oscillator mask option selected
and the CLKDLY bit reset, the WATCHDOG service window will resume following HALT mode from where it left
off before entering the HALT mode.
WATCHDOG AND CLOCK MONITOR SUMMARY
The following salient points regarding the WATCHDOG and
Clock Monitor should be noted:
•
Both WATCHDOG and Clock Monitor detector circuits
are inhibited during reset.
•
Following reset, the WATCHDOG and Clock Monitor are
both enabled, with the WATCHDOG having the maximum
service window selected.
•
The WATCHDOG service window and Clock Monitor
enable/disable option can only be changed once, during
the initial WATCHDOG service following reset.
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24
•
ers, E2PROMs etc.) and with other microcontrollers which
support the MICROWIRE interface. It consists of an 8-bit
serial shift register (SIO) with serial data input (SI), serial
data output (SO) and serial shift clock (SK). Figure 13 shows
a block diagram of the MICROWIRE logic.
(Continued)
With the crystal oscillator mask option selected, or with
the single-pin R/C oscillator mask option selected and the
CLKDLY bit set, the WATCHDOG service window will be
set to its selected value from WDSVR following HALT.
Consequently, the WATCHDOG should not be serviced
for at least 2048 instruction cycles following HALT, but
must be serviced within the selected window to avoid a
WATCHDOG error.
•
•
The IDLE timer T0 is not initialized with reset.
•
A hardware WATCHDOG service occurs just as the device exits the IDLE mode. Consequently, the Watchdog
should not be serviced for at least 2048 instruction cycles
following IDLE, but must be serviced within the selected
window to avoid a WATCHDOG error.
•
Following reset, the initial WATCHDOG service (where
the service window and the Clock Monitor enable/disable
must be selected) may be programmed anywhere within
the maximum service window (65,536 instruction cycles)
initialized by RESET. Note that this initial WATCHDOG
service may be programmed within the initial 2048 instruction cycles without causing a WATCHDOG error.
The shift clock can be selected from either an internal source
or an external source. Operating the MICROWIRE/PLUS
arrangement with the internal clock source is called the
Master mode of operation. Similarly, operating the MICROWIRE arrangement with an external shift clock is called
the Slave mode of operation.
The user can sync in to the IDLE counter cycle with an
IDLE counter (T0) interrupt or by monitoring the T0PND
flag. The T0PND flag is set whenever the thirteenth bit of
the IDLE counter toggles (every 4096 instruction cycles).
The user is responsible for resetting the T0PND flag.
DS009766-20
FIGURE 13. MICROWIRE/PLUS Block Diagram
The CNTRL register is used to configure and control the
MICROWIRE/PLUS mode. To use the MICROWIRE/PLUS,
the MSEL bit in the CNTRL register is set to one. In the
master mode, the SK clock rate is selected by the two bits,
SL0 and SL1, in the CNTRL register. Table IV details the
different clock rates that may be selected.
Detection of Illegal Conditions
The device can detect various illegal conditions resulting
from coding errors, transient noise, power supply voltage
drops, runaway programs, etc.
Reading of undefined ROM gets zeros. The opcode for
software interrupt is zero. If the program fetches instructions
from undefined ROM, this will force a software interrupt, thus
signaling that an illegal condition has occurred.
The subroutine stack grows down for each call (jump to
subroutine), interrupt, or PUSH, and grows up for each
return or POP. The stack pointer is initialized to RAM location
06F Hex during reset. Consequently, if there are more returns than calls, the stack pointer will point to addresses 070
and 071 Hex (which are undefined RAM). Undefined RAM
from addresses 070 to 07F Hex is read as all 1’s, which in
turn will cause the program to return to address 7FFF Hex.
This is an undefined ROM location and the instruction
fetched (all 0’s) from this location will generate a software
interrupt signaling an illegal condition.
Thus, the chip can detect the following illegal conditions:
1. Executing from undefined ROM
2. Over “POP”ing the stack by having more returns than
calls.
When the software interrupt occurs, the user can re-initialize
the stack pointer and do a recovery procedure before restarting (this recovery program is probably similar to that following reset, but might not contain the same program initialization procedures). The recovery program should reset the
software interrupt pending bit using the RPND instruction.
MICROWIRE/PLUS OPERATION
Setting the BUSY bit in the PSW register causes the
MICROWIRE/PLUS to start shifting the data. It gets reset
when eight data bits have been shifted. The user may reset
the BUSY bit by software to allow less than 8 bits to shift. If
enabled, an interrupt is generated when eight data bits have
been shifted. The device may enter the MICROWIRE/PLUS
mode either as a Master or as a Slave. Figure 14 shows how
two COP888CL microcontrollers and several peripherals
may be interconnected using the MICROWIRE/PLUS arrangements.
Warning:
The SIO register should only be loaded when the SK clock is
low. Loading the SIO register while the SK clock is high will
result in undefined data in the SIO register. The SK clock is
normally low when not shifting.
Setting the BUSY flag when the input SK clock is high in the
MICROWIRE/PLUS slave mode may cause the current SK
clock for the SIO shift register to be narrow. For safety, the
BUSY flag should only be set when the input SK clock is low.
MICROWIRE/PLUS Master Mode Operation
In the MICROWIRE/PLUS Master mode of operation the
shift clock (SK) is generated internally. The MICROWIRE
Master always initiates all data exchanges. The MSEL bit in
the CNTRL register must be set to enable the SO and SK
functions onto the G Port. The SO and SK pins must also be
selected as outputs by setting appropriate bits in the Port G
configuration register. Table V summarizes the bit settings
required for Master mode of operation.
MICROWIRE/PLUS
MICROWIRE/PLUS is a serial synchronous communications
interface. The MICROWIRE/PLUS capability enables the
device to interface with any of National Semiconductor’s
MICROWIRE peripherals (i.e. A/D converters, display driv25
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COP888CL
WATCHDOG Operation
COP888CL
MICROWIRE/PLUS
Alternate SK Phase Operation
(Continued)
The device allows either the normal SK clock or an alternate
phase SK clock to shift data in and out of the SIO register. In
both the modes the SK is normally low. In the normal mode
data is shifted in on the rising edge of the SK clock and the
data is shifted out on the falling edge of the SK clock. The
SIO register is shifted on each falling edge of the SK clock.
In the alternate SK phase operation, data is shifted in on the
falling edge of the SK clock and shifted out on the rising edge
of the SK clock.
MICROWIRE/PLUS Slave Mode Operation
In the MICROWIRE/PLUS Slave mode of operation the SK
clock is generated by an external source. Setting the MSEL
bit in the CNTRL register enables the SO and SK functions
onto the G Port. The SK pin must be selected as an input
and the SO pin is selected as an output pin by setting and
resetting the appropriate bit in the Port G configuration register. Table V summarizes the settings required to enter the
Slave mode of operation.
The user must set the BUSY flag immediately upon entering
the Slave mode. This will ensure that all data bits sent by the
Master will be shifted properly. After eight clock pulses the
BUSY flag will be cleared and the sequence may be repeated.
DS009766-21
FIGURE 14. MICROWIRE/PLUS Application
A control flag, SKSEL, allows either the normal SK clock or
the alternate SK clock to be selected. Resetting SKSEL
causes the MICROWIRE/PLUS logic to be clocked from the
normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition, selecting the normal SK signal.
This table assumes that the control flag MSEL is set.
TABLE 7.
G4
G5
(SO)
(SK)
G4
G5
Config.
Config.
Fun.
Fun.
Bit
Bit
1
1
SO
Int.
MICROWIRE/PLUS
SK
Master
MICROWIRE/PLUS
0
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26
1
Operation
TRI-
Int.
STATE
SK
Master
MICROWIRE/PLUS
1
0
SO
Ext.
SK
Slave
0
0
TRI-
Ext.
MICROWIRE/PLUS
STATE
SK
Slave
Address
All RAM, ports and registers (except A and PC) are mapped
into data memory address space
Address
Contents
COP888CL
Memory Map
Contents
EE
CNTRL Control Register
EF
PSW Register
F0 to FB
On-Chip RAM Mapped as Registers
00 to 6F
On-Chip RAM bytes
FC
X Register
70 to BF
Unused RAM Address Space
FD
SP Register
C0
Timer T2 Lower Byte
FE
B Register
C1
Timer T2 Upper Byte
FF
Reserved
C2
Timer T2 Autoload Register T2RA Lower
Byte
Reading memory locations 70-7F Hex will return all ones. Reading other
unused memory locations will return undefined data.
C3
Timer T2 Autoload Register T2RA Upper
Byte
Addressing Modes
C4
Timer T2 Autoload Register T2RB Lower
Byte
The device has ten addressing modes, six for operand addressing and four for transfer of control.
C5
Timer T2 Autoload Register T2RB Upper
Byte
C6
Timer T2 Control Register
C7
WATCHDOG Service Register
(Reg:WDSVR)
C8
MIWU Edge Select Register
(Reg:WKEDG)
OPERAND ADDRESSING MODES
Register Indirect
This is the “normal” addressing mode. The operand is the
data memory addressed by the B pointer or X pointer.
Register Indirect (with auto post increment or
decrement of pointer)
This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B
pointer or X pointer. This is a register indirect mode that
automatically post increments or decrements the B or X
register after executing the instruction.
Direct
The instruction contains an 8-bit address field that directly
points to the data memory for the operand.
Immediate
The instruction contains an 8-bit immediate field as the
operand.
Short Immediate
This addressing mode is used with the Load B Immediate
instruction. The instruction contains a 4-bit immediate field
as the operand.
Indirect
This addressing mode is used with the LAID instruction. The
contents of the accumulator are used as a partial address
(lower 8 bits of PC) for accessing a data operand from the
program memory.
C9
MIWU Enable Register (Reg:WKEN)
CA
MIWU Pending Register (Reg:WKPND)
CB
Reserved
CC
Reserved
CD to CF
Reserved
D0
Port L Data Register
D1
Port L Configuration Register
D2
Port L Input Pins (Read Only)
D3
Reserved for Port L
D4
Port G Data Register
D5
Port G Configuration Register
D6
Port G Input Pins (Read Only)
D7
Port I Input Pins (Read Only)
D8
Port C Data Register
D9
Port C Configuration Register
DA
Port C Input Pins (Read Only)
DB
Reserved for Port C
DC
Port D Data Register
TRANSFER OF CONTROL ADDRESSING MODES
DD to DF
Reserved for Port D
E0 to E5
Reserved
E6
Timer T1 Autoload Register T1RB Lower
Byte
E7
Timer T1 Autoload Register T1RB Upper
Byte
E8
ICNTRL Register
Relative
This mode is used for the JP instruction, with the instruction
field being added to the program counter to get the new
program location. JP has a range from −31 to +32 to allow a
1-byte relative jump (JP + 1 is implemented by a NOP
instruction). There are no “pages” when using JP, since all 15
bits of PC are used.
E9
MICROWIRE Shift Register
EA
Timer T1 Lower Byte
EB
Timer T1 Upper Byte
EC
Timer T1 Autoload Register T1RA Lower
Byte
ED
Timer T1 Autoload Register T1RA Upper
Byte
Absolute
This mode is used with the JMP and JSR instructions, with
the instruction field of 12 bits replacing the lower 12 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory segment.
27
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COP888CL
Addressing Modes
Absolute Long
contents of this program memory location serve as a partial
address (lower 8 bits of PC) for the jump to the next instruction.
This mode is used with the JMPL and JSRL instructions, with
the instruction field of 15 bits replacing the entire 15 bits of
the program counter (PC). This allows jumping to any location in the current 4k program memory space.
Note: The VIS is a special case of the Indirect Transfer of Control addressing
mode, where the double byte vector associated with the interrupt is
transferred from adjacent addresses in the program memory into the
program counter (PC) in order to jump to the associated interrupt
service routine.
(Continued)
Indirect
This mode is used with the JID instruction. The contents of
the accumulator are used as a partial address (lower 8 bits of
PC) for accessing a location in the program memory. The
Instruction Set
Register and Symbol Definition
Registers
A
8-Bit Accumulator Register
B
8-Bit Address Register
X
8-Bit Address Register
SP
8-Bit Stack Pointer Register
PC
15-Bit Program Counter Register
PU
Upper 7 Bits of PC
PL
Lower 8 Bits of PC
C
1 Bit of PSW Register for Carry
HC
1 Bit of PSW Register for Half Carry
GIE
1 Bit of PSW Register for Global Interrupt
Enable
VU
Interrupt Vector Upper Byte
VL
Interrupt Vector Lower Byte
[B]
Memory Indirectly Addressed by B Register
Symbols
[X]
Memory Indirectly Addressed by X Register
MD
Direct Addressed Memory
Mem
Direct Addressed Memory or [B]
Meml
Direct Addressed Memory or [B] or
Immediate Data
Imm
8-Bit Immediate Data
Reg
Register Memory: Addresses F0 to FF
(Includes B, X and SP)
Bit
←
Loaded with
↔
Exchanged with
www.national.com
Bit Number (0 to 7)
28
COP888CL
Instruction Set
(Continued)
INSTRUCTION SET
A← A + Meml
A← A + Meml + C, C ← Carry
HC← Half Carry
ADD
A,Meml
ADD
ADC
A,Meml
ADD with Carry
SUBC
A,Meml
Subtract with Carry
A← A − MemI + C, C← Carry
HC← Half Carry
AND
A,Meml
Logical AND
A← A and Meml
ANDSZ
A,Imm
Logical AND Immed., Skip if Zero
OR
A,Meml
Logical OR
Skip next if (A and Imm) = 0
A← A or Meml
XOR
A,Meml
Logical EXclusive OR
A← A xor Meml
IFEQ
MD,Imm
IF EQual
Compare MD and Imm, Do next if MD = Imm
IFEQ
A,Meml
IF EQual
IFNE
A,Meml
IF Not Equal
Compare A and Meml, Do next if A = Meml
Compare A and Meml, Do next if A ≠ Meml
IFGT
A,Meml
IF Greater Than
IFBNE
#
If B Not Equal
DRSZ
Reg
Decrement Reg., Skip if Zero
Compare A and Meml, Do next if A > Meml
Do next if lower 4 bits of B ≠ Imm
Reg← Reg− 1, Skip if Reg = 0
SBIT
#,Mem
Set BIT
1 to bit, Mem (bit = 0 to 7 immediate)
RBIT
#,Mem
Reset BIT
0 to bit, Mem
IFBIT
#,Mem
RPND
IF BIT
If bit in A or Mem is true do next instruction
Reset PeNDing Flag
Reset Software Interrupt Pending Flag
X
A,Mem
EXchange A with Memory
A↔Mem
X
A,[X]
EXchange A with Memory [X]
LD
A,Meml
LoaD A with Memory
A↔[X]
A←Meml
LD
A,[X]
LoaD A with Memory [X]
LD
B,Imm
LoaD B with Immed.
LD
Mem,Imm
LoaD Memory Immed
LD
Reg,Imm
LoaD Register Memory Immed.
X
A, [B ± ]
EXchange A with Memory [B]
X
EXchange A with Memory [X]
LD
A, [X ± ]
A, [B ± ]
A, [X ± ]
[B ± ],Imm
CLR
A
CLeaR A
INC
A
INCrement A
DEC
A
DECrementA
LD
LD
A←[X]
B← Imm
Mem← Imm
Reg← Imm
A↔[B], (B← B ± 1)
A↔[X], (X← ± 1)
A←[B], (B← B ± 1)
A←[X], (X← X ± 1)
[B]← Imm, (B← ± 1)
LoaD A with Memory [B]
LoaD A with Memory [X]
LoaD Memory [B] Immed.
Load A InDirect from ROM
A←0
A←A + 1
A←A − 1
A← ROM (PU,A)
DCOR
A
Decimal CORrect A
A← BCD correction of A (follows ADC, SUBC)
RRC
A
Rotate A Right thru C
RLC
A
Rotate A Left thru C
C ↔ A7 ↔…↔ A0 ↔ C
C← A7 ← …← A0 ← C
SWAP
A
LAID
SC
Set C
RC
Reset C
A7…A4 ↔ A3…A0
C← 1, HC← 1
C← 0, HC← 0
IFC
IF C
IF C is true, do next instruction
IFNC
IF Not C
If C is not true, do next instruction
SP←SP + 1, A← [SP]
SWAP nibbles of A
POP
A
POP the stack into A
PUSH
A
PUSH A onto the stack
VIS
[SP]← A, SP← SP − 1
PU← [VU], PL ←[VL]
Vector to Interrupt Service Routine
JMPL
Addr.
Jump absolute Long
JMP
Addr.
Jump absolute
PC← ii (ii = 15 bits, 0 to 32k)
PC9…0←i (i = 12 bits)
JP
Disp.
Jump relative short
PC← PC + r (r is −31 to +32, except 1)
29
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COP888CL
Instruction Set
(Continued)
INSTRUCTION SET
(Continued)
JSRL
Addr.
Jump SubRoutine Long
JSR
Addr
Jump SubRoutine
[SP]← PL, [SP−1]← PU,SP−2, PC← ii
[SP]← PL, [SP−1] ← PU,SP−2, PC9…0← i
PL← ROM (PU,A)
JID
Jump InDirect
RET
RETurn from subroutine
RETSK
RETurn and SKip
RETI
RETurn from Interrupt
INTR
Generate an Interrupt
SP+2, PL← [SP],PU← [SP−1],GIE← 1
[SP]← PL, [SP−1]← PU, SP−2, PC← 0FF
NOP
No OPeration
PC← PC+1
SP+2, PL← [SP], PU← [SP−1]
SP+2, PL← [SP],PU← [SP−1]
Instruction Execution Time
Most instructions are single byte (with immediate addressing
mode instructions taking two bytes).
Most single byte instructions take one cycle time to execute.
Skipped instructions require x number of cycles to be
skipped, where x equals the number of bytes in the skipped
instruction opcode.
See the BYTES and CYCLES per INSTRUCTION table for
details.
Bytes and Cycles per Instruction
The following table shows the number of bytes and cycles for
each instruction in the format of byte/cycle.
Instructions Using A & C
Arithmetic and Logic Instructions
1/1
INCA
1/1
DECA
1/1
LAID
1/3
DCOR
1/1
RRCA
1/1
RLCA
1/1
SWAPA
1/1
SC
1/1
RC
1/1
IFC
1/1
IFNC
1/1
PUSHA
1/3
POPA
1/3
ANDSZ
2/2
[B]
Direct
ADD
1/1
3/4
2/2
ADC
1/1
3/4
2/2
SUBC
1/1
3/4
2/2
AND
1/1
3/4
2/2
OR
1/1
3/4
2/2
XOR
1/1
3/4
2/2
IFEQ
1/1
3/4
2/2
JMPL
3/4
IFNE
1/1
3/4
2/2
JMP
2/3
2/2
JP
1/3
JSRL
3/5
1/3
JSR
2/5
3/4
JID
1/3
3/4
VIS
1/5
3/4
RET
1/5
RETSK
1/5
RETI
1/5
INTR
1/7
NOP
1/1
IFGT
IFBNE
1/1
RBIT
1/1
1/1
IFBIT
1/1
RPND
1/1
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Transfer of Control Instructions
1/1
DRSZ
SBIT
3/4
Immed.
CLRA
30
COP888CL
Instruction Execution Time
(Continued)
Memory Transfer Instructions
Register
Direct
Immed.
Indirect
Register Indirect
Auto Incr. & Decr.
[B]
[X]
[B+, B−]
X A,*
1/1
1/3
2/3
LD A,*
1/1
1/3
2/3
2/2
[X+, X−]
1/2
1/3
1/2
1/3
LD B, Imm
1/1
(IF B < 16)
LD B, Imm
2/2
(IF B > 15)
LD Mem, Imm
2/2
3/3
LD Reg, Imm
2/3
IFEQ MD, Imm
3/3
* =
2/2
> Memory location addressed by B or X or directly.
31
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32
JP−18
JP−17
JP−16
JP−2
JP−1
JP−0
LD 0FF, #i
LD 0FE, #i
LD 0FD, #i
LD 0FC, #i
LD 0FB, #i
LD 0FA, #i
LD 0F9, #i
LD 0F8, #i
LD 0F7, #i
LD 0F6, #i
LD 0F5, #i
LD 0F4, #i
LD 0F3, #i
LD 0F2, #i
LD 0F1, #i
LD 0F0, #i
D
DRSZ
0FF
DRSZ
0FE
DRSZ
0FD
DRSZ
0FC
DRSZ
0FB
DRSZ
0FA
DRSZ
0F9
DRSZ
0F8
DRSZ
0F7
DRSZ
0F6
DRSZ
0F5
DRSZ
0F4
DRSZ
0F3
DRSZ
0F2
DRSZ
0F1
DRSZ
0F0
C
B
*
LD
A,[X]
DIR
LD
Md,#i
LD
A,[X−]
LD
A,[X+]
IFNE
A,[B]
NOP
*
X A,[X]
RPND
VIS
X
A,[X−]
X
A,[X+]
*
RRCA
Where,
i is the immediate data
Md is a directly addressed memory location
* is an unused opcode
The opcode 60 Hex is also the opcode for IFBIT #i,A
JP−19
JP−3
JP−24
JP−8
JP−20
JP−25
JP−9
JP−4
JP−26
JP−10
JP−21
JP−27
JP−11
JP−5
JP−28
JP−12
JP−22
JP−29
JP−13
JP−6
JP−30
JP−14
JP−23
JP−31
JP−15
JP−7
E
F
OPCODE TABLE
OR A,#i
XOR
A,#i
AND
A,#i
ADD
A,#i
IFGT
A,#i
IFEQ
A,#i
SUBC
A, #i
ADC
A,#i
9
LD
[B−],#i
LD
[B+],#i
IFNE
A,#i
*
LD
A,[B]
JSRL
LD B,#i
LD
[B],#i
LD
A,Md
JMPL X A,Md
LD
A,[B−]
LD
A,[B+]
IFEQ
Md,#i
RLCA LD A,#i
*
X
A,[B]
JID
LAID
X
A,[B−]
X
A,[B+]
SC
RC
A
RETI
RET
6
CLRA
*
*
*
LD
B,#0B
LD
B,#0C
LD
B,#0D
LD
B,#0E
LD
B,#0F
5
SBIT
7,[B]
SBIT
6,[B]
SBIT
5,[B]
SBIT
4,[B]
SBIT
3,[B]
SBIT
2,[B]
SBIT
1,[B]
SBIT
0,[B]
RBIT
7,[B]
RBIT
6,[B]
RBIT
5,[B]
RBIT
4,[B]
RBIT
3,[B]
RBIT
2,[B]
RBIT
1,[B]
RBIT
0,[B]
IFBIT PUSHA
7,[B]
IFBIT DCORA
6,[B]
LD
B,#00
LD
B,#01
LD
B,#02
LD
B,#03
LD
B,#04
LD
B,#05
LD
B,#06
LD
B,#07
LD
B,#08
LD
B,#09
IFBIT SWAPA
LD
5,[B]
B,#0A
IFBIT
4,[B]
IFBIT
3,[B]
IFBIT
2,[B]
IFBIT
1,[B]
IFBIT ANDSZ
0,[B]
A, #i
7
Upper Nibble
RETSK
POPA
DECA
INCA
IFNC
IFC
OR
A,[B]
XOR
A,[B]
AND
A,[B]
ADD
A,[B]
IFGT
A,[B]
IFEQ
A,[B]
SUBC
A,[B]
ADC
A,[B]
8
IFBNE 0F
IFBNE 0E
IFBNE 0D
IFBNE 0C
IFBNE 0B
IFBNE 0A
IFBNE 9
IFBNE 8
IFBNE 7
IFBNE 6
IFBNE 5
IFBNE 4
IFBNE 3
IFBNE 2
IFBNE 1
IFBNE 0
4
1
0
8
7
6
5
4
3
2
1
0
JMP
JP+26 JP+10 9
x900–x9FF
JMP
JP+25 JP+9
x800–x8FF
JMP
JP+24 JP+8
x700–x7FF
JMP
JP+23 JP+7
x600–x6FF
JMP
JP+22 JP+6
x500–x5FF
JMP
JP+21 JP+5
x400–x4FF
JMP
JP+20 JP+4
x300–x3FF
JMP
JP+19 JP+3
x200–x2FF
JMP
JP+18 JP+2
x100–x1FF
JMP
JP+17 INTR
x000–x0FF
2
JSR
JMP
JP+32 JP+16 F
xF00–xFFF xF00–xFFF
JSR
JMP
JP+31 JP+15 E
xE00–xEFF xE00–xEFF
JSR
JMP
JP+30 JP+14 D
xD00–xDFF xD00–xDFF
JSR
JMP
JP+29 JP+13 C
xC00–xCFF xC00–xCFF
JSR
JMP
JP+28 JP+12 B
xB00–xBFF xB00–xBFF
JSR
JMP
JP+27 JP+11 A
xA00–xAFF xA00–xAFF
JSR
x900–x9FF
JSR
x800–x8FF
JSR
x700–x7FF
JSR
x600–x6FF
JSR
x500–x5FF
JSR
x400–x4FF
JSR
x300–x3FF
JSR
x200–x2FF
JSR
x100–x1FF
JSR
x000–x0FF
3
Lower Nibble
COP888CL
Instruction Execution Time
(Continued)
COP888CL
Mask Options
The mask programmable options are shown below. The
options are programmed at the same time as the ROM
pattern submission.
OPTION 1: CLOCK CONFIGURATION
= 1 Crystal Oscillator (CKI/10)
G7 (CKO) is clock generator
output to crystal/resonator
CKI is the clock input
= 2 Single-pin RC controlled
oscillator (CKI/10)
G7 is available as a HALT
restart and/or general purpose
input
OPTION 2: HALT
= 1 Enable HALT mode
= 2 Disable HALT mode
OPTION 3: BONDING
= 1 44-Pin PCC
= 2 40-Pin DIP
= 3 N.A.
= 4 28-Pin DIP
= 5 28-Pin SO
33
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COP888CL
Development Support
•
A full 64k hardware configurable break, trace on, trace off
control, and pass count increment events.
SUMMARY
•
Tool
set
integrated
interactive
symbolic
debugger — supports both assembler (COFF) and C
Compiler (.COD) linked object formats.
•
Real time performance profiling analysis; selectable
bucket definition.
•
iceMASTER™ : IM-COP8/400 — Full feature in-circuit
emulation for all COP8 products. A full set of COP8 Basic
and Feature Family device and package specific probes
are available.
•
COP8 Debug Module: Moderate cost in-circuit emulation
and development programming unit.
•
Watch windows, content updated automatically at each
execution break.
•
COP8
Evaluation
and
Programming
Unit:
EPU-COP888GG — low cost in-circuit simulation and development programming unit.
•
Instruction by instruction memory/register changes displayed on source window when in single step operation.
•
•
Assembler: COP8-DEV-IBMA. A DOS installable cross
development Assembler, Linker, Librarian and Utility Software Development Tool Kit.
Single base unit and debugger software reconfigurable to
support the entire COP8 family; only the probe personality needs to change. Debugger software is processor
customized, and reconfigured from a master model file.
•
C Compiler: COP8C. A DOS installable cross development Software Tool kit.
•
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
•
OPT/EPROM Programmer Support: Covering needs
from engineering prototype, pilot production to full production environments.
•
•
Halt/Idle mode notification.
•
Includes a copy of COP8-DEV-IBMA assembler and
linker SDK.
IceMASTER (IM) IN-CIRCUIT EMULATION
The iceMASTER IM-COP8/400 is a full feature, PC based,
in-circuit emulation tool developed and marketed by MetaLink Corporation to support the whole COP8 family of
products. National is a resale vendor for these products.
See Figure 15 for configuration.
IM Order Information
Base Unit
IM-COP8/400-1
The iceMASTER IM-COP8/400 with its device specific
COP8 Probe provides a rich feature set for developing,
testing and maintaining product:
•
•
•
•
On-line HELP customized to specific processor using
master model file.
iceMASTER Base Unit,
110V Power Supply
IM-COP8/400-2
iceMASTER Base Unit,
220V Power Supply
Real-time in-circuit emulation; full 2.4V–5.5V operation
range, full DC-10 MHz clock. Chip options are programmable or jumper selectable.
iceMASTER Probe
MHW-884CL28DWPC
28 DIP
Direct connection to application board by package compatible socket or surface mount assembly.
MHW-888CL40DWPC
40 DIP
MHW-888CL44PWPC
44 PLCC
Full 32 kbyte of loadable programming space that overlays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated on the
probe as necessary.
Adapter for SO package
MHW-SO -SOIC28
28 SO
Full 4k frame synchronous trace memory. Address, instruction, and 8 unspecified, circuit connectable trace
lines. Display can be HLL source (e.g., C source), assembly or mixed.
DS009766-35
FIGURE 15. COP8 iceMASTER Environment
www.national.com
34
(Continued)
IceMASTER DEBUG MODULE (DM)
The iceMASTER IM-COP8/400 is a PC based, combination
in-circuit emulation tool and COP8 based OPT/EPROM programming tool developed and marketed by MetaLink Corporation to support the whole COP8 family of products. National is a resale vendor for these products.
See Figure 16 for configuration.
The iceMASTER Debug Module is a moderate cost development tool. It has the capability of in-circuit emulation for a
specific COP8 microcontroller and in addition serves as a
programming tool for COP8 OTP and EPROM product families. Summary of features is as follows:
•
Real-time in-circuit emulation; full operating voltage
range operation, full DC-10 MHz clock.
•
All processor I/O pins can be cabled to an application
development board with package compatible cable to
socket and surface mount assembly.
•
•
•
Full 32 kbyte of loadable programming space that overlays (replaces) the on-chip ROM or EPROM. On-chip
RAM and I/O blocks are used directly or recreated on the
probe as necessary.
•
Instruction by instruction memory/register changes displayed when in single step operation.
•
Processor specific symbolic display of registers and bit
level assignments, configured from master model file.
•
•
Halt/Idle mode notification.
•
Programming of 44PLCC and 68PLCC parts requires
external programming adapters.
•
•
Includes wallmount power supply.
•
ON-Line HELP customized to specific processor using
master model file.
•
Includes a copy of COP8-DEV-IBMA assembler and
linker SDK.
Programming menu supports full product line of programmable OTP and EPROM COP8 products. Program data
is taken directly from the overlay RAM.
On-board VPP generator from 5V input or connection to
external supply supported. Requires VPPlevel adjustment
per the family programming specification (correct level is
provided on an on-screen pop-down display).
Debug Module Unit
COP8-DM/888CF
Cable Adapters
DM-COP8/28D
Configured break points; uses INTR instruction which is
modestly intrusive.
Software — only supported features are selectable.
Debugger software is processed customized, and reconfigured from a master model file.
DM Order Information
100 frames of synchronous trace memory. The display
can be HLL source (C source), assembly or mixed. The
most recent history prior to a break is available in the
trace memory.
•
•
•
28 DIP
DM-COP8/40D
40 DIP
DM-COP8/44P
44 PLCC
Adapter for SO package
Tool set integrated interactive symbolic debugger - supports both assembler (COFF) and C Compiler (.COD)
SDK linked object formats.
MHW-SO -SOIC28
28 SO
DS009766-36
FIGURE 16. COP8-DM Environment
35
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COP888CL
Development Support
COP888CL
Development Support
COP8 C COMPILER
A C Compiler is developed and marketed by Byte Craft
Limited. The COP8C compiler is a fully integrated development tool specifically designed to support the compact embedded configuration of the COP8 family of products.
(Continued)
COP8 ASSEMBLER/LINKER SOFTWARE
DEVELOPMENT TOOL KIT
National Semiconductor offers a relocateable COP8 macro
cross assembler, linker, librarian and utility software development tool kit. Features are summarized as follows:
Features are summarized as follows:
• ANSI C with some restrictions and extensions that optimize development for the COP8 embedded application.
• BITS data type extension. Register declaration #pragma
with direct bit level definitions.
• Basic and Feature Family instruction set by “device” type
• Nested macro capability.
• Extensive set of assembler directives.
• Supported on PC/DOS platform.
• Generates National standard COFF output files.
• Integrated Linker and Librarian.
• Integrated utilities to generate ROM code file outputs.
• DUMPCOFF utility.
This product is integrated as a part of MetaLink tools as a
development kit, fully supported by the MetaLink debugger.
It may be ordered separately or it is bundled with the MetaLink products at no additional cost.
•
•
C language support for interrupt routines.
•
Performs consistency checks against the architectural
definitions of the target COP8 device.
•
•
Generates program memory code.
•
•
Global optimization of linked code.
Expert system, rule based code geration and optimization.
Supports linking of compiled object or COP8 assembled
object formats.
Symbolic debug load format fully source level supported
by the MetaLink debugger.
Order Information
Assembler SDK:
COP8-DEV-IBMA Assembler SDK on installable 3.5"
PC/DOS Floppy Disk Drive format.
Periodic upgrades and most recent
version is available on National’s BBS
and Internet.
Approved List
Manufacturer
North
Europe
Asia
America
BP
(800) 225-2102
+49-8152-4183
+852-234-16611
Microsystems
(713) 688-4600
+49-8856-932616
+852-2710-8121
Fax: (713) 688-0920
Data I/O
(800) 426-1045
+44-0734-440011
(206) 881-6444
Call
North America
Fax: (206) 882-1043
HI–LO
(510) 623-8860
Call Asia
+886-2-764-0215
Fax: +886-2-756-6403
ICE
(800) 624-8949
+44-1226-767404
Technology
(919) 430-7915
Fax: 0-1226-370-434
MetaLink
(800) 638-2423
+49-80 9156 96-0
(602) 926-0797
Fax: +49-80 9123 86
+852-737-1800
Fax: (602) 693-0681
Systems
(408) 263-6667
+41-1-9450300
General
Needhams
(916) 924-8037
Fax: (916) 924-8065
www.national.com
+886-2-917-3005
Fax: +886-2-911-1283
36
DIAL-A-HELPER BBS via a Standard Modem
(Continued)
Modem:
SINGLE CHIP OTP/EMULATOR SUPPORT
CANADA/U.S.:
EUROPE:
(+49) 0-8141-351332
Baud:
14.4k
Set-Up:
Length:
OTP Emulator Ordering Information
Clock
(800) NSC-MICRO
(800) 672-6427
The COP8 family is supported by single chip OTP emulators.
For detailed information refer to the emulator specific
datasheet and the emulator selection table below:
Device Number
Parity:
Package
Emulates
COP888CL
Development Support
8-Bit
None
Stop Bit:
Option
Operation:
1
24 Hours, 7 Days
COP87L84CLN-XE
Crystal
28 DIP
COP884CL
COP87L84CLM-XE
Crystal
28 SO
COP884CL
COP87L88CLN-XE
Crystal
40 DIP
COP888CL
ftp nscmicro.nsc.com
COP87L88CLV-XE
Crystal
44 PLCC
COP888CL
user:
anonymous
password:
username @yourhost.site.domain
DIAL-A-HELPER via FTP
INDUSTRY WIDE OTP/EPROM PROGRAMMING
SUPPORT
Programming support, in addition to the MetaLink development tools, is provided by a full range of independent approved vendors to meet the needs from the engineering
laboratory to full production.
DIAL-A-HELPER via a WorldWide Web Browser
ftp://nscmicro.nsc.com
National Semiconductor on the WorldWide Web
See us on the WorldWide Web at: http://www.national.com
AVAILABLE LITERATURE
For more information, please see the COP8 Basic Family
User’s Manual, Literature Number 620895, COP8 Feature
Family User’s Manual, Literature Number 620897 and National’s Family of 8-bit Microcontrollers COP8 Selection
Guide, Literature Number 630009.
CUSTOMER RESPONSE CENTER
Complete product information and technical support is available from National’s customer response centers.
CANADA/U.S.:
Tel:
DIAL-A-HELPER SERVICE
Dial-A-Helper is a service provided by the Microcontroller
Applications group. The Dial-A-Helper is an Electronic Information System that may be accessed as a Bulletin Board
System (BBS) via data modem, as an FTP site on the
Internet via standard FTP client application or as an FTP site
on the Internet using a standard Internet browser such as
Netscape or Mosaic.
The Dial-A-Helper system provides access to an automated
information storage and retrieval system. The system capabilities include a MESSAGE SECTION (electronic mail,
when accessed as a BBS) for communications to and from
the Microcontroller Applications Group and a FILE SECTION
which consists of several file areas where valuable application software and utilities could be found.
EUROPE
37
[email protected]c.com
email:
Deutsch
Tel:
+49 (0) 180-530 85 85
English
Tel:
+49 (0) 180-532 78 32
Francais
Tel:
+49 (0) 180-532 93 58
Italiano
Tel:
+49 (0) 180-534 16 80
Tel:
+81-043-299-2309
Tel:
(+86)10-6856-8601
Shanghai Tel:
(+86)21-6415-4092
Hong
Kong
Tel:
(+852) 2737-1600
Korea
Tel:
(+82) 2-3771-6909
Malaysia
Tel:
(+60-4) 644-9061
JAPAN:
S.E. ASIA:
(800) 272-9959
support @tevm2.nsc.com
email:
Beijing
Singapore Tel:
(+65) 255-2226
Taiwan
Tel:
+886-2-521-3288
AUSTRALIA:
Tel:
(+61) 3-9558-9999
INDIA:
Tel:
(+91) 80-559-9467
www.national.com
COP888CL
Physical Dimensions
inches (millimeters) unless otherwise noted
28-Lead Small Outline Package (M)
Order Number COP684CL-XXX/WM, COP884CL-XXX/WM, COP984CL-XXX/WM or COP984CLH-XXX/WM
NS Package Number M28B
Molded Dual-In-Line Package (N)
Order Number COP684CL-XXX/N, COP884CL-XXX/N, COP984CL-XXX/N or COP984CLH-XXX/N
NS Package Number N28B
www.national.com
38
COP888CL
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package (N)
Order Number COP688CL-XXX/N, COP888CL-XXX/N, COP988CL-XXX/N or COP988CLH-XXX/N
NS Package Number N40A
Plastic Leaded Chip Carrier (V)
Order Number COP688CL-XXX/V, COP888CL-XXX/V, COP988CL-XXX/V, COP988CLH-XXX/V
NS Package Number V44A
39
www.national.com
COP888CL
8-Bit Microcontroller
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Email: [email protected]
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 180-530 85 86
Email: [email protected]
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: [email protected]
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.