e5551 Standard R/W Identification IC with Anticollision Description The e5551 is a contactless R/W-IDentification IC (IDIC)* for general-purpose applications in the 125 kHz range. A single coil, connected to the chip, serves as the IC’s power supply and bidirectional communication interface. Coil and chip together form a transponder. The on-chip 264-bit EEPROM (8 blocks 33 bits each) can be read and written blockwise from a base station. The blocks can be protected against overwriting. One block is reserved for setting the operation modes of the IC. Another block can contain a password to prevent unauthorized writing. Reading occurs by damping the coil by an internal load. There are different bitrates and encoding schemes possible. Writing occurs by interrupting the RF field in a special way. Features D Low-power, low-voltage operation D Anticollision using Answer-On-Request (AOR) D Contactless power supply D Typical < 50 ms to write and verify a block D Contactless read/write data transmission D Radio Frequency (RF): 100 kHz to 150 kHz D 264 bit EEPROM memory in 8 blocks of 33 bits D 224 bits in 7 blocks of 32 bits are free for user data D Block write protection D Extensive protection against contactless malprogramming of the EEPROM D Other options set by EEPROM: Bitrate [bit/s]: RF/8, RF/16, RF/32, RF/40 RF/50, RF/64, RF/100, RF/128 Modulation: BIN, FSK, PSK, Manchester, Biphase Other: Terminator mode, Password mode Base station Data Controller Power Coil interface Transponder Memory e5551 Figure 1. RFID system using e5551 tag Ordering Information * Extended Type Number Package e5551A-DOW e5551A-DIT e5551A-FP008 DOW Dice in tray SO8 Remarks Configuration after production test is an erased memory (’0’) IDIC stands for IDentification Integrated Circuit and is a trademark of Atmel Wireless & Microcontrollers Rev. A3, 04-Oct-00 1 (21) e5551 Pads ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Name Coil1 Coil2 Vdd Vss Test1 Test2 Test3 Pad Window 136 136 mm2 136 136 mm2 78 78 mm2 78 78 mm2 78 78 78 Coil 2 78 mm2 78 mm2 78 mm2 Function 1st coil pad 2nd coil pad Positive supply voltage Negative supply voltage (gnd) Test pad Test pad Test pad 1 8 2 7 Coil 1 The main controller has following functions: D Load mode register with configuration data from EEPROM block 0 after power-on and also during reading D Control memory access (read, write) D Handle write data transmission and the write error modes D The first two bits of the write data stream are the OPcode. There are two valid OP-codes (standard and stop) which are decoded by the controller. D In password mode, the 32 bits received after the OPcode are compared with the stored password in block 7. Bitrate Generator The bitrate generator can deliver the following bitrates: e5551 Note: Controller 3 6 4 5 RF/8 - RF/16 - RF/32 - RF/40 - RF/50 - RF/64 - RF/100 - RF/128 Write Decoder Pins 2 to 7 have to be open. They are not specified for applications Decode the detected gaps during writing. Check if write data stream is valid. Test Logic Test circuitry allows rapid programming and verification of the IC during test. Figure 2. Pinning SO8 HV Generator e5551 Building Blocks Analog Front End (AFE) The AFE includes all circuits which are directly connected to the coil. It generates the IC’s power supply and handles the bidirectional data communication with the reader unit. It consists of the following blocks: Voltage pump which generates [18 V for programming of the EEPROM. Pad Layout Coil 1 D Rectifier to generate a dc supply voltage from the ac coil voltage D Clock extractor D Switchable load between Coil1/ Coil2 for data transmission from the IC to the reader unit (read) D Field gap detector for data transmission from the reader unit into the IC (write) 2 (21) e5551 Coil 2 V DD V SS Test pads Figure 3. Pad layout Rev. A3, 04-Oct-00 e5551 POR Modulator Coil 1 Analog front end Write decoder Mode register Memory (264 bit EEPROM) Bitrate generator Controller Coil 2 Input register Test logic VDD HV generator Test pads VSS Figure 4. Block diagram e5551 Power-On Reset (POR) D Manchester: rising edge = H; falling edge = L The power-on reset is a delay reset which is triggered when supply voltage is applied. D Biphase: every bit creates a change, a data ‘H’ creates an additional mid-bit change Mode Register Note: The following modulation type combinations will not work: The mode register stores the mode data from EEPROM block 0. It is continually refreshed at the start of every block. This increases the reliability of the device (if the originally loaded mode information is false, it will be corrected by subsequent refresh cycles). D Stage1 Manchester or Biphase, stage2 PSK2, at any PSK carrier frequency (because the first stage output frequency is higher than the second stage strobe frequency) Modulator The modulator consists of several data encoders in two stages, which may be freely combined to obtain the desired modulation. The basic types of modulation are: D PSK: phase shift: 1) every change; 2) every ‘1’; 3) every rising edge (carrier: fc/2, fc/4 or fc/8) D FSK: 1) f1 = rf/8 f2 = rf/5; 2) f1 = rf/8, f2 = rf/10 Rev. A3, 04-Oct-00 D Stage1 Manchester or Biphase and stage2 PSK with bitrate = rf/8 and PSK carrier frequency = rf/8 (for the same reason as above) D Any stage1 option with any PSK for bitrates rf/50 or rf/100 if the PSK carrier frequency is not an integer multiple of the bitrate (e.g., br = rf/50, PSKcf = rf/4, because 50/4 = 12.5). This is because the PSK carrier frequency must maintain constant phase with respect to the bit clock. 3 (21) e5551 Memory The memory of the e5551 is a 264 bit EEPROM, which is arranged in 8 blocks of 33 bits each. All 33 bits of a block, including the lock bit, are programmed simultaneously. The programming voltage is generated on-chip. between 0 and 7 (if maxblk=0, only block 0 will be transmitted). Block 0 contains the mode data, which are not normally transmitted (see figure 6). Block 1 to 6 are freely programmable. Block 7 may be used as a password. If password protection is not required, it may be used for user data. Bit 0 of every block is the lock bit for that block. Once locked, the block (including the lockbit itself) cannot be field-reprogrammed. Data from the memory is transmitted serially, starting with block 1, bit 1, up to block ‘MAXBLK’, bit 32. ‘MAXBLK’ is a mode parameter set by the user to a value 0 1 32 Block 7 L L User data or password User data L User data L L User data User data L User data Block 3 Block 2 L User data Block 1 L Configuration data Block 0 Block 6 Block 5 Block 4 32 bits Not transmitted Figure 5. Memory map Carrier frequency PSK1 PSK2 Manchester From memory Direct Biphase PSK3 Mux Direct Mux To load FSK1, 1a FSK2, 2a Figure 6. Modulator block diagram 4 (21) Rev. A3, 04-Oct-00 e5551 0 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 reserved BR [2] [1] [0] lock bit (never transmitted) * ”0” MAXBLK PSKCF MS1 MS2 [1] [0] [2] [1] [0] [1] [0] * res’d [2] [1] [0] *useSTOP ”0” useBT AOR useST usePWD Key: ––––––––––––––––––––––––––––––––––––– AOR Anwer-On-Request BT use Block Terminator ST use Sequence Terminator PWD use Password STOP obey stop header (active low!) BR Bit Rate MS1 Modulator Stage 1 MS2 Modulator Stage 2 PSKCF PSK Clock Frequency MAXBLK see Maxblock feature reserved do not use send blocks: 0 0 0 0 1 1 1 1 * Bit 15 and 24 must always be at ”0”, otherwise malfunction will appear. 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 RF/8 RF/16 RF/32 RF/40 RF/50 RF/64 RF/100 RF/128 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 1 to 2 1 to 3 1 to 4 1 to 5 1 to 6 1 to 7 RF/2 RF/4 RF/8 reserved direct psk1 (phase change when input changes) psk2 (phase change on bitclk if input high) psk3 (phase change on rising edge of input) ––––––––––––––––––––––––––––––––––– o/p freq. DATA=1 DATA=0 fsk1 rf/8 rf/5 fsk2 rf/8 rf/10 fsk1a rf/5 rf/8 fsk2a rf/10 rf/8 direct Manchester Biphase reserved bitrate_8cpb bitrate_16cpb bitrate_32cpb bitrate_40cpb bitrate_50cpb bitrate_64cpb bitrate_100cpb bitrate_128cpb Figure 7. Memory map of block 0 Rev. A3, 04-Oct-00 5 (21) e5551 Operating the e5551 General Read The basic functions of the e5551 are: supply IC from the coil, read data from the EEPROM to the reader, write data into the IC and program these data into the EEPROM. Several errors can be detected to protect the memory from being written with the wrong data (see figure 21). Supply The e5551 is supplied via a tuned LC circuit which is connected to the Coil 1 and Coil 2 pads. The incoming RF (actually a magnetic field) induces a current into the coil. The on-chip rectifier generates the dc supply voltage (VDD, VSS pads). Overvoltage protection prevents the IC from damage due to high-field strengths. Depending on the coil, the open-circuit voltage across the LC circuit can reach more than 100 V. The first occurrence of RF triggers a power-on reset pulse, ensuring a defined start-up state. Reader coil Reading is the default mode after power-on reset. It is done by switching a load between the coil pads on and off. This changes the current through the IC coil, which can be detected from the reader unit. Start-Up The many different modes of the e5551 are activated after the first readout of block 0. The modulation is off while block 0 is read. After this set-up time of 256 field clock periods, modulation with the selected mode starts. Any field gap during this initialization will restart the complete sequence. Read Datastream The first block transmitted is block 1. When the last block is reached, reading restarts with block 1. Block 0, which contains mode data, is normally never transmitted. However, the mode register is continuously refreshed with the contents of EEPROM block 0. Tuned LC Energy IAC 125 kHz e5551 Data Figure 8. Application circuit Damping on Damping off VCoil 1 – Coil 2 v2 ms Power-on reset Loading block 0 (256 FC[2 ms) Read data with configured modulation and bitrate * FC –> Field clocks Figure 9. Voltage at Coil1/Coil2 after power-on 6 (21) Rev. A3, 04-Oct-00 e5551 Bit period Block terminator ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏÏ Data bit ’1’ Last bit Block First bit Sequence terminator Data bit ’1’ Data bit ’1’ Last bit Sequence VCoil 1 – Coil 2 Waveforms for different modulations First bit First bit ’0’ or ’1’ Manchester FSK PSK Terminator not suitable for Biphase modulation Figure 10. Terminators ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏÏÏÏ ÏÏÏ ÏÏÏ ÏÏÏÏÏÏ ST BT off off off on off on ÏÏÏÏÏÏ ÏÏÏÏÏÏ on on Ï ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏ Ï ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏ Ï ÏÏÏÏÏ ÏÏÏÏ ÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏÏÏÏ Ï ÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏ ÏÏÏÏÏÏÏÏ ÏÏÏÏÏ Ï ÏÏ ÏÏÏÏ ÏÏÏÏ Ï ÏÏÏÏÏ Ï ÏÏÏÏÏ Ï ÏÏÏÏÏ Ï ÏÏÏÏÏ Ï ÏÏÏÏÏ Ï Ï ÏÏÏÏÏ Ï ÏÏÏÏÏ Ï ÏÏÏÏÏ Ï ÏÏÏÏÏ Ï ÏÏÏÏÏ Ï Ï ÏÏ ÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏ Ï ÏÏÏÏÏ ÏÏÏÏÏ Ï Ï ÏÏ ÏÏÏÏ ÏÏÏÏÏÏ ÏÏÏÏÏ Ï ÏÏÏÏÏ ÏÏÏÏÏ Ï Ï 0 Block 1 Block 2 Block 7 Block 1 Block 2 Loading block 0 Sequence terminator 0 Block 1 Block 2 Block 7 Block 1 Block 2 Loading block 0 Block terminator 0 Block 1 Block 2 Block 7 Block 1 Block 2 Loading block 0 0 Block 1 Block 2 Block 7 Block 1 Block 2 Loading block 0 Figure 11. Read data streams and terminators MAXBLK = 5 0 Block 1 Block 4 Block 5 Block 1 Block 2 Block 2 Block 1 Block 2 Block 1 Block 0 Block 0 Block 0 Block 0 Loading block 0 MAXBLK = 2 0 Block 1 Loading block 0 MAXBLK = 0 0 Block 0 Loading block 0 Figure 12. MAXBLK examples Rev. A3, 04-Oct-00 7 (21) e5551 Maxblock Feature Direct Access If it is not necessary to read all user data blocks; the MAXBLK field in block 0 can be used to limit the number of blocks read. For example, if MAXBLK = 5, the e5551 repeatedly reads and transmits only blocks 1 to 5 (see figure 11). If MAXBLK is set to ‘0’, block 0 – which is normally not transmitted – can be read. Terminators The terminators are (optionally selectable) special damping patterns, which may be used to synchronize the reader. There are two types available; a block terminator which precedes every block, and a sequence terminator which always follows the last block. The sequence terminator consists of two consecutive block terminators. The terminators may be individually enabled with the mode bits ST (sequence terminator enable) or BT (block terminator enable). Note: It is not possible to include a sequence terminator in a transmission where MAXBLK = 0. The direct access command allows the reading of an individual block by sending the OP-code (’10‘), the lock-bit and the 3-bit address. Note: PWD has to be 0. Modulation and Bitrate There are two modulator stages in the e5551 (see figure 4) whose mode can be selected using the appropriate bits in block 0 (MS1[1:0] and MS[2:0]). Also the bitrate can be selected using BR[2:0] in block 0. These options are described in detail in figures 21 through 26. Anticollision Mode When the AOR bit is set, the IC does not start modulation after loading configuration block 0. It waits for a valid AOR data stream (wake-up command) from the reader before modulation is enabled. The wake-up command consists of the OP-code (’10‘) folowing by a valid password. The IC will remain active until the RF field is turned off or a stop OP-code is received. Table 2. e5551 – modes of operation PWD 1 AOR 1 STOP 0 Behavior of Tag after Reset / POR Anticollision mode: D Modulation starts after wake-up with a matching PWD D Programming needs valid PWD D AOR allows programing with read protection (no read after write) 1 0 0 0 1 0 Password mode: D Modulation starts after reset D Programming needs valid PWD D Modulation starts after wake-up command D Programming with modulation defeat without previous wake-up possible D AOR allows programing with read protection (no read after write) 0 0 0 x 0 1 8 (21) D Modulation starts after reset D Direct access command D Programming without password See corresponding modes above STOP Function STOP OP-code (’11‘) defeats modulation until RF field is turned off STOP OP-code ignored, modulation continues until RF field is turned off Rev. A3, 04-Oct-00 e5551 Modulation on VCoil 1 – Coil 2 Loading block 0 POR No modulation OP-code (’10’) followed by valid password (STOP = 0, AOR = 1) Figure 13. Answer-on-request (AOR) mode BASE station TAG init tags with AOR = ’1’, PWD = ’1’, Stop = ’0’ Field OFF –> ON wait for t W > 2.5ms POWER ON RESET read configuration wait for OPCODE + PWD (== wake up command) ”select single tag” send OPCODE + PWD (== wake up command) write damping NO PWD correct ? YES decode data send block 1...MAXBLK until STOP command send stop command enter AOR mode internal reset sequence NO all tags read ? YES EXIT Figure 14. Anticollision procedure Rev. A3, 04-Oct-00 9 (21) e5551 >64 FCs = stop write RF_Field 1 Start Gap 0 1 1 0 Write mode Modulation during read mode Damping Load Off Load On Write data Data Clock Field clock Read mode Writing Programming Read mode Figure 15. Signals during writing 1 16 fail Write data decoder 32 0 48 fail 64 1 writing done Figure 16. Write data decoding schemes Standard write OP 10 L OP Password mode 10 1 1 Data bits Password OP AOR (wake-up command) 10 1 Password OP 10 L 2 Addr 0 Direct access Stop command 32 2 Addr 0 32 L 1 Data bits 32 2 Addr 0 32 OP 11 Figure 17. e5551 – OP-code formats Write Start Gap Writing data into the IC occurs via the Atmel Wireless & Microcontrollers’ write method. It is based on interrupting the RF field with short gaps. The time between two gaps encodes the ‘0/1’ information to be transmitted. The first gap is the start gap which triggers write mode. In write mode, the damping is permanently enabled which eases gap detection. The start gap may need to be longer than subsequent gaps in order to be detected reliably. A start gap will be detected at any time after block 0 has been read (field-on plus approximately 2 ms). 10 (21) Rev. A3, 04-Oct-00 e5551 Read mode Write mode RF Start of writing (start gap) a steady RF field where single transponders are collected one by one. Each IC is read and than disabled, so that it does not interfere with the next IC. Note: The STOP OP-code should contain only the two OP-code bits to disable the IC. Any additional data sent will not be ignored, and the IC will not stop modulation. Standard OP-code Figure 18. Start of writing Decoder The duration of the gaps is usually 50 to 150 µs. The time between two gaps is nominally 24 field clocks for a ‘0’ and 56 field clocks for a ‘1’. When there is no gap for more than 64 field clocks after previous gap, the IDIC exits write mode; it starts with programming if the correct number of valid bits were received. If there is a gap fail – i.e., one or more of the intervals did represent not a valid ‘0’ or ‘1’ – the IC does not program, but enters read mode beginning with block 1, bit 1. 1 0 more data ... Start gap Stop OP-code 1 Read mode 1 > 64 clocks Write mode Figure 19. OP-code transmission Writing Data into the e5551 The e5551 expects a two bit OP-code first. There are two valid OP-codes (’10‘ and ’11‘). If the OP-code is invalid, the e5551 starts read mode beginning with block 1 after the last gap. The OP-code (’10‘) is followed by different information (see figure 16): D Standard writing needs the OP-code, the lock bit, the 32 data bits and the 3-bit block address. D Writing with usePWD set requires a valid password between OP-code and address/data bits. D In AOR mode with usePWD, OP-code and a valid password are necessary to enable modulation. D The STOP OP-code is used to silence the e5551 (disable damping until power is cycled). Note: The data bits are read in the same order as written. STOP OP-Code The STOP OP-code (‘11’) is used to stop modulation until a power-on reset occurs. This feature can be used to have Rev. A3, 04-Oct-00 Password When password mode is on (usePWD = 1), the first 32 bits after the OP-Code are regarded as the password. They are compared bit-by-bit with the contents of block 7, starting at bit 1. If the comparison fails, the IC will not program the memory, but restart in read mode at block 1 once writing has completed. Notes: D If PWD is not set, but the IC receives a write datastream containing any 32 bits in place of a password, the IC will enter programming mode. D In password mode, MAXBLK should be set to a value below 7 to prevent the password from being transmitted by the e5551. D Every transmission of 2 OP-code bits, 32 password bits, one lock bit, 32 data bits and 3 address bits (= 70 bits) needs about 35 ms. Testing all 232 possible combinations (about 4.3 billion) takes about 40,000 h, or over four years. This is a sufficient password protection for a general-purpose IDIC. 11 (21) e5551 Writing done (> 64 clocks since last gap) Write mode Programming ends 16 ms Check V pp 0.12 ms Programming starts (HV at EEPROMs) HV on HV on for testing if Vpp is ok Modulation Reading starts No modulation Write Operation Vpp/Lock ok? Program EEPROM READ Figure 20. Programming VCoil 1 – Coil 2 16 ms Programming Read programming block (= block 0) Read next block with updated modes (e.g., new bitrate) Write data into the IC Figure 21. Coil voltage after programming of block 0 Programming Errors During Writing When all necessary information has been written to the e5551, programming may proceed. There is a 32-clock delay between the end of writing and the start of programming. During this time, Vpp – the EEPROM programming voltage – is measured and the lock bit for the block to be programmed is examined. Further, Vpp is continually monitored throughout the programming cycle. If at any time Vpp is too low, the chip enters read mode immediately. There are four detectable errors which could occur during writing data into the e5551: The programming time is 16 ms. After programming is done, the e5551 enters read mode, starting with the block just programmed. If either block or sequence terminators are enabled, the block is preceded by a block terminator. If the mode register (block 0) has been reprogrammed, the new mode will be activated after the just-programmed block has been transmitted using the previous mode. Error Handling Several error conditions can be detected to ensure that only valid bits are programmed into the EEPROM. There are two error types which lead to different actions. 12 (21) D Wrong number of field clocks between two gaps D The OP-code is neither the standard OP-code (’10‘) nor the stop OP-code (’11‘) D Password mode is active but the password does not match the contents of block 7 D The number of bits received is incorrect; valid bit counts are D Standard write 38 bits (PWD not set) D Password write 70 bits (PWD set) D AOR wake-up 34 bits D Stop command 2 bits If any of these four conditions are detected, the IC starts read mode immediately after leaving write mode. Reading starts with block 1. Rev. A3, 04-Oct-00 e5551 Errors During Programming If writing was successful, the following errors could prevent programming: D The lock bit of the addressed block is set D VPP is too low In these cases, programming stops immediately. The IC reverts to read mode, starting with the currently addressed block. Power-on reset Loading block 0 READ Stop Write mode 11 OP-code addr+1 addr+current fail ok 10 Password fail ok Number of bits ok Lock bit ok HV fail fail fail ok PROGRAM fail ok Figure 22. Functional diagram of the e5551 Rev. A3, 04-Oct-00 13 (21) 0 8 FC 0 1 1 e5551 Figure 23. Example of Manchester coding with data rate RF/16 14 (21) 1 Data rate = 50 Field Clocks (FC) 0 8 FC Data stream Inverted modulator signal Manchester coded 9 1 2 16 1 8 8 1 9 8 16 9 16 1 16 8 9 1 2 16 1 8 8 9 16 RF-field Rev. A3, 04-Oct-00 Figure 24. Example of Biphase coding with data rate RF/16 1 0 Data rate = 50 Field Clocks (FC) 8 FC 0 1 1 0 8 FC Data stream Inverted modulator signal Biphase coded 1 2 8 1 9 RF-field 16 8 9 16 1 1 8 16 8 1 2 9 16 1 8 9 16 8 9 16 Figure 25. Example of FSK coding with data rate RF/40, subcarrier f0 = RF/8, f1 = RF/5 Rev. A3, 04-Oct-00 1 0 Data rate= 40 Field Clocks (FC) 0 1 1 0 Data stream Inverted modulator signal f0= RF/8, f 1= RF/5 1 5 1 8 1 8 1 5 1 5 1 8 RF-field 8 FC 0 1 1 0 8 FC Data stream Inverted modulator signal subcarrier RF/2 1 2 RF-field 8 9 16 1 8 16 1 8 16 1 8 16 1 8 16 1 8 e5551 15 (21) Figure 26. Example of PSK1 coding with data rate RF/16 0 1 Data rate = 16 Field Clocks (FC) 0 8 FC 0 1 1 0 8 FC Datas stream Inverted modulator signal subcarrier RF/2 1 2 8 9 16 1 8 16 1 8 16 1 8 16 1 8 16 1 8 RF-field Rev. A3, 04-Oct-00 Figure 28. Example of PSK3 coding with data rate RF/16 1 0 Data rate = 16 Field Clocks (FC) 8 FC 0 1 1 0 8 FC Data stream Inverted modulator signal sub carrier RF/2 1 2 RF-field 8 9 16 1 8 16 1 8 16 1 8 16 1 8 16 1 8 e5551 Figure 27. Example of PSK2 coding with data rate RF/16 16 (21) 1 Data rate = 16 Field Clocks (FC) e5551 IDD 100 W VDD Coil 1 Coil 1 ~ ~2V = Mod 2V Coil 2 Coil 2 VSS 100 W ~2V Vpp Coil ≅ 1.5 V Figure 29. Measurement setup for IDD Figure 30. Simplified damping circuit Application Example From oscillator IAC 740 µH 4.2 mH 360 pF Energy 125 kHz Input capacitance 5 pF static, 25 pF dynamic Coil 1 (Pin 8) e5551 Coil 2 (Pin 1) Data To read amplifier fres + 2.2 nF 1 + 125 kHz 2p ǸLC Figure 31. Typical application circuit Rev. A3, 04-Oct-00 17 (21) e5551 Absolute Maximum Ratings Parameters Symbol Value Unit Icoil 10 mA icoil pp 20 mA Ptot 100 mW Electro-static discharge maximum to MIL-Standard 883 C method 3015 Vmax 2000 V Operating ambient temperature range Tamb –40 to +85 °C Tstg –40 to +125 °C Tsld +150 °C Maximum DC current into Coil 1/ Coil 2 Maximum AC current into Coil 1/ Coil 2, f = 125 kHz Power dissipation (dice) 1) Storage temperature range 2) Maximum assembly temperature for less than 5 min Notes: 1) 2) 3) 3) Free-air condition, time of application: 1 s Data retention reduced Assembly temperature of 150°C for less than 5 minutes does not affect the data retention. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Operating Characteristics Tamb = 25°C; fRF = 125 kHz, reference terminal is VSS ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ ÁÁÁÁ ÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁ Parameters Comments Symbol Min. Typ. Max. Unit fRF 100 125 150 kHz IDD 5 7.5 µA Programming over the full temperature range IDD 100 200 µA Clamp voltage 10 mA current into Coil1/2 Vcl 9.5 11.5 V Programming voltage From on-chip HVGenerator Vpp 16 20 V RF frequency range Supply current (see figure 27) Read and write over the full temperature range Programming time tP Startup time 18 tstartup ms 4 ms Data retention 1) tretention 10 Programming cycles 1) ncycle 100 000 Supply voltage Read and write VDD 1.6 V Supply voltage Read-mode, T = – 30°C VDD 2.0 V Coil voltage Read and write Vcoil pp 6.0 V Coil voltage Programming, RF field not damped Vcoil pp 10 V Damping resistor Note 1) 18 (21) RD Years 300 W Since EEPROM performance may be influenced by assembly and packaging, we can confirm the parameters for dow (= die-on-wafer) and ICs assembled in standard package. Rev. A3, 04-Oct-00 e5551 Chip Dimensions (mm) Rev. A3, 04-Oct-00 19 (21) e5551 Package Information Package SO8 Dimensions in mm 5.2 4.8 5.00 4.85 3.7 1.4 0.25 0.10 0.4 1.27 6.15 5.85 3.81 8 0.2 3.8 5 technical drawings according to DIN specifications 1 20 (21) 4 Rev. A3, 04-Oct-00 e5551 Ozone Depleting Substances Policy Statement It is the policy of Atmel Germany GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Atmel Germany GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Atmel Germany GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. 4. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Atmel Wireless & Microcontrollers products for any unintended or unauthorized application, the buyer shall indemnify Atmel Wireless & Microcontrollers against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Data sheets can also be retrieved from the Internet: http://www.atmel–wm.com Atmel Germany GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2594, Fax number: 49 (0)7131 67 2423 Rev. A3, 04-Oct-00 21 (21)