ETC EM78450

EM78450
MASK ROM
1. GENERAL DESCRIPTION
The EM78450 is an 8-bit microprocessor developed with low-power, high speed CMOS technology.
Integrated into a single chip, are on-chip watchdog timer (WDT), RAM, ROM, real time clock/counter,
power down mode, and bi-directional tri-state I/O ports. It is most suited for keyboard encoder
development and other related applications.
This specification is subject to change without prior notice.
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EM78450
MASK ROM
2. FEATURE
• Operating voltage range: 2.3V~4V, 4V ~ 5.5V option by code.
• Operating temperature range: 0°C ~ 70°C.
• Operating frequency range (base on 2 clocks ):
* Crystal Type : DC ~ 20MHz at 5V, DC ~ 8MHz at 3V and DC ~ 4MHz at 2.3V.
* RC Type : DC ~ 4MHz at 5V, DC ~ 4MHz at 3V and DC ~ 4MHz at 2.3V.
• Low power consumption:
* Less then 3 mA at 5V/4MHz
* Typically 10 µA during sleep mode
• 4K x 13 on chip ROM.
• 11 special function registers.
• 146 × 8 on chip general purpose registers.
• 5 bi-directional I/O ports (35 I/O pins).
• 3 LED direct sink pins with internal serial resistor, option by code.
• One interrupt pin available.
• Built-in RC oscillator with external serial resistor, ±10% variation.
• Built-in power on reset.
• 5 level stacks for subroutine nesting.
• 8-bit real time clock/counter (TCC) with overflow interrupt.
• Options for two oscillator cycle or four oscillator cycle per instruction.
• Power down mode.
• Programmable wake up from sleep circuit on I/O ports.
• Programmable free running on-chip watchdog timer.
• 12 wake-up pins.
• 2 open-drain pins.
• 2 R-option pins.
• Two types of interrupts:
* External interrupt (/INT).
* TCC overflow interrupt.
• Package:
* 40 pins DIP 600mil: EM78450P
This specification is subject to change without prior notice.
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MASK ROM
3. PIN ASSIGNMENT
1
40
OSCO
INT
2
39
R-OSCI
DATA
3
38
VDD
CLK
4
37
P70
P90
5
36
P71
P91
6
35
P72
P92
7
34
P67
P93
8
33
P66
P94
9
32
P65
P95
10
31
P64
P50
11
30
P63
P51
12
29
P62
P52
13
28
P61
P53
14
27
P60
P54
15
26
P87
P55
16
25
P86
P56
17
24
P85
P57
18
23
P84
P80
19
22
P83
P81
20
21
P82
EM78450P
VSS
Fig. 1 Pin Assignment
Table 1 Pin Description – EM78450
Symbol
Type
Function Description
R-OSCI
I
XTAL Type: Crystal input; In internal C, external R mode: 56K ohm±5% pull high for
1.8432MHz.
OSCO
O
XTAL Type: Crystal output; In RC mode: Instruction clock output.
P90~P95
I/O
P80~P87
I/O
P70~P72
I/O
CLK
I/O
DATA
I/O
P60~P67
I/O
P50~P57
I/O
VDD
-
General bi-directional I/O port. All of its pins can be pulled-high by software. P90 and
P91 are pin-change wake up pins.
General bi-directional I/O port. All of its pins can be pulled-high by software. P80 and
P81 are also used as the R-option pins.
3 LED direct-driving pins with internal serial resistor used as output and is software
defined.
By connecting P74 and P76 together. P74 can be pulled-high by software and it is
also a pin-change wake up pin. P76 can be defined as an open-drain output.
By connecting P75 and P77 together. P75 can be pulled-high by software and it is
also a pin-change wake up pin. P77 can be defined as an open-drain output.
General bi-directional port. All of its pins can be pulled-high in software, and
pin-change wake up pins.
General bi-directional I/O port. All of its pins can be pulled-high by software.
Power supply pin.
This specification is subject to change without prior notice.
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EM78450
MASK ROM
VSS
-
Ground pin.
/INT
I
An interrupt schmitt-triggered pin. The function of interrupts triggers at the falling
edge. Users can enable it by software. The internal pull-up resistor is around 50K
ohms.
This specification is subject to change without prior notice.
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MASK ROM
4. FUNCTION DESCRIPTION
WDT Timer
WDT
Time-out
STACK 1
P C
Prescaler
STACK 2
STACK 3
Oscillator/
/ INT
Timming
STACK 4
ROM
STACK 5
Control
Interrupt
Instruction
Control
Register
R1(TCC)
ALU
Instruction
Sleep
RAM
&
Decoder
R3
Wake Up
Control
ACC
R4
DATA & CONTROL BUS
IOC5
R5
IOC6
R6
P PPPPP PP
5 5 5 5 5 5 5 5
PPPP PPPP
6 6 6 6 6 6 6 6
P
7
P
7
P
7
PPPP PPPP
8 8 8 8 8 8 8 8
0 1 2 3
0 1 2 3
0
1
2
0 1 2 3
4
5 6 7
4
IOC7
R7
5 6 7
IOC8
R8
4
5 6 7
IOC9
R 9
P P P P P P
9 9 9 9 9 5
0 1 2 3 4 5
Fig. 2 Functional Block Diagram
4.1 Operational Registers
1. R0 (Indirect Address Register)
R0 is not a physically implemented register. It is used as indirect addressing pointer. Any instruction
using R0 as register actually accesses data pointed by the RAM Select Register (R4).
2. R1 (TCC)
• Increased by the instruction cycle clock.
• Written and read by the program as any other register.
3. R2 (Program Counter) & Stack
• Depending on the device type, R2 and hardware stack are 12 bits wide. The structure is depicted in
Fig. 3.
• Generates 4K× 13 on-chip ROM addresses to the relative programming instruction codes. One
program page is 1K words long.
• R2 is set as all “1”s when under RESET condition.
This specification is subject to change without prior notice.
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MASK ROM
• ”JMP” instruction allows direct loading of the lower 10 program counter bits. Thus, JMP” allows jump
to any location on one page.
• “CALL” instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus,
the subroutine entry address can be located anywhere within a page.
• “RET” (“RETL k”, “RETI”) instruction loads the program counter with the contents at the top of stack.
• “MOV R2,A” allows the loading of an address from the “A” register to the lower 8 bits of PC, and the
ninth and tenth bits (A8~A9) of PC are cleared.
• “ADD R2,A” allows a relative address be added to the current PC, and the ninth and tenth bits of PC
are cleared.
• Any instruction that is written to R2 (e.g. “ADD R2,A”, “MOV R2,A”, “BC R2,6”,⋅⋅⋅⋅×) (except “TBL”)
will cause the ninth and tenth bits (A8~A9) of PC to be cleared. Thus, the computed jump is limited
to the first 256 locations of any program page.
• “TBL” allows a relative address be added to the current PC (R2+Α ®R2), and contents of the ninth
and tenth bits (A8~A9) of PC are not changed. Thus, the computed jump can be on the second (or
third, 4th) 256 locations on one program page.
• In case of EM78450, the most significant bits (A10~A11) will be loaded with the contents of bits
PS0~PS1 in the status register (R3) upon the execution of a “JMP”, “CALL”, or any instructions
which writes to R2.
• All instructions are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would
change the contents R2. Such instruction will need one more instruction cycle.
CALL
PC
A11A10
00
01
10
11
A9A8
A7
~
A0
Stack 1
RET
Stack 2
RETL
Stack 3
RETI
Stack 4
Stack 5
000
3FF
Page 0
400
7FF
Page 1
002: Software interrupt (INT
instruction) location
800
BFF
Page 2
FFF:Reset location
C00
FFF
Page 3
001:Hareware interrupt location
Fig. 3 Program Counter Organization
This specification is subject to change without prior notice.
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MASK ROM
4. R3 (Status Register)
7
GP
6
PS1
5
PS0
4
T
3
P
2
Z
1
DC
0
C
• Bit 0 (C) Carry flag
• Bit 1 (DC) Auxiliary carry flag
• Bit 2 (Z) Zero flag. Set to “1” if the result of an arithmetic or logic operation is zero.
• Bit 3 (P) Power down bit. Set to 1 during power on or by a “WDTC” command and reset to 0 by a
“SLEP” command.
• Bit 4 (T) Time-out bit. Set to 1 with the “SLEP” and “WDTC” commands, or during power up and
reset to 0 with WDT timeout.
• Bit 5 (PS0)~6 (PS1) Page select bits. PS0~PS1 are used to preselect a program memory page.
When executing a “JMP”, “CALL”, or other instructions which causes the program counter to be
changed (e.g., MOV R2,A), PS0~PS1 are loaded into the 11th and 12th bits of the program counter
where it selects one of the available program memory pages. Note that RET (RETL, RETI)
instruction does not change the PS0~PS1 bits. That is, the return will always be to the page from
where the subroutine was called, regardless of the current setting of PS0~PS1 bits.
PS1
PS0
Program memory page [Address]
0
0
Page 0 [000-3FF]
0
1
Page 1 [400-7FF]
1
0
Page 2 [800-BFF]
1
1
Page 3 [C00-FFF]
• Bit 7 (GP) General read/write bit.
5. R4 (RAM Select Register)
• Bits 0~5 are used to select the registers (address: 00~3F) in the indirect addressing mode.
• Bits 6~7 determine which bank is activated among the 4 banks.
• If no indirect addressing is used, the RSR is used as an 8-bit wide general purpose read/write
register.
• See the configuration of the data memory in Fig. 4.
6. R5~R8 (Port 5 ~ Port8)
• Four 8-bit I/O registers, P74 and P76 read/write data from DATA pin. P75 and P77 read/write data
from CLK pin.
7. R9 (Port 9)
• 6-bit I/O registers. The upper 2 bits of R9 are fixed "0".
This specification is subject to change without prior notice.
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EM78450
MASK ROM
00
R0
01
R1 (TCC)
02
R2 (PC)
STACK 0
03
R3 (Status)
STACK 1
04
R4 (RSR)
STACK 2
05
R5 (Port 5)
STACK 3
IOC5
06
R6 (Port 6)
STACK 4
IOC6
07
R7 (Port 7)
IOC7
08
R8 (Port 8)
IOC8
09
R9 (Port 9)
IOC9
0A
RA
0B
RB
0C
RC
0D
RD
IOCD
0E
RE
IOCE
0F
RF
IOCF
10
11
16 x8
Common
Register
1E
1F
00
01
10
11
31 x8
Bank
Register
31 x8
Bank
Register
31 x8
Bank
Register
31 x8
Bank
Register
(Bank 0)
(Bank 1)
(Bank 2)
(Bank 3)
20
21
3E
3F
R3F
Fig. 4 Data Memory Configuration
This specification is subject to change without prior notice.
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EM78450
MASK ROM
8. RA ~ R1F, R20~R3E (General Purpose Register)
• RA~R1F and R20~R3E (including Banks 0~3) are general-purpose registers.
9. R3F (Interrupt Status Register)
7
6
5
4
-
-
-
-
3
2
1
0
EXIF
TCIF
• Bit 0 (TCIF) TCC timer overflow interrupt flag. Set when TCC timer overflows, reset by software.
• Bit 1 (EXIF) External interrupt flag. Set by falling edge on /INT pin, reset by software.
• Bits 2~~7 Not used.
• “1” means interrupt request, “0” means non-interrupt.
• R3F can be cleared by instruction and cannot be set by instruction.
• IOCF is the interrupt mask register.
• Note that reading R3F by instruction will result to “logic AND” of R3F and IOCF.
4.2 Special Purpose Registers
1. A (Accumulator)
• Internal data transfer, or instruction operand holding.
• It is a non-addressable register.
2. CONT (Control Register)
7
6
5
4
3
2
1
0
/PHEN
/INT
-
-
PAB
PSR2
PSR1
PSR0
• Bit 0 (PSR0)~Bit 2 (PSR2) TCC/WDT prescaler bits.
PSR2
PSR1
PSR0
TCC Rate WDT Rate
0
0
0
1:2
1:1
0
0
1
1:4
1:2
0
1
0
1:8
1:4
0
1
1
1:16
1:8
1
0
0
1:32
1:16
1
0
1
1:64
1:32
1
1
0
1:128
1:64
1
1
1
1:256
1:128
• Bit 3 (PAB) Prescaler assignment bit.
0: TCC
1: WDT
• Bit 6 (INT) Interrupt enable flag which cannot be written by CONTW instruction.
This specification is subject to change without prior notice.
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MASK ROM
0: interrupt masked by DISI.
1: interrupt enabled by ENI/RETI instruction.
• Bit 7 (/PHEN) I/O pin pull-high enable flag.
0: P60~P67, P74~P75, and P90~P95 have internal pull-high.
1: pull-high is disabled.
• Bits 0~3, 7 of CONT registers are both readable and writable.
• Bit 4,5
Not used.
3. IOC5 ~ IOC9 (I/O Port Control Register)
• “1” put the relative I/O pin into high impedance, while “0” put the relative I/O pin as output.
• IOC5 ~ IOC9 are five I/O direction control registers. Both P74 with P76 and P75 with P77 should not
be defined as output pins at same time. Only the lower 6 bits of IOC9 are used.
4. IOCD (Pull-high Control Register)
7
S7
6
-
5
-
4
-
3
/PU9
2
/PU8
1
/PU6
0
/PU5
• PU5, PU6, PU8, PU9 Default = 1, Disable pull high.
• PU6 and PU9 are "AND" gating with PHEN, when each one is set to "0," pull high is enabled.
• S7 selects P70~P72 driving ability.
0 : Normal output.
1 : LEDs Driver.
5. IOCE (WDT Control Register)
7
-
6
ODE
5
WDTE
4
SLPC
3
ROC
2
-
1
-
0
/WUE
• Bit 0 (WUE) Control bit used to enable wake-up function of P60~P67, P74~P75, P90~P91.
0: Enable wake-up function
1: Disable wake-up function
WUE bit is readable and writable.
• Bit 3 (ROC) ROC is used for the R-option. Setting ROC to “1” will enable the status of R-option pin
(P80, P81) to be read by the controller. Clearing ROC will disable the R-option function. If the
R-option function is used, the user must connect the P81 pin or/and P80 pin to VSS by a
560ΚΩ external resistor (Rex). If Rex is connected/disconnected, the status of P80(P81) will be
read as “0”/“1” when ROC is set to “1” (refer to Fig. 7(b)). ROC bit is readable and writable.
• Bit 4 (SLPC) This bit is set by hardware at the falling edge of wake-up signal and is cleared by
software. SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator is
stopped, the controller enters the SLEEP2 MODE) on high-to-low transition of SLPC bit and is
This specification is subject to change without prior notice.
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MASK ROM
enabled (the controller is awakened from SLEEP2 MODE) on low-to-high transition of SLPC bit. In
order to ensure the stable output of the oscillator, once the oscillator is disabled and is enabled
again, there should be a delay of approximately 18 ms (oscillator start-up timer, (OST)) before the
next program instruction is executed. The OST is always activated by wake-up from sleep mode,
whether the Code Option bit ENWDT is “0” or not. After waking up, the WDT is enabled if Code
Option ENWDT is “1”. The block diagram of SLEEP2 MODE and wake-up caused by input triggered
is depicted in Fig. 5. SLPC bit is readable and writable.
• Bit 5 (WDTE) Control bit used to enable Watchdog timer. WDTE bit is used only if the CODE Option
bit ENWDT is “1”. If ENWDT bit is “1”, then WDT is disabled/enabled by WDTE bit.
0: Disable WDT
1: Enable WDT
WDTE bit is not used if the CODE Option bit ENWDT is “0”. That is, if ENWDT bit is “0”, WDT is
always disabled no matter what the WDTE bit is. WDTE bit is readable and writable.
• Bit 6 (ODE) Open-drain control bit.
0: Both P76 and P77 are normal I/O pins.
1: Both P76 and P77 pins have open-drain output, but built-in internally.
ODE bit is readable and writable.
• Bits 1,2,7 Not used.
This specification is subject to change without prior notice.
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MASK ROM
/WUE
Oscillator
Enable
Disable
/WUE
Reset
Q
Q
P D
R
CLK
C
L
VCC
Clear
Set
/WUE
8
from S/W
P60~P67
VCC
/WUE
/PHEN
4
P74~P75, P90~P91
Fig. 5 Block Diagram of Sleep Mode and Wake-up Circuits on I/O Ports
6. IOCF (Interrupt Mask Register)
7
6
5
4
-
-
-
-
3
2
1
0
EXIE
TCIE
• Bit 0(TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt.
1: enable TCIF interrupt.
• Bit 1 (EXIE) EXIF interrupt enable bit
This specification is subject to change without prior notice.
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MASK ROM
0: disable EXIF interrupt.
1: enable EXIF interrupt.
• Bits 2~7 Not used.
• Individual interrupt is enabled by setting its associated control bit in IOCF to “1”.
• IOCF Register is readable and writable.
4.3 TCC/WDT Prescaler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available for either the
TCC or WDT only at any given time, and the PAB bit of CONT register is used to determine the
prescaler assignment. The PSR0~PSR2 bits determine the prescale ratio. The prescaler is cleared
each time the instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to
WDT mode, are cleared by the WDTC or SLEP instructions. Fig. 6 depicts the circuit diagram of
TCC/WDT.
• R1(TCC) is an 8-bit timer/counter. TCC will increase by one at every instruction cycle (without
prescaler).
• The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even when the
oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a
WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any
time during the normal mode by software programming (if Code Option bit ENWDT is “1”). Refer to
WDTE bit of IOCE register. Without presacler, the WDT time-out period is approximately 18 ms 1.
4.4 I/O Ports
The I/O registers, Port 5 ~ Port 9, are bi-directional tri-state I/O ports. P60~P67, P74~P75, and
P90~P91 provide internal pull-high and wake-up function through software control. P76~P77 can have
open-drain output by software control. P80~P81 are the R-option pins which are enabled by software.
When R-option function is used, it is recommended that P80~P81 are used as output pins. When
R-option is enabled, P80~P81 must be programmed as input pins. If external resistor is connected to
P80 (P81) for R-option function, the current consumption should be taken as an important factor in the
applications for low power consideration.
The I/O ports can be defined as “input” or “output” pins by the I/O control registers (IOC5~IOC9) under
1
Note: VDD=5V, setup time period = 16.5ms±5%
VDD=3V, setup time period = 18ms±5%
This specification is subject to change without prior notice.
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MASK ROM
program control. The I/O registers and I/O control registers are both readable and writable. The I/O
interface circuit is shown in Fig. 7. Note that the reading path source of input and output pins is different
when reading the I/O port.
Data Bus
CLK(=Fosc/2)
1
M
U
X
SYNC
TCC(R1)
2 cycles
0
TCC overflow interrupt
PAB
0
WDT
1
M
U
X
8- b i t C o u n t e r
PSR0~PSR2
8 - to - 1 MUX
0
WDTE
1
MUX
PAB
(in IOCE)
WDT timeout
Fig. 6 Block diagram of TCC WDT
This specification is subject to change without prior notice.
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MASK ROM
PCRD
Q
P
D
R
Q
C
PCWR
CLK
L
IOD
PORT
Q
Q
0
1
P
D
R
C CLK
PDWR
L
M
U
X
PDRD
Fig. 7 (a) The Circuit of I/O Port and I/O Control Register
PCRD
VCC
ROC
Q
Weakly
Pull u
-p
P
D
R
Q
C
CLK
PCWR
L
IOD
Q
PORT
P
D
R
C CLK
Q
0
Rex*
1
PDWR
L
M
U
X
PDRD
*The Rex is 560K ohm external resistor
Fig.7(b) The Circuit of I/O Port with R-option (P80,P81)
This specification is subject to change without prior notice.
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MASK ROM
VDD
D
Oscillator
Q
CLK
CLK
CLR
Power-on
Reset
Voltage
Detector
WDTE
Setup
Time
WDT timeout
WDT
Reset
Fig. 8 Block Diagram of Reset of Controller
4.5 Reset and Wake-up
A RESET is initiated by
(1) Power on reset, or
(2) WDT timeout. (if enabled)
The device is kept in a RESET condition for a period of approx. 18ms (one oscillator start-up timer
period) after the reset is detected. Once the RESET occurs, the following functions are performed.
• The oscillator is running, or will be started.
• The Program Counter (R2) is set to all “1’’.
• When power is switched on, the upper 2 bits of R4 are cleared.
• All I/O port pins are configured as input mode (high-impedance state).
• The Watchdog timer and prescaler are cleared.
• The Watchdog timer is enabled if Code Option bit ENWDT is “1’’.
• The CONT register is set to all “1” except bit 6 (INT flag).
• Bits 3,6 of IOCE register are cleared, bits 0,4~5 of IOCE register are set to “1’’.
• Bits 0 of R3F and bits 0 of IOCF registers are cleared.
The sleep mode (power down) is attained by executing the SLEP instruction (designated as SLEEP1
MODE). While entering into sleep mode, the WDT (if enabled) is cleared but keeps on running. The
This specification is subject to change without prior notice.
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controller is awakened by WDT timeout (if enabled), and it will cause the controller to reset. The T and P
flags of R3 are used to determine the source of the reset (wake-up).
In addition to the basic SLEEP1 MODE, EM78450 has another sleep mode (caused by clearing “SLPC”
bit of IOCE register, designated as SLEEP2 MODE). In the SLEEP2 MODE, the controller can be
awakened by(a) Any one of the wake-up pins is set to “0.” (refer to Figure 9). Upon waking, the controller will
continue to execute the program in-line. In this case, before entering SLEEP2 MODE, the wake-up
function of the trigger sources (P60~P67, P74~P75, and P90~P91) should be selected (e.g. input
pin) and enabled (e.g. pull-high, wake-up control). One caution should be noted is that after waking
up, the WDT is enabled if Code Option bit ENWDT is “1”. The WDT operation (to be enabled or
disabled) should be appropriately controlled by software after waking up.
(b) WDT time-out (if enabled). On wake-up, will cause the controller to reset.
Table 2 The Summary of the Initialized Values for Registers
Address
Name
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
C57
C56
C55
C54
C53
C52
C51
C50
N/A
IOC5
N/A
IOC6
N/A
IOC7
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
1
1
P
C67
1
1
P
C77
1
1
P
1
1
P
C66
1
1
P
C76
1
1
P
1
1
P
C65
1
1
P
C75
1
1
P
1
1
P
C64
1
1
P
C74
1
1
P
1
1
P
C63
1
1
P
C73
1
1
P
1
1
P
C62
1
1
P
C72
1
1
P
1
1
P
C61
1
1
P
C71
1
1
P
1
1
P
C60
1
1
P
C70
1
1
P
Bit Name
C87
C86
C85
C84
C83
C82
C81
C80
Power-On
/RESET and WDT
Wake-Up from Pin Change
1
1
P
1
1
P
1
1
P
1
1
P
1
1
P
1
1
P
1
1
P
1
1
P
Bit Name
C97
C96
C95
C94
C93
C92
C91
C90
1
1
P
/INT
1
1
P
U
1
1
P
1
1
P
U
1
1
P
1
1
P
U
1
1
P
PAB
1
1
P
U
N/A
IOC8
N/A
IOC9
N/A
CONT
0x00
R0(IAR)
Power-On
1
/RESET and WDT
1
Wake-Up from Pin Change
P
Bit Name
/PHEN
Power-On
1
/RESET and WDT
1
Wake-Up from Pin Change
P
Bit Name
Power-On
U
This specification is subject to change without prior notice.
17
1
1
1
1
1
1
P
P
P
PSR2 PSR1 PSR0
1
1
1
1
1
1
P
P
P
U
U
U
2002/03/01
EM78450
MASK ROM
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x3F
0x0D
0x0E
/RESET and WDT
P
P
P
Wake-Up from Pin Change
P
P
P
Bit Name
Power-On
0
0
0
R1(TCC)
/RESET and WDT
0
0
0
Wake-Up from Pin Change
P
P
P
Bit Name
Power-On
1
1
1
R2(PC)
/RESET and WDT
1
1
1
Wake-Up from Pin Change
**P
**P
**P
Bit Name
GP
PS1
PS0
Power-On
0
0
0
R3(SR)
/RESET and WDT
0
0
0
Wake-Up from Pin Change
P
P
P
Bit Name
RSR.1 RSR.0
Power-On
0
0
0
R4(RSR)
/RESET and WDT
0
0
0
Wake-Up from Pin Change
P
P
P
Bit Name
P57
P56
P55
Power-On
U
U
U
R5(P5)
/RESET and WDT
P
P
P
Wake-Up from Pin Change
P
P
P
Bit Name
P67
P66
P65
Power-On
U
U
U
R6(P6)
/RESET and WDT
P
P
P
Wake-Up from Pin Change
P
P
P
Bit Name
P77
P76
P75
Power-On
U
U
U
R7(P7)
/RESET and WDT
P
P
P
Wake-Up from Pin Change
P
P
P
Bit Name
P87
P86
P85
Power-On
U
U
U
R8(P8)
/RESET and WDT
P
P
P
Wake-Up from Pin Change
P
P
P
Bit Name
P97
P96
P95
Power-On
U
U
U
R9(P9)
/RESET and WDT
P
P
P
Wake-Up from Pin Change
P
P
P
Bit Name
Power-On
U
U
U
R3F(ISR)
/RESET and WDT
U
U
U
Wake-Up from Pin Change
U
U
U
Bit Name
S7
Power-On
1
1
1
IOCD
/RESET and WDT
1
1
1
Wake-Up from Pin Change
P
P
P
Bit Name
ODE WTE
Power-On
U
0
1
IOCE
/RESET and WDT
U
0
1
Wake-Up from Pin Change
U
P
1
This specification is subject to change without prior notice.
18
P
P
0
0
P
1
1
**P
T
t
t
t
0
0
P
P54
U
P
P
P64
U
P
P
P74
U
P
P
P84
U
P
P
P94
U
P
P
U
U
U
1
1
P
SLPC
1
1
1
P
P
0
0
P
1
1
**P
P
t
t
t
0
0
P
P53
U
P
P
P63
U
P
P
P73
U
P
P
P83
U
P
P
P93
U
P
P
U
U
U
/PU9
1
1
P
ROC
0
0
P
P
P
0
0
P
1
1
**P
Z
U
P
P
0
0
P
P52
U
P
P
P62
U
P
P
P72
U
P
P
P82
U
P
P
P92
U
P
P
U
U
U
/PU8
1
1
P
U
U
U
P
P
0
0
P
1
1
**P
DC
U
P
P
0
0
P
P51
U
P
P
P61
U
P
P
P71
U
P
P
P81
U
P
P
P91
U
P
P
EXIF
0
0
P
/PU6
1
1
P
U
U
U
P
P
0
0
P
1
1
**P
C
U
P
P
0
0
P
P50
U
P
P
P60
U
P
P
P70
U
P
P
P80
U
P
P
P90
U
P
P
TCIF
0
0
P
/PU5
1
1
P
/WUE
1
1
P
2002/03/01
EM78450
MASK ROM
0x0F
IOCF
0x0A~0x3E
GPR
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin Change
U
U
U
U
P
P
U
U
U
U
P
P
U
U
U
U
P
P
U
U
U
U
P
P
U
U
U
U
P
P
U
U
U
U
P
P
EXIE
0
0
P
U
P
P
TCIE
0
0
P
U
P
P
** To execute the next instruction after the ”SLPC” bit status of IOCE register being on high-to-low
transition.
X: Not used. U: Unknown or don’t care. P: Previous value before reset.
t: Check Table VI.6-1
The Status of RST, T, and P of STATUS Register
A RESET condition is initiated by the following events:
1. Power-on condition,
2. Watchdog timer time-out.
The values of T and P, listed in Table 3 are used to check how the processor wakes up.
Table 4 shows the events which may affect the status of T and P .
Table 3 The Values of RST, T and P after RESET
Reset Type
Power on
WDT during Operating mode
WDT wake-up during SLEEP1 mode
WDT wake-up during SLEEP2 mode
Wake-Up on pin change during SLEEP2 mode
T
P
1
0
0
0
P
1
P
0
P
P
*P: Previous status before reset
Table 4 The Status of RST, T and P being Affected by Events
Event
Power on
WDTC instruction
WDT time-out
SLEP instruction
Wake-Up on pin change during SLEEP2 mode
T
1
1
0
1
P
P
1
1
*P
0
P
*P: Previous value before reset
4.6 Interrupt
The EM78450 has the following interrupts.
(1) TCC overflow interrupt
This specification is subject to change without prior notice.
19
2002/03/01
EM78450
MASK ROM
(2) External interrupt (/INT)
R3F is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt
mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When
one of the interrupts (if enabled) is generated, it will cause the next instruction to be fetched from
address 001H. Once in the interrupt service routine, the source of the interrupt can be determined by
polling the flag bits in the R3F register. The interrupt flag bit must be cleared in software before leaving
the interrupt service routine and enabling interrupts to avoid recursive interrupts. The flag in the
Interrupt Status Register (R3F) is set regardless of the status of its mask bit or the execution of ENI
instruction. Note that reading R3F will obtain the output of logic AND of R3F and IOCF (refer to Fig. 9).
The RETI instruction exits interrupt routine and enables the global interrupt (ENI instruction execution).
When an interrupt is generated by INT instruction (if enabled), it causes the next instruction to be
fetched from address 002H.
IRQn
PQ
R
CLKC
LQ
D
/IRQn
RFRD
R3F
RESET
interrupt
IRQm
ENI/DISI
Q P D
R
CCLK
QL
IOCF
IOD
IOCFWR
IOCF
RD
RFWR
Fig. 9 Interrupt Input Circuit
This specification is subject to change without prior notice.
20
2002/03/01
EM78450
MASK ROM
4.7 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more
operands. All instructions are executed within one single instruction cycle (consisting of 2 oscillator
periods), unless the program counter is changed (a) by executing the instruction “MOV R2,A”, “ADD R2,A”, “TBL”, or any instruction which writes to R2
(e.g. “SUB R2,A”, “BS R2,6”, “CLR R2”, ⋅⋅⋅×).
(b) if CALL, RET, RETI, RETL, JMP, Conditional skip (JBS, JBC, JZ, JZA, DJZ, DJZA) are tested to
be true.
In these cases, the execution takes two instruction cycles.
In addition, the instruction set provides the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction can operate on
I/O register.
The symbol “R” represents a register designator that specifies which one of the registers (including
operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4
determine the selected register bank. “b” represents a bit designator that selects the value for the bit
which is located in the register "R", and affects the operation. "k" represents an 8 or 10-bit constant or
literal value.
INSTRUCTION BINARY
0 0000 0000 0000
0 0000 0000 0001
0 0000 0000 0010
0 0000 0000 0011
0 0000 0000 0100
0 0000 0000 rrrr
0 0000 0001 0000
0 0000 0001 0001
0 0000 0001 0010
HEX
0000
0001
0002
0003
0004
000r
0010
0011
0012
MNEMONIC
NOP
DAA
CONTW
SLEP
WDTC
IOW R
ENI
DISI
RET
0 0000 0001 0011
0013
RETI
0 0000 0001 0100
0 0000 0001 rrrr
0014
001r
CONTR
IOR R
0 0000 0010 0000
0020
TBL
0
0
0
0
0
0
00rr
0080
00rr
01rr
01rr
01rr
MOV R,A
CLRA
CLR R
SUB A,R
SUB R,A
DECA R
0000
0000
0000
0001
0001
0001
01rr
1000
11rr
00rr
01rr
10rr
rrrr
0000
rrrr
rrrr
rrrr
rrrr
This specification is subject to change without prior notice.
OPERATION
No Operation
Decimal Adjust A
A → CONT
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
CONT → A
IOCR → A
R2+A → R2,
Bits 8~9 of R2 unchanged
A→ R
0→A
0→R
R-A → A
R-A → R
R-1 → A
21
STATUS AFFECTED
None
C
None
T,P
T,P
None <Note1>
None
None
None
None
None
None <Note1>
Z,C,DC
None
Z
Z
Z,C,DC
Z,C,DC
Z
2002/03/01
EM78450
MASK ROM
INSTRUCTION BINARY
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0 0101 01rr rrrr
0 0101 10rr rrrr
0 0101 11rr rrrr
HEX
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
MNEMONIC
DEC R
OR A,R
OR R,A
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
INCA R
INC R
DJZA R
DJZ R
0 0110 00rr rrrr
06rr
RRCA R
0 0110 01rr rrrr
06rr
RRC R
0 0110 10rr rrrr
06rr
RLCA R
0 0110 11rr rrrr
06rr
RLC R
0 0111 00rr rrrr
07rr
SWAPA R
0
0
0
0
0
0
0
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
SWAP R
JZA R
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
1 00kk kkkk kkkk
1kkk
CALL k
1
1
1
1
1
1
1
1
1
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1E02
1Fkk
JMP k
MOV A,k
OR A,k
AND A,k
XOR A,k
RETL k
SUB A,k
INT
ADD A,k
0111
0111
0111
100b
101b
110b
111b
01kk
1000
1001
1010
1011
1100
1101
1110
1111
01rr
10rr
11rr
bbrr
bbrr
bbrr
bbrr
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
kkkk kkkk
0000 0010
kkkk kkkk
OPERATION
R-1 → R
A ∨ VR → A
A ∨ VR → R
A&R→A
A&R→R
A⊕ R → A
A⊕ R → R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP],
(Page, k) → PC
(Page, k) → PC
k→A
A∨ k→ A
A&k→A
A⊕ k→ A
k → A, [Top of Stack] → PC
k-A → A
PC+1 → [SP], 002H → PC
k+A → A
STATUS AFFECTED
Z
Z
Z
Z
Z
Z
Z
Z,C,DC
Z,C,DC
Z
Z
Z
Z
Z
Z
None
None
C
C
C
C
None
None
None
None
None <Note2>
None <Note3>
None
None
None
None
None
Z
Z
Z
None
Z,C,DC
None
Z,C,DC
<Note1> This is applicable to IOC5 ~ IOC9, IOCD~IOCF only
<Note2> This instruction is not recommended for R3F operation.
<Note3> This instruction cannot operate under R3F.
This specification is subject to change without prior notice.
22
2002/03/01
EM78450
MASK ROM
4.8 CODE Option Register
The EM78450 has one CODE option register that is not the part of the normal program memory. The
option bits cannot be accessed during normal program execution.
7
-
6
-
5
RCT
4
LVDD
3
HLF
2
MS
1
CK2
0
ENWDT
• Bit 0 (ENWDT): WDT option.
0 : WDT is always disabled. Control bit WDTE in IOCE is unused.
1 : WDT is enabled. WDT can be disabled/enabled by software programming. Control bit WDTE in
IOCE register is used to disable/enable WDT.
• Bit 1 (CK2): Input clock divided by two selection.
0 : System clock is from oscillator clock directly.
1 : System clock is from oscillator clock divided by two.
• Bit 2 (MS): Oscillator type selection.
0 : RC Type
1 : XTAL Type
• Bit 3 (HLF): XTAL frequency selection.
0 : Low frequency, 32.768KHz
1 : High frequency
• Bit 4 (LVDD): Operating voltage.
0 : 4V~5.5V
1 : 2.3V~4V
• Bit 5 (RCT): RC mode selection
0: Internal C, external R oscillation.
1: External RC oscillation
• Bit 6~Bit 7 : Not used, must bt "0"s.
This specification is subject to change without prior notice.
23
2002/03/01
EM78450
MASK ROM
4.9 Timing Diagram
AC Test Input/Output Waveform
2.4
2.0
2.0
TEST POINTS
0.8
0.8
0.4
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Timing measurements are
made at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
This specification is subject to change without prior notice.
24
2002/03/01
EM78450
MASK ROM
5. ABSOLUTE MAXIMUM RATING
Items
Temperature under bias
Storage temperature
Input voltage
Output voltage
Operating Frequency (2clk)
This specification is subject to change without prior notice.
0°C
-65°C
-0.3V
-0.3V
DC
25
Rating
to
to
to
to
to
70°C
150°C
+6.0V
+6.0V
20MHz
2002/03/01
EM78450
MASK ROM
6. ELECTRICAL CHARACTERISTICS
6.1 DC Characteristic
(Ta=0°C~70°C, VDD=5V±5%, VSS=0V)
Symbol
FXT
FRC
IIL
VIH1
VIL1
VIHX1
VILX1
VIH2
VIL2
VIHX2
VILX2
VOH1
VOH2
VOH3
VOL1
VOL2
VOL3
VOL4
IPH
Parameter
XTAL VDD to 2.3V
XTAL VDD to 3V
XTAL VDD to 5V
RC VDD to 2.3V
RC VDD to 3V
RC VDD to 5V
Input Leakage Current
Input High Voltage VDD=5V)
Input Low Voltage (VDD=5V)
Clock Input High Voltage
(VDD=5V
Clock Input Low Voltage
(VDD=5V
Input High Voltage(VDD=3V)
Input Low Voltage (VDD=3V)
Clock Input High Voltage
(VDD=3V)
Clock Input Low Voltage
(VDD=3V)
Output High Voltage
(Ports 5,6,8, P74~P77,
P90~P92,P95~P97,and
PF5~PF7)
Condition
Two clocks
Two clocks
Typ
VIN = VDD, VSS
Max
4
8
20
4
4
4
±1
2.0
0.8
OSCI
2.5
S7=1(IOCD Register bit7),
IOH = -7.0mA
S7=0(IOCD Register bit7),
IOH = -7.0mA
Output High Voltage
(P93/SDO,P94/SCK)
Output Low Voltage
(Ports 5,6,8, P74~P77,
P90~P92,P95~P97,and
PF5~PF7))
IOH = -5.0mA
V
V
V
2.4
2.4
V
2.4
2.4
V
0.4
S7=1(IOCD Register bit7),
IOH = 10.0mA
S7=0(IOCD Register bit7),
IOH = 10.0mA
This specification is subject to change without prior notice.
0.4
V
0.4
0.4
IOL = 15.0mA
0.4
26
V
0.8
IOL = 7.0mA
Pull-high active, input pin at VSS
V
V
IOL = 5.0mA
Output Low Voltage
(P70~P72)
µA
V
V
0.4
0.6
2
MHz
V
1.5
OSCI
IOH = -8.0mA
MHz
1.0
1.5
OSCI
Unit
V
OSCI
Output High Voltage
(P70~P72)
Output Low Voltage
(P93/SDO, P94/SCK)
Output Low Voltage
(P74~P77)
Pull-high current
Min
DC
DC
DC
DC
DC
DC
-50
-100
-240
V
µA
2002/03/01
EM78450
MASK ROM
IPH2
Pull-high current
(P74,P75)
ISB
Power down current
ICC
Operating supply current
Pull-high active, input pin at VSS
1
mA
All input and I/O pin at VDD, output
pin floating, WDT enabled
/RESET="High",
Fosc=1.84324MHz (CK2="0"),
output pin floating
10
µA
3
mA
6.2 AC Characteristic
(Ta=0°C~70°C, VDD=5V±5%, VSS=0V)
Symbol
Dclk
Tins
Ttcc
Twdt
Tdrh
Parameter
Input CLK duty cycle
Instruction cycle time
(CK2="0")
TCC input period
Watchdog timer period
Device reset hold period
Conditions
Min
45
RC Type
250
Typ
50
(Tins+20)/N*
Ta=25°C
Ta=25°C
18
1
18
Max
55
Unit
%
DC
ns
ns
ms
ms
N= selected prescaler ratio.
1
NOTE : VDD=5V, setup time period = 16.5ms ± 5%.
VDD=3V, setup time period = 18.0ms ± 5%.
This specification is subject to change without prior notice.
27
2002/03/01
EM78450
MASK ROM
7. APPLICATION CIRCUIT
EM78450
This specification is subject to change without prior notice.
28
2002/03/01