EM78P163N 8-Bit Microcontroller with OTP ROM Product Specification DOC. VERSION 1.8 ELAN MICROELECTRONICS CORP. February 2013 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2008~2013 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Hong Kong: USA: No. 12, Innovation 1 Road Hsinchu Science Park Hsinchu, TAIWAN 30076 Tel: +886 3 563-9977 Fax: +886 3 563-9966 [email protected] http://www.emc.com.tw Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 Elan Information Technology Group (U.S.A.) PO Box 601 Cupertino, CA 95015 U.S.A. Tel: +1 408 366-8225 Fax: +1 408 366-8225 Korea: Shenzhen: Shanghai: Elan Korea Electronics Company, Ltd. Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai, Ltd. 301 Dong-A Building 632 Kojan-Dong, Namdong-ku Incheon City, KOREA Tel: +82 32 814-7730 Fax: +82 32 813-7730 8A Floor, Microprofit Building Gaoxin South Road 6 6F, Ke Yuan Building No. 5 Bibo Road Zhangjiang Hi-Tech Park Shanghai, CHINA 201203 Tel: +86 21 5080-3866 Fax: +86 21 5080-0273 [email protected] Headquarters: st Shenzhen Hi-tech Industrial Park South Area, Shenzhen CHINA 518057 Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 [email protected] Contents Contents 1 General Description .................................................................................................. 1 2 Features ..................................................................................................................... 1 3 Pin Assignment ......................................................................................................... 2 4 Pin Description.......................................................................................................... 3 5 Functional Description ............................................................................................. 4 5.1 Operational Registers......................................................................................... 5 5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.1.7 5.1.8 5.1.9 5.1.10 5.1.11 5.1.12 5.1.13 5.1.14 5.1.15 5.1.16 5.1.17 5.2 R0 (Indirect Addressing Register) ....................................................................... 5 R1 (Timer Clock/Counter) ................................................................................... 5 R2 (Program Counter) and Stack........................................................................ 5 R3 (Status Register) ............................................................................................ 7 R4 (RAM Select Register)................................................................................... 7 R5 (Port 5)........................................................................................................... 7 R6 (Port 6)........................................................................................................... 8 R7 ( TBLP : Table Point Register ) ...................................................................... 8 R8 ( TBHP : Table Point Register )...................................................................... 8 R9 (Unused) ........................................................................................................ 8 RA (PWMCON: PWM Control Register) ............................................................. 8 RB ( CMPCON I : Comparator Control Register I )............................................. 9 RC (CMPCON II: Comparator Control Register II) ...........................................10 RD (System Control Register)........................................................................... 11 RE (WUCR: Wake-up Control Register) ...........................................................12 RF (Interrupt Status Register) ...........................................................................12 R10 ~ R3F .........................................................................................................13 Special Purpose Registers ............................................................................... 13 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.2.9 5.2.10 5.2.11 5.2.12 5.2.13 A (Accumulator).................................................................................................13 CONT (Control Register)...................................................................................13 IOC5 (I/O Port Control Register) .......................................................................14 IOC6 (I/O Port Control Register) .......................................................................14 IOC7 (TMRH: Most Significant Bits of the PWM Timer)....................................14 IOC8 (TMRL: Least Significant Byte of the PWM Timer) ..................................15 IOC9 (PRDL: Least Significant Byte of the PWM Time Period)........................15 IOCA (DTL: Least Significant Byte of the PWM Duty Cycle) ............................15 IOCB (Pull-down Control Register) ...................................................................15 IOCC (Open-drain Control Register).................................................................16 IOCD (Pull-high Control Register).....................................................................16 IOCE (WDT Control Register) ...........................................................................17 IOCF (Interrupt Mask Register).........................................................................18 Product Specification (V1.8) 02.27.2013 • iii Contents 5.3 TCC/WDT and Prescaler.................................................................................. 19 5.4 I/O Ports ........................................................................................................... 20 5.5 Reset and Wake-up.......................................................................................... 23 5.5.1 5.5.2 5.5.3 5.5.4 Reset .................................................................................................................23 Wake-up and Interrupt Modes Operation Summary .........................................25 /RESET Configure.............................................................................................31 Status of RST, T, and P of the Status Register..................................................31 5.6 Interrupt ............................................................................................................ 32 5.7 PWM (Pulse Width Modulation) ....................................................................... 34 5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 5.7.6 5.8 Timer ................................................................................................................ 36 5.8.1 5.8.2 5.8.3 5.8.3.1 5.8.4 5.9 Overview ...........................................................................................................34 Increment Timer Counter (TMRX: TMRH/TMRL)..............................................35 PWM Time Period (PRDX: TMRH/PRDL).........................................................35 PWM Duty Cycle (DTX: TMRH/DTL) ................................................................36 Comparator .......................................................................................................36 PWM Programming Process/Steps...................................................................36 Overview ...........................................................................................................36 Function Description..........................................................................................37 Programming the Related Registers .................................................................37 TMR Related Control Registers..................................................................................................... 37 Timer Programming Process/Steps...................................................................37 Comparator ...................................................................................................... 38 5.9.1 5.9.2 5.9.3 5.9.4 External Reference Signal ................................................................................38 Comparator Outputs..........................................................................................39 Comparator Interrupt .........................................................................................39 Wake-up from Sleep Mode................................................................................40 5.10 Oscillator .......................................................................................................... 40 5.10.1 5.10.2 5.10.3 5.10.4 Oscillator Modes................................................................................................40 Crystal Oscillator/Ceramic Resonator (Crystal) ................................................41 External RC Oscillator Mode.............................................................................42 Internal RC Oscillator Mode ..............................................................................43 5.11 Power-on Considerations ................................................................................. 45 5.11.1 External Power-on Reset Circuit .......................................................................45 5.11.2 Residual Voltage Protection ..............................................................................46 5.12 Code Option Register....................................................................................... 46 5.12.1 Code Option Register (Word 0).........................................................................47 5.12.2 Code Option Register (Word 1).........................................................................48 5.12.3 Customer ID Register (Word 2).........................................................................49 5.13 Instruction Set .................................................................................................. 50 iv • Product Specification (V1.8) 02.27.2013 Contents 6 Absolute Maximum Ratings ................................................................................... 53 7 Electrical Characteristics ....................................................................................... 53 8 7.1 DC Electrical Characteristic.............................................................................. 53 7.2 Comparator Characteristics.............................................................................. 55 7.3 AC Electrical Characteristics ............................................................................ 56 7.4 Device Characteristics...................................................................................... 56 Timing Diagram ....................................................................................................... 68 APPENDIX A Package Type........................................................................................................... 69 B Package Information............................................................................................... 70 C Quality Assurance and Reliability ......................................................................... 74 C.1 Address Trap Detect......................................................................................... 74 Product Specification (V1.8) 02.27.2013 •v Contents Specification Revision History Doc. Version Revision Description Date 1.0 Initial version 2008/07/09 1.1 Modified some descriptions of the code option 2008/08/11 1.2 Added description of RC Bit 7 2008/12/09 1.3 Modified the DC Electrical Characteristics 2009/03/24 1.4 Modified the operation voltage range 2009/08/10 1.5 Added P51~P54 IOH DC electrical characteristics 2010/01/29 Modified some description error 1.6 2010/02/10 Modified the pin description format Added device characteristics 1.7 1.8 vi • Modified the package name from EM78P163NSO16J to EM78P163NSO16AJ 1. Added Ordering and Manufacturing Information. 2. Added LVR specification 2010/11/02 2013/02/27 Product Specification (V1.8) 02.27.2013 EM78P163N 8-Bit Microcontroller with OTP ROM 1 General Description The EM78P163N is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS technology. It has an on-chip 1K×13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides three protection bits to prevent intrusion of user’s OTP memory code as well as from unwanted external accesses. Several code option bits are available to meet user’s requirements. With its enhanced OTP-ROM feature, the EM78P163N provides a convenient way of developing and verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code. 2 Features CPU Configuration • 1K×13 bits on-chip ROM • 48×8 bits on-chip registers (SRAM, Drift Rate Internal RC Temperature Voltage Frequency (-40°C~85°C ) (2.0V~5.5V) Process 455kHz 4 MHz 8 MHz 16 MHz general purpose) • 5-level stacks for subroutine nesting • Less than 1.5mA at 5V/IRC 4 MHz • Typically 15 μA, at 3V/32kHz • Typically 1 μA, during Sleep mode • • • Power-on Reset (POR): 1.8V • Wake-up port : P6 • 7 programmable pull-down I/O pins • 7 programmable pull-high I/O pins • 7 programmable open-drain I/O pins • External interrupt : P60 8-bit real time clock/counter (TCC) with selective signal One comparator (typical offset voltage 10 mV when input and Cin- 4 channel switch. • One Pulse Width Modulation (PWM ) with 10-bit resolution • High EFT immunity • Power down mode (Sleep mode) Five available Interrupts: • TCC overflow interrupt • Input-port status changed interrupt (wake-up from sleep mode) Operating Voltage Range: • External interrupt Operating voltage: 2.1V~5.5V at 0°C ~70°C • PWM period match completion (commercial) • Comparator output change interrupt Operating voltage: 2.3V~5.5V at -40°C ~85°C ± 13% ± 13% ± 13% ± 14% voltage range 0.5V~4.5V) with Cin+/internal Vref level select I/O Port Configuration 2 bidirectional I/O ports : P5, P6 ± 3% ± 3% ± 3% ± 3% sources, trigger edges, and overflow interrupt 3 programmable Level Voltage Reset (LVR): • ± 5% ± 5% ± 5% ± 5% Peripheral Configuration • 4.0V, 3.3V 2.4V ± 5% ± 5% ± 5% ± 6% Total Other Features (industrial) • Operating Frequency range (base on 2 clocks): • • • One security register to prevent intrusion of user’s OTP memory code Crystal Mode: DC~20MHz/2clks @ 5V • One configuration register to match user’s requirements DC~8MHz/2clks @ 3V • Two clocks per instruction cycle DC~4MHz/2clks @ 2.1V • TBRD instruction ERC Mode: Package Type: DC~16 MHz/2clks @ 4.5V • 14-pin DIP 300mil : EM78P163ND14J DC~12 MHz/2clks @ 4V • 14-pin SOP 150mil : EM78P163NSO14J • 16-pin DIP 300mil : EM78P163ND16J • 16-pin SOP 150mil : EM78P163NSO16AJ DC~4MHz/2clks @ 2.1V • Programmable prescaler of oscillator set-up time Internal RC Drift Rate: (Ta=25°C, VDD=5V ± 5%, VSS=0V) Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) Note: These are Green products that do not contain hazardous substances. •1 EM78P163N 8-Bit Microcontroller with OTP ROM 3 Pin Assignment Figure 3-1 EM78P163ND16/SO16 2• Figure 3-2 EM78P163ND14/SO14 Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 4 Pin Description Name Function Input Type Output Type Description VDD VDD Power VSS VSS Power P50 ST CinD- AN P51 P51 ST CMOS Bidirectional I/O pin with programmable pull-down P52 P52 ST CMOS Bidirectional I/O pin with programmable pull-down P53 P53 ST CMOS Bidirectional I/O pin with programmable pull-down P54 P54 ST CMOS Bidirectional I/O pin P55 P55 ST CMOS Bidirectional I/O pin P60 ST CMOS Bidirectional I/O pin with programmable pull-down, pull-high, open-drain, and pin change wakeup /INT ST − external interrupt pin CMOS Output of comparator CMOS Bidirectional I/O pin with programmable pull-down, pull-high, open-drain, and pin change wakeup P50/CinD- P60//INT/CO CO P61 P61/PWM/Cin+ P62/TCC/CinA- P63//RST P64/OSCO PWM P66/CinB- P67/CinC- ST − Power Ground CMOS Bidirectional I/O pin with programmable pull-down Inverting end D of comparator − PWM output Non-inverting end of comparator Cin+ AN − P62 ST CMOS TCC ST − TCC clock input CinA- AN − Inverting end of comparator P63 ST CMOS /RST ST − P64 ST CMOS Bidirectional I/O pin with programmable pull-high, open-drain, and pin change wakeup XTAL Clock output of crystal/ resonator oscillator CMOS Bidirectional I/O pin with programmable pull-high, open-drain, and pin change wakeup OSCO P65/OSCI − − − P65 ST OSCI XTAL P66 ST CMOS CinB- AN − P67 ST CMOS CinC- AN − − Bidirectional I/O pin with programmable pull-down, pull-high, open-drain, and pin change wakeup Bidirectional I/O pin Internal pull-high reset pin Clock input of crystal/ resonator oscillator Bidirectional I/O pin with programmable pull-high, open-drain, and pin change wakeup Inverting end of comparator Bidirectional I/O pin with programmable pull-high, open-drain, and pin change wakeup Inverting end of comparator Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) •3 EM78P163N 8-Bit Microcontroller with OTP ROM 5 Functional Description P6 P60 P61 P62 P63 P64 P65 P66 P67 ROM PC Instruction Register 5-level stack (13 bit) Int. RC Ext. RC Oscillation Generation Reset Instruction Decoder WDT PWM (Timer) TCC PWM TCC Mux ALU P5 P50 P51 P52 P53 P54 P55 Crystal R4 RAM ACC R3 (Status Reg.) Interrupt control register LVR Interrupt circuit Comparator (CO) Ext INT Cin+, CinA-~CinD-, CO Figure 5-1 Functional Block Diagram 4• Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.1 Operational Registers 5.1.1 R0 (Indirect Addressing Register) R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4). 5.1.2 R1 (Timer Clock/Counter) Incremented by an external signal edge, through the TCC pin, or by the instruction cycle clock. External signal of TCC trigger pulse width must be greater than one instruction. The signals to increase the counter are determined by Bit 4 and Bit 5 of the CONT register. Writable and readable as any other registers. 5.1.3 R2 (Program Counter) and Stack Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in the following figure. Figure 5-2 Program Counter Organization The configuration structure generates 1K×13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long. R2 is set as all "0" when under Reset condition. "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows the PC to go to any location within a page. Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) •5 EM78P163N 8-Bit Microcontroller with OTP ROM "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed onto the stack. Thus, the subroutine entry address can be located anywhere within a page. "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level stack. "ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits of the PC will increase progressively. "MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC will remain unchanged. Any instruction except “ADD R2,A” written to R2 (e.g. "MOV R2, A", "BC R2, 6",⋅etc.) will cause the ninth bit and the tenth bit (A8 ~ A9) of the PC to remain unchanged. All instructions are single instruction cycle (fclk/2 or fclk/4) except for instructions that would change the contents of R2. Such instructions will need one more instruction cycle. The Data Memory Configuration is as follows: Address R PAGE Registers 00 R0 01 R1 (TCC) 02 R2 (PC) 03 R3 (Status) 04 R4 (RSR) 05 R5 06 R6 IOC PAGE Registers CONT (Control Register) (Port 5) IOC5 (I/O Port Control Register) (Port 6) IOC6 (I/O Port Control Register) 07 R7 ( TBLP: Table Pointer Register ) IOC7 (TMRH: PWM timer) 08 R8 ( TBHP: Table Pointer Register ) IOC8 (TIMEL: PWM timer) 09 R9 (Option Control bits) IOC9 (PRDL: PWM period) 0A RA (PWM Control Register) IOCA (DTL: Duty cycle of PWM) 0B RB (Comparator Control Register I) IOCB (Pull-down Register) 0C RC (Comparator Control Register II) IOCC (Open-drain Register) 0D RD (System Control Register) IOCD (Pull-high Register) 0E RE (Wake-up Control Register) IOCE (WDT Control Register) 0F RF (Interrupt Status Register) IOCF (Interrupt Mask Register) 10 : General Registers 3F 6• Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.1.4 R3 (Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RST GP1 GP0 T P Z DC C Bit 7 (RST): Bit for reset type (read only) 0 : Set to 0 if the device wakes up from other reset type 1 : Set to 1 if the device wakes up from sleep mode on a pin change Bits 6 ~ 5 (GP1 ~ GP0): General purpose read/write bits. Bit 4 (T): Time-out bit Set to 1 with the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT time-out. Bit 3 (P): Power down bit Set to 1 during power-on or by a "WDTC" command and reset to 0 by a "SLEP" command. NOTE Bit 4 and Bit 3 (T and P) are read only. Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Bit 1 (DC): Auxiliary carry flag Bit 0 (C): Carry flag 5.1.5 R4 (RAM Select Register) Bits 7 ~ 6 are general-purpose read/write bits. See the Data Memory Configuration. Bits 5 ~ 0 are used to select registers (Address: 10~3F) in the indirect addressing mode. 5.1.6 R5 (Port 5) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 P55 P54 P53 P52 P51 P50 Bits 7 ~ 6 (Unused): Unused bits. Set to 0 all the time. Bits 5 ~ 0 (P55 ~ P50): I/O data registers. User can use the IOC5 to define each bit as input/output Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) •7 EM78P163N 8-Bit Microcontroller with OTP ROM 5.1.7 R6 (Port 6) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P67 P66 P65 P64 P63 P62 P61 P60 Bits 7 ~ 0 (P67 ~ P60): I/O data registers. User can use the IOC6 to define each bit as input/output. 5.1.8 R7 ( TBLP : Table Point Register ) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TBA7 TBA6 TBA5 TBA4 TBA3 TBA2 TBA1 TBA0 Bits 7 ~ 0 (TBA7 ~ TBA0): Table Point Address Bits 7~0. 5.1.9 R8 ( TBHP : Table Point Register ) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HLB 0 0 0 0 0 TBA9 TBA8 Bit 7 (HLB): Take MSB or LSB of machine code. 0: LSB of machine code. 1: MSB of machine code. Bits 6 ~ 2 (Unused): Unused bits. Set to 0 all the time. Bits 1 ~ 0 (TBA9 ~ TBA8): Table Point Address Bits 9 ~ 8. 5.1.10 R9 (Unused) 5.1.11 RA (PWMCON: PWM Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 PWME TEN TP2 TP1 TP0 Bits 7 ~ 5 (Unused): Unused bits. Set to 0 all the time. Bit 4 (PWME): PWM enable bit 0 : PWM is off (default value), and its related pin carries out the P61 function. 1 : PWM is on, and its related pin is automatically set to output. NOTE The P61/PWM/Cin+ pin priority is as follows: P61/CO/PWM Priority 8• High Medium Low Cin+ PWM P61 Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM TMR enable bit Bit 3 (TEN): 0 : TMR is off (default value) 1 : TMR is on Bits 2 ~ 0 (TP2 ~ TP0): TMR clock prescaler bits TP2 TP1 TP0 0 0 0 0 0 1 1:1 (default) 1:2 0 1 0 1:4 0 1 1 1:8 1 0 0 1:16 1 1 0 1 1 0 1:64 1:128 1 1 1 1:256 5.1.12 Prescale RB ( CMPCON I : Comparator Control Register I ) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACOS1 ACOS0 BCOS1 BCOS0 CCOS1 CCOS0 DCOS1 DCOS0 Bits 7 ~ 0 (XCOS1 ~ XCOS0): Comparator Select bits XCOS1 XCOS0 Function Description 0 0 1 1 Comparator is not used. P50, P60, P61, P62, P66, and P67 functions as normal I/O pins. 0 1 Used as Comparator and P60 functions as normal I/O pin *1 1 0 Used as Comparator and P60 funcions as Comparator output pin (CO) *1 *1: For Cin+ and Cin- definition, refer to RC control register. NOTE The P60//INT/CO pin priority is as follows: P61/PWM/Cin+ Priority High Medium Low CO /INT P60 Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) •9 EM78P163N 8-Bit Microcontroller with OTP ROM 5.1.13 RC (CMPCON II: Comparator Control Register II) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CRS CIRL2 CIRL1 CIRL0 CPOUT COE CRCS1 CRCS0 Bit 7 (CRS): Comparator reference voltage source select bit. When the comparator is disabled, this bit must also be set to 0. 0 : Disable internal voltage reference, CIN+ source external (default value). If the comparator is disabled, P61/PWM/CIN+ pin activates as I/O. 1 : Enable internal voltage reference. P61/PWM/CIN+ pin activates as I/O. Bits 6 ~ 4 (CIRL2 ~ CIRL0): Comparator internal reference level CIRL2 CIRL1 CIRL0 Voltage Level (V) 0 0 0 0.1VDD 0 0 1 0.15VDD 0 1 0 0.2VDD 0 1 1 0.3VDD 1 0 0 0.4VDD 1 0 1 0.45VDD 1 1 0 0.5VDD 1 1 1 0.6VDD Bit 3 (CPOUT): Result of the comparator output. Bit 2 (COE): Comparator enable bit (RB effect when this bit = 1) 0 : Comparator function is disabled (default value) 1 : Comparator function is enabled Bits 1 ~ 0 (CRCS1 ~ CRCS0): Comparator CIN- channel switch CRCS1 CRCS0 Prescale 0 0 P62/TCC/CinA- is set as CinA- pin (default) 0 1 P66/CinB- is set as CinB- pin 1 0 P67/CinC- is set as CinC- pin 1 1 P50/CinD- is set as CinD- pin NOTE The P62/TCC/CinA- Pin Priority is as follows: P62/TCC/CinA- Priority 10 • High Medium Low CinA- TCC P62 Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.1.14 RD (System Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIMERSC CPUS IDLE 0 0 0 0 0 Bit 7 (TIMERSC): TCC, TMR clock source select 0 : Fs, sub frequency for WDT internal RC time base 1 : Fm, main-oscillator clock Bit 6 (CPUS): CPU Oscillator Source Select 0 : sub-oscillator (fs) 1 : main oscillator (fosc) When CPUS=0, the CPU oscillator selects sub-oscillator and the main oscillator is stopped. Bit 5 (IDLE): Idle mode enable bit. 0 : IDLE=”0”+SLEP instruction → sleep mode 1 : IDLE=”1”+SLEP instruction → idle mode CPU Operation Mode RESET Normal Mode fosc: oscillation fs: oscillation external interrupt CPU: using fosc wake up IDLE="0" SLEP Sleep Mode CPUS="1" external interrupt fosc: stop fs: stop CPU: stop CPUS="0" Green Mode IDLE="1" SLEP IDLE="1" SLEP fosc: stop fs: oscillation IDLE="0" SLEP CPU: using fs Idle Mode fosc: stop fs: oscillation wake up CPU: stop Figure 5-3 CPU Operation Mode Bits 4 ~ 0 (Unused): Unused bits, set to 0 all the time. Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 11 EM78P163N 8-Bit Microcontroller with OTP ROM 5.1.15 RE (WUCR: Wake-up Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 CMPWE ICWE 0 Bits 7 ~ 3 (Unused): Unused bits. Set to 0 all the time. Bit 2 (CMPWE): Comparator wake-up enable bit 0 : Disable Comparator wake up 1 : Enable Comparator wake up When the Comparator output status change is used to enter an interrupt vector or to wake-up the EM78P163N from sleep mode, the CMPWE bit must be set to “Enable“. Port 6 input change to wake-up status enable bit Bit 1 (ICWE): 0 : Disable Port 6 input change to wake-up status 1 : Enable Port 6 input change wake-up status When the Port 6 Input Status Change is used to enter an interrupt vector or to wake-up the EM78P163N from sleep mode, the ICWE bit must be set to “Enable“. Unused bit, set to 0 all the time Bit 0 (Unused): 5.1.16 RF (Interrupt Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 PWMIF CMPIF EXIF ICIF TCIF “1” means there is an interrupt request “0” means no interrupt occurs. Bits 7 ~ 5 (unused): Unused bits. Set to 0 all the time. Bit 4 (PWMIF): PWM (Pulse Width Modulation) interrupt flag. Set when a selected duration is reached. Reset by software. Bit 3 (CMPIF): Comparator Interrupt flag. Set when a change occurs in the Comparator output. Reset by software. 12 • Bit 2 (EXIF): External interrupt flag. Set by falling edge on /INT pin, reset by software. Bit 1 (ICIF): Port 6 input status changed interrupt flag. Set when Port 6 input changes, reset by software. Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows, reset by software. RF can be cleared by instruction but cannot be set. IOCF is the interrupt mask register. Note that the result of reading RF is the "logic AND" of RF and IOCF. Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.1.17 R10 ~ R3F All of these are 8-bit general-purpose registers. 5.2 Special Purpose Registers 5.2.1 A (Accumulator) Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator, which is not an addressable register. 5.2.2 CONT (Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTE INT TS TE PSTE PST2 PST1 PST0 Bit 7 (INTE): INT signal edge 0 : interrupt occurs at a rising edge of the INT pin 1 : interrupt occurs at a falling edge of the INT pin Bit 6 (INT): Interrupt enable flag 0 : masked by DISI or hardware interrupt 1 : enabled by ENI/RETI instructions Bit 5 (TS): TCC signal source 0 : internal instruction cycle clock, P62 is a bidirectional I/O pin. 1 : transition on the TCC pin NOTE The P62/TCC/CinA- Pin Priority is as follows: P62/TCC/CinA- Priority Bit 4 (TE): High Medium Low CinA- TCC P62 TCC signal edge 0 : increment if a transition from low to high takes place on the TCC pin. 1 : increment if a transition from high to low takes place on the TCC pin. Bit 3 (PSTE): Prescaler enable bit for TCC 0 : prescaler disable bit. TCC rate is 1:1. 1 : prescaler enable bit. TCC rate is set at Bit 2 ~ Bit 0. Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 13 EM78P163N 8-Bit Microcontroller with OTP ROM Bits 2 ~ 0 (PST2 ~ PST0): TCC prescaler bits PST2 PST1 PST0 TCC Rate 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 5.2.3 IOC5 (I/O Port Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - IOC55 IOC54 IOC53 IOC52 IOC51 IOC50 Bits 7 ~ 6 (Unused): unused bits Bits 5 ~ 0 (IOC55 ~ IOC50): I/O direction control register 0 : defines the relative I/O pin as output 1 : puts the relative I/O pin into high impedance 5.2.4 IOC6 (I/O Port Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 IOC61 IOC60 Bits 7~0 (IOC67 ~ IOC60): I/O direction control register 0 : defines the relative I/O pin as output 1 : puts the relative I/O pin into high impedance 5.2.5 IOC7 (TMRH: Most Significant Bits of the PWM Timer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 TMR[9] TMR[8] PRD[9] PRD[8] DT[9] DT[8] Bits 7 ~ 6 (unused): unused bits. Set to 0 all the time. Bits 5 ~ 4 (TMR[9]~TMR[8]): Most significant bits of the PWM timer, read-only bit. Bits 3 ~ 2 (PRD[9]~PRD[8]): Most significant bits of the PWM time period. Bits 1 ~ 0 (DT[9]~DT[8]): Most significant bits of the PWM duty cycle. 14 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.2.6 IOC8 (TMRL: Least Significant Byte of the PWM Timer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMR[7] TMR[6] TMR[5] TMR[4] TMR[3] TMR[2] TMR[1] TMR[0] The content of IOC8 is read-only. 5.2.7 IOC9 (PRDL: Least Significant Byte of the PWM Time Period) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRD[7] PRD[6] PRD[5] PRD[4] PRD[3] PRD[2] PRD[1] PRD[0] The content of IOC9 is the time period (time base) of PWM. The PWM frequency is the reverse of the period. Most Significant Bits (Bits 9, 8) of the PWM Period Cycle are located in IOC7<3, 2>. 5.2.8 IOCA (DTL: Least Significant Byte of the PWM Duty Cycle) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DT[7] DT[6] DT[5] DT[4] DT[3] DT[2] DT[1] DT[0] A specified value keeps the PWM output to remain high until the value matches with TMR. 5.2.9 IOCB (Pull-down Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 /PD62 /PD61 /PD60 /PD53 /PD52 /PD51 /PD50 Bit 7 (Unused): Unused bit, set to 0 all the time Bit 6 (/PD62): Control bit used to enable pull-down of P62 pin. 0 : Enable internal pull-down 1 : Disable internal pull-down Bit 5 (/PD61): Control bit used to enable pull-down of the P61 pin. Bit 4 (/PD60): Control bit used to enable pull-down of the P60 pin. Bit 3 (/PD53): Control bit used to enable pull-down of the P53 pin. Bit 2 (/PD52): Control bit used to enable pull-down of the P52 pin. Bit 1 (/PD51): Control bit used to enable pull-down of the P51 pin. Bit 0 (/PD50): Control bit used to enable pull-down of the P50 pin. The IOCB Register is both readable and writable. Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 15 EM78P163N 8-Bit Microcontroller with OTP ROM 5.2.10 IOCC (Open-drain Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OD67 OD66 OD65 OD64 0 OD62 OD61 OD60 Bit 7 (OD67): Control bit used to enable open-drain of the P67 pin. 0 : Disable open-drain output 1 : Enable open-drain output Bit 6 (OD66): Control bit used to enable open-drain of the P66 pin. Bit 5 (OD65): Control bit used to enable open-drain of the P65 pin. Bit 4 (OD64): Control bit used to enable open-drain of the P64 pin. Bit 3 (unused): Unused bit. Set to 0 all the time. Bit 2 (OD62): Control bit used to enable open-drain of the P62 pin. Bit 1 (OD61): Control bit used to enable open-drain of the P61 pin. Bit 0 (OD60): Control bit used to enable open-drain of the P60 pin. The IOCC Register is both readable and writable. 5.2.11 IOCD (Pull-high Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 /PH67 /PH66 /PH65 /PH64 0 /PH62 /PH61 /PH60 Bit 7 (/PH67): Control bit used to enable pull-high of the P67 pin. 0 : Enable internal pull-high 1 : Disable internal pull-high Bit 6 (/PH66): Control bit used to enable pull-high of the P66 pin. Bit 5 (/PH65): Control bit used to enable pull-high of the P65 pin. Bit 4 (/PH64): Control bit used to enable pull-high of the P64 pin. Bit 3 (unused): Unused bit. Set to 0 all the time. Bit 2 (/PH62): Control bit used to enable pull-high of the P62 pin. Bit 1 (/PH61): Control bit used to enable pull-high of the P61 pin. Bit 0 (/PH60): Control bit used to enable pull-high of the P60 pin. The IOCD Register is both readable and writable. 16 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.2.12 IOCE (WDT Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTE EIS PSWE PSW2 PSW1 PSW0 0 0 Bit 7 (WDTE): Control bit used to enable the Watchdog Timer 0 : Disable WDT 1 : Enable WDT WDTE is both readable and writable. Bit 6 (EIS): Control bit used to define the function of the P60 (/INT) pin 0 : P60, normal I/O pin 1: /INT, external interrupt pin. In this case, the I/O control bit of P60 (Bit 0 of IOC6) must be set to "1" NOTE ■ When EIS is "0," the path of /INT is masked. When EIS is "1," the status of the /INT pin can also be read by way of reading Port 6 (R6). Refer to Figure 6-5 (I/O Port and I/O Control Register Circuit for P60 (/INT)) under Section 6.4 (I/O Ports). ■ The EIS is both readable and writable. Bit 5 (PSWE): prescaler enable bit for WDT 0 : prescaler disable bit. WDT rate is 1:1 1 : prescaler enable bit. WDT rate is set at Bit 4~Bit 2 Bits 4 ~ 2 (PSW2 ~ PSW0): WDT prescaler bits. PSW2 PSW1 PSW0 0 0 0 1:2 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 Bits 1 ~ 0: WDT Rate Unused bits. Set to 0 all the time. Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 17 EM78P163N 8-Bit Microcontroller with OTP ROM 5.2.13 IOCF (Interrupt Mask Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 PWMIE CMPIE EXIE ICIE TCIE Bits 7 ~ 5: Unused bits. Set to 0 all the time. Bit 4 (PWMIE): PWMIF interrupt enable bit 0 : Disable PWM interrupt 1 : Enable PWM interrupt Bit 3 (CMPIE): CMPIF interrupt enable bit 0 : Disable CMPIF interrupt 1 : Enable CMPIF interrupt When the Comparator output status change is used to enter an interrupt vector or to enter the next instruction, the CMPIE bit must be set to “Enable“. Bit 2 (EXIE): EXIF interrupt enable bit 0 : disable EXIF interrupt 1 : enable EXIF interrupt Bit 1 (ICIE): ICIF interrupt enable bit. 0 : Disable ICIF interrupt 1 : Enable ICIF interrupt Bit 0 (TCIE): TCIF interrupt enable bit. 0 : Disable TCIF interrupt 1 : Enable TCIF interrupt The IOCF register is both readable and writable. 18 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.3 TCC/WDT and Prescaler There are two 8-bit counters available as prescalers for the TCC and WDT respectively. The PST0 ~ PST2 bits of the CONT register are used to determine the ratio of the TCC prescaler, and the PSW0 ~ PSW2 bits of the IOCE0 register are used to determine the WDT prescaler. The prescaler counter is cleared by the instructions each time such instructions are written into the TCC. The WDT and prescaler will be cleared by the “WDTC” and “SLEP” instructions. Figure 5-4 depicts the block diagram of TCC/WDT. TCC (R1) is an 8-bit timer/counter. The TCC clock source can be an internal clock or external signal input (edge selectable from the TCC pin). If the TCC signal source is from an internal clock, TCC will be incremented by 1 at every 1/Fc clock (without prescaler). If TCC signal source is from the external clock input, TCC will be incremented by 1 at every falling edge or rising edge of the TCC pin. The TCC pin input time length (kept at High or Low level) must be greater than 1CLK. The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when the oscillator driver has been turned off (i.e., in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during normal mode through software programming. Refer to WDTE bit of the IOCE0 register. Without prescaler, the WDT time-out duration is approximately 18ms.1 CLK (Fosc/2 or Fosc/4) Data Bus 0 TCC Pin 1 8-Bit Counter (IOCC1) MUX 8 to 1 MUX TE (CONT) TS (CONT) WDT WDTE (IOCE0) 8-Bit Counter 8 to 1 MUX WDT Time out SYNC 2 cycles Prescaler TCC (R1) TCC overflow interrupt PSR2~0 (CONT) Prescaler PSW2~0 (IOCE0) Figure 5-4 TCC and WDT Block Diagram 1 VDD=5V, Setup time period = 16.5ms ± 30%. VDD=3V, Setup time period = 18ms ± 30%. Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 19 EM78P163N 8-Bit Microcontroller with OTP ROM 5.4 I/O Ports The I/O registers, both Port 5 and Port 6, are bidirectional tri-state I/O ports. Port 6 can be pulled-high internally by software except P63. In addition, Port 6 can also have open-drain output by software except P63. Input status changed interrupt (or wake-up) function is available from Port 6. P53 ~ P50 and P62 ~ P60 pins can be pulled-down by software. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC6) except P63. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5 and Port 6 are shown in Figure 5-5, Figure 5-6 and Figure 5-7 respectively. PCRD PORT Q P R _ Q C L Q _ Q P R C L D CLK PCWR IOD D CLK PDWR PDRD 0 1 M U X Note: Pull-down is not shown in the figure. Figure 5-5 Circuit of I/O Port and I/O Control Register for Port 5 20 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM PCRD PORT B it 6 o f IO C E P R CLK C L D 0 Q 1 _ Q Q _ Q P D R CLK C L PCW R Q _ Q P R D CLK C L PDW R IO D M U X PDRD D T10 P R Q CLK _ C Q L Note: Pull-high (down), open-drain is not shown in the figure. Figure 5-6 Circuit of I/O Port and I/O Control Register for P60 (/INT) PORT 0 1 Q _ Q P R D CLK C L PCW R Q _ Q P D R CLK C L PDW R IOD M U X PDRD P R CLK C L D TIN Q _ Q Note: Pull-high (down), open-drain is not shown in the figure. Figure 5-7 Circuit of I/O Port and I/O Control Register for P61~P67 Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 21 EM78P163N 8-Bit Microcontroller with OTP ROM ICIE D P R Q Interrupt CLK _ C Q L ICIF ENI Instruction P D R Q P60 P61 P62 P63 CLK _ C Q L P64 P65 P66 P67 P Q R D CLK _ Q C L DISI Instruction Interrupt (Wake-up from SLEEP) /SLEP Next Instruction (Wake-up from SLEEP) Figure 5-8 Block Diagram of I/O Port 6 with input Change Interrupt/Wake-up Table 5-1 Usage of Port 6 input change wake-up/interrupt function Usage of Port 6 Input Status Change Wake-up/Interrupt (I) Wake-up from Port 6 Input Status Change (a) Before Sleep (II) Port 6 Input Status Change Interrupt 1. Read I/O Port 6 (MOV R6,R6) 1. Disable WDT 2. Execute "ENI" 2. Read I/O Port 6 (MOV R6,R6) 3. Enable interrupt (Set IOCF.1) 3. Execute "ENI" or "DISI" 4. IF Port 6 change (interrupt) 4. Enable interrupt (Set IOCF.1) → Interrupt Vector (006H) 5. Execute "SLEP" instruction (b) After Wake-up 1. IF "ENI" → Interrupt vector (006H) 2. IF "DISI" → Next instruction 22 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.5 Reset and Wake-up 5.5.1 Reset Input Status Change (1) Power-on reset (2) /RESET pin input "low" (3) WDT time-out (if enabled) 2 The device is kept in a reset condition for a period of approx. 18ms (one oscillator start-up timer period) after a reset is detected. Once a reset occurs, the following functions are performed. The oscillator is running, or will be started. The Program Counter (R2) is set to all "0". All I/O port pins are configured as input mode (high-impedance state). The Watchdog timer and prescaler are cleared. When power is switched on, the upper 3 bits of R3 are cleared. The bits of the CONT register are set to all "1" except for Bit 6 (INT flag). The bits of the IOCB register are set to all "1". The IOCC register is cleared. The bits of the IOCD register are set to all "1". Bit 7 of the IOCE register is set to "1", and Bits 6~0 are cleared Bits 0~4 of RF and bits 0~4 of IOCF register are cleared. Sleep (power down) mode is attained by executing the “SLEP” instruction. While entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by: (1) External reset input on the /RESET pin, (2) WDT time-out (if enabled), or (3) Port 6 input status changes (if enabled). The first two cases will cause the EM78P163N to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). The last case is considered a continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) determines whether or not the controller branches to the interrupt vector following a wake-up. If ENI is executed before SLEP, the instruction will begin to execute from the interrupt vector address after a wake-up. If DISI is executed before SLEP, the operation will restart from the instruction right next to SLEP after a wake-up. 2 Vdd = 5V, Setup time period = 16.5ms ± 30% Vdd = 3V, Setup time period = 18ms ± 30% Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 23 EM78P163N 8-Bit Microcontroller with OTP ROM Only one of Cases 2 and 3 can be enabled before entering sleep mode. That is, [a] if Port 6 input status changed interrupt is enabled before SLEP, WDT must be disabled by software. However, the WDT bit in the option register remains enabled. Hence, the EM78P163N can be awakened only by Case 1 or 3. [b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be disabled. Hence, the EM78P163N can be awakened only by Case 1 or 2. Refer to the section on Interrupt. If Port 6 Input Status Changed Interrupt is used to wake-up the EM78P163N (Case [a] above), the following instructions must be executed before SLEP: MOV A, @xxxx1110b CONTW WDTC MOV IOW MOV MOV A, @0xxxxxxxb RE R6, R6 A, @00000x1xb IOW ENI (or DISI) SLEP ; Select WDT prescaler, ; the prescaler must be set over ; 1:1 ; Clear WDT and prescaler ; Disable WDT ; Read Port 6 ; Enable Port 6 input change ; interrupt RF ; Enable (or disable) global ; interrupt ; Sleep NOTE 1. After waking up from sleep mode, the WDT is automatically enabled. The WDT enable/disable operation after waking up from sleep mode should be properly defined in the software. 2. To avoid a reset from occurring when the Port 6 Input Status Changed Interrupt enters into an interrupt vector or when it is used to wake-up the MCU, the WDT prescaler must be set above the 1:1 ratio. 24 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.5.2 Wake-up and Interrupt Modes Operation Summary All categories under Wake-up and Interrupt modes are summarized below. The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as follows: After wake up: Wake-up Signal Sleep Mode Idle Mode × Wake-up + interrupt (if interrupt is enabled) + next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction If ICWE bit is enabled Wake-up + interrupt (if interrupt is enabled) + next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction × Wake-up + interrupt (if interrupt is enabled) + next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction If CMPWE bit is enabled Wake-up + interrupt (if interrupt is enabled) + next instruction If CMPWE bit is enabled Wake-up + interrupt (if interrupt is enabled) + next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction × Wake-up + interrupt (if interrupt is enabled) + next instruction Interrupt (if interrupt is enabled) or next instruction Interrupt (if interrupt is enabled) or next instruction WDT Time out RESET RESET RESET RESET Low Voltage Reset RESET RESET RESET RESET External interrupt Port 6 pin change If ICWE bit is enabled Wake-up + interrupt (if interrupt is enabled) + next instruction TCC overflow interrupt Comparator interrupt PWM (When TMR matches PRD) Green Mode Normal Mode Note: 1. If interrupt is enabled → interrupt+ next instruction 2. If interrupt is disabled → next instruction Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 25 EM78P163N 8-Bit Microcontroller with OTP ROM Signal Sleep Mode Normal Mode DISI + IOCF0 (TCIE) Bit 0 = 1 TCC Overflow Next Instruction+ Set RF (TCIF) = 1 N/A ENI + IOCF0 (TCIE) Bit 0 = 1 Interrupt Vector (0x09 )+ Set RF (TCIF) = 1 RE (ICWE) Bit 1 = 0, IOCF0 (ICIE) Bit 1 = 0 Oscillator, TCC and TIMERX are stopped. Port 6 input status change wake up is invalid. RE (ICWE) Bit 1 = 0, IOCF0 (ICIE) Bit 1 = 1 IOCF0 (ICIE) Bit 1 = 0 Port 6 input status change interrupt is invalid − Set RF (ICIF) = 1, Oscillator, TCC and TIMERX are stopped. Port 6 input status change wake up is invalid. − Port 6 Input Status RE (ICWE) Bit 1 = 1, IOCF0 (ICIE) Bit 1 = 0 − Change Wake-up+ Next Instruction Oscillator, TCC and TIMERX are stopped. RE (ICWE) Bit 1 = 1, DISI + IOCF0 (ICIE) Bit 1 = 1 − DISI + IOCF0 (ICIE) Bit 1 = 1 Wake-up+ Next Instruction+ Set RF (ICIF) = 1 Oscillator, TCC and TIMERX are stopped. Next Instruction+ Set RF (ICIF) = 1 RE (ICWE) Bit 1=1, ENI + IOCF0 (ICIE) Bit 1 = 1 ENI + IOCF0 (ICIE) Bit 1 = 1 Wake-up+ Interrupt Vector (0x06 )+ Set RF (ICIF)=1 Interrupt Vector (0x06 )+ Set RF (ICIF)=1 Oscillator, TCC and TIMERX are stopped. DISI + IOCF0 (EXIE) Bit 3 = 1 INT Pin Next Instruction+ Set RF (EXIF) = 1 N/A ENI + IOCF0 (EXIE) Bit 3 = 1 Interrupt Vector (0x03 )+ Set RF (EXIF)=1 DISI + IOCF0 (PWMIE)=1 PWM (When TMR matches Next Instruction+ Set RF (PWMIF) = 1 N/A ENI + IOCF0 (PWMIE)=1 PRD) Interrupt Vector (0x0F)+ Set RF (PWMIF) = 1 RE (CMPWE) Bit 2 = 0, IOCF0 (CMPIE) Bit 2 = 0 IOCF0 (CMPIE) Bit 7 = 0 Comparator output status change wake-up is invalid. Comparator output status change interrupt is invalid. Oscillator, TCC and TMR are stopped. RE (CMPWE) Bit 2 = 0, IOCF0 (CMPIE) Bit 2 = 1 Comparator Set RF (CMPIF) = 1, Comparator output status change wake up is invalid. Oscillator, TCC and TMR are stopped. RE (CMPWE) Bit 2 = 1, IOCF0 (CMPIE) Bit 2 = 0 (Comparator Output Wake-up+ Next Instruction, Oscillator, TCC and TMR are stopped. Status Change) RE (CMPWE) Bit 2=1, DISI + IOCF0 (CMPIE) Bit 2 = 1 DISI + IOCF0 (CMPIE) Bit 7 = 1 Wake-up+ Next Instruction+ Set RF (CMPIF) = 1, Oscillator, TCC and TMR are stopped. Next Instruction+ Set RF (CMPIF) = 1 RE (CMPWE) Bit 2 = 1, ENI + IOCF0 (CMPIE) Bit 2 = 1 ENI + IOCF0 (CMPIE) Bit 7 = 1 Wake-up+ Interrupt Vector (0x0C)+ Set RF (CMPIF)=1 Interrupt Vector (0x0C)+ Set RF (CMPIF) = 1 Oscillator, TCC and TMR are stopped. WDT Time Out IOCE (WDTE) Wake-up+ Reset (Address 0x00) Reset (Address 0x00) Bit 7 = 1 26 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM Table 5-2 Summary of the Initialized Register Values Address N/A N/A 0×05 0×06 0×07 N/A 0×00 Name IOC5 IOC6 P5 P6 R7 (TBLP) CONT R0 (IAR) Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name × × C55 C54 C53 C52 C51 C50 Power-on 0 0 1 1 1 1 1 1 /RESET and WDT 0 0 1 1 1 1 1 1 Wake-up from Pin Change 0 0 P P P P P P Bit Name C67 C66 C65 C64 C63 C62 C61 C60 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name × × P55 P54 P53 P52 P51 P50 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P Bit Name P67 P66 P65 P64 P63 P62 P61 P60 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P Bit Name − − − − − − − − Power-on U U U U U U U U /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P Bit Name INTE INT TS TE PSTE PST2 PST1 PST0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P 0 P P P P P P Bit Name − − − − − − − − Power-on U U U U U U U U /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 27 EM78P163N 8-Bit Microcontroller with OTP ROM Address 0×01 0×02 0×03 0×04 ~0×09 0×0A Name R1 (TCC) R2 (PC) R3 (SR) R4 (RSR) R9 RA (PWMCON) Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name − − − − − − − − Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name − − − − − − − − Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P N P P P Bit Name RST GP1 GP0 T P Z DC C Power-on 0 0 0 1 1 U U U /RESET and WDT 0 0 0 t t P P P Wake-up from Pin Change 1 P P t t P P P Bit Name GP1 GP0 − − − − − − Power-on U U U U U U U U /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P Bit Name − − − − − − − − Power-on U U U U U U U U /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P Bit Name − − − PWME TEN TP2 TP1 TP0 Power-on − − − 0 0 0 0 0 /RESET and WDT − − − 0 0 0 0 0 Wake-up from Pin Change − − − P P P P P Bit Name 0×0B 28 • RB (CMPCON I ) ACOS1 ACOS0 BCOS1 BCOS0 CCOS1 CCOS0 DCOS1 DCOS0 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM Address 0×0C Name Bit 7 Bit 6 Bit 5 Bit Name CRS CIRL2 CIRL1 Power-on 0 0 0 0 0 0 0 0 (CMPCON II) /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P IDLE − − − − − RC Reset Type Bit Name 0×0D 0×0E 0×0F N/A RD (SCR) RE (WUCR) RF (ISR) IOC7 (TMRH) IOC8 (TMRL) N/A (PRDL) CIRL0 CPOUT Bit 2 COE Bit 1 Bit 0 CRCS1 CRCS0 0 1 1 0 0 0 0 0 /RESET and WDT 0 1 1 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name − − − − − Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name − − - PWMIF EXIF CMPIF ICIF TCIF Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name − − DT[9] DT[8] Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P CMPWE ICWE TMR[9] TMR[8] PRD[9] PRD[8] − TMR[7] TMR[6] TMR[5] TMR[4] TMR[3] TMR[2] TMR[1] TMR[0] Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name IOC9 Bit 3 Power-on Bit Name N/A TIMERSC CPUS Bit 4 PRD[7] PRD[6] PRD[5] PRD[4] PRD[3] PRD[2] PRD[1] PRD[0] Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 29 EM78P163N 8-Bit Microcontroller with OTP ROM Address N/A N/A N/A N/A N/A N/A 0×10 ~0×3F Name IOCA (DTL) IOCB IOCC (ODCR) IOCD (PHCR) IOCE (WDTCR) IOCF (IMR) R10~R3F Legend : × : Not used 30 • Reset Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit Name DT[7] DT[6] DT[5] DT[4] DT[3] DT[2] DT[1] DT[0] Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name × /PD62 /PD61 /PD60 /PD53 /PD52 /PD51 /PD50 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name OD67 OD66 OD65 OD64 × OD62 OD61 OD60 Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name /PH67 /PH66 /PH65 /PH64 × /PH62 /PH61 /PH60 Power-on 1 1 1 1 1 1 1 1 /RESET and WDT 1 1 1 1 1 1 1 1 Wake-up from Pin Change P P P P P P P P Bit Name WDTE EIS PSW1 PSW0 − − Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name − − − PWMIE EXIE CMPIE ICIE TCIE Power-on 0 0 0 0 0 0 0 0 /RESET and WDT 0 0 0 0 0 0 0 0 Wake-up from Pin Change P P P P P P P P Bit Name − − − − − − − − Power-on U U U U U U U U /RESET and WDT P P P P P P P P Wake-up from Pin Change P P P P P P P P U : Unknown or don’t care PSWE PSW2 P : Previous value before reset − : not defined Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.5.3 /RESET Configure Refer to Figure 5-8 when the reset bit in the Option word is programmed to 0, the external /RESET is enabled. When programmed to 1, the internal /RESET is enabled, tied to the internal Vdd and the pin is defined as P63. 5.5.4 Status of RST, T, and P of the Status Register A reset condition is initiated by the following events: 1. Power-on condition 2. High-low-high pulse on /RESET pin 3. Watchdog timer time-out The values of RST, T and P, listed in Table 5-2 are used to check how the processor wakes up. Table 5-4 shows the events which may affect the status of RST, T and P. Table 5-3 Values of RST, T and P after Reset Reset Type RST T P Power on 0 1 1 /RESET during Operating mode 0 *P *P /RESET wake-up during Sleep mode 0 1 0 WDT during Operating mode 0 0 P WDT wake-up during Sleep mode 0 0 0 Wake-up on pin change during Sleep mode 1 1 0 *P: Previous status before reset Table 5-4 Status of RST, T and P being Affected by Events Event RST T P Power on 0 1 1 WDTC instruction *P 1 1 WDT time-out 0 0 *P SLEP instruction *P 1 0 Wake-up on pin change during Sleep mode 1 1 0 *P: Previous value before reset Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 31 EM78P163N 8-Bit Microcontroller with OTP ROM VDD D CLK Oscillator Q CLK CLR Power-on Reset Voltage Detector WDTE WDT WDT Timeout Setup Time RESET /RESET Figure 5-9 Controller Reset Block Diagram 5.6 Interrupt The EM78P163N has five interrupts as listed below: (1) TCC overflow interrupt (2) Port 6 Input Status Change Interrupt (3) External interrupt [(P60, /INT) pin] (4) When TMR matches with PRD respectively in PWM (5) When the comparators output changes Before the Port 6 Input Status Changed Interrupt is enabled, reading Port 6 (e.g. "MOV R6, R6") is necessary. Each pin of Port 6 will have this feature if its status changes. Any pin configured as output or P60 pin configured as /INT, is excluded from this function. The Port 6 Input Status Changed Interrupt can wake up the EM78P163N from sleep mode if Port 6 is enabled prior to going into sleep mode by executing SLEP instruction. When the device wakes-up, the controller will continue to execute the program in-line if the global interrupt is disabled. If the global interrupt is enabled, it will branch to the interrupt Vector 006H. 32 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM RF is the interrupt status register that records the interrupt requests in the relative flags/bits. IOCF is an interrupt mask register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (enabled) occurs, the next instruction will be fetched from interrupt vector address. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine and before interrupts are enabled to avoid recursive interrupts. The flag (except ICIF bit) in the Interrupt Status Register (RF) is set regardless of the status of its mask bit or the execution of ENI. Note that the outcome of RF will be the logic AND of RF and IOCF (refer to Figure 5-9). The RETI instruction ends the interrupt routine and enables the global interrupt (execution of ENI). When an interrupt is generated by the Timer clock / counter (if enabled), the next instruction will be fetched from Address 009H, and 00FH (TCC, Timer 1 respectively). Before an interrupt subroutine is executed, the contents of ACC and the R3 and R4 registers will be saved by the hardware. If another interrupt occurs, the ACC, R3, and R4 will be replaced by the new interrupt. After the interrupt service routine is completed, the ACC, R3, and R4 registers are restored. Interrupt sources ACC Interrupt occurs STACKACC ENI/DISI R3 RETI R4 STACKR3 STACKR4 Figure 5-10 Interrupt Backup Diagram In EM78P163N, each individual interrupt source has its own interrupt vector as depicted in the table below. Interrupt Vector Interrupt Status Priority* 003H External interrupt 1 006H Port 6 pin change 2 009H TCC overflow interrupt 3 00CH Comparator interrupt 4 00FH Timer 1 (PWM) overflow interrupt 5 *Priority : 1 = highest ; 5 = lowest priority Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 33 EM78P163N 8-Bit Microcontroller with OTP ROM VCC P R D /IRQn CLK C L Q IRQn INT _ Q IRQm RFRD RF ENI/DISI IOCF Q P R _ Q C L IOD D CLK IOCFWR /RESET IOCFRD RFWR Figure 5-11 Interrupt input Circuit 5.7 PWM (Pulse Width Modulation) 5.7.1 Overview In PWM mode, PWM pins produce up to a 10-bit resolution PWM output (see the functional block diagram below). A PWM output consists of a time period and a duty cycle, and it keeps the output high. The baud rate of the PWM is the inverse of the time period. Figure 5-13 PWM Output Timing depicts the relationships between a time period and a duty cycle. TO PWMIF latch DTH+DTL DLH+DLL Fosc Duty match Comparator 1:1 1:2 1:4 1:8 1:16 1:64 1:128 1:256 PWM TMRH+TMRL MUX reset R S Q PWME Comparator Period match TP2 TP1 TP0 TEN PRD Data bus Figure 5-12 PWM Functional Block Diagram 34 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM Period Duty Cycle PRD1 = TMR1 DT1 = TMR1 Figure 5-13 PWM Output Timing 5.7.2 Increment Timer Counter (TMRX: TMRH/TMRL) TMRX are 10-bit clock counters with programmable prescalers. They are designed for the PWM module as baud rate clock generators. TMRX can be read only. If employed, they can be turned off for power saving by setting the T1EN Bit [RB<3>] to 0. 5.7.3 PWM Time Period (PRDX: TMRH/PRDL) The PWM time period is defined by writing to the PRDL register. When TMRX is equal to PRDX, the following events occur on the next increment cycle: TMRX is cleared The PWMX pin is set to 1 The PWM duty cycle is latched from DT to DTL NOTE The PWM output will not be set if the duty cycle is 0. The PWMIF pin is set to 1 The following formula describes how to calculate the PWM Time Period: Period = (PRDX + 1) ⎛ 1 × ⎜⎜ ⎝ FOSC ⎞ ⎟⎟ × (TMRX prescale value) ⎠ Example: PRDX = 49; Fosc = 4 MHz; TMRX (0, 0, 0) = 1 : 1, Then ⎛ 1 ⎞ Period = (49 + 1) × ⎜ ⎟ × = 12.5 μs ⎝ 4M ⎠ Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 35 EM78P163N 8-Bit Microcontroller with OTP ROM 5.7.4 PWM Duty Cycle (DTX: TMRH/DTL) The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared. DTX can be loaded anytime. However, it cannot be latched into DLX until the current value of DLX is equal to TMRX. The following formula describes how to calculate the PWM duty cycle: Duty cycle = (DTX ) ⎛ 1 × ⎜⎜ ⎝ FOSC ⎞ ⎟⎟ × (TMRX prescale value ) ⎠ Example: DTX = 10; Fosc = 4 MHz; TMRX (0, 0, 0) = 1 : 1, Then ⎛ 1 ⎞ Duty cycle = (10) × ⎜ ⎟ × = 2.5 μs ⎝ 4M ⎠ 5.7.5 Comparator Changing the output status while a match occurs will set the TMRIF flag at the same time. 5.7.6 PWM Programming Process/Steps Load PRD with the PWM time period. 1. Load DT with the PWM Duty Cycle. 2. Enable interrupt function by writing IOCF0, if required. 3. Set PWMX pin to be output by writing a desired value to RB. 4. Load a desired value to IOC9 with TMR prescaler value and enable both PWM and TMR. 5.8 Timer 5.8.1 Overview The Timer (TMRX) is a 10-bit clock counter with programmable prescalers. It is designed for the PWM module as baud rate clock generator. TMRX can be read only. The Timer will stop running when sleep mode occurs. 36 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.8.2 Function Description The following figure shows the TMRX block diagram followed by descriptions of its signals and blocks: Figure 5-14 TMRX Block Diagram Fosc: Input clock. Prescaler (TP2, TP1 and TP0 ): The Options 1:1, 1:2, 1:4, 1:8, 1:16, 1:64, 1:128, and 1:256 are defined by TMR. It is cleared when any type of reset occurs. TMR (TMRH/TMRL): Timer register; TMR is increased until it matches with PRD, and then it is reset to 1 (default valve). PRD: PWM time period register. Comparator: Reset TMR while a match occurs. The TMRIF flag is set at the same time. 5.8.3 Programming the Related Registers When defining TMR, refer to the operation of its related registers as shown in the table below. It must be noted that the PWM bits must be disabled if their related TMR are employed. That is, Bit 4 of the PWMCON register must be set to ‘0’. 5.8.3.1 Addr. 0x0B TMR Related Control Registers Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWMCON/RB CPOUT COS1 COS0 PWME TEN TP2 TP1 TP0 5.8.4 Timer Programming Process/Steps 1. Load PRD with the Timer duration 2. Enable interrupt function by writing IOCF0, if required 3. Load a desired TMR prescaler value to PWMCON, enable TMR and disable PWM Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 37 EM78P163N 8-Bit Microcontroller with OTP ROM 5.9 Comparator The EM78P163N has one comparator comprising of five analog inputs and one output. The comparator can be utilized to wake up the EM78P163N from sleep mode. The comparator circuit diagram is depicted in the figure below. CinA-/P62 CinChannel Switch CinB-/P66 CinC-/P67 CO CMP CinD-/P50 + Cin+/P61 Cin+ Cin10mV 10mV CO Figure 5-15 Comparator Circuit Diagram and Operating Mode 5.9.1 External Reference Signal The analog signal that is presented at CinX– compares to the signal at Cin+, and the digital output (CO) of the comparator is adjusted accordingly by taking the following notes into considerations: NOTE 38 • ■ The reference signal must be between Vss and Vdd. ■ The reference voltage can be applied to either pin or comparator. ■ Threshold detector applications may be of the same reference. ■ The comparator can operate from the same or different reference sources. Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.9.2 Comparator Outputs The compared result is stored in the CPOUT of RB. The comparator outputs are sent to CO (P60) by programming Bit 1, Bit 0 <COS1, COS0> of the RB register to <1, x>. See Section 6.2.6, RB for Comparator select bits function description. NOTE ■ The CO and PWM of the P60/INT/CO pins cannot be used at the same time. ■ The P60/INT/CO pin priority is as follows: P60/INT/CO Priority High Medium Low CO INT P60 The following figure shows the Comparator Output block diagram. To C0 F r o m O P I/O CMRD EN Q EN D Q D To CM PO UT RESET T o C P IF CMRD F r o m o th e r c o m p a r a to r Figure 5-16 Comparator Output Configuration 5.9.3 Comparator Interrupt CMPIE (IOCF0.3) must be enabled for the “ENI” instruction to take effect. Interrupt is triggered whenever a change occurs on the comparator output pin. The actual change on the pin can be determined by reading the Bit CPOUT, RB<2>. CMPIF (RF.3), the comparator interrupt flag, can only be cleared by software. Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 39 EM78P163N 8-Bit Microcontroller with OTP ROM 5.9.4 Wake-up from Sleep Mode If enabled, the comparator remains active and the interrupt remains functional, even in Sleep mode. If a mismatch occurs, the interrupt will wake up the device from Sleep mode. Power consumption should be taken into consideration for the benefit of energy conservation. If the function is not implemented during Sleep mode, turn off the comparator before entering into sleep mode. 5.10 Oscillator 5.10.1 Oscillator Modes The EM78P163N can be operated in four different oscillator modes, such as High Crystal oscillator mode (HXT), Low Crystal oscillator mode (LXT), External RC oscillator mode (ERC), and RC oscillator mode with Internal RC oscillator mode (IRC). One of the four modes can be selected by programming the OSC3, OSC2, OCS1, and OSC0 in the Code Option register. The Oscillator modes defined by OSC3, OSC2, OCS1, and OSC0 are described below. Oscillator Modes OSC3 OSC2 OSC1 OSC0 1 0 0 0 0 1 ERC (External RC oscillator mode); P64/OSCO funcions as P64 ERC (External RC oscillator mode); P64/OSCO functions as OSCO 0 0 0 1 2 0 0 1 0 2 IRC (Internal RC oscillator mode); P64/OSCO functions as OSCO 0 0 1 1 LXT1 (Frequency range of LXT1 mode is 100kHz ~ 1 MHz) 0 1 0 0 IRC (Internal RC oscillator mode); P64/OSCO functions as P64 HXT1 (Frequency range of HXT mode is 12 MHz ~ 20 MHz) 0 1 0 1 LXT2 (Frequency range of XT mode is 32kHz) 0 1 1 0 HXT2 (Frequency range of XT mode is 6 MHz ~ 12 MHz) 0 1 1 1 XT (Frequency range of XT mode is 1 MHz ~ 6 MHz) (default) 1 1 1 1 1 In ERC mode, OSCI is used as oscillator pin. OSCO/P64 is defined by Code Option Word 0 Bit 9 ~ Bit 6. 2 In IRC mode, P65 is normal I/O pin. OSCO/P64 is defined by Code Option Word 0 Bit 9 ~ Bit 6. The maximum operating frequency limit of the crystal/resonator at different VDDs, are as follows: Conditions VDD Max. Freq. (MHz) 2.3 4 4.5 16 Two clocks 40 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.10.2 Crystal Oscillator/Ceramic Resonator (Crystal) The EM78P163N can be driven by an external clock signal through the OSCO pin as illustrated below. Ext. Clock OSCI OSCO Figure 5-17 External Clock Input Circuit In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Figure 5-18 depicts such a circuit. The same applies to the HXT mode and the LXT mode. C1 OSCI Crystal OSCO RS C2 Figure 5-18 Crystal/Resonator Circuit The following table provides the recommended values for C1 and C2. Since each resonator has its own attribute, refer to the resonator specifications for appropriate values of C1 and C2. RS, a serial resistor, may be required for AT strip cut crystal or low frequency mode. Capacitor selection guide for crystal oscillator or ceramic resonators: Oscillator Type Frequency Mode Ceramic Resonators HXT LXT Crystal Oscillator HXT Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) Frequency 455kHz 2.0 MHz 4.0 MHz 32.768kHz 100kHz 200kHz 455kHz 1.0 MHz 2.0 MHz 4.0 MHz C1 (pF) 100~150 20~40 10~30 25 25 25 20~40 15~30 15 15 C2 (pF) 100~150 20~40 10~30 15 25 25 20~150 15~30 15 15 • 41 EM78P163N 8-Bit Microcontroller with OTP ROM 5.10.3 External RC Oscillator Mode For some applications that do not require precise timing calculation, the RC oscillator (Figure 5-19) offers an effective cost savings. Nevertheless, it should be noted that the frequency of the RC oscillator is influenced by the supply voltage, the values of the resistor (Rext), the capacitor (Cext), and even by the operation temperature. Moreover, the frequency also changes slightly from one chip to another due to manufacturing process variations. Vcc Rext OSCI Cext Figure 5-19 External RC Oscillator Mode Circuit In order to maintain a stable system frequency, the values of the Cext should be no less than 20pF, and the value of Rext should not be greater than 1 MΩ. If the frequency cannot be kept within this range, it can be affected easily by noise, humidity, and leakage. The smaller the Rext in the RC oscillator is, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 KΩ, the oscillator will become unstable because the NMOS cannot discharge the capacitance current correctly. Based on the above reasons, it must be kept in mind that all supply voltage, operation temperature, components of the RC oscillator, package type, and PCB layout, have certain effect on the system frequency. 42 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM The RC Oscillator frequencies: Cext 20 Pf 100 Pf 300 Pf Rext Average Fosc 5V, 25°C Average Fosc 3V, 25°C 3.3k 3.5 MHz 3.0 MHz 5.1k 2.4 MHz 2.2 MHz 10k 1.27 MHz 1.24 MHz 100k 140kHz 143kHz 3.3k 1.21 MHz 1.18 MHz 5.1k 805kHz 790kHz 10k 420kHz 418kHz 100k 45kHz 46kHz 3.3k 550kHz 526kHz 5.1k 364kHz 350kHz 10k 188kHz 185kHz 100k 20kHz 20kHz 1 Note: : Measured based on DIP packages. 2 : The values are for design reference only. 3 : The frequency drift is ± 30% 5.10.4 Internal RC Oscillator Mode The EM78P163N offers a versatile internal RC mode with default frequency value of 4 MHz. Internal RC oscillator mode has other frequencies (16 MHz, 8 MHz, and 455kHz) that can be set by Code Option (Word 1), RCM1, and RCM0. The Table below describes the EM78P163N internal RC drift with voltage, temperature, and process variations. Internal RC Drift Rate (Ta=25°C, VDD=5V±5%, VSS=0V) Internal RC Frequency Drift Rate Temperature (-40°C ~ +85°C) Voltage (2.3V~5.5V) Process Total 16 MHz ± 6% ± 5% ± 3% ± 14% 8 MHz ± 5% ± 5% ± 3% ± 13% 4 MHz ± 5% ± 5% ± 3% ± 13% 455kHz ± 5% ± 5% ± 3% ± 13% Note : These are theoretical values which are provided for reference only. Actual values may vary depending on the actual process. Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 43 EM78P163N 8-Bit Microcontroller with OTP ROM Table 5-5 Calibration Selection for Internal RC Mode C4 C3 C2 C1 C0 *Frequency (MHz) 0 0 0 0 0 (1-24.2%) x F 0 0 0 0 1 (1-23.1%) x F 0 0 0 1 0 (1-21.9%) x F 0 0 0 1 1 (1-20.6%) x F 0 0 1 0 0 (1-19.4%) x F 0 0 1 0 1 (1-18%) x F 0 0 1 1 0 (1-16.7%) x F 0 0 1 1 1 (1-15.3%) x F 0 1 0 0 0 (1-13.8%) x F 0 1 0 0 1 (1-12.3%) x F 0 1 0 1 0 (1-10.7%) x F 0 1 0 1 1 (1-9.1%) x F 0 1 1 0 0 (1-7.4%) x F 0 1 1 0 1 (1-5.7%) x F 0 1 1 1 0 (1-3.8%) x F 0 1 1 1 1 (1-2%) x F 1 1 1 1 1 F (default) 1 1 1 1 0 (1+2%) x F 1 1 1 0 1 (1+4.2%) x F 1 1 1 0 0 (1+6.4%) x F 1 1 0 1 1 (1+8.7%) x F 1 1 0 1 0 (1+11.1%) x F 1 1 0 0 1 (1+13.6%) x F 1 1 0 0 0 (1+16.3%) x F 1 0 1 1 1 (1+19%) x F 1 0 1 1 0 (1+22%) x F 1 0 1 0 1 (1+25%) x F 1 0 1 0 0 (1+28.2%) x F 1 0 0 1 1 (1+31.6%) x F 1 0 0 1 0 (1+35.1%) x F 1 0 0 0 1 (1+38.9%) x F 1 0 0 0 0 (1+42.9%) x F * These are theoretical values which are provided for reference only. Actual values may vary depending on the actual process. 44 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.11 Power-on Considerations Any microcontroller is not warranted to start operating properly before the power supply has stabilized to a steady state. The EM78P163N has a built-in Power-on Reset (POR) with reset level range of 1.7V to 1.9V. The circuitry eliminates the extra external reset circuit. It will work well if Vdd rises quickly enough (50 ms or less). However, under critical applications, extra devices are still required to assist in solving power-on problems. 5.11.1 External Power-on Reset Circuit The circuits shown in the VDD figure implement an external RC to produce a /RESET R reset pulse. The pulse D width (time constant) should be kept long enough to Rin allow Vdd to reach the C minimum operating voltage. This circuit is used when the power supply has a slow Figure 5-20 External Power-on Reset Circuit power rise time. Because the current leakage from the /RESET pin is ± 5 μA, it is recommended that R should not be greater than 40K. This way, the voltage at Pin /RESET is held below 0.2V. The diode (D) functions as a short circuit at power-down. The “C” capacitor is discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD (electrostatic discharge) from flowing into Pin /RESET. Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 45 EM78P163N 8-Bit Microcontroller with OTP ROM 5.11.2 Residual Voltage Protection When the battery is replaced, device power (Vdd) is removed but residual voltage remains. The residual voltage may trip below Vdd minimum, but not to zero. This condition may cause a poor power-on reset. Figure 5-21 and Figure 5-22 show how to create a protection circuit against residual voltage. VDD VDD 33K Q1 10K /RESET 100K 1N4684 Figure 5-21 Residual Voltage Protection Circuit 1 VDD VDD R1 Q1 /RESET R2 R3 Figure 5-22 Residual Voltage Protection Circuit 2 5.12 Code Option Register The EM78P163N has Code Option words that are not part of the normal program memory. The option bits cannot be accessed during normal program execution. Code Option Register and Customer ID Register arrangement distribution: 46 • Word 0 Word 1 Word 2 Bit 12~Bit 0 Bit 12~Bit 0 Bit 12~Bit 0 Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 5.12.1 Code Option Register (Word 0) Word 0 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Mnemonic 0 CLKS TYPE1 1 - 4CLKS High High High High 0 - 2LCKS Low Low Low Bit 6 Bit 5 TYPE0 LVR1 LVR0 RESETDG Low Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ENWDT NRHL NRE PR2 PR1 PR0 Disable Disable 32/fc Disabl e Disable Enable Enable Enabl e Enable Bit 12: Unused bit, set to 0 all the time Bit 11 (CLKS): Instruction period selection bit 8/fc 0 : Two oscillator periods 1 : Four oscillator periods Refer to the Instruction Set section. Bits 10 ~ 9 (TYPE1 ~ TYPE0): Type selection for EM78P163N TYPE1, TYPE0 Selection No. 1X EM78P163N-16pin 01 EM78P163N-14pin 00 Reserved Bits 8 ~ 7 (LVR1 ~ LVR0): Low Voltage Reset enable bits LVR1, LVR0 VDD Reset Level 11 VDD Release Level NA (Power-on Reset) 10 2.4V 2.6V 01 3.3V 3.5V 00 4.0V 4.2V Bit 6 (RESETDG): Reset pin delete glitch function 0: Enable 1: Disable Bit 5 (ENWDT): Watchdog timer enable bit. 0: Enable Watchdog timer 1: Disable Watchdog timer NOTE This bit must enable the WDTE reg. (IOCE reg). Bit 7 must be disabled when Port 6 pin change wake-up function is used. Bit 4 (NRHL): Noise rejection high/low pulse defined bit 0 : Pulses equal to 8/fc [s] is regarded as signal 1 : Pulses equal to 32/fc [s] is regarded as signal Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 47 EM78P163N 8-Bit Microcontroller with OTP ROM Noise rejection enable bit Bit 3 (NRE): 0 : Disable noise rejection 1 : Enable noise rejection Bits 2 ~ 0 (PR2 ~ PR0): Protect Bits 5.12.2 Code Option Register (Word 1) Word 1 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Mnemonic HLP C4 C3 C2 C1 C0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCM1 RCM0 OSC3 OSC2 OSC1 OSC0 RCOUT 1 Low High High High High High High High High High High High System clock 0 High Low Low Low Low Low Low Low Open drain Low Low Low Low High/Low power mode Bit 12 (HLP): 0 : Low power mode 1 : High power mode (default) Bits 11 ~ 7 (C4 ~ C0): Calibrator of internal RC mode. These bits must always be set to “1” only (auto calibration) Bits 6 ~ 5 (RCM1 ~ RCM0): RC mode select bits RCM 1 RCM 0 Frequency (MHz) 1 1 4 1 0 16 0 1 8 0 0 455kHz Bits 4~1 (OSC3 ~ OSC0): Oscillator mode select bits Oscillator Modes OSC3 OSC2 OSC1 OSC0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 ERC (External RC oscillator mode); P64/OSCO funcions as P64 ERC (External RC oscillator mode); P64/OSCO functions as OSCO 2 IRC (Internal RC oscillator mode); P64/OSCO functions as P64 2 48 • IRC (Internal RC oscillator mode); P64/OSCO functions as OSCO 0 0 1 1 LXT1 (Frequency range of LXT1 mode is 100kHz ~ 1 MHz) 0 1 0 0 HXT1 (Frequency range of HXT mode is 12 MHz ~ 20 MHz) 0 1 0 1 LXT2 (Frequency range of XT mode is 32kHz) 0 1 1 0 HXT2 (Frequency range of XT mode is 6 MHz ~ 12 MHz.) 0 1 1 1 XT (Frequency range of XT mode is 1 MHz ~ 6 MHz) (default) 1 1 1 1 Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM Bit 0 (RCOUT): Select bit of Oscillator output or I/O port. RCOUT 5.12.3 Pin Function 0 OSCO pin is open drain 1 OSCO output system clock (default) Customer ID Register (Word 2) Word 2 Bit Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 RESETEN EFT_SEL SUT0 Mnemonic 1 1 CMP_DE 1 1 - - High - P63 Long 0 - - Low - /RST Short Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 1 1 1 1 1 18ms - - - - - - 4.5ms - - - - - - Bit 12 (Unused): Unused bit, set to 1 all the time Bit 11 (Unused): Unused bit, set to 1 all the time Bit 10 (CMP_DE): Comparator de-glitch enable bit 0 : Disable 1 : Enable Bit 9 (Unused): Unused bit, set to 1 all the time Bit 8 (RESETEN): P63//RST pin select bit 0 : P63//RST set to /RST pin 1 : P63//RST set to P63 pin Bit 7 (EFT_SEL): EFT hold time selection 0 : Short hold time 8 µs × 16 1 : Long hold time 8 µs × 64 Bit 6 (SUT0): Set up time select bit 0 : 4.5 ms 1 : 18 ms Bit 5 ~ Bit 0: Unused bit, set to 1 all the time Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 49 EM78P163N 8-Bit Microcontroller with OTP ROM 5.13 Instruction Set Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A", "ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6", "CLR R2", etc.). In this case, the execution takes two instruction cycles. If for some reasons, the specification of the instruction cycle is not suitable for certain applications, try modifying the instruction as follows: (A) Modify one instruction cycle to consist of 4 oscillator periods. (B) Execute within two instruction cycles the "JMP", "CALL", "RET", "RETL", "RETI" commands, or the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") which were tested to be true. The instructions that are written to the program counter, should also take two instruction cycles. Case (A) is selected by the Code Option bit, called CLKS. One instruction cycle will consist of two oscillator clocks if CLKS is Low, and four oscillator clocks if CLKS is high. Note that once the 4 oscillator periods within one instruction cycle is selected under Case (A), the internal clock source to TCC should be CLK=Fosc/4 , instead of Fosc/2 as illustrated in Figure 5-3. In addition, the instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operate on the I/O register. 50 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM Convention: R = Register designator that specifies which one of the registers (including operation and general purpose registers) is to be utilized by the instruction. b = Bit field designator that selects the value for the bit located in the register R and which affects the operation. k = 8 or 10-bit constant or literal value Binary Instruction Hex Mnemonic 0 0000 0000 0000 0000 NOP No Operation 0 0000 0000 0001 0001 DAA Decimal Adjust A 0 0000 0000 0010 0002 CONTW A → CONT None 0 0000 0000 0011 0003 SLEP 0 → WDT, Stop oscillator T, P 0 0000 0000 0100 0004 WDTC 0 → WDT T, P 0 0000 0000 rrrr 000r IOW R A → IOCR None1 0 0000 0001 0000 0010 ENI Enable Interrupt None 0 0000 0001 0001 0011 DISI Disable Interrupt None 0 0000 0001 0010 0012 RET [Top of Stack] → PC None 0 0000 0001 0011 0013 RETI [Top of Stack] → PC, Enable Interrupt None 0 0000 0001 0100 0014 CONTR CONT → A None 0 0000 0001 rrrr 001r IOR R IOCR → A None1 0 0000 01rr rrrr 00rr MOV R,A A→R None 0 0000 1000 0000 0080 CLRA 0→A Z 0 0000 11rr rrrr 00rr CLR R 0→R Z 0 0001 00rr rrrr 01rr SUB A,R R-A → A Z, C, DC 0 0001 01rr rrrr 01rr SUB R,A R-A → R Z, C, DC 0 0001 10rr rrrr 01rr DECA R R-1 → A Z 0 0001 11rr rrrr 01rr DEC R R-1 → R Z 0 0010 00rr rrrr 02rr OR A,R A ∨ VR → A Z 0 0010 01rr rrrr 02rr OR R,A A ∨ VR → R Z 0 0010 10rr rrrr 02rr AND A,R A&R→A Z 0 0010 11rr rrrr 02rr AND R,A A&R→R Z 0 0011 00rr rrrr 03rr XOR A,R A⊕R→A Z 0 0011 01rr rrrr 03rr XOR R,A A⊕R→R Z 0 0011 10rr rrrr 03rr ADD A,R A+R→A Z, C, DC 0 0011 11rr rrrr 03rr ADD R,A A+R→R Z, C, DC Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) Operation Status Affected None C • 51 EM78P163N 8-Bit Microcontroller with OTP ROM Binary Instruction Hex Mnemonic Operation Status Affected 0 0100 00rr rrrr 04rr MOV A,R R→A Z 0 0100 01rr rrrr 04rr MOV R,R R→R Z 0 0100 10rr rrrr 04rr COMA R /R → A Z 0 0100 11rr rrrr 04rr COM R /R → R Z 0 0101 00rr rrrr 05rr INCA R R+1 → A Z 0 0101 01rr rrrr 05rr INC R R+1 → R Z 0 0101 10rr rrrr 05rr DJZA R R-1 → A, skip if zero None 0 0101 11rr rrrr 05rr DJZ R R-1 → R, skip if zero None 0 0110 00rr rrrr 06rr RRCA R R(n) → A(n-1), R(0) → C, C → A(7) C 0 0110 01rr rrrr 06rr RRC R R(n) → R(n-1), R(0) → C, C → R(7) C 0 0110 10rr rrrr 06rr RLCA R R(n) → A (n+1), R(7) → C, C → A(0) C 0 0110 11rr rrrr 06rr RLC R R(n) → R (n+1), R(7) → C, C → R(0) C 0 0111 00rr rrrr 07rr SWAPA R R(0-3) → A (4-7), R(4-7) → A(0-3) 0 0111 01rr rrrr 07rr SWAP R R(0-3) ↔ R(4-7) None 0 0111 10rr rrrr 07rr JZA R R+1 → A, skip if zero None 0 0111 11rr rrrr 07rr JZ R R+1 → R, skip if zero None 0 100b bbrr rrrr 0xxx BC R,b 0 → R(b) None 2 0 101b bbrr rrrr 0xxx BS R,b 1 → R(b) None 3 0 110b bbrr rrrr 0xxx JBC R,b if R(b)=0, skip None 0 111b bbrr rrrr 0xxx JBS R,b if R(b)=1, skip None 1 00kk kkkk kkkk 1kkk CALL k PC+1 → [SP], (Page, k) → PC None 1 01kk kkkk kkkk 1kkk JMP k (Page, k) → PC None 1 1000 kkkk kkkk 18kk MOV A,k k→A None 1 1001 kkkk kkkk 19kk OR A,k A∨k→A Z 1 1010 kkkk kkkk 1Akk AND A,k A&k→A Z 1 1011 kkkk kkkk 1Bkk XOR A,k A⊕k→A Z 1 1100 kkkk kkkk 1Ckk RETL k k → A, [Top of Stack] → PC 1 1101 kkkk kkkk 1Dkk SUB A,k k-A → A 1 1110 0000 0001 1E01 INT PC+1 → [SP],001H → PC 1 1111 kkkk kkkk 1Fkk ADD A,k k+A → A 1 1110 11rr rrrr 1Err TBRD R If R8 Bit 7=0, Machine code (7:0) → R Else machine code (12:8) → R None None Z, C, DC None Z, C, DC None 1 Note: This instruction is applicable to IOC5~IOCF only. 2 This instruction is not recommended for RF operation. 3 This instruction cannot operate under RF. 52 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 6 Absolute Maximum Ratings Items Rating Temperature under bias -40°C to 85°C Storage temperature -65°C to 150°C Input voltage -0.3V to + 6.0V Output voltage -0.3V to + 6.0V Working Voltage 2.5V to 5.5V DC to 20 MHz Working Frequency 7 Electrical Characteristics 7.1 DC Electrical Characteristics Ta= 25°C, VDD= 5.0V ± 5%, VSS= 0V Symbol Max. Unit Fxt Crystal: VDD to 2.3V Parameter Two cycles with two clocks Condition Min. Typ. DC − 4.0 MHz Fxt Crystal: VDD to 3V Two cycles with two clocks DC − 8.0 MHz Fxt Crystal: VDD to 5V Two cycles with two clocks DC − 20.0 MHz ERC RC: VDD to 5V R: 5 KΩ, C: 39 pF IIL Input Leakage Current for input pins VIN = VDD, VSS VIH1 Input High Voltage (Schmitt Trigger) VIL1 Input Low Voltage (Schmitt Trigger ) VIHT1 F-30% 1500 F+30% kHz − − ±1 μA Ports 5, 6 0.7Vdd − Vdd+0.3V V Ports 5, 6 -0.3V − 0.3Vdd V Input High Threshold Voltage (VDD=5.0V) /RESET, TCC (Schmitt Trigger) 0.7Vdd − Vdd+0.3V V VILT1 Input Low Threshold Voltage (VDD=5.0V) /RESET, TCC (Schmitt Trigger) -0.3V − 0.3Vdd V VIHX1 Clock Input High Voltage (VDD=5.0V) OSCI 2.9 3.0 3.1 V VILX1 Clock Input Low Voltage (VDD=5.0V) OSCI 1.7 1.8 1.9 V VIHT2 Input High Threshold Voltage (VDD=3.0V) /RESET, TCC (Schmitt Trigger) 0.7Vdd − Vdd+0.3V V VILT2 Input Low Threshold Voltage (VDD=3.0V) /RESET, TCC (Schmitt Trigger) -0.3V − 0.3Vdd V -9 -12 − -6.5 -8 − 22 28 − mA Ta= 25°C 2.11 2.4 2.69 V Ta= -40~85°C 1.84 2.4 2.95 V Ta= 25°C 2.9 3.3 3.72 V Ta= -40~85°C 2.53 3.3 4.05 V Ta= 25°C 3.56 4.0 4.43 V Ta= -40~85°C 3.16 4.0 4.81 V IOH1 Output High Voltage (P50, P55, Port 6) Output High Voltage (P51~P54) IOL1 Output Low Voltage (Ports 5, 6) LVR1 Low voltage reset level LVR2 Low voltage reset level LVR3 Low voltage reset level Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) VOH = 0.9VDD VOL = 0.1VDD mA • 53 EM78P163N 8-Bit Microcontroller with OTP ROM Symbol Parameter Condition Min. Typ. Max. Unit IPH Pull-high current Pull-high active, input pin at VSS -70 -75 -80 μA IPL Pull-low current Pull-low active, input pin at Vdd 35 40 45 μA ISB1 Power down current All input and I/O pins at VDD, Output pin floating, WDT disabled 0.6 2.0 2.5 μA ISB2 Power down current All input and I/O pins at VDD, Output pin floating, WDT enabled 6 7 8 μA Operating supply current at two clocks /RESET= 'High', Fosc=32kHz (Crystal type, CLKS="0") Output pin floating, WDT enabled 25 27 29 μA ICC2 Operating supply current at two clocks /RESET= 'High', Fosc=4MHz (IRC type, CLKS="0"), Output pin floating, WDT enabled 1.2 1.4 1.6 mA ICC3 Operating supply current at two clocks /RESET= 'High', Fosc = 4 MHz (Crystal type, CLKS="0"), Output pin floating, WDT enabled 2.4 2.6 3 mA Operating supply current at two clocks /RESET= 'High', Fosc = 10 MHz (Crystal type, CLKS="0"), Output pin floating, WDT enabled 2.4 2.6 3 mA ICC1 ICC4 Internal RC Electrical Characteristics (Ta=25°C, VDD=5V, VSS=0V) Internal RC Drift Rate Temperature Voltage Min. Typ. Max. 4 MHz 25°C 5V 3.88 MHz 4 MHz 4.12 MHz 8 MHz 25°C 5V 7.76 MHz 8 MHz 8.24 MHz 16 MHz 25°C 5V 15.52 MHz 16 MHz 16.48 MHz 455kHz 25°C 5V 441.3kHz 455kHz 468.7kHz Internal RC Electrical Characteristics (Ta=-40 ~85°C, VDD=2.2~5.5 V, VSS=0V) Internal RC 54 • Drift Rate Temperature Voltage Min. Typ. Max. 4 MHz -40 ~85°C 2.2V~5.5V 3.48 MHz 4 MHz 4.52 MHz 8 MHz -40 ~85°C 2.2V~5.5V 6.96 MHz 8 MHz 9.04 MHz 16 MHz -40 ~85°C 2.2V~5.5V 13.92 MHz 16 MHz 18.08 MHz 455kHz -40 ~85°C 2.2V~5.5V 395.85kHz 455kHz 514.15kHz Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 7.2 Comparator Characteristics Vdd = 5.0V, Vss=0V, Ta=-40 to 85°C Symbol Parameter SR Slew rate Vos Input offset voltage IVR Input voltage range Condition Min. Typ. Max. Unit – 0.1 0.2 – V/µs 1 10 15 mV 0.5 − 4.5 V 0 0.2 0.3 4.7 4.8 5 – – 300 – µA – 2.5 – 5.5 V RL=5.1K, (Note 1) Vdd =5.0V, VSS = 0.0V Vd =5.0V, OVS Output voltage swing VSS = 0.0V, RL=10 KΩ Ico Vs Supply current of Comparator Operating range V Note: 1. These parameters are hypothetical (not tested), provided here for design reference use only. 2. These parameters are subject to change without prior notice. Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 55 EM78P163N 8-Bit Microcontroller with OTP ROM 7.3 AC Electrical Characteristics Ta=-40°C ~ 85°C, VDD=5V±5%, VSS=0V Symbol Dclk Tins Parameter Conditions Min Typ Max Unit Input CLK duty cycle − 45 50 55 % Instruction cycle time Crystal type 100 − DC ns (CLKS="0") RC type 500 − DC ns (Tins+20)/N* − − ns 17.6-30% 17.6 17.6+30% ms 2000 − − ns 17.6-30% 17.6 17.6+30% ms 4.5-30% 4.5 4.5+30% ms − Ttcc TCC input period Tdrh Device reset hold time TXAL, SUT1, SUT0=1,1 Trst /RESET pulse width Ta = 25°C Twdt1* Watchdog timer period Twdt2* Watchdog timer period Tset Input pin setup time − − 0 − ns Thold Input pin hold time − − 20 − ns Tdelay Output pin delay time Cload=20pF − 50 − ns Ta = 25°C Ta = 25°C SUT0=1 Ta = 25°C SUT0=0 Note: 1. N = selected prescaler ratio 2. Twdt1: The Option Word 1 (SUT1, SUT0) is used to define the oscillator set-up time. In Crystal mode, the WDT timeout length is the same as the set-up time (18ms). 3. Twdt2: The Option Word 1 (SUT1, SUT0) is used to define the oscillator set-up time. In Crystal mode, the WDT timeout length is the same as set-up time (4.5ms). 4. These parameters are hypothetical (not tested) and are provided for design reference only. 5. Data under Minimum, Typical, and Maximum (Min, Typ, and Max) columns are based on hypothetical results at 25°C. These data are for design reference use only. 6. The Watchdog timer duration is determined by Code Option Word 1 (Bit 6, Bit 5). 7.4 Device Characteristics The graphs provided in the following pages were derived based on a limited number of samples and are shown here for reference only. The device characteristics illustrated herein are not guaranteed for its accuracy. In some graphs, the data may be out of the specified warranted operating range. 56 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM P50/P60 Vih/Vil_VDD(25℃) 3.5 3.0 Vih/Vil (V) 2.5 2.0 VIH 1.5 VIL 1.0 0.5 0.0 2 2.2 2.5 3 3.5 4 4.5 5 5.5 VDD(V) Figure 7-1 Vih, Vil vs. VDD (25°C) P50/P60 Vih/Vil_VDD(-40℃) 3.5 3.0 Vih/Vil (V) 2.5 2.0 VIH VIL 1.5 1.0 0.5 0.0 2.2 2.5 3 3.5 4 4.5 5 5.5 VDD(V) Figure 7-2 Vih, Vil vs. VDD (-40 °C) Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 57 EM78P163N 8-Bit Microcontroller with OTP ROM P50/P60 Vih/Vil_VDD(85℃) 3.0 2.5 Vih/Vil (V) 2.0 VIH 1.5 VIL 1.0 0.5 0.0 2.2 2.5 3 3.5 4 4.5 5 5.5 VDD(V) Figure 7-3 Vih, Vil vs. VDD (85°C) Voh_Ioh (VDD=3V) 0.0 -2.0 -4.0 Ioh (mA) -6.0 85℃ -8.0 25℃ -10.0 -40℃ -12.0 -14.0 -16.0 -18.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 Voh (V) Figure 7-4 Voh vs. Ioh at VDD=3V 58 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM Voh_Ioh (VDD=5V) 0.0 -5.0 -10.0 Ioh (mA) -15.0 -20.0 -25.0 85℃ -30.0 25℃ -40℃ -35.0 -40.0 -45.0 -50.0 0.5 1 1.5 2 2.5 Voh (V) 3 3.5 4 4.5 Figure 7-5 Voh vs. Ioh at VDD=5V Vol_Iol (VDD=3V) 45.0 40.0 35.0 Iol (mA) 30.0 25.0 85℃ 20.0 25℃ -40℃ 15.0 10.0 5.0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 Vol (V) Figure 7-6 Vol vs. Iol at VDD=3V Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 59 EM78P163N 8-Bit Microcontroller with OTP ROM Vol_Iol (VDD=5V) 100.0 90.0 80.0 Iol (mA) 70.0 60.0 85℃ 50.0 25℃ -40℃ 40.0 30.0 20.0 10.0 0.0 0.5 1 1.5 2 2.5 Vol (V) 3 3.5 4 4.5 Figure 7-7 Vol vs. Iol at VDD=5V IPH vs Temperature for P60(VDD=3V or 5V) 100 90 80 IPH (uA) 70 3.0V 60 5.0V 50 40 30 20 10 0 -40 -20 0 25 50 Temperature (℃) 70 85 Figure 7-8 IPH vs. Temperature 60 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM IPL vs Temperature for P50 (VDD=3V or 5V) 50 45 40 IPL (uA) 35 30 3.0V 5.0V 25 20 15 10 5 0 -40 -20 0 25 50 Temperature (℃) 70 85 Figure 7-9 IPL vs. Temperature WDT time_out_VDD(Normal mode/Crystal=4MHz) 35 30 Time(ms) 25 85℃ 25℃ -40℃ 20 15 10 5 0 2.2 2.5 3 3.5 4 4.5 5 5.5 VDD(V) Figure 7-10 WDT time out vs. VDD, with prescaler set to 1:1 Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 61 EM78P163N 8-Bit Microcontroller with OTP ROM Typical ISB1 and ISB2 vs Temp(VDD=5V) 8.0 7.0 Current(uA) 6.0 ISB1 5.0 ISB2 4.0 3.0 2.0 1.0 0.0 -40 -20 0 25 50 70 85 Temperature (℃) Figure 7-11 Typical Standby Current (VDD=5V) vs. Temperature Maximum ISB1 and ISB2 vs Temp(VDD=5V) 9.0 8.0 Current(uA) 7.0 6.0 5.0 ISB1 ISB2 4.0 3.0 2.0 1.0 0.0 -40 -20 0 25 50 70 85 Temperature (℃) Figure 7-12 Maximum Standby Current (VDD=5V) vs. Temperature 62 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM Typical ISB1 and ISB2 vs Temp(VDD=3V) 3.0 Current(uA) 2.5 2.0 ISB1 ISB2 1.5 1.0 0.5 0.0 -40 -20 0 25 50 70 85 Temperature(℃) Figure 7-13 Typical Standby Current (VDD=3V) vs. Temperature Maximum ISB1 and ISB2 vs Temp(VDD=3V) 3.0 Current(uA) 2.5 2.0 1.5 ISB1 ISB2 1.0 0.5 0.0 -40 -20 0 25 50 70 85 Temperature(℃) Figure 7-14 Maximum Standby Current (VDD=3V) vs. Temperature Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 63 EM78P163N 8-Bit Microcontroller with OTP ROM Typical ICC1 and ICC2 vs Temp.(VDD=5V) 1600 1400 Current(uA) 1200 1000 ICC1 ICC2 800 600 400 200 0 -40 -20 0 25 50 75 85 Temperature (℃) Figure 7-15 Typical Operating Current (VDD=5V) vs. Temperature Maximum ICC1 and ICC2 vs Temp.(VDD=5V) 1800 1600 Current(uA) 1400 1200 ICC1 ICC2 1000 800 600 400 200 0 -40 -20 0 25 50 75 85 Temperature (℃) Figure 7-16 Maximum Operating Current (VDD=5V) vs. Temperature 64 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM Typical ICC1 and ICC2 vs Temp.(VDD=3V) 900 800 Current(uA) 700 600 ICC1 500 ICC2 400 300 200 100 0 -40 -20 0 25 50 70 85 Temperature(℃) Figure 7-17 Typical Operating Current (VDD=3V) vs. Temperature Maximum ICC1 and ICC2 vs Temp(VDD=3V) 1200 Current(uA) 1000 800 ICC1 ICC2 600 400 200 0 -40 -20 0 25 50 70 85 Temperature(℃) Figure 7-18 Maximum Operating Current (VDD=3V) vs. Temperature Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 65 EM78P163N 8-Bit Microcontroller with OTP ROM Typical ICC3 and ICC4 vs Temp(VDD=5V) 2.8 2.7 Current (mA) 2.7 ICC3 ICC4 2.6 2.6 2.5 2.5 2.4 2.4 -40 -20 0 25 50 70 85 Temperature (℃) Figure 7-19 Typical Operating Current (VDD=5V) vs. Temperature Maximum ICC3 and ICC4 vs Temp(VDD=5V) 3.3 3.3 Current (mA) 3.2 3.2 3.1 ICC3 ICC4 3.1 3.0 3.0 2.9 2.9 -40 -20 0 25 50 70 85 Temperature (℃) Figure 7-20 Maximum Operating Current (VDD=5V) vs. Temperature 66 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM Typical ICC3 and ICC4 vs Temp(VDD=3V) 1.9 1.9 Current(mA) 1.8 1.8 ICC3 ICC4 1.7 1.7 1.6 1.6 1.5 -40 -20 0 25 50 70 85 Temperature(℃) Figure 7-21 Typical Operating Current (VDD=3V) vs. Temperature Maximum ICC3 and ICC4 vs Temp(VDD=3V) 2.3 2.3 2.2 Current(mA) 2.2 ICC3 ICC4 2.1 2.1 2.0 2.0 1.9 1.9 1.8 -40 -20 0 25 50 70 85 Temperature(℃) Figure 7-22 Maximum Operating Current (VDD=3V) vs. Temperature Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 67 EM78P163N 8-Bit Microcontroller with OTP ROM 8 68 • Timing Diagram Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM APPENDIX A Package Type OTP MCU Package Type Pin Count Package Size EM78P163ND14J DIP 14 300 mil EM78P163NSO14J SOP 14 150 mil EM78P163ND16J DIP 16 300 mil EM78P163NSO16AJ SOP 16 150 mil These are Green products which do not contain hazardous substances and comply with the third edition of Sony SS-00259 standard. Pb content is less than 100ppm and complies with Sony specifications. Part No. EM78P163N/J Electroplate type Pure Tin Ingredient (%) Sn: 100% Melting point (°C) 232°C Electrical resistivity (μΩ-cm) 11.4 Hardness (hv) 8~10 Elongation (%) >50% Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 69 EM78P163N 8-Bit Microcontroller with OTP ROM B Package Information 70 • 14-Lead Plastic Dual in line (PDIP) — 300 mil Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 14-Lead Plastic Small Outline (SOP) — 150 mil Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 71 EM78P163N 8-Bit Microcontroller with OTP ROM 72 • 16-Lead Plastic Dual in line (PDIP) — 300 mil Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM 16- Lead Plastic Small Outline (SOP) — 150 mil Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 73 EM78P163N 8-Bit Microcontroller with OTP ROM C Quality Assurance and Reliability Test Category Test Conditions Remarks Solder temperature=245±5°C, for 5 seconds up to the stopper using a rosin-type flux Solderability – Step 1: TCT, 65°C (15 min)~150°C (15mins), 10 cycles Step 2: Bake at 125°C, TD (endurance)=24 hrs Step 3: Soak at 30°C/60%，TD (endurance)=192 hrs Step 4: IR flow 3 cycles Pre-condition (Pkg thickness ≥ 2.5 mm or 3 Pkg volume ≥ 350 mm ----225 ± 5°C) For SMD IC (such as SOP, QFP, SOJ, etc) (Pkg thickness ≤ 2.5 mm or 3 Pkg volume ≤ 350 mm ----240 ± 5°C) Temperature cycle test -65°C (15mins)~150°C (15 min), 200 cycles – Pressure cooker test TA =121°C, RH=100%, pressure=2 atm, TD (endurance)= 96 hrs – High temperature / High humidity test TA=85°C, RH=85%，TD (endurance) = 168 , 500 hrs – High-temperature storage life TA=150°C, TD (endurance) = 500, 1000 hrs – High-temperature operating life TA=125°C, VCC = Max. operating voltage, TD (endurance) = 168, 500, 1000 hrs – Latch-up TA=25°C, VCC = Max. operating voltage, 150mA/20V – ESD (HBM) TA=25°C, ≥∣± 3KV∣ IP_ND,OP_ND,IO_ND IP_NS,OP_NS,IO_NS IP_PD,OP_PD,IO_PD, ESD (MM) IP_PS,OP_PS,IO_PS, TA=25°C, ≥ ∣± 300V∣ VDD-VSS(+),VDD_VSS (-) mode C.1 Address Trap Detect An address trap detect is one of the MCU embedded fail-safe functions that detects MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an instruction from a certain section of ROM, an internal recovery circuit is auto started. If a noise-caused address error is detected, the MCU will repeat execution of the program until the noise is eliminated. The MCU will then continue to execute the next program. 74 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) EM78P163N 8-Bit Microcontroller with OTP ROM D Ordering and Manufacture Information EM78P163NSO14J Material Type J: RoHS complied Pin Number Package Type D: DIP SO: SOP SS: SSOP Specific Annotation K: Industrial Grad Product Number Product Type P: OTP Elan 8-bit Product For example: EM78P163NSO14J is EM78P163N with OTP program memory, industrial grade product, in 14-pin SOP package with RoHS complied Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice) • 75 EM78P163N 8-Bit Microcontroller with OTP ROM 76 • Product Specification (V1.8) 02.27.2013 (This specification is subject to change without further notice)