ETC HT23C040H

HT23C040H
CMOS 512K´8-Bit High Speed Mask ROM
Features
· Operating voltage: 2.7V~5.5V
· 512K´8-bit of mask ROM
· Low power consumption
· Mask option: chip enable CE/CE, and output enable
- Operation: 25mA max. (VCC=5V)
OE/OE/NC
· TTL compatible inputs and outputs
10mA max. (VCC=3V)
- Standby: 60mA max. (VCC=5V)
20mA max. (VCC=3V)
· Access time: 90ns max. (VCC=5V)
250ns max. (VCC=3V)
· Tristate outputs
· Fully static operation
· 32-pin DIP/SOP package
General Description
tion in multiple bus microprocessor systems. An additional feature of the HT23C040H is its ability to enter the
standby mode whenever the chip enable (CE/CE) is inactive, thus reducing current consumption to below
60mA. The combination of these functions makes the
chip suitable for high density low power memory applications.
The HT23C040H is a read-only memory with high performance CMOS storage device whose 4096K of memory is arranged into 512K word by 8 bits.
For application flexibility, the chip enable and output enable control pins can be selected as active high or active
low. This flexibility not only allows easy interface with
most microprocessors, but also eliminates bus conten-
Block Diagram
P re -c h a rg e C K T
A 0
A d d re s s
B u ffe rs
A T D
A 1 8
Y -D e c
R O M C e ll
A rra y
( 5 1 2 K ´ 8 - B its )
Z -D e c
Z - s e le c to r
X -D e c
X Y
P re -d e c o d e r
P u ll- h ig h N M O S
S e n s e A m p lifie r s
C E /C E
O E /O E /N C
M u x
M u x
C T R L
L a tc h
O u tp u t B u ffe rs
V S S
Rev. 1.00
1
V C C
D 0
D 7
August 15, 2002
HT23C040H
Pin Assignment
N C
1
3 2
V C C
A 1 6
2
3 1
A 1 8
A 1 5
3
3 0
A 1 7
A 1 2
4
2 9
A 1 4
A 7
5
2 8
A 1 3
A 6
6
2 7
A 8
A 5
7
2 6
A 9
A 4
8
2 5
A 1 1
A 3
9
2 4
O E /O E /N C
A 2
1 0
2 3
A 1 0
A 1
1 1
2 2
C E /C E
A 0
1 2
2 1
D 7
D 0
1 3
2 0
D 6
D 1
1 4
1 9
D 5
D 2
1 5
1 8
D 4
V S S
1 6
1 7
D 3
H T 2 3 C 0 4 0 H
3 2 D IP -A /S O P -A
Pin Description
Pin Name
I/O
Description
¾
No connection
A0~A18
I
Address inputs
D0~D7
O
Data outputs
VSS
¾
Negative power supply, ground
NC
CE/CE
I
Chip enable/Output enable input
OE/OE/NC
I
Output enable input
VCC
¾
Positive power supply
Absolute Maximum Ratings
Supply Voltage ............................................-0.3V to 6V
Storage Temperature ............................-50°C to 125°C
Input Voltage....................................-0.3V to VCC+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.00
2
August 15, 2002
HT23C040H
D.C. Characteristics
Symbol
Ta=-40°C to 85°C
Parameter
Test Conditions
Conditions
VCC
Min.
Typ.
Max.
Unit
4.5
¾
5.5
V
¾
¾
25
mA
Supply voltage: 4.5V~5.5V
VCC
Operating Voltage
¾
¾
O/P No load,
f=5MHz
ICC1
Operating Current
VIL1
Input Low Voltage
5V
¾
VSS
¾
0.8
V
VIH1
Input High Voltage
5V
¾
2.2
¾
VCC
V
VOL1
Output Low Voltage
5V
IOL=3.2mA
¾
¾
0.4
V
VOH1
Output High Voltage
5V
IOH=-1mA
2.4
¾
VCC
V
ILI
Input Leakage Current
5V
VIN=0 to VCC
¾
¾
10
mA
ILO
Output Leakage Current
5V
VOUT=0 to VCC
¾
¾
10
mA
5V
CE=VIL, CE=VIH
¾
¾
1.5
mA
¾
¾
60
mA
ISTB1
Standby Current
5V
ISTB2
Standby Current
5V
CE£0.2V
CE³VCC-0.2V
CIN
Input Capacitance (See note)
¾
f=1MHz
¾
¾
10
pF
COUT
Output Capacitance (See note)
¾
f=1MHz
¾
¾
10
pF
2.7
¾
3.3
V
¾
¾
10
mA
Supply voltage: 2.7V~3.3V
VCC
Operating Voltage
¾
¾
ICC2
Operating Current
3V
VIL2
Input Low Voltage
3V
¾
VSS
¾
0.4
V
VIH2
Input High Voltage
3V
¾
1.5
¾
VCC
V
O/P No load,
f=5MHz
VOL2
Output Low Voltage
3V
IOL=2mA
¾
¾
0.4
V
VOH2
Output High Voltage
3V
IOH=-0.6mA
1.5
¾
VCC
V
ILI
Input Leakage Current
3V
VIN=0 to VCC
¾
¾
10
mA
ILO
Output Leakage Current
3V
VOUT=0 to VCC
¾
¾
10
mA
CIN
Input Capacitance (See Note)
¾
f=1MHz
¾
¾
10
pF
COUT
Output Capacitance (See Note)
¾
f=1MHz
¾
¾
10
pF
Note: These parameters are periodically sampled but not 100% tested.
A.C. Characteristics
Symbol
Ta=-40°C to 85°C
3V±10%
Parameter
tCYC
Cycle Time
5V±10%
Unit
Min.
Max.
Min.
Max.
200
¾
90
¾
ns
tAA
Address Access Time
¾
250
¾
90
ns
tACE
Chip Enable Access Time
¾
250
¾
90
ns
tAOE
Output Enable Access Time
¾
150
¾
60
ns
tOH
Output Hold Time
¾
¾
7.5
¾
ns
tOD
Output Disable Time (See Note)
¾
¾
¾
60
ns
tOE
Output Enable Time (See Note)
¾
¾
7.5
¾
ns
Note: These parameters are periodically sampled but not 100% tested.
Rev. 1.00
3
August 15, 2002
HT23C040H
A.C. test condition
V
C C
Output load: see figure right
Input rise and fall time: 10ns
1 2 5 0 W
Input pulse levels: 0.4V to 2.4V
O u tp u t
7 7 5 W
Input and output timing reference levels:
0.8V and 2.0V (VCC=5V)
1.5V (VCC=3V)
1 0 0 p F *
* In c lu d in g s c o p e a n d jig
Output load circuit
Functional Description
The HT23C040H has two modes, namely data read
mode and standby mode, controlled by CE/CE and
OE/OE/NC inputs.
· Data read mode
When both the chip enable (CE/CE) and the output
enable (OE/OE/NC) are active, the chip is in data read
mode. Otherwise, active CE/CE and inactive
OE/OE/NC result in deselect mode. The output will remain in Hi-Z state.
· Standby mode
The HT23C040H offers lower current consumption,
controlled by the chip enable input (CE/CE). When a
low/high level is applied to the CE/CE input regardless
of the output enable (OE/OE/NC) states the chip will
enter the standby mode.
Operation truth table
Mode
CE/CE
OE/OE
A0~A18
Read
H/L
H/L
Valid
Deselect
H/L
L/H
X
High Z
Standby
L/H
X
X
High Z
D0~D7
Data Out
Note: H=VIH, L=VIL, X=VIH or VIL
Timing Diagrams
· Propagation delay due to address (CE/CE and OE/OE are active)
tC
Y C
V a lid
A d d re s s
tA
tO
A
H
V a lid
D o u t
· Propagation delay due to chip and output enable (address valid)
tA
C E
C E
C E
tA
O E
O E
O E
tO
tO
E
D o u t
Rev. 1.00
D
V a lid
4
August 15, 2002
HT23C040H
Package Information
32-pin DIP (600mil) outline dimensions
A
1 7
3 2
B
1 6
1
H
C
D
E
Symbol
Rev. 1.00
F
=
G
I
Dimensions in mil
Min.
Nom.
Max.
A
1635
¾
1665
B
535
¾
555
C
145
¾
155
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
595
¾
615
I
635
¾
670
a
0°
¾
15°
5
August 15, 2002
HT23C040H
32-pin SOP (450mil) outline dimensions
3 2
1 7
A
B
1
1 6
C
C '
G
H
D
E
Symbol
Rev. 1.00
=
F
Dimensions in mil
Min.
Nom.
Max.
A
543
¾
557
B
440
¾
450
C
14
¾
20
C¢
¾
¾
817
D
100
¾
112
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
6
August 15, 2002
HT23C040H
Product Tape and Reel Specifications
Reel dimensions
D
T 2
A
C
B
T 1
SOP 32W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
100±0.1
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
32.8+0.3
-0.2
T2
Reel Thickness
38.2+0.2
Rev. 1.00
7
August 15, 2002
HT23C040H
Carrier tape dimensions
P 0
D
P 1
t
E
F
W
D 1
C
B 0
K 1
P
K 2
A 0
SOP 32W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
32.0+0.3
-0.1
P
Cavity Pitch
16.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
14.2±0.1
D
Perforation Diameter
1.55+0.1
D1
Cavity Hole Diameter
2.0+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
14.7±0.1
B0
Cavity Width
20.9±0.1
K1
Cavity Depth
3.0±0.1
K2
Cavity Depth
3.4±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
Rev. 1.00
0.35±0.05
25.5
8
August 15, 2002
HT23C040H
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http://www.holmate.com
Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most
up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
9
August 15, 2002