HT62L256 CMOS 32K´8 Low Power SRAM Preliminary Features · Operation voltage: 2.7V~3.3V · Automatic power down when chip is deselected · Low power consumption: · Three state outputs - Operating current: 20mA max. - Standby current: 2mA · Fully static operation · Data retention supply voltage as low as 2.0V · High speed access time: 70ns · Easy expansion with CS and OE options · Input levels are LVTTL-compatible · 28-pin SOP/TSOP package General Description The HT62L256 is a 262,144-bit static random access memory organized into 32,768 words by 8 bits and operating from a low power range of 2.7V to 3.3V supply voltage. It is fabricated with high performance CMOS process that provides both high speed and low power feature with typical standby current of 2mA and maximum access time of 70ns. The HT62L256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The HT62L256 supports the JEDEC standard 28-pin SOP and TSOP package. Block Diagram A 0 X -D e c A d d re s s B u ffe rs A 1 4 C S M e m o r y C e ll A r r a y ( 3 2 K ´ 8 B its Y -D e c S e n s e A m p lifie r R e a d /W r ite C o n tr o l L o g ic W E O E O u tp u t B u ffe rs V D D V S S D 0 D 7 Pin Assignment A 1 4 1 2 8 V D D A 1 2 2 2 7 W E A 7 3 2 6 A 1 3 A 6 4 2 5 A 8 A 5 5 2 4 A 9 A 4 6 2 3 A 1 1 A 3 7 2 2 O E A 2 8 2 1 A 1 0 A 1 9 2 0 C S A 0 1 0 1 9 D 7 D 0 1 1 1 8 D 6 D 1 1 2 1 7 D 5 D 2 1 3 1 6 D 4 V S S 1 4 1 5 D 3 O A 1 A A A 1 W V D A 1 A 1 A A A A A E 2 8 1 1 9 8 3 E H T 6 2 L 2 5 6 2 8 T S O P -A D 4 2 7 6 3 4 5 1 4 1 5 A 1 0 C S D 7 D 6 D 5 D 4 D 3 V S S D 2 D 1 D 0 A 0 A 1 A 2 H T 6 2 L 2 5 6 2 8 S O P -A Rev. 0.00 1 August 15, 2002 Preliminary HT62L256 Pin Description Pin Name I/O Description A0~A14 I Address input pins WE I Write enable signal pin, active LOW OE I Output enable signal pin, active LOW CS I Chip select signal pin, active LOW D0~D7 I/O Data input and output signal pins VDD ¾ Positive power supply VSS ¾ Negative power supply, ground Absolute Maximum Rating VDD to VSS ........................................... -0.5V to +3.6V Operating Temperature, TOP ......................0°C to 70°C IN, IN/OUT Voltage to VSS ............. -0.5V to VDD+0.5V Storage Temperature (Plastic), Tstg ... -55°C to 125°C Power Consumption, PT .......................................0.7W Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter Ta=25°C, VDD=3.0V±10%, TOP=0°C to 70°C Test Conditions Min. Typ. Max. Unit VDD Operating Voltage ¾ 2.7 3.0 3.3 V VIL Input Low Voltage ¾ ¾ 0 0.4 V VIH Input High Voltage ¾ 0.7´VDD ¾ V ILI Input Leakage Current VIN=0 to VDD ¾ ¾ 1 mA ILO Output Leakage Current CS=VIH or OE=VIH, VOUT=0 to VDD ¾ ¾ 1 mA VOL Output Low Voltage VDD=Max, IOL=2mA ¾ ¾ 0.3 V VOH Output High Voltage VDD=Min, IOH=-1mA VDD-0.3 ¾ ¾ V Operating Current CS=VIH, IOUT=0mA ¾ ¾ 20 mA ISB1 Standby Current CS=VIH, IOUT=0mA ¾ ¾ 50 mA ISB2 Power Down Supply Current CS ³ VDD - 0.2V, VIN³0V ¾ 2 10 mA IDD Rev. 0.00 2 August 15, 2002 Preliminary HT62L256 A.C. Characteristics Symbol Ta=25°C, VDD=3.0V±10% Parameter Min. Typ. Max. Unit Read cycle tRC Read Cycle Time 70 ¾ ¾ ns tAA Address Access Time ¾ ¾ 70 ns tACS Chip Selection Access Time ¾ ¾ 70 ns tAOE Output Enable to Valid Outputs ¾ ¾ 35 ns tCLZ* Chip Selection to Output in Low-Z 10 ¾ ¾ ns tOLZ* Output Enabled to Output in Low-Z 5 ¾ ¾ ns tCHZ* Chip Deselected to Output in High-Z ¾ ¾ 25 ns tOHZ* Output Disable to Output in High-Z ¾ ¾ 25 ns tOH Output Hold from Address Change 10 ¾ ¾ ns Write cycle tWC Write Cycle Time 70 ¾ ¾ ns tCW Chip Selection to End of Write 60 ¾ ¾ ns tAS Address Setup Time 0 ¾ ¾ ns tAW Address Valid to End of Write 60 ¾ ¾ ns tWP Write Pulse Width 50 ¾ ¾ ns tWR Write Recovery Time 0 ¾ ¾ ns tWHZ Write to Output in High-Z ¾ ¾ 20 ns tDW Data Valid to End of Write 30 ¾ ¾ ns tDH Data Hold from End of Write 0 ¾ ¾ ns tOW Output Active from End of Write 5 ¾ ¾ ns Note: 1. A write cycle occurs during the overlap of a low CS and a low WE 2. OE may be both high and low in a write cycle 3. tAS is specified from CS or WE, whichever occurs last 4. tWP is an overlap time of a low CS and a low WE 5. tWR, tDW and tDH are specified from CS or WE, whichever occurs first 6. tWHZ is specified by the time when DATA OUT is floating and not defined by the output level 7. When the I/O pins are in data output mode, they should not be forced with inverse signals Rev. 0.00 3 August 15, 2002 Preliminary HT62L256 A.C. Test Conditions Item Conditions Input Pulse Level 0V to 3V Input Rise and Fall Time 5ns Input and Output Timing Reference Level 1.5V Output Load See figures below + 1 .5 V + 1 .5 V 1 .8 k W 1 .8 k W I/O I/O 1 0 0 p F 9 9 0 W 5 p F 9 9 0 W * In c lu d in g s c o p e a n d jig * In c lu d in g s c o p e a n d jig O u tp u t lo a d tC L Z , tO O u tp u t lo a d fo r L Z , tC H Z , tW H Z a n d tO W Functional Description Operation truth table CS OE WE Mode D0~D7 H X X Standby High-Z L H H Output Disable High-Z L L H Read Dout L X L Write Din Data retention characteristics Symbol Ta=-40°C to 85°C Parameter Conditions Min. Max. Unit VDR VDD for Data Retention CS ³ VDD-0.2V VIN ³ VDD-0.2V or VIN£0.2V 2.0 3.3 V ICCDR Data Retention Current CS ³ VDD-0.2V VIN ³ VDD-0.2V or VIN£0.2V ¾ 2 mA tCDR Chip Disable Data Retention Time See retention timing 0 ¾ ns See retention timing tRC* ¾ ns tR Operation Recovery Time Low VDD data retention timing V D D 3 .0 V 3 .0 V V tC C S V D D tR D R V IH C S ³ V Rev. 0.00 ³ 2 .0 V D D IH -0 .2 V 4 August 15, 2002 Preliminary HT62L256 Timing Diagrams Read cycle 1 output enable controlled (1) tR C A d d re s s tA A O E tA tO O E tO H L Z C S tA tC D tO C S tC L Z H Z H Z O U T D o n 't C a r e U n u s e d Read cycle 2 address controlled (1, 2, 4) tR C A d d re s s tA tO D A tO H H O U T D o n 't C a r e U n u s e d Read cycle 3 chip select controlled (1, 3, 4) A d d re s s tA tC D C S tC L Z H Z O U T D o n 't C a r e U n u s e d Note: 1. WE is high for read cycle 2. Device is continuously enabled, CS=VIL 3. Address is valid prior to or coincident with the CS transition low 4. OE=VIL 5. Transition is measured at ±500mV from the steady state Rev. 0.00 5 August 15, 2002 Preliminary HT62L256 Write cycle 1 OE clock (1) tW C A d d re s s tW R O E tC W (5 ) C S tA W tW W E tA S tO D P (1 , 4 ) H Z O U T tD D W tD H IN D o n 't C a r e U n u s e d Write cycle 2 OE=VIL Fixed (1, 6) tW C A d d re s s tC tW W (5 ) C S tA W tW W E tA P tO S tW D R H Z tO W H (7 ) (8 ) O U T tD D W tD H IN D o n 't C a r e U n u s e d Rev. 0.00 6 August 15, 2002 Preliminary Note: HT62L256 1. WE must be high during all address transitions 2. A write occurs during the overlap (tWP) of a low CS and a low WE 3. tWR is measured from the earliest high going edge of CS or WE to the end of the write cycle 4. During this period, I/O pins are in the output state, so the input signals of opposite phase to the outputs should not be applied. 5. If the CS low transition occurs simultaneously or after with the WE low transition, the outputs remain in a high impedance state 6. OE is continuously low (OE=VIL) 7. DOUT is at the same phase as the write data of this write cycle 8. DOUT is the read data of the next address 9. If CS is low during this period, then the I/O pins are in the output state and the data input signals of the opposite phase to the outputs should not be applied 10. Transition is measured at ±500mV from the steady state Rev. 0.00 7 August 15, 2002 Preliminary HT62L256 Package Information 28-pin SOP (330mil) outline dimensions 2 8 1 5 A B 1 1 4 C C ' G H D E Symbol Rev. 0.00 a F Dimensions in mil Min. Nom. Max. A 453 ¾ 477 B 326 ¾ 336 C 14 ¾ 20 C¢ 700 ¾ 728 D 92 ¾ 104 E ¾ 50 ¾ F 4 ¾ ¾ G 32 ¾ 38 H 4 ¾ 12 a 0° ¾ 10° 8 August 15, 2002 Preliminary HT62L256 28-pin TSOP (8´13.4) outline dimensions H D 1 2 8 E q 0 .0 1 0 L D e ta il F 1 4 1 5 D A 2 S e e D e ta il F L 1 S b S e a tin g P la n e Symbol Rev. 0.00 y e A A 1 Dimensions in mm Min. Nom. Max. A ¾ ¾ 1.25 A1 0.08 ¾ 0.18 A2 0.95 ¾ 1.05 b ¾ 0.20 ¾ D 11.70 ¾ 11.90 HD 13.20 ¾ 13.60 E 7.90 ¾ 8.10 e ¾ 0.55 ¾ L ¾ 0.50 ¾ L1 ¾ 0.8 ¾ q 0° ¾ 5° 9 August 15, 2002 Preliminary HT62L256 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Sales Office) 11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan Tel: 886-2-2782-9635 Fax: 886-2-2782-9636 Fax: 886-2-2782-7128 (International sales hotline) Holtek Semiconductor (Shanghai) Inc. 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor (Hong Kong) Ltd. RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong Tel: 852-2-745-8288 Fax: 852-2-742-8657 Holmate Semiconductor, Inc. 48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 0.00 10 August 15, 2002