ETC IS89LV51

ISSI®
ISSI
IS89LV51
IS89LV51
CMOS SINGLE CHIP LOW VOLTAGE
8-BIT MICROCONTROLLER
with 4-Kbytes of FLASH
®
ADVANCE INFORMATION
OCTOBER 1998
FEATURES
GENERAL DESCRIPTION
• 80C51 based architecture
• 4-Kbytes of on-chip Reprogrammable Flash
Memory
• 128 x 8 RAM
• Two 16-bit Timer/Counters
• Full duplex serial channel
• Boolean processor
• Four 8-bit I/O ports, 32 I/O lines
• Memory addressing capability
– 64K ROM and 64K RAM
• Program memory lock
– Lock bits (3)
• Power save modes:
– Idle and power-down
• Six interrupt sources
• Most instructions execute in 0.3 µs
• CMOS and TTL compatible
• Maximum speed: 40 MHz @ Vcc = 3.3V
• Operating Range: 3.3V to 5V, ± 10%
• Industrial temperature available
• Packages available:
– 40-pin DIP
– 44-pin PLCC
– 44-PIN PQFP
The ISSI IS89LV51 is a high-performance microcontroller
fabricated using high-density CMOS technology. The
CMOS IS89LV51 is functionally compatible with the
industry standard 80C51 microcontrollers.
The IS89LV51 is designed with 4-Kbytes of Flash
memory, 128 x 8 RAM; 32 programmable I/O lines; a serial
I/O port for either multiprocessor communications, I/O
expansion or full duplex UART; two 16-bit timer/counters;
an six-source, two-priority-level, nested interrupt structure;
and an on-chip oscillator and clock circuit. The IS89LV51
can be expanded using standard TTL compatible memory.
P1.0
1
40
VCC
P1.1
2
39
P0.0/AD0
P1.2
3
38
P0.1/AD1
P1.3
4
37
P0.2/AD2
P1.4
5
36
P0.3/AD3
P1.5
6
35
P0.4/AD4
P1.6
7
34
P0.5/AD5
P1.7
8
33
P0.6/AD6
RST
9
32
P0.7/AD7
RxD/P3.0
10
31
EA/VPP
TxD/P3.1
11
30
ALE/PROG
INT0/P3.2
12
29
PSEN
INT1/P3.3
13
28
P2.7/A15
T0/P3.4
14
27
P2.6/A14
T1/P3.5
15
26
P2.5/A13
WR/P3.6
16
25
P2.4/A12
RD/P3.7
17
24
P2.3/A11
XTAL2
18
23
P2.2/A10
XTAL1
19
22
P2.1/A9
GND
20
21
P2.0/A8
Figure 1. IS89LV51 Pin Configuration: 40-pin PDIP
This document contains ADVANCE INFORMATION. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible
product. We assume no responsibility for any errors which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC020-0A
10/27/98
1
ISSI
P1.3
P1.2
P1.1
P1.0
NC
VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
INDEX
P1.4
IS89LV51
6
5
4
3
2
1
44
43
42
41
40
P1.5
7
39
P0.4/AD4
P1.6
8
38
P0.5/AD5
P1.7
9
37
P0.6/AD6
RST
10
36
P0.7/AD7
RxD/P3.0
11
35
EA/VPP
NC
12
34
NC
TxD/P3.1
13
33
ALE/PROG
INT0/P3.2
14
32
PSEN
INT1/P3.3
15
31
P2.7/A15
T0/P3.4
16
30
P2.6/A14
T1/P3.5
17
29
P2.5/A13
22
23
24
RD/P3.7
XTAL2
XTAL1
GND
NC
A8/P2.0
25
26
27
28
A12/P2.4
21
A11/P2.3
20
A10/P2.2
19
A9/P2.1
18
WR/P3.6
TOP VIEW
®
Figure 2. IS89LV51 Pin Configuration: 44-pin PLCC
2
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ADVANCE INFORMATION MC020-0A
10/27/98
ISSI
P1.4
P1.3
P1.2
P1.1
P1.0
NC
VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
IS89LV51
44
43
42
41
40
39
38
37
36
35
34
P0.6/AD6
RST
4
30
P0.7/AD7
RxD/P3.0
5
29
EA
NC
6
29
NC
TxD/P3.1
7
27
ALE
INT0/P3.2
8
26
PSEN
INT1/P3.3
9
25
P2.7/A15
T0/P3.4
10
24
P2.6/A14
T1/P3.5
11
23
P2.5/A13
12
13
14
15
16
17
18
19
20
21
22
A12/P2.4
31
A11/P2.3
3
A10/P2.2
P1.7
A9/P2.1
P0.5/AD5
A8/P2.0
32
NC
2
GND
P1.6
XTAL1
P0.4/AD4
XTAL2
33
RD/P3.7
1
WR/P3.6
P1.5
®
Figure 3. IS89LV51 Pin Configuration: 44-pin PQFP
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ADVANCE INFORMATION MC020-0A
10/27/98
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3
ISSI
IS89LV51
Vcc
P2.0-P2.7
P0.0-P0.7
P2
DRIVERS
P0
DRIVERS
®
GND
ADDRESS
DECODER
& 256
BYTES RAM
RAM ADDR
REGISTER
P2
LATCH
STACK
POINT
B
REGISTER
PCON SCON
T2CON TH0
TL1
TH2
RCAP2L SBUF
P0
LATCH
ADDRESS
DECODER
&
8K FLASH
PROGRAM
ADDRESS
REGISTER
ACC
TMOD TCON
TL0
TH1
TL2 RCAP2H
IE
IP
3 LOCK BITS
&
32 BYTES
ENCRYPTION
TMP2
INTERRUPT BLOCK
SERIAL PORT BLOCK
TIMER BLOCK
TMP1
PROGRAM
COUNTER
PC
INCREMENTER
ALU
PSW
PSEN
ALE/PROG
RST
TIMING
AND
CONTROL
EA/VPP
INSTRUCTION
REGISTER
BUFFER
DPTR
P3
LATCH
P1
LATCH
OSCILLATOR
XTAL1
XTAL2
P3
DRIVERS
P1
DRIVERS
P3.0-P3.7
P1.0-P1.7
Figure 4. IS89LV51 Block Diagram
4
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ADVANCE INFORMATION MC020-0A
10/27/98
ISSI
IS89LV51
®
Table 1. Detailed Pin Description
Symbol
PDIP
PLCC
PQFP
I/O
Name and Function
ALE/PROG
30
33
27
I/O
EA/VPP
Address Latch Enable: Output pulse for latching the low byte
of the address during an address to the external memory. In
normal operation, ALE is emitted at a constant rate of 1/6 the
oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each
access to external data memory. This pin is also the Program
Pulse input (PROG) during Flash programming.
31
35
29
I
P0.0-P0.7
39-32
43-36
37-30
I/O
Port 0: Port 0 is an 8-bit open-drain, bidirectional I/O port. Port
0 pins that have 1s written to them float and can be used as highimpedance inputs. Port 0 is also the multiplexed low-order
address and data bus during accesses to external program and
data memory. In this application, it uses strong internal pullups
when emitting 1s.
Port 0 also receives the code bytes during programmable
memory programming and outputs the code bytes during
program verification. External pullups are required during program verification.
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal
pullups. Port 1 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally pulled low will source current
because of the internal pullups. (See DC Characteristics: IIL).
The Port 1 output buffers can sink/source four TTL inputs.
External Access enable: EA must be externally held low to
enable the device to fetch code from external program memory
locations 0000H to FFFFH. If EA is held high, the device
executes from internal program memory unless the program
counter contains an address greater than 0FFFH. This also
receives the 12V programming enable voltage (VPP) during
Flash programming.
Port 1 also receives the low-order address byte during Flash
programming and verification.
P2.0-P2.7
21-28
24-31
18-25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal
pullups. Port 2 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally pulled low will source current
because of the internal pullups. (See DC Characteristics: IIL).
Port 2 emits the high order address byte during fetches from
external program memory and during accesses to external data
memory that used 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pullups when emitting
1s. During accesses to external data memory that use 8-bit
addresses (MOVX @ Ri [i = 0, 1]), Port 2 emits the contents of
the P2 Special Function Register.
Port 2 also receives the high-order bits and some control
signals during Flash programming and verification. P2.6 and
P2.7 are the control signals while the chip programs and
erases.
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10/27/98
5
ISSI
IS89LV51
®
Table 1. Detailed Pin Description (continued)
Symbol
PDIP
PLCC
PQFP
I/O
Name and Function
P3.0-P3.7
10-17
11, 13-19
5, 7-13
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pullups. Port 3 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally pulled low will source current
because of the internal pullups. (See DC Characteristics: IIL).
Port 3 also serves the special features of the IS89LV51, as
listed below:
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
9
10
11
12
13
I
O
I
I
I
I
O
O
PSEN
RxD (P3.0): Serial input port.
TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupt 0.
INT1 (P3.3): External interrupt 1.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
29
32
26
O
Program Store Enable: The read strobe to external program
memory. When the device is executing code from the external
program memory, PSEN is activated twice each machine cycle
except that two PSEN activations are skipped during each
access to external data memory. PSEN is not activated during
fetches from internal program memory.
RST
9
10
4
I
Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device. An internal MOS resistor
to GND permits a power-on reset using only an external
capacitor connected to Vcc.
XTAL 1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input
to the internal clock generator circuits.
XTAL 2
18
20
14
O
Crystal 2: Output from the inverting oscillator amplifier.
GND
20
22
16
I
Ground: 0V reference.
Vcc
40
44
38
I
Power Supply: This is the power supply voltage for operation.
6
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ISSI
IS89LV51
®
OPERATING DESCRIPTION
The detail description of the IS89LV51 included in this
description are:
addressing. Figure 6 shows internal data memory
organization and SFR Memory Map.
• Memory Map and Registers
The lower 128 bytes of RAM can be divided into three
segments as listed below and shown in Figure 7.
• Timer/Counters
1. Register Banks 0-3: locations 00H through 1FH (32
bytes). The device after reset defaults to register bank
0. To use the other register banks, the user must select
them in software. Each register bank contains eight 1byte registers R0-R7. Reset initializes the stack point
to location 07H, and is incremented once to start from
08H, which is the first register of the second register
bank.
• Serial Interface
• Interrupt System
• Other Information
• Flash Memory
MEMORY MAP AND REGISTERS
Memory
The IS89LV51 has separate address spaces for program
and data memory. The program and data memory can be
up to 64K bytes long. The lower 4K program memory can
reside on-chip. Figure 5 shows a map of the IS89LV51
program and data memory.
The IS89LV51 has 128 bytes of on-chip RAM, plus numbers
of special function registers. The lower 128 bytes can be
accessed either by direct addressing or by indirect
2. Bit Addressable Area: 16 bytes have been assigned
for this segment 20H-2FH. Each one of the 128 bits of
this segment can be directly addressed (0-7FH). Each
of the 16 bytes in this segment can also be addressed
as a byte.
3. Scratch Pad Area: 30H-7FH are available to the user
as data RAM. However, if the data pointer has been
initialized to this area, enough bytes should be left
aside to prevent SP data destruction.
Program Memory
(Read Only)
Data Memory
(Read/Write)
FFFFH
FFFFH:
64K
External
External
Internal
0FFFH:
4K
FFH
EA = 1
Internal
EA = 0
External
0000
PSEN
7FH
00
80H
0000
RD WR
Figure 5. IS89LV51 Program and Data Memory Structure
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10/27/98
7
ISSI
IS89LV51
®
SPECIAL FUNCTION REGISTERS
The Special Function Registers (SFR's) are located in
upper 128 Bytes direct addressing area. The SFR Memory
Map in Figure 6 shows that.
Not all of the addresses are occupied. Unoccupied
addresses are not implemented on the chip. Read accesses
to these addresses in general return random data, and
write accesses have no effect.
User software should not write 1s to these unimplemented
locations, since they may be used in future microcontrollers
to invoke new features. In that case, the reset or inactive
values of the new bits will always be 0, and their active
values will be 1.
FFH
Not
Available
in the
IS89LV51
Upper
128
Accessible
by Direct
Addressing
80H
7FH
80H
Accessible
by Direct
and Indirect
Addressing
Lower
128
Special
Function
Registers
0
Ports,
Status and
Control Bits,
Timer,
Registers,
Stack Pointer,
Accumulator
(Etc.)
F8
F0
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
98
90
88
80
The functions of the SFRs are outlined in the following
sections, and detailed in Table 2.
Accumulator (ACC)
ACC is the Accumulator register. The mnemonics for
Accumulator-specific instructions, however, refer to the
Accumulator simply as A.
B Register (B)
The B register is used during multiply and divide operations.
For other instructions it can be treated as another scratch
pad register.
Program Status Word (PSW). The PSW register contains
program status information.
B
ACC
PSW
IP
P3
IE
P2
SCON
P1
TCON
P0
SBUF
TMOD
SP
TL0
DPL
TL1
DPH
TH0
TH1
PCON
FF
F7
EF
E7
DF
D7
CF
C7
BF
B7
AF
A7
9F
97
8F
87
Bit
Addressable
Figure 6. Internal Data Memory and SFR Memory Map
8 BYTES
78
7F
70
77
68
6F
60
67
58
5F
50
57
48
4F
40
47
38
3F
30
37
...7F
28
20
SCRATCH
PAD
AREA
0 ...
2F
27
18
BANK3
1F
10
BANK2
17
08
BANK 1
0F
00
BANK 0
07
BIT
ADDRESSABLE
SEGMENT
REGISTER
BANKS
Figure 7. Lower 128 Bytes of Internal RAM
8
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IS89LV51
ISSI
®
SPECIAL FUNCTION REGISTERS
(Continued)
Stack Pointer (SP)
The Stack Pointer Register is eight bits wide. It is
incremented before data is stored during PUSH and CALL
executions. While the stack may reside anywhere in onchip RAM, the Stack Pointer is initialized to 07H after a
reset. This causes the stack to begin at location 08H.
Serial Data Buffer (SBUF)
The Serial Data Buffer is actually two separate registers,
a transmit buffer and a receive buffer register. When data
is moved to SBUF, it goes to the transmit buffer, where it
is held for serial transmission. (Moving a byte to SBUF
initiates the transmission.) When data is moved from
SBUF, it comes from the receive buffer.
Data Pointer (DPTR)
The Data Pointer consists of a high byte (DPH) and a low
byte (DPL). Its function is to hold a 16-bit address. It may
be manipulated as a 16-bit register or as two independent
8-bit registers.
Timer Registers
Register pairs (TH0, TL0) and (TH1, TL1) are the 16-bit
Counter registers for Timer/Counters 0 and 1, respectively.
Ports 0 To 3
P0, P1, P2, and P3 are the SFR latches of Ports 0, 1, 2, and
3, respectively.
Control Registers
Special Function Registers IP, IE, TMOD, TCON, SCON,
and PCON contain control and status bits for the interrupt
system, the Timer/Counters, and the serial port. They are
described in later sections of this chapter.
Integrated Silicon Solution, Inc. — 1-800-379-4774
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9
ISSI
IS89LV51
®
Table 2. Special Function Registers
Symbol
Description
Direct Address
ACC(1)
B(1)
DPH
DPL
Accumulator
B register
Data pointer (DPTR) high
Data pointer (DPTR) low
E0H
F0H
83H
82H
IE(1)
Interrupt enable
A8H
IP(1)
Interrupt priority
B8H
P0(1)
Port 0
80H
P1(1)
Port 1
90H
P2(1)
Port 2
A0H
P3(1)
Port 3
B0H
PCON
Power control
87H
PSW(1)
SBUF
Program status word
Serial data buffer
D0H
99H
SCON(1)
SP
Serial controller
Stack pointer
98H
81H
TCON(1)
TMOD
TH0
TH1
TL0
TL1
Timer control
Timer mode
Timer high 0
Timer high 1
Timer low 0
Timer low 1
88H
89H
8CH
8DH
8AH
8BH
Bit Address, Symbol, or Alternative Port Function
E7
F7
E6
F6
E5
F5
E4
F4
E3
F3
E2
F2
AF
EA
BF
—
87
P0.7
AD7
97
P1.7
A7
P2.7
AD15
B7
P3.7
AE
—
BE
—
86
P0.6
AD6
96
P1.6
A6
P2.6
AD14
B6
P3.6
AA
EX1
BA
PX1
82
P0.2
AD2
92
P1.2
A2
P2.2
AD10
B2
P3.2
—
D6
AC
AC
ES
BC
PS
84
P0.4
AD4
94
P1.4
A4
P2.4
AD12
B4
P3.4
T0
—
D4
RS1
AB
ET1
BB
PT1
83
P0.3
AD3
93
P1.3
A3
P2.3
AD11
B3
P3.3
SMOD
D7
CY
AD
—
BD
—
85
P0.5
AD5
95
P1.5
A5
P2.5
AD13
B5
P3.5
T1
—
D5
F0
GF1
D3
RS0
A9
ET0
B9
PT0
81
P0.1
AD1
91
P1.1
A1
P2.1
AD9
B1
P3.1
INT0 TXD
GF0 PD
D2
D1
OV
—
9F
SM0
9E
SM1
9D
SM2
9C
REN
9B
TB8
9A
RB8
99
TI
98
RI
8F
8E
TF1 TR1
GATE C/T
8D
TF0
M1
8C
8B
TR0 IE1
M0 GATE
8A
IT1
C/T
89
IE0
M1
88
IT0
M0
RD
WR
INT1
E1
F1
Reset Value
E0
F0
A8
EX0
B8
PX0
80
P0.0
AD0
90
P1.0
A0
P2.0
AD8
B0
P3.0
RXD
IDL
D0
P
00H
00H
00H
00H
0XX00000B
XXX00000B
FFH
FFH
FFH
FFH
0XXX0000B
00H
XXXXXXXXB
00H
07H
00H
00H
00H
00H
00H
00H
Notes:
1. Denotes bit addressable.
10
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ADVANCE INFORMATION MC020-0A
10/27/98
ISSI
IS89LV51
®
The detail description of each bit is as follows:
PSW:
IE:
Program Status Word. Bit Addressable.
Interrupt Enable Register. Bit Addressable.
7
CY
6
AC
5
F0
4
RS1
3
RS0
2
OV
1
—
0
P
Register Description:
CY
PSW.7
Carry flag.
AC
PSW.6
Auxiliary carry flag.
F0
PSW.5
Flag 0 available to the user for g e n e r a l
purpose.
RS1 PSW.4
Register bank selector bit 1.(1)
RS0 PSW.3
Register bank selector bit 0.(1)
OV
PSW.2
Overflow flag.
—
PSW.1
Usable as a general purpose flag
P
PSW.0
Parity flag. Set/Clear by hardware each
instruction cycle to indicate an odd/even
number of “1” bits in the accumulator.
Note:
1. The value presented by RS0 and RS1 selects the corresponding register bank.
RS1
RS0
Register Bank
Address
0
0
0
00H-07H
0
1
1
08H-0FH
1
0
2
10H-17H
1
1
3
18H-1FH
Power Control Register. Not Bit Addressable.
6
—
5
—
4
—
3
GF1
2
GF0
1
PD
6
—
5
—
4
ES
3
ET1
2
EX1
1
0
ET0 EX0
Register Description:
EA
IE.7
Disable all interrupts. If EA=0, no
interrupt will be acknowledged. If EA=1,
each interrupt source is individually
enabled or disabled by setting or
clearing its enable bit.
—
IE.6
Not implemented, reserve for future
use.(5)
—
IE.5
Not implemented, reserve for future
use.(5)
ES
IE.4
Enable or disable the serial port
interrupt.
ET1 IE.3
Enable or disable the Timer 1 overflow
interrupt.
EX1 IE.2
Enable or disable External Interrupt 1.
ET0 IE.1
Enable or disable the Timer 0 overflow
interrupt.
EX0 IE.0
Enable or disable External Interrupt 0.
Note: To use any of the interrupts in the 80C51 Family, the
following three steps must be taken:
1. Set the EA (enable all) bit in the IE register to 1.
2. Set the coresponding individual interrupt enable bit in
the IE register to 1.
3. Begin the interrupt service routine at the corresponding
Vector Address of that interrupt (see below).
PCON:
7
SMOD
7
EA
0
IDL
Register Description:
SMOD
Double baud rate bit. If Timer 1 is used to generate
baud rate and SMOD=1, the baud rate is doubled
when the serial port is used in modes 1, 2, or 3.
—
Not implemented, reserve for future use.(1)
—
Not implemented, reserve for future use.(1)
—
Not implemented, reserve for future use.(1)
GF1
General purpose flag bit.
GF0
General purpose flag bit.
PD
Power-down bit. Setting this bit activates powerdown mode.
IDL
Idle mode bit. Setting this bit activates idle mode.
If 1s are written to PD and IDL at the same time,
PD takes precedence.
Interrupt Source
IE0
TF0
IE1
TF1
RI & TI
Vector Address
0003H
000BH
0013H
001BH
0023H
4. In addition, for external interrupts, pins INT0 and INT1
(P3.2 and P3.3) must be set to 1, and depending on
whether the interrupt is to be level or transition activated, bits IT0 or IT1 in the TCON register may need to
be set to 0 or 1.
ITX = 0 level activated (X = 0, 1)
ITX = 1 transition activated
5. User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new
features.
Note:
1. User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new features.
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11
ISSI
IS89LV51
IP:
TCON:
Interrupt Priority Register. Bit Addressable.
Timer/Counter Control Register. Bit Addressable
7
—
6
—
5
—
4
PS
3
PT1
2
PX1
1
0
PT0 PX0
Register Description:
—
IP.7
Not implemented, reserve for future use(3)
—
IP.6
Not implemented, reserve for future use(3)
—
IP.5
Not implemented, reserve for future use(3)
PS
IP.4
Defines Serial Port interrupt priority level
PT1 IP.3
Defines Timer 1 interrupt priority level
PX1 IP.2
Defines External Interrupt 1 priority level
PT0 IP.1
Defines Timer 0 interrupt priority level
PX0 IP.0
Defines External Interrupt 0 priority level
Notes:
1. In order to assign higher priority to an interrupt the
coresponding bit in the IP register must be set to 1. While
an interrupt service is in progress, it cannot be interrupted
by a lower or same level interrupt.
2. Priority within level is only to resolve simultaneous
requests of the same priority level. From high-to-low,
interrupt sources are listed below:
IE0
TF0
IE1
TF1
RI or TI
3. User software should not write 1s to reserved bits. These
bits may be used in future products to invoke new features.
12
7
TF1
6
TR1
5
TF0
4
TR0
3
IE1
2
IT1
1
IE0
®
0
IT0
Register Description:
TF1 TCON.7 Timer 1 overflow flag. Set by hardware
when the Timer/Counter 1 overflows.
Cleared by hardware as processor
vectors to the interrupt service routine.
TR1 TCON.6 Timer 1 run control bit. Set/Cleared by
software to turn Timer/Counter 1 ON/
OFF.
TF0 TCON.5 Timer 0 overflow flag. Set by hardware
when the Timer/Counter 0 overflows.
Cleared by hardware as processor
vectors to the interrupt service routine.
TR0 TCON.4 Timer 0 run control bit. Set/Cleared by
software to turn Timer/Counter 0 ON/
OFF.
IE1
TCON.3 External Interrupt 1 edge flag. Set by
hardware when the External Interrupt
edge is detected. Cleared by hardware
when interrupt is processed.
IT1
TCON.2 Interrupt 1 type control bit. Set/Cleared
by software specify falling edge/low level
triggered External Interrupt.
IE0
TCON.1 External Interrupt 0 edge flag. Set by
hardware when the External Interrupt
edge is detected. Cleared by hardware
when interrupt is processed.
IT0
TCON.0 Interrupt 0 type control bit. Set/Cleared
by software specify falling edge/low level
triggered External Interrupt.
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ISSI
IS89LV51
TMOD:
SCON:
Timer/Counter Mode Control Register.
Not Bit Addressable.
Serial Port Control Register. Bit Addressable.
Timer 1
GATE C/T M1 M0
GATE
Timer 0
C/T M1 M0
GATE When TRx (in TCON) is set and GATE=1, TIMER/
COUNTERx will run only while INTx pin is high
(hardware control). When GATE=0, TIMER/
COUNTERx will run only while TRx=1 (software
control).
C/T
Timer or Counter selector. Cleared for Timer
operation (input from internal system clock). Set
for Counter operation (input from Tx input pin).
M1
Mode selector bit.(1)
Mode selector bit.(1)
M0
Note 1:
M1
M0
Operating Mode
0
0
Mode 0. (13-bit Timer)
0
1
Mode 1. (16-bit Timer/Counter)
1
0
Mode 2. (8-bit auto-load Timer/Counter)
1
1
Mode 3. (Splits Timer 0 into TL0 and
TH0. TL0 is an 8-bit Timer/Counter
controller by the standard Timer 0
control bits. TH0 is an 8-bit Timer and
is controlled by Timer 1 control bits.)
1
1
Mode 3. (Timer/Counter 1 stopped).
7
6
5
SM0 SM1 SM2
4
REN
3
TB8
2
RB8
1
TI
®
0
RI
Register Description:
SM0 SCON.7 Serial port mode specifier.(1)
SM1 SCON.6 Serial port mode specifier.(1)
SM2 SCON.5 Enable the multiprocessor communication feature in mode 2 and 3. In
mode 2 or 3, if SM2 is set to 1 then RI
will not be activated if the received 9th
data bit (RB8) is 0. In mode 1, if SM2=1
then RI will not be activated if valid stop
bit was not received. In mode 0, SM2
should be 0.
REN SCON.4 Set/Cleared by software to Enable/
Disable reception.
TB8 SCON.3 The 9th bit that will be transmitted in
mode 2 and 3. Set/Cleared by software.
RB8 SCON.2 In modes 2 and 3, RB8 is the 9th data
bit that was received. In mode 1, if
SM2=0, RB8 is the stop bit that was
received. In mode 0, RB8 is not used.
TI
SCON.1 Transmit interrupt flag. Set by hardware
at the end of the eighth bit time in mode
0, or at the beginning of the stop bit in
the other modes. Must be cleared by
software.
RI
SCON.0 Receive interrupt flag. Set by hardware
at the end of the eighth bit time in mode
0, or halfway through the stop bit time
in the other modes (except see SM2).
Must be cleared by software.
Note 1:
SM0 SM1 MODE
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Description
Baud Rate
0
0
0
Shift register
Fosc/12
0
1
1
8-bit UART
Variable
1
0
2
9-bit UART
Fosc/64 or
Fosc/32
1
1
3
9-bit UART
Variable
13
ISSI
IS89LV51
®
TIMER/COUNTERS
Timer 0 and Timer 1
The IS89LV51 has two 16-bit Timer/Counter registers:
Timer 0 and Timer 1. All two can be configured to operate
either as Timers or event Counters.
The Timer or Counter function is selected by control bits
C/T in the Special Function Regiser TMOD. These two
Timer/Counters have four operating modes, which are
selected by bit pairs (M1, M0) in TMOD. Modes 0, 1, and 2
are the same for both Timer/Counters, but Mode 3 is different.
The four modes are described in the following sections.
As a Timer, the register is incremented every machine cycle.
Thus, the register counts machine cycles. Since a machine
cycle consists of 12 oscillator periods, the count rate is 1/12
of the oscillator frequency.
As a Counter, the register is incremented in response to a
1-to-0 transition at its corresponding external input pin, T0
and T1. The external input is sampled during S5P2 of every
machine cycle. When the samples show a high in one cycle
and a low in the next cycle, the count is incremented. The
new count value appears in the register during S3P1 of the
cycle following the one in which the transition was detected.
Since two machine cycles (24 oscillator periods) are required
to recognize a 1-to-0 transition, the maximum count rate is
1/24 of the oscillator frequency. There are no restrictions on
the duty cycle of the external input signal, but it should be
held for at least one full machine cycle to ensure that a given
level is sampled at least once before it changes.
In addition to the Timer or Counter functions, Timer 0 and
Timer 1 have four operating modes: 13-bit timer, 16-bit timer,
8-bit auto-reload, split timer.
Mode 0:
Both Timers in Mode 0 are 8-bit Counters with a divide-by-32
prescaler. Figure 8 shows the Mode 0 operation as it applies
to Timer 1.
In this mode, the Timer register is configured as a 13-bit
register. As the count rolls over from all 1s to all 0s, it sets the
Timer interrupt flag TF1. The counted input is enabled to the
Timer when TR1 = 1 and either GATE = 0 or INT1 = 1. Setting
GATE = 1 allows the Timer to be controlled by external input
INT1, to facilitate pulse width measurements. TR1 is a
control bit in the Special Function Register TCON. Gate is in
TMOD.
The 13-bit register consists of all eight bits of TH1 and the
lower five bits of TL1. The upper three bits of TL1 are
indeterminate and should be ignored. Setting the run flag
(TR1) does not clear the registers.
Mode 0 operation is the same for Timer 0 as for Timer 1,
except that TR0, TF0 and INT0 replace the corresponding
Timer 1 signals in Figure 8. There are two different GATE
bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
ONE MACHINE
ONE MACHINE
CYCLE
CYCLE
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S1
S2
S3
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
OSC
(XTAL2)
OSC
DIVIDE 12
C/T = 0
TL1
(5 BITS)
TH1
(8 BITS)
TF1
INTERRUPT
C/T = 1
T1 PIN
CONTROL
TR1
GATE
INT1 PIN
Figure 8. Timer/Counter 1 Mode 0: 13-Bit Counter
14
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ISSI
IS89LV51
Mode 1:
Mode 1 is the same as Mode 0, except that the Timer
register is run with all 16 bits. The clock is applied to the
combined high and low timer registers (TL1/TH1). As clock
pulses are received, the timer counts up: 0000H, 0001H,
0002H, etc. An overflow occurs on the FFFFH-to-0000H
overflow flag. The timer continues to count. The overflow
flag is the TF1 bit in TCON that is read or written by software
(see Figure 9).
Mode 2:
Mode 2 configures the Timer register as an 8-bit Counter
(TL1) with automatic reload, as shown in Figure 10. Overflow
from TL1 not only sets TF1, but also reloads TL1 with the
contents of TH1, which is preset by software. The reload
leaves the TH1 unchanged. Mode 2 operation is the same
for Timer/Counter 0.
TIMER
CLOCK
TL1
(8 BITS)
®
Mode 3:
Timer 1 in Mode 3 simply holds its count. The effect is the
same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0
and TH0 as two separate counters. The logic for Mode 3 on
Timer 0 is shown in Figure 11. TL0 uses the Timer 0 control
bits: C/T, GATE, TR0, INT0, and TF0. TH0 is locked into a
timer function (counting machine cycles) and over the use
of TR1 and TF1 from Timer 1. Thus, TH0 now controls the
Timer 1 interrupt.
Mode 3 is for applications requiring an extra 8-bit timer or
counter. With Timer 0 in Mode 3, the IS89LV51 can appear
to have three Timer/Counters. When Timer 0 is in Mode 3,
Timer 1 can be turned on and off by switching it out of and
into its own Mode 3. In this case, Timer 1 can still be used
by the serial port as a baud rate generator or in any
application not requiring an interrupt.
TH1
(8 BITS)
TF1
OVERFLOW
FLAG
Figure 9. Timer/Counter 1 Mode 1: 16-Bit Counter
OSC
DIVIDE 12
C/T = 0
TL1
(8 BITS)
TF1
INTERRUPT
C/T = 1
T1 PIN
RELOAD
CONTROL
TR1
GATE
TH1
(8 BITS)
INT0 PIN
Figure 10. Timer/Counter 1 Mode 2: 8-Bit Auto-Reload
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15
ISSI
IS89LV51
OSC
DIVIDE 12
®
1/12 FOSC
1/12 FOSC
C/T = 0
TL0
(8 BITS)
TF0
INTERRUPT
TH0
(8 BITS)
TF1
INTERRUPT
C/T = 1
T0 PIN
CONTROL
TR0
GATE
INT0 PIN
1/12 FOSC
TR1
CONTROL
Figure 11. Timer/Counter 0 Mode 3: Two 8-Bit Counters
16
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ISSI
IS89LV51
Timer Setup
Table 5. Timer/Counter 1 Used as a Timer
Tables 3 through 6 give TMOD values that can be used to
set up Timers in different modes.
It assumes that only one timer is used at a time. If Timers
0 and 1 must run simultaneously in any mode, the value in
TMOD for Timer 0 must be ORed with the value shown for
Timer 1 (Tables 5 and 6).
For example, if Timer 0 must run in Mode 1 GATE (external
control), and Timer 1 must run in Mode 2 COUNTER, then
the value that must be loaded into TMOD is 69H (09H from
Table 3 ORed with 60H from Table 6).
Moreover, it is assumed that the user is not ready at this
point to turn the timers on and will do so at another point
in the program by setting bit TRx (in TCON) to 1.
Table 3. Timer/Counter 0 Used as a Timer
Mode
Timer 0
Function
®
TMOD
Internal
External
Control(1) Control(2)
0
13-Bit Timer
00H
08H
1
16-Bit Timer
01H
09H
2
8-Bit Auto-Reload
02H
0AH
3
Two 8-Bit Timers
03H
0BH
TMOD
Internal
External
Control(1) Control(2)
Mode
Timer 1
Function
0
13-Bit Timer
00H
80H
1
16-Bit Timer
10H
90H
2
8-Bit Auto-Reload
20H
A0H
3
Does Not Run
30H
B0H
Table 6. Timer/Counter 1 Used as a Counter
TMOD
Internal
External
Control(1) Control(2)
Mode
Timer 1
Function
0
13-Bit Timer
40H
C0H
1
16-Bit Timer
50H
D0H
2
8-Bit Auto-Reload
60H
E0H
3
Not Available
—
—
Notes:
1. The Timer is turned ON/OFF by setting/clearing bit TR1
in the software.
2. The Timer is turned ON/OFF by the 1-to-0 transition on
INT1 (P3.3) when TR1 = 1 (hardware control).
Table 4. Timer/Counter 0 Used as a Counter
TMOD
Internal
External
Control(1)
Control(2)
Mode
Timer 0
Function
0
13-Bit Timer
04H
0CH
1
16-Bit Timer
05H
0DH
2
8-Bit Auto-Reload
06H
0EH
3
One 8-Bit Counter
07H
0FH
Notes:
1. The Timer is turned ON/OFF by setting/clearing bit TR0
in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on
INT0 (P3.2) when TR0 = 1 (hardware control).
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17
IS89LV51
ISSI
®
SERIAL INTERFACE
The Serial port is full duplex, which means it can transmit
and receive simultaneously. It is also receive-buffered,
which means it can begin receiving a second byte before
a previously received byte has been read from the receive
register. (However, if the first byte still has not been read
when reception of the second byte is complete, one of the
bytes will be lost.) The serial port receive and transmit
registers are both accessed at Special Function Register
SBUF. Writing to SBUF loads the transmit register, and
reading SBUF accesses a physically separate receive
register.
The serial port can operate in the following four modes:
Mode 0:
Serial data enters and exits through RXD. TXD outputs the
shift clock. Eight data bits are transmitted/received, with
the LSB first. The baud rate is fixed at 1/12 the oscillator
frequency (see Figure 12).
Mode 1:
Ten bits are transmitted (through TXD) or received (through
RXD): a start bit (0), eight data bits (LSB first), and a stop
bit (1). On receive, the stop bit goes into RB8 in Special
Function Register SCON. The baud rate is variable (see
Figure 13).
18
Mode 2:
Eleven bits are transmitted (through TXD) or received
(through RXD): a start bit (0), eight data bits (LSB first), a
programmable ninth data bit, and a stop bit (1). On transmit,
the ninth data bit (TB8 in SCON) can be assigned the value
of 0 or 1. Or, for example, the parity bit (P, in the PSW) can
be moved into TB8. On receive, the ninth data bit goes into
RB8 in Special Function Register SCON, while the stop bit
is ignored. The baud rate is programmable to either 1/32 or
1/64 the oscillator frequency (see Figure 14).
Mode 3:
Eleven bits are transmitted (through TXD) or received
(through RXD): a start bit (0), eight data bits (LSB first), a
programmable ninth data bit, and a stop bit (1). In fact,
Mode 3 is the same as Mode 2 in all respects except the
baud rate, which is variable in Mode 3 (see Figure 15).
In all four modes, transmission is initiated by any instruction
that uses SBUF as a destination register. Reception is
initiated in Mode 0 by the condition RI = 0 and REN = 1.
Reception is initiated in the other modes by the incoming
start bit if REN = 1.
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ISSI
IS89LV51
Multiprocessor Communications
Modes 2 and 3 have a special provision for multiprocessor
communications. In these modes, nine data bits are
received, followed by a stop bit. The ninth bit goes into
RB8; then comes a stop bit. The port can be programmed
such that when the stop bit is received, the serial port
interrupt is activated only if RB8 = 1. This feature is
enabled by setting bit SM2 in SCON.
The following example shows how to use the serial interrupt
for multiprocessor communications. When the master
processor must transmit a block of data to one of several
slaves, it first sends out an address byte that identifies the
target slave. An address byte differs from a data byte in
that the ninth bit is 1 in an address byte and 0 in a data byte.
With SM2 = 1, no slave is interrupted by a data byte. An
address byte, however, interrupts all slaves, so that each
slave can examine the received byte and see if it is being
addressed. The addressed slave clears its SM2 bit and
prepares to receive the data bytes that follows. The slaves
that are not addressed set their SM2 bits and ignore the
data bytes.
SM2 has no effect in Mode 0 but can be used to check the
validity of the stop bit in Mode 1. In a Mode 1 reception, if
SM2 = 1, the receive interrupt is not activated unless a
valid stop bit is received.
®
Using the Timer 1 to Generate Baud Rates
When Timer 1 is the baud rate generator, the baud rates in
Modes 1 and 3 are determined by the Timer 1 overflow rate
and the value of SMOD according to the following equation.
Mode 1, 3
=
Baud Rate
2SMOD
32
X
(Timer 1 Overflow Rate)
The Timer 1 interrupt should be disabled in this application.
The Timer itself can be configured for either timer or
counter operation in any of its three running modes. In the
most typical applications, it is configured for timer operation
in auto-reload mode (high nibble of TMOD = 0010B). In this
case, the baud rate is given by the following formula.
Mode 1,3
=
Baud Rate
2SMOD
32
X
Oscillator Frequency
12x [256 – (TH1)]
Programmers can achieve very low baud rates with Timer
1 by leaving the Timer 1 interrupt enabled, configuring the
Timer to run as a 16-bit timer (high nibble of TMOD =
0001B), and using the Timer 1 interrupt to do a 16-bit
software reload.
Table 7 lists commonly used baud rates and how they can
be obtained from Timer 1.
Baud Rates
The baud rate in Mode 0 is fixed as shown in the following
equation.
Oscillator Frequency
12
The baud rate in Mode 2 depends on the value of the
SMOD bit in Special Function Register PCON. If SMOD =
0 (the value on reset), the baud rate is 1/64 of the oscillator
frequency. If SMOD = 1, the baud rate is 1/32 of the
oscillator frequency, as shown in the following equation.
Mode 0 Baud Rate =
Mode 2 Baud Rate =
2SMOD
x (Oscillator Frequency)
64
In the IS89LV51, the Timer 1 overflow rate determines the
baud rates in Modes 1 and 3.
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19
ISSI
IS89LV51
®
Table 7. Commonly Used Baud Rates Generated by Timer 1
Timer 1
Baud Rate
Mode 0 Max: 1 MHz
Mode 2 Max: 375K
Modes 1, 3: 62.5K
19.2K
9.6K
4.8K
2.4K
1.2K
137.5
110
110
fOSC
12 MHz
12 MHz
12 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.059 MHz
11.986 MHz
6 MHz
12 MHz
SMOD
X
1
1
1
0
0
0
0
0
0
0
More About Mode 0
Serial data enters and exits through RXD. TXD outputs the
shift clock. Eight data bits are transmitted/received, with
the LSB first. The baud rate is fixed at 1/12 the oscillator
frequency.
Figure 12 shows a simplified functional diagram of the
serial port in Mode 0 and associated timing.
Transmission is initiated by any instruction that uses SBUF
as a destination register. The "write to SBUF" signal at
S6P2 also loads a 1 into the ninth position of the transmit
shift register and tells the TX Control block to begin a
transmission. The internal timing is such that one full
machine cycle will elapse between "write to SBUF" and
activation of SEND.
SEND transfer the output of the shift register to the
alternate output function line of P3.0, and also transfers
SHIFT CLOCK to the alternate output function line of P3.1.
SHIFT CLOCK is low during S3, S4, and S5 of every
machine cycle, and high during S6, S1, and S2. At S6P2
of every machine cycle in which SEND is active, the
contents of the transmit shift register are shifted one
position to the right.
As data bits shift out to the right, 0s come in from the left.
When the MSB of the data byte is at the output position of
the shift register, the 1 that was initially loaded into the
ninth position is just to the left of the MSB, and all positions
to the left of that contain 0s. This condition flags the TX
Control block to do one last shift, then deactivate SEND
and set TI. Both of these actions occur at S1P1 of the tenth
machine cycle after "write to SBUF."
20
C/T
X
X
0
0
0
0
0
0
0
0
0
Mode
X
X
2
2
2
2
2
2
2
2
1
Reload Value
X
X
FFH
FDH
FDH
FAH
F4H
E8H
1DH
72H
FEEBH
Reception is initiated by the condition REN = 1 and
RI = 0. At S6P2 of the next machine cycle, the RX Control
unit writes the bits 11111110 to the receive shift register
and activates RECEIVE in the next clock phase.
RECEIVE enables SHIFT CLOCK to the alternate output
function line of P3.1. SHIFT CLOCK makes transitions at
S3P1 and S6P1 of every machine cycle. At S6P2 of every
machine cycle in which RECEIVE is active, the contents of
the receive shift register are shifted on position to the left.
The value that comes in from the right is the value that was
sampled at the P3.0 pin at S5P2 of the same machine
cycle.
As data bits come in from the right, 1s shift out to the left.
When the 0 that was initially loaded into the right-most
position arrives at the left-most position in the shift register,
it flags the RX Control block to do one last shift and load
SBUF. At S1P1 of the tenth machine cycle after the write
to SCON that cleared RI, RECEIVE is cleared and RI is set.
More About Mode 1
Ten bits are transmitted (through TXD), or received (through
RXD): a start bit (0), eight data bits (LSB first), and a stop
bit (1). On receive, the stop bit goes into RB8 in SCON. In
the IS89LV51 the baud rate is determined by the Timer 1
overflow rate.
Figure 13 shows a simplified functional diagram of the
serial port in Mode 1 and associated timings for transmit
and receive.
Transmission is initiated by any instruction that uses SBUF
as a destination register.
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IS89LV51
The "write to SBUF" signal also loads a 1 into the ninth bit
position of the transmit shift register and flags the TX
control unit that a transmission is requested. Transmission
actually commences at S1P1 of the machine cycle following
the next rollover in the divide-by-16 counter. Thus, the bit
times are synchronized to the divide-by-16 counter, not to
the "write to SBUF" signal.
The transmission begins when SEND is activated, which
puts the start bit at TXD. One bit time later, DATA is
activated, which enables the output bit of the transmit shift
register to TXD. The first shift pulse occurs one bit time
after that.
As data bits shift out to the right, 0s are clocked in from the
left. When the MSB of the data byte is at the output position
of the shift register, the 1 that was initially loaded into the
ninth position is just to the left of the MSB, and all positions
to the left of that contain 0s. This condition flags the TX
Control unit to do one last shift, then deactivate SEND and
set TI. This occurs at the tenth divide-by-16 rollover after
"write to SBUF".
Reception is initiated by a 1-to-0 transition detected at
RXD. For this purpose, RXD is sampled at a rate of 16
times the established baud rate. When a transition is
detected, the divide-by-16 counter is immediately reset,
and 1FFH is written into the input shift register. Resetting
the divide-by-16 counter aligns its rollovers with the
boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16th.
At the seventh, eighth, and ninth counter states of each bit
time, the bit detector samples the value of RXD. The value
accepted is the value that was seen in at least two of the
three samples. This is done to reject noise. In order to
reject false bits, if the value accepted during the first bit
time is not 0, the receive circuits are reset and the unit
continues looking for another 1-to-0 transition. If the start
bit is valid, it is shifted into the input shift register, and
reception of the rest of the frame proceeds.
As data bits come in from the right, 1s shift to the left. When
the start bit arrives at the leftmost position in the shift
register, (which is a 9-bit register in Mode 1), it flags the RX
Control block to do one last shift, load SBUF and RB8, and
set RI. The signal to load SBUF and RB8 and to set RI is
generated if, and only if, the following conditions are met
at the time the final shift pulse is generated.
1) RI = 0 and
ISSI
®
If either of these two conditions is not met, the received
frame is irretrievably lost. If both conditions are met, the
stop bit goes into RB8, the eight data bits go into SBUF,
and RI is activated. At this time, whether or not the above
conditions are met, the unit continues looking for a 1-to-0
transition in RXD.
More About Modes 2 and 3
Eleven bits are transmitted (through TXD), or received
(through RXD): a start bit (0), eight data bits (LSB first), a
programmable ninth data bit, and a stop bit (1). On
transmit, the ninth data bit (TB8) can be assigned the value
of 0 or 1. On receive, the ninth data bit goes into RB8 in
SCON. The baud rate is programmable to either 1/32 or
1/64 of the oscillator frequency in Mode 2. Mode 3 may
have a variable baud rate generated from Timer 1.
Figures 14 and 15 show a functional diagram of the serial
port in Modes 2 and 3. The receive portion is exactly the
same as in Mode 1. The transmit portion differs from Mode
1 only in the ninth bit of the transmit shift register.
Transmission is initiated by any instruction that uses SBUF
as a destination register. The "write to SBUF" signal also
loads TB8 into the ninth bit position of the transmit shift
register and flags the TX Control unit that a transmission
is requested. Transmission commences at S1P1 of the
machine cycle following the next rollover in the divide-by16 counter. Thus, the bit times are synchronized to the
divide-by-16 counter, not to the "write to SBUF" signal.
The transmission begins when SEND is activated, which
puts the start bit at TXD. One bit timer later, DATA is
activated, which enables the output bit of the transmit shift
register to TXD. The first shift pulse occurs one bit time
after that. The first shift clocks a 1 (the stop bit) into the
ninth bit position of the shift register. Thereafter, only 0s
are clocked in. Thus, as data bits shift out to the right, 0s
are clocked in from the left. When TB8 is at the output
position of the shift register, then the stop bit is just to the
left of TB8, and all positions to the left of that contain 0s.
This condition flags the TX Control unit to do one last shift,
then deactivate SEND and set TI. This occurs at the
eleventh divide-by-16 rollover after "write to SBUF".
Reception is initiated by a 1-to-0 transition detected at
RXD. For this purpose, RXD is sampled at a rate of 16
times the established baud rate. When a transition is
detected, the divide-by-16 counter is immediately reset,
and 1FFH is written to the input shift register.
2) Either SM2 = 0, or the received stop bit =1
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21
ISSI
IS89LV51
At the seventh, eighth, and ninth counter states of each bit
time, the bit detector samples the value of RXD. The value
accepted is the value that was seen in at least two of the
three samples. If the value accepted during the first bit time
is not 0, the receive circuits are reset and the unit continues
looking for another 1-to-0 transition. If the start bit proves
valid, it is shifted into the input shift register, and reception
of the rest of the frame proceeds.
As data bits come in from the right, 1s shift out to the left.
When the start bit arrives at the leftmost position in the shift
register (which in Modes 2 and 3 is a 9-bit register), it flags
the RX Control block to do one last shift, load SBUF and
RB8, and set RI. The signal to load SBUF and RB8 and to
set RI is generated if, and only if, the following conditions
are met at the time the final shift pulse is generated:
®
Table 8. Serial Port Setup
Mode
SCON
0
10H
1
50H
2
90H
3
D0H
0
NA
1
70H
2
B0H
3
F0H
SM2Variation
Single Processor
Environment
(SM2 = 0)
Multiprocessor
Environment
(SM2 = 1)
1) RI = 0, and
2) Either SM2 = 0 or the received ninth data bit = 1
If either of these conditions is not met, the received frame
is irretrievably lost, and RI is not set. If both conditions are
met, the received ninth data bit goes into RB8, and the first
eight data bits go into SBUF. One bit time later, whether the
above conditions were met or not, the unit continues
looking for a 1-to-0 transition at the RXD input.
Note that the value of the received stop bit is irrelevant to
SBUF, RB8, or RI.
22
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ISSI
IS89LV51
®
IS89LV51 INTERNAL BUS
WRITE
TO
SBUF
S
D Q
CL
RXD
P3.0 ALT
OUTPUT
FUNCTION
SBUF
SHIFT
ZERO DETECTOR
START
SHIFT
TX CONTROL
S6
TX CLOCK
SEND
SERIAL
PORT
INTERRUPT
RI
RX CLOCK
REN
RI
TXD
P3.1 ALT
OUTPUT
FUNCTION
SHIFT
CLOCK
RECEIVE
RX CONTROL
SHIFT
1 1 1 1 1 1 1 0
START
RXD
P3.0 ALT
INPUT
FUNCTION
INPUT SHIFT REG.
LOAD
SBUF
SHIFT
SBUF
READ
SBUF
IS89LV51 INTERNAL BUS
S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1
ALE
WRITE TO SBUF
SEND
S6P2
SHIFT
RXD (DOUT)
D0
D1
D2
D3
D5
D4
D6
D7
TRANSMIT
TXD (SHIFT CLOCK)
S6P1
S3P1
TI
WRITE TO SCON (CLEAR RI)
RI
RECEIVE
SHIFT
RXD (DIN)
RECEIVE
D0
D1
D2
D3
D4
D5
D6
D7
S5P2
TXD (SHIFT CLOCK)
Figure 12. Serial Port Mode 0
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ISSI
IS89LV51
®
IS89LV51 INTERNAL BUS
TB8
TIMER 1
OVERFLOW
TIMER 2
OVERFLOW
WRITE
TO
SBUF
2
S
D Q
CL
SMOD
=1
SMOD
=0
SBUF
TXD
ZERO DETECTOR
"0"
"1"
SHIFT DATA
TX CONTROL
RX CLOCK
SEND
TI
START
TCLK
16
"1"
"0"
SERIAL
PORT
INTERRUPT
RCLK
16
SAMPLE
LOAD
SBUF
SHIFT
1FFH
RI
RX CLOCK
1-TO-0
TRANSITION
DETECTOR
RX CONTROL
START
BIT
DETECTOR
INPUT SHIFT REG.
(9 BITS)
RXD
LOAD
SBUF
SHIFT
SBUF
READ
SBUF
IS89LV51 INTERNAL BUS
TX CLOCK
WRITE TO SBUF
SEND
S1P1
DATA
TRANSMIT
SHIFT
START
BIT
TXD
D0
D1
D2
D3
D4
D5
D6
STOP BIT
D7
TI
RECEIVE
RX
CLOCK
16 RESET
RXD
START
BIT
D0
D1
D2
D3
D4
D5
D6
D7
STOP BIT
BIT DETECTOR SAMPLE TIMES
SHIFT
RI
Figure 13. Serial Port Mode 1
24
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ISSI
IS89LV51
®
IS89LV51 INTERNAL BUS
TB8
WRITE
TO
SBUF
S
D Q
CL
SBUF
TXD
ZERO DETECTOR
PHASE 2 CLOCK
(1/2 fOSC)
START STOP BIT GEN SHIFT DATA
TX CONTROL
TX CLOCK
SEND
TI
MODE 2
16
SMOD 1
2
SERIAL
PORT
INTERRUPT
SMOD 0
16
(SMOD IS PCON. 7)
SAMPLE
1-TO-0
TRANSITION
DETECTOR
START
LOAD
SBUF
SHIFT
1FFH
RI
RX
CLOCK
RX CONTROL
BIT
DETECTOR
INPUT SHIFT REG.
(9 BITS)
RXD
LOAD
SBUF
SHIFT
SBUF
READ
SBUF
IS89LV51 INTERNAL BUS
TX
CLOCK
WRITE TO SBUF
SEND
S1P1
DATA
TRANSMIT
SHIFT
START
BIT
TXD
D0
D1
D2
D3
D4
D5
D6
D2
D3
D4
D7
TB8
STOP BIT
D6
D7
TI
STOP BIT GEN
RX
CLOCK
RXD
RECEIVE
16 RESET
START
BIT
D0
D1
D5
RB8
STOP
BIT
BIT DETECTOR SAMPLE TIMES
SHIFT
RI
Figure 14. Serial Port Mode 2
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25
ISSI
IS89LV51
®
IS89LV51 INTERNAL BUS
TB8
TIMER 1
OVERFLOW
TIMER 2
OVERFLOW
WRITE
TO
SBUF
2
S
D Q
CL
SMOD
=1
SMOD
=0
SBUF
TXD
ZERO DETECTOR
"0"
"1"
SHIFT DATA
TX CONTROL
TX CLOCK
SEND
TI
START
TCLK
16
"0"
SERIAL
PORT
INTERRUPT
"1"
RCLK
16
SAMPLE
START
LOAD
SBUF
SHIFT
1FFH
RI
RX CLOCK
1-TO-0
TRANSITION
DETECTOR
RX CONTROL
BIT
DETECTOR
INPUT SHIFT REG.
(9 BITS)
RXD
LOAD
SBUF
SHIFT
SBUF
READ
SBUF
IS89LV51 INTERNAL BUS
TX
CLOCK
WRITE TO SBUF
SEND
S1P1
DATA
TRANSMIT
SHIFT
START
BIT
TXD
D0
D1
D2
D3
D4
D5
D6
D7
TB8
STOP BIT
D3
D4
D5
D6
D7
TI
STOP BIT GEN
RX
CLOCK
RXD
RECEIVE
16 RESET
START
BIT
D0
D1
D2
RB8
STOP
BIT
BIT DETECTOR SAMPLE TIMES
SHIFT
RI
Figure 15. Serial Port Mode 3
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ISSI
IS89LV51
®
INTERRUPT SYSTEM
The Serial Port Interrupt is generated by the logical OR of
RI and TI. Neither of these flags is cleared by hardware
when the service routine is vectored to. In fact, the service
routine normally must determine whether RI or TI generated
the interrupt, and the bit must be cleared in software.
The IS89LV51 provides six interrupt sources: two external
interrupts, two timer interrupts, and a serial port interrupt.
These are shown in Figure 16.
The External Interrupts INT0 and INT1 can each be either
level-activated or transition-activated, depending on bits
IT0 and IT1 in Register TCON. The flags that actually
generate these interrupts are the IE0 and IE1 bits in
TCON. When the service routine is vectored, hardware
clears the flag that generated an external interrupt only if
the interrupt was transition-activated. If the interrupt was
level-activated, then the external requesting source (rather
than the on-chip hardware) controls the request flag.
All of the bits that generate interrupts can be set or cleared
by software, with the same result as though they had been
set or cleared by hardware. That is, interrupts can be
generated and pending interrupts can be canceled in
software.
Each of these interrupt sources can be individually enabled
or disabled by setting or clearing a bit in Special Function
Register IE (interrupt enable) at address 0A8H. As well as
individual enable bits for each interrupt source, there is a
global enable/disable bit that is cleared to disable all
interrupts or set to turn on interrupts (see SFR IE).
The Timer 0 and Timer 1 Interrupts are generated by TF0
and TF1, which are set by a rollover in their respective
Timer/Counter registers (except for Timer 0 in Mode 3).
When a timer interrupt is generated, the on-chip hardware
clears the flag that generated it when the service routine is
vectored to.
POLLING
HARDWARE
TCON.1
INT0
IE.0
IE.7
HIGH PRIORITY
INTERRUPT
REQUEST
IP.0
EXTERNAL
INT RQST 0
IE0
EX0
PX0
TCON.5
IE.1
IP.1
TF0
ET0
PT0
TCON.3
IE.2
IP.2
IE1
EX1
PX1
TCON.7
IE.3
IP.3
TF1
ET1
PT1
SCON.0
INTERNAL
RI
SERIAL
SCON.1
PORT
TI
IE.4
IP.4
TIMER/COUNTER 0
INT1
SOURCE
I.D.
VECTOR
EXTERNAL
INT RQST 1
TIMER/COUNTER 1
ES
EA
LOW PRIORITY
INTERRUPT
REQUEST
PS
SOURCE
I.D.
VECTOR
Figure 16. Interrupt System
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27
ISSI
IS89LV51
®
Priority Level Structure
interrupt system will generate an LCALL to the appropriate
service routine, provided this hardware generated LCALL
is not blocked by any of the following conditions:
Each interrupt source can also be individually programmed
to one of two priority levels by setting or clearing a bit in
Special Function Register IP (interrupt priority) at address
0B8H. IP is cleared after a system reset to place all
interrupts at the lower priority level by default. A lowpriority interrupt can be interrupted by a high-priority
interrupt but not by another low-priority interrupt. A highpriority interrupt can not be interrupted by any other
interrupt source.
1. An interrupt of equal or higher priority level is already
in progress.
2. The current (polling) cycle is not the final cycle in the
execution of the instruction in progress.
3. The instruction in progress is RETI or any write to the
IE or IP registers.
If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced. If requests of the same priority level are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority level
there is a second priority structure determined by the
polling sequence, as follows:
1.
2.
3.
4.
5.
Source
IE0
TF0
IE1
TF1
RI + TI
Any of these three conditions will block the generation of
the LCALL to the interrupt service routine. Condition 2
ensures that the instruction in progress will be completed
before vectoring to any service routine. Condition 3 ensures
that if the instruction in progress is RETI or any access to
IE or IP, then at least one more instruction will be executed
before any interrupt is vectored to.
Priority Within Level
(Highest)
The polling cycle is repeated with each machine cycle, and
the values polled are the values that were present at S5P2
of the previous machine cycle. If an active interrupt flag is
not being serviced because of one of the above conditions
and is not still active when the blocking condition is
removed, the denied interrupt will not be serviced. In other
words, the fact that the interrupt flag was once active but
not serviced is not remembered. Every polling cycle is
new. The polling cycle/LCALL sequence is illustrated in
Figure 17.
(Lowest)
Note that the "priority within level" structure is only used to
resolve simultaneous requests of the same priority level.
How Interrupts Are Handled
Note that if an interrupt of higher priority level goes active
prior to S5P2 of the machine cycle labeled C3 in Figure 17,
then in accordance with the above rules it will be serviced
during C5 and C6, without any instruction of the lower
priority routine having been executed.
The interrupt flags are sampled at S5P2 of every machine
cycle. The samples are polled during the following machine
cycle. If one of the flags was in a set condition at S5P2 of
the preceding cycle, the polling cycle will find it and the
S5P2
C1
S6
E
INTERRUPT
GOES ACTIVE
INTERRUPT
LATCHED
C2
C3
INTERRUPTS
ARE POLLED
C4
C5
LONG CALL TO
INTERRUPT
VECTOR ADDRESS
INTERRUPT
ROUTINE
Figure 17. Interrupt Response Timing Diagram
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ISSI
IS89LV51
Thus, the processor acknowledges an interrupt request by
executing a hardware-generated LCALL to the appropriate
servicing routine. In some cases it also clears the flag that
generated the interrupt, and in other cases it does not. It
never clears the Serial Port flags. This must be done in the
user's software. The processor clears an external interrupt
flag (IE0 or IE1) only if it was transition-activated. The
hardware-generated LCALL pushes the contents of the
Program Counter onto the stack (but it does not save the
PSW) and reloads the PC with an address that depends on
the source of the interrupt being serviced, as shown in the
following table.
Interrupt
Source
INT0
Timer 0
INT1
Timer 1
Serial Port
System
Reset
Interrupt
Request Bits
IE0
TF0
IE1
TF1
RI, TI
RST
Cleared by
Hardware
No (level)
Yes (trans.)
Yes
No (level)
Yes (trans.)
Yes
No
Vector
Address
0003H
000BH
0013H
001BH
0023H
0000H
Execution proceeds from that location until the RETI
instruction is encountered. The RETI instruction informs
the processor that this interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the interrupted
program continues from where it left off.
Note that a simple RET instruction would also have returned
execution to the interrupted program, but it would have left
the interrupt control system thinking an interrupt was still in
progress.
Interrupt
External 0
External 1
Timer 1
Timer 0
Serial Port
Serial Port
Flag
IE0
IE1
TF1
TF0
TI
RI
SFR Register and
Bit Position
TCON.1
TCON.3
TCON.7
TCON.5
SCON.1
SCON.0
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®
When an interrupt is accepted, the following action occurs:
1. The current instruction completes operation.
2. The PC is saved on the stack.
3. The current interrupt status is saved internally.
4. Interrupts are blocked at the level of the interrupts.
5. The PC is loaded with the vector address of the ISR
(interrupts service routine).
6. The ISR executes.
The ISR executes and takes action in response to the
interrupt. The ISR finishes with RETI (return from interrupt)
instruction. This retrieves the old value of the PC from the
stack and restores the old interrupt status. Execution of the
main program continues where it left off.
External Interrupts
The external sources can be programmed to be levelactivated or transition-activated by setting or clearing bit
IT1 or IT0 in Register TCON. If ITx= 0, external interrupt x
is triggered by a detected low at the INTx pin. If ITx = 1,
external interrupt x is edge-triggered. In this mode if
successive samples of the INTx pin show a high in one
cycle and a low in the next cycle, interrupt request flag IEx
in TCON is set. Flag bit IEx then requests the interrupt.
Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at least
12 oscillator periods to ensure sampling. If the external
interrupt is transition-activated, the external source has to
hold the request pin high for at least one machine cycle,
and then hold it low for at least one machine cycle to
ensure that the transition is seen so that interrupt request
flag IEx will be set. IEx will be automatically cleared by the
CPU when the service routine is called.
If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then the external source
must deactivate the request before the interrupt service
routine is completed, or else another interrupt will be
generated.
29
ISSI
IS89LV51
Response Time
The INT0 and INT1 levels are inverted and latched into the
interrupt flags IE0 and IE1 at S5P2 of every machine cycle.
Similarly, the Serial Port flags RI and TI are set at S5P2.
The values are not actually polled by the circuitry until the
next machine cycle.
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
S5P2 of the cycle in which the timers overflow. The values
are then polled by the circuitry in the next cycle.
If a request is active and conditions are right for it to be
acknowledged, a hardware subroutine call to the requested
service routine will be the next instruction executed. The
call itself takes two cycles. Thus, a minimum of three
complete machine cycles elapsed between activation of
an external interrupt request and the beginning of execution
of the first instruction of the service routine. Figure 16
shows response timings.
A longer response time results if the request is blocked by
one of the three previously listed conditions. If an interrupt
of equal or higher priority level is already in progress, the
additional wait time depends on the nature of the other
interrupt's service routine. If the instruction in progress is
not in its final cycle, the additional wait time cannot be more
than three cycles, since the longest instructions (MUL and
DIV) are only four cycles long. If the instruction in progress
is RETI or an access to IE or IP, the additional wait time
cannot be more than five cycles (a maximum of one more
cycle to complete the instruction in progress, plus four
cycles to complete the next instruction if the instruction is
MUL or DIV).
®
Single-Step Operation
The IS89LV51 interrupt structure allows single-step
execution with very little software overhead. As previously
noted, an interrupt request will not be serviced while an
interrupt of equal priority level is still in progress, nor will it
be serviced after RETI until at least one other instruction
has been executed. Thus, once an interrupt routine has
been entered, it cannot be re-entered until at least one
instruction of the interrupted program is executed. One
way to use this feature for single-step operation is to
program one of the external interrupts (for example, INT0)
to be level-activated. The service routine for the interrupt
will terminate with the following code:
JNB
P3.2,$
;Wait Here Till INT0 Goes High
JB
P3.2,$
;Now Wait Here Till it Goes Low
RETI
;Go Back and Execute One
Instruction
If the INT0 pin, which is also the P3.2 pin, is held normally
low, the CPU will go right into the External Interrupt 0
routine and stay there until INT0 is pulsed (from low-tohigh-to-low). Then it will execute RETI, go back to the task
program, execute one instruction, and immediately reenter the External Interrupt 0 routine to await the next
pulsing of P3.2. One step of the task program is executed
each time P3.2 is pulsed.
Thus, in a single-interrupt system, the response time is
always more than three cycles and less than nine cycles.
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ISSI
IS89LV51
OTHER INFORMATION
®
Table 9. Reset Values of the SFR's
SFR Name
PC
ACC
B
PSW
SP
DPTR
P0-P3
IP
IE
TMOD
TCON
TH0
TL0
TH1
TL1
SCON
SBUF
PCON
Reset
The reset input is the RST pin, which is the input to a
Schmitt Trigger.
A reset is accomplished by holding the RST pin high for at
least two machine cycles (24 oscillator periods), while the
oscillator is running. The CPU responds by generating an
internal reset, with the timing shown in Figure 18.
The external reset signal is asynchronous to the internal
clock. The RST pin is sampled during State 5 Phase 2 of
every machine cycle. The port pins will maintain their
current activities for 19 oscillator periods after a logic 1 has
been sampled at the RST pin; that is, for 19 to 31 oscillator
periods after the external reset signal has been applied to
the RST pin.
The internal reset algorithm writes 0s to all the SFRs
except the port latches, the Stack Pointer, and SBUF. The
port latches are initialized to FFH, the Stack Pointer to 07H,
and SBUF is indeterminate. Table 9 lists the SFRs and
their reset values.
Then internal RAM is not affected by reset. On power-up
the RAM content is indeterminate.
Reset Value
0000H
00H
00H
00H
07H
0000H
FFH
XXX00000B
0XX00000B
00H
00H
00H
00H
00H
00H
00H
Indeterminate
0XXX0000B
12 OSC. PERIODS
S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6 S1 S2 S3 S4
RST
INTERNAL RESET SIGNAL
SAMPLE
RST
SAMPLE
RST
ALE
PSEN
P0
INST
ADDR
INST
ADDR
INST
ADDR
INST
ADDR
INST
ADDR
19 OSC. PERIODS
11 OSC. PERIODS
Figure 18. Reset Timing
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31
ISSI
IS89LV51
®
Power-on Reset
For the IS89LV51, the external resistor can be removed
because the RST pin has an internal pulldown.
The capacitor value can then be reduced to 1 µF (see
Figure 19).
When power is turned on, the circuit holds the RST pin high
for an amount of time that depends on the value of the
capacitor and the rate at which it charges. To ensure a
good reset, the RST pin must be high long enough to allow
the oscillator time to start-up (normally a few msec) plus
two machine cycles.
Vcc
1.0 µF
+
Vcc
IS89LV51
RST
Note that the port pins will be in a random state until the
oscillator has start and the internal reset algorithm has
written 1s to them.
With this circuit, reducing VCC quickly to 0 causes the RST
pin voltage to momentarily fall below 0V. However, this
voltage is internally limited and will not harm the device.
GND
Figure 19. Power-On Reset Circuit
32
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ISSI
IS89LV51
®
Power-Saving Modes of Operation
The IS89LV51 has two power-reducing modes. Idle and
Power-down. The input through which backup power is
supplied during these operations is Vcc. Figure 20 shows
the internal circuitry which implements these features. In
the Idle mode (IDL = 1), the oscillator continues to run and
the Interrupt, Serial Port, and Timer blocks continue to be
clocked, but the clock signal is gated off to the CPU. In
Power-down (PD = 1), the oscillator is frozen. The Idle and
Power-down modes are activated by setting bits in Special
Function Register PCON.
XTAL 2
XTAL 1
OSC
INTERRUPT,
SERIAL PORT,
TIMER BLOCKS
CLOCK
GEN
CPU
PD
IDL
Idle Mode
An instruction that sets PCON.0 is the last instruction
executed before the Idle mode begins. In the Idle mode, the
internal clock signal is gated off to the CPU, but not to the
Interrupt, Timer, and Serial Port functions. The CPU status
is preserved in its entirety; the Stack Pointer, Program
Counter, Program Status Word, Accumulator, and all other
registers maintain their data during Idle. The port pins hold
the logical states they had at the time Idle was activated.
ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any
enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be
serviced, and following RETI the next instruction to be
executed will be the one following the instruction that put
the device into Idle.
The flag bits GF0 and GF1 can be used to indicate whether
an interrupt occurred during normal operation or during an
Idle. For example, an instruction that activates Idle can
also set one or both flag bits. When Idle is terminated by an
interrupt, the interrupt service routine can examine the flag
bits.
Figure 20. Idle and Power-Down Hardware
Power-down Mode
An instruction that sets PCON.1 is the last instruction
executed before Power-down mode begins. In the Powerdown mode, the on-chip oscillator stops. With the clock
frozen, all functions are stopped, but the on-chip RAM and
Special function Registers are held. The port pins output
the values held by their respective SFRs. ALE and PSEN
output lows.
In the Power-down mode of operation, Vcc can be reduced
to as low as 2V. However, Vcc must not be reduced before
the Power-down mode is invoked, and Vcc must be restored
to its normal operating level before the Power-down mode
is terminated. The reset that terminates Power-down also
frees the oscillator. The reset should not be activated
before Vcc is restored to its normal operating level and
must be held active long enough to allow the oscillator to
restart and stabilize (normally less than 10 msec).
The only exit from Power-down is a hardware reset. Reset
redefines all the SFRs but does not change the on-chip
RAM.
The other way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still running,
the hardware reset must be held active for only two
machine cycles (24 oscillator periods) to complete the
reset.
The signal at the RST pin clears the IDL bit directly and
asynchronously. At this time, the CPU resumes program
execution from where it left off; that is, at the instruction
following the one that invoked the Idle Mode. As shown in
Figure 18, two or three machine cycles of program execution
may take place before the internal reset algorithm takes
control. On-chip hardware inhibits access to the internal
RAM during his time, but access to the port pins is not
inhibited. To eliminate the possibility of unexpected outputs
at the port pins, the instruction following the one that
invokes Idle should not write to a port pin or to external data
RAM.
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33
ISSI
IS89LV51
®
Table 10. Status of the External Pins During Idle and Power-down Modes.
Mode
Memory
ALE
PSEN
PORT 0
PORT 1
PORT 2
PORT 3
Idle
Internal
1
1
Data
Data
Data
Data
Idle
External
1
1
Float
Data
Address
Data
Power-down
Internal
0
0
Data
Data
Data
Data
Power-down
External
0
0
Float
Data
Data
Data
On-Chip Oscillators
The on-chip oscillator circuitry of the IS89LV51 is a single
stage inverter, intended for use as a crystal-controlled,
positive reactance oscillator. In this application the crystal
is operated in its fundamental response mode as an
inductive reactance in parallel resonance with capacitance
external to the crystal (Figure 21). Examples of how to
drive the clock with external oscillator are shown in
Figure 22.
The crystal specifications and capacitance values (C1 and
C2 in Figure 21) are not critical. 20 pF to 30 pF can be used
in these positions at a 12 MHz to 24 MHz frequency with
good quality crystals. (For ranges greater than 24 MHz
refer to Figure 23.) A ceramic resonator can be used in
place of the crystal in cost-sensitive applications. When a
ceramic resonator is used, C1 and C2 are normally selected
to be of somewhat higher values. The manufacturer of the
ceramic resonator should be consulted for recommendation
on the values of these capacitors.
C2
XTAL2
C1
XTAL1
GND
Figure 21. Oscillator Connections
34
NC
EXTERNAL
OSCILLATOR
SIGNAL
XTAL2
XTAL1
GND
Figure 22. External Clock Drive Configuration
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ADVANCE INFORMATION MC020-0A
10/27/98
ISSI
IS89LV51
XTAL2
®
XTAL1
R
C2
C1
Figure 23. Oscillator Connections for High Speed (> 24 MHz)
Note:
When the frequency is higher than 24 MHz, please refer to Table 11 for recommended values of C1, C2, and R.
Table 11. Recommended Value for C1, C2, R
C1
C2
R
Frequency Range
3.5 MHz - 24 MHz
30 MHz - 40 MHz
20 pF-30 pF
3 pF-10 pF
20 pF-30 pF
3 pF-10 pF
Not Apply
6.2K-10K
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10/27/98
35
ISSI
IS89LV51
®
Program Memory Lock System
The program lock system, when programmed, protects
the code against software piracy. The IS89LV51 has a
three-level program lock system (see Table 12). The lockbits are programmed in the same manner as the program
memory.
The detailed lock-bits features are listed in Table 12.
Table 12. Program Lock Bits
1
2
LB1
U
P
LB2
U
U
LB3
U
U
3
4
P
P
P
P
U
P
Protection Type
No Program Lock Features enabled.
MOVC instructions executed from external program memory are diabled
form fetching code bytes from internal memory, EA is sampled and
latched on Reset and further programming of the Flash is disabled.
Same as 2, also verify is disabled.
Same as 3, also external execution is disabled.
FLASH MEMORY
Programming the IS89LV51
Programming Interface
The IS89LV51 is normally shipped with the on-chip Flash
memory array in the erased state (i.e., contents = FFH)
and ready to be programmed. The IS89LV51 is
programmed byte-by-byte in programming mode. Before
the on-chip flash code memory can be re-programmed,
the entire memory array must be erased electrically.
Every code byte in the Flash array can be written and the
entire array can be erased using the appropriate
combination of control signals. The write operation cycles
is self-timed once initiated, will automatically time itself to
completion. The programming interface is shown in
Table 13 and Figures 24 and 25.
Table 13. Flash Programming Mode
RST
PSEN
EA/VPP
P2.6
P2.7
P3.6
P3.7
Program Code Data
H
L
12V
L
H
H
H
Verify Code Data
H
L
H
L
L
H
H
Program Lock Bit 1
H
L
12V
H
H
H
H
Program Lock Bit 2
H
L
12V
H
H
L
L
Program Lock Bit 3
H
L
12V
H
L
H
L
Read Signature Byte
H
L
H
L
L
L
L
Chip Erase
H
L
12V
H
L
L
L
Mode
ALE/PROG
36
H
H
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10/27/98
ISSI
IS89LV51
+ 5V
IS89LV51
A0-A7
P1
A11-A8
P2.0-P2.3
®
Vcc
P2.6
P0
PGM
DATA
ALE
PROG
P2.7
CONTROL
SIGNALS
P3.6
EA
VPP
RST
VIH
P3.7
XTAL2
3.5-12 MHz
XTAL1
GND
PSEN
Figure 24. Programming the Flash Memory
+ 5V
IS89LV51
A0-A7
P1
A12-A8
P2.0-P2.4
Vcc
P0
P2.6
CONTROL
SIGNALS
ALE
VIH
P2.7
P3.6
PGM DATA
(USE 10K
PULLUPS)
EA
P3.7
XTAL2
RST
VIH
3.5-12 MHz
XTAL1
GND
PSEN
Figure 25. Verifying the Flash Memory
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37
ISSI
IS89LV51
®
Programming Algorithm
Erasing Chip
Before programming the IS89LV51, the control signals,
the address, data should be setup according to the
programming mode table and programming interface. To
program the IS89LV51, the following sequence should be
followed:
1. Insert the desired memory location on the
address bus.
2. Insert the appropriate data byte on the data bus.
3. Active the correct combination of control signals.
4. Raise EA / VPP to 12V.
5. Pulse ALE / PROG once to program a byte in the
Flash array, Encryption array or the lock bits.
6. Set EA / VPP to 5 V and verify data. If the data is correct
then execute step 7, otherwise execute steps 1-6.
7. Repeat steps 1 through 6, changing the address
and data for the entire array or until the end of the
object file is reached.
All Flash memory cells must be programmed to '00' (include
encryption array and lock bits) before the chip is erased.
The entire Flash array is erased electrically by using the
proper combination of control signals and by holding ALE/
PROG low for tGLGHE duration (See Table 14. Flash
Programming and Verification Characteristics for tGLGHE
value.) After the chip is erased, the code array and lock bits
are written with all “1”s. If any Flash memory cell is not '1'
(including lock bits), repeat the chip erase again. The chip
erase operation must be executed successfully before the
code memory can be re-programmed.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a
normal verification of locations 030H, 031H and 032H,
except that P3.6 and P3.7 need to be pulled to a logic low.
The values returned are:
Program Verify
If lock bits LB1, LB2 and LB3 have not been programmed,
the programmed code data can be read back via the
address and data lines for verification. The lock bits cannot
be verified directly. Verification of lock bits is achieved by
observing that their features are enabled.
To verify the data after all addresses are programmed
completely, power down the IS89LV51 and then reapply
power. The programmed data can then be verified by
applying the verify signals to the device.
38
Signature
Location
(030H)
(031H)
(032H)
Value
D5H indicates manufactured
by ISSI
52H indicates IS89LV51
FFH indicates programming
voltage is 12V
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ADVANCE INFORMATION MC020-0A
10/27/98
ISSI
IS89LV51
®
FLASH PROGRAMMING AND VERIFICATION CHARACTERISTICS AND WAVEFORMS
Table 14. Flash Programming and Verification Characteristics(1)
Symbol
Parameter
Min
Max
Unit
VPP
1/tCLCL
tAVGL
tGHAX
tDVGL
tGHDX
tEHSH
tSHGL
tGHSL
tGLGH
tGHGL
tAVQV
tELQV
tEHQZ
tGLGHE
tELPL
tPLPH
tPHEH
tEHVH
Programming Supply Voltage
Oscillator Frequency
Address Setup to PROG Low
Address Hold after PROG
Data Setup to PROG Low
Data Hold after PROG
COND ENABLE to VPPH
VPPH Setup to PROG Low
VPPH Hold after PROG
PROG Pulse Width
PROG High to PROG Low
Address to Data Valid
COND ENABLE to Data Valid
Data Float after COND DISABLE
Erase PROG Pulse Width
COND DISABLE to Power Low
Power Off Time
Power On to VPPL
VPPL to COND ENABLE
11.5
3.5
48
48
48
48
48
10
10
120
10
—
—
—
200
0
10
10
0
12.5
12
—
—
—
—
—
—
—
—
—
48
48
48
—
—
—
—
—
V
MHz
tCLCL
tCLCL
tCLCL
tCLCL
tCLCL
µs
µs
µs
µs
tCLCL
tCLCL
tCLCL
ms
ns
µs
ms
ns
Notes:
1. TA = 21°C to 27°C, Vcc = 5.0V ± 10%.
2. COND ENABLE and COND DISABLE are generated and depend on the control signals on pins P2.6,
P2.7, P3.6 and P3.7. The signals set the device in to and out of different processing conditions, such
as programming condition, erasing condition, and verify condition.
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39
ISSI
IS89LV51
P2.3-P2.0
P1.7-P1.0
ADDRESS
tAVGL
ADDRESS
tGHAX
P0.7-P0.0
tAVQV
DATAIN
tDVGL
®
DATAOUT
tGHDX
VPPH
VPPL
EA/VPP
tGHSL
tSHGL
0V
25 PULSE(1)
tGLGH
ALE/PROG
tGHGL
tEHSH
P2.6, P2.7
P3.6, P3.7
DON'T
CARE
tELQV
tELQZ
VERIFY COND.(2)
PROGRAMMING COND.
DON'T
CARE
Figure 26. Flash Memory Programming and Verification Timing Waveform
Notes:
1. One pulse for the main code array, 25 pulses for the encryption array and lock bits.
2. This verify condition is using at main code verification.
3. Power off waveform not shown.
Vcc
0V
tPLPH
tELPL
P2.3-P2.0
P1.7-P1.0
ADDRESS
0V
tAVQV
P0.7-P0.0
DATAOUT
0V
VPPH
0V
EA/VPP
tPHEH
VPPL
0V
tGHSL
tSHGL
ALE/PROG
0V
tGLGHE
tEHSH
P2.6, P2.7
P3.6, P3.7
DON'T
CARE
tELQV
tEHQZ
tEHVH
ERASE COND.
0V
VERIFY COND.
DON'T
CARE
Figure 27. Flash Memory Erase Timing Waveform
Note:
1. The power off and power on waveform can be used in programming or erasing.
40
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ADVANCE INFORMATION MC020-0A
10/27/98
ISSI
IS89LV51
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VTERM
TBIAS
TSTG
PT
Parameter
Terminal Voltage with Respect to GND(2)
Temperature Under Bias(3)
Storage Temperature
Power Dissipation
Value
–2.0 to +7.0
–40 to +85
–65 to +125
1.5
Unit
V
°C
°C
W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –
2.0V for periods less than 20 ns. Maximum DC voltage on output pins is Vcc + 0.5V
which may overshoot to Vcc + 2.0V for periods less than 20 ns.
3. Operating temperature is for commercial products only defined by this specification.
OPERATING RANGE(1)
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
VCC
3.3V to 5V ± 10%
Oscillator Frequency
3.5 to 40 MHz
–40°C to +85°C
3.3V to 5V ± 10%
3.5 to 40 MHz
Note:
1. Operating ranges define those limits between which the functionality of the device is guaranteed.
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10/27/98
41
ISSI
IS89LV51
®
DC CHARACTERISTICS
(Over Operating Range; GND = 0V)
Symbol
Parameter
Test conditions
Input low voltage (All except EA)
VIL
VIL1
Input low voltage (EA)
VIH
Input high voltage
(All except XTAL 1, RST)
Min
Max
Unit
–0.5
0.2Vcc – 0.1
V
–0.5
0.2Vcc – 0.3
V
0.2Vcc + 0.9
Vcc + 0.5
V
VIH1
Input high voltage (XTAL 1)
0.7Vcc
Vcc + 0.5
V
VSCH+
RST positive schmitt-trigger
threshold voltage
0.7Vcc
Vcc + 0.5
V
VSCH–
RST negative schmitt-trigger
threshold voltage
0
0.2Vcc
V
VOL(1)
Output low voltage
Iol = 100 µA
—
0.3
V
(Ports 1, 2, 3)
IOL = 1.6 mA
—
0.45
V
IOL = 3.5 mA
—
1.0
V
Output low voltage
IOL = 200 µA
—
0.3
V
(Port 0, ALE, PSEN)
IOL = 3.2 mA
—
0.45
V
(1)
VOL1
IOL = 7.0 mA
VOH
VOH1
Output high voltage
(Ports 1, 2, 3, ALE, PSEN)
Output high voltage
(Port 0, ALE, PSEN)
—
1.0
V
IOH = –10 µA
Vcc = 4.5V-5.5V
0.9Vcc
—
V
IOL = –25 µA
0.75Vcc
—
V
IOL = –60 µA
2.4
—
V
IOH = –80 µA
Vcc = 4.5V-5.5V
0.9Vcc
—
V
IOH = –300 µA
0.75Vcc
—
V
IOH = –800 µA
2.4
—
V
—
–80
µA
–10
+10
µA
—
–650
µA
50
300
KΩ
IIL
Logical 0 input current (Ports 1, 2, 3) VIN = 0.45V
ILI
Input leakage current (Port 0)
0.45V < VIN < Vcc
ITL
Logical 1-to-0 transition current
(Ports 1, 2, 3)
VIN = 2.0V
RRST
RST pulldown resister
Note:
1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum IOL per port pin: 10 mA
Maximum IOL per 8-bit port
Port 0: 26 mA
Ports 1, 2, 3: 15 mA
Maximum total IOL for all output pins: 71 mA
If IOL exceeds the test condition, VOL may exceed the related specification.
Pins are not guaranteed to sink greater than the listed test conditions.
42
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ADVANCE INFORMATION MC020-0A
10/27/98
ISSI
IS89LV51
®
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Icc
Test conditions
Power supply current
(1)
Min
Max
Unit
12 MHz
—
20
mA
16 MHz
—
26
mA
20 MHz
—
32
mA
24 MHz
—
38
mA
32 MHz
—
50
mA
40 MHz
—
62
mA
12 MHz
—
5
mA
16 MHz
—
6
mA
20 MHz
—
7.6
mA
24 MHz
—
9
mA
32 MHz
—
12
mA
40 MHz
—
15
mA
VCC = 5V
—
50
µA
Vcc = 5.0V
Active mode
Idle mode
Power-down mode
Note:
1. See Figures 28, 29, 30, and 31 for Icc test conditiions.
Vcc
Vcc
Vcc
Icc
Icc
RST
RST
Vcc
Vcc
Vcc
Vcc
NC
XTAL2
CLOCK
SIGNAL
XTAL1
GND
P0
EA
NC
XTAL2
CLOCK
SIGNAL
XTAL1
GND
Figure 28. Active Mode
P0
EA
Figure 29. Idle Mode
Vcc
Icc
RST
Vcc
Vcc
NC
XTAL2
P0
XTAL1
GND
EA
Figure 30. Power-down Mode
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43
ISSI
IS89LV51
tCLCX
Vcc – 0.5V
0.45V
®
tCHCX
0.7Vcc
0.2Vcc – 0.1
tCHCL
tCLCH
tCLCL
Figure 31. Icc Test Conditions
Note:
1. Clock signal waveform for Icc tests in active and idle mode (tCLCH = tCHCL = 5 ns)
AC CHARACTERISTICS
(Over Operating Range; GND = 0V; CL for Port 0, ALE and PSEN Outputs = 100 pF; CL for Other Outputs = 80 pF)
EXTERNAL MEMORY CHARACTERISTICS
Symbol
1/tCLCL
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
tRLRH
tWLWH
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tQVWX
tWHQX
tRLAZ
tWHLH
44
Parameter
Oscillator frequency
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instr in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instr in
Input instr hold after PSEN
Input instr float after PSEN
Address to valid instr in
PSEN low to address float
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address to RD or WR low
Data valid to WR transition
Data hold after WR
RD low to address float
RD or WR high to ALE high
24 MHz
Clock
Min Max
—
—
68
—
26
—
31
—
—
147
31
—
110
—
—
105
0
—
—
37
—
188
—
10
230
—
230
—
—
157
0
—
—
78
—
282
—
323
105 145
146
—
26
—
31
—
—
0
26
57
40 MHz
Clock
Min Max
— —
35 —
10 —
15 —
— 80
15 —
60 —
— 55
0
—
— 20
— 105
— 10
130 —
130 —
— 90
0
—
— 45
— 165
— 190
55 95
80 —
10 —
15 —
—
0
10 40
Variable Oscillator
(3.5 - 40 MHz)
Min
Max
3.5
40
2tCLCL–15
—
tCLCL–15
—
tCLCL–10
—
—
4tCLCL–20
tCLCL–10
—
3tCLCL–15
—
—
3tCLCL–20
0
—
—
tCLCL–5
—
5tCLCL–20
—
10
6tCLCL–20
—
6tCLCL–20
—
—
4tCLCL–10
0
—
—
2tCLCL–5
—
7tCLCL–10
—
8tCLCL–10
3tCLCL–20
3tCLCL+20
4tCLCL–20
—
tCLCL–15
—
tCLCL–10
—
—
0
tCLCL–15
tCLCL+15
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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ADVANCE INFORMATION MC020-0A
10/27/98
ISSI
IS89LV51
®
SERIAL PORT TIMING: SHIFT REGISTER MODE
Symbol
tXLXL
tQVXH
tXHQX
tXHDX
tXHDV
Parameter
Serial port clock cycle time
Output data setup to
clock rising edge
Output data hold after
clock rising edge
Input data hold after
clock rising edge
Clock rising edge to
input data valid
24 MHz
Clock
Min Max
490 510
406
—
40 MHz
Clock
Min Max
290 310
240 —
Variable Oscillator
(3.5-40 MHz)
Min
Max
12tCLCL–10
12tCLCL+10
10tCLCL–10
—
Unit
ns
ns
73
—
40
—
2tCLCL–10
—
ns
0
—
0
—
0
—
ns
—
417
—
250
—
10tCLCL
ns
Max
40
—
—
10
10
Unit
MHz
ns
ns
ns
ns
EXTERNAL CLOCK DRIVE CHARACTERISTICS
Symbol
1/tCLCL
tCHCX
tCLCX
tCLCH
tCHCL
Parameter
Oscillator Frequency
High time
Low time
Rise time
Fall time
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC020-0A
10/27/98
Min
3.5
10
10
—
—
45
ISSI
IS89LV51
®
TIMING WAVEFORMS
tLHLL
ALE
tLLPL
tPLPH
tPLIV
tAVLL
PSEN
tPLAZ
tLLAX
PORT 0
A7-A0
tPXIX
tPXIZ
INSTR IN
A7-A0
tLLIV
tAVIV
PORT 2
A15-A8
A15-A8
Figure 32. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV
tLLWL
RD
PORT 0
tAVLL
tRLAZ
tLLAX
tRLRH
tRHDZ
tRLDV
tRHDX
A7-A0 FROM RI OR DPL
DATA IN
A7-A0 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 33. External Data Memory Read Cycle
46
1-800-379-4774 — Integrated Silicon Solution, Inc.
ADVANCE INFORMATION MC020-0A
10/27/98
ISSI
IS89LV51
®
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tWHQX
tQVWX
tLLAX
A7-A0 FROM RI OR DPL
DATA OUT
A7-A0 FROM PCL
INSTR IN
tAVWL
PORT 2
A15-A8 FROM DPH
A15-A8 FROM PCH
Figure 34. External Data Memory Write Cycle
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tXHQX
tQVXH
0
DATAOUT
1
2
tXHDX
tXHDV
DATAIN
VALID
VALID
3
4
5
6
7
SET TI
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
Figure 35. Shift Register Mode Timing Waveform
tCLCX
Vcc – 0.5V
0.45V
tCHCX
0.7Vcc
0.2Vcc – 0.1
tCHCL
tCLCH
tCLCL
Figure 36. External Clock Drive Waveform
Vcc - 0.5V
0.2Vcc + 0.9V
0.2Vcc - 0.1V
0.45V
Figure 37. AC Test Point
Note:
1. AC inputs during testing are driven at VCC – 0.5V for logic “1” and 0.45V for logic “0”.
Timing measurements are made at VIH min for logic “1” and max for logic “0”.
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC020-0A
10/27/98
47
ISSI
IS89LV51
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed
12 MHz
20 MHz
24 MHz
40 MHz
Order Part Number
IS89LV51-12PL
IS89LV51-12W
IS89LV51-12PQ
IS89LV51-20PL
IS89LV51-20W
IS89LV51-20PQ
IS89LV51-24PL
IS89LV51-24W
IS89LV51-24PQ
IS89LV51-40PL
IS89LV51-40W
IS89LV51-40PQ
Package
PLCC – Plastic Leaded Chip Carrier
600-mil Plastic DIP
PQFP
PLCC – Plastic Leaded Chip Carrier
600-mil Plastic DIP
PQFP
PLCC – Plastic Leaded Chip Carrier
600-mil Plastic DIP
PQFP
PLCC – Plastic Leaded Chip Carrier
600-mil Plastic DIP
PQFP
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Speed
12 MHz
20 MHz
24 MHz
40 MHz
Order Part Number
IS89LV51-12PLI
IS89LV51-12WI
IS89LV51-12PQI
IS89LV51-20PLI
IS89LV51-20WI
IS89LV51-20PQI
IS89LV51-24PLI
IS89LV51-24WI
IS89LV51-24PQI
IS89LV51-40PLI
IS89LV51-40WI
IS89LV51-40PQI
Package
PLCC – Plastic Leaded Chip Carrier
600-mil Plastic DIP
PQFP
PLCC – Plastic Leaded Chip Carrier
600-mil Plastic DIP
PQFP
PLCC – Plastic Leaded Chip Carrier
600-mil Plastic DIP
PQFP
PLCC – Plastic Leaded Chip Carrier
600-mil Plastic DIP
PQFP
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Fax: (408) 588-0806
Toll Free: 1-800-379-4774
http://www.issi.com
48
1-800-379-4774 — Integrated Silicon Solution, Inc.
ADVANCE INFORMATION MC020-0A
10/27/98