24-Bit Capacitance-to-Digital Converter with Temperature Sensor AD7745/AD7746 FEATURES GENERAL DESCRIPTION Capacitance-to-digital converter New standard in single chip solutions Interfaces to single or differential floating sensors Resolution down to 4 aF (that is, up to 21 ENOB) Accuracy: 4 fF Linearity: 0.01% Common-mode (not changing) capacitance up to 17 pF Full-scale (changing) capacitance range: ±4 pF Tolerant of parasitic capacitance to ground up to 60 pF Update rate: 10 Hz to 90 Hz Simultaneous 50 Hz and 60 Hz rejection at 16 Hz Temperature sensor on-chip Resolution: 0.1°C, accuracy: ±2°C Voltage input channel Internal clock oscillator 2-wire serial interface (I2C®-compatible) Power 2.7 V to 5.25 V single-supply operation 0.7 mA current consumption Operating temperature: –40°C to +125°C 16-lead TSSOP package The AD7745/AD7746 are a high resolution, Σ-Δ capacitance-todigital converter (CDC). The capacitance to be measured is connected directly to the device inputs. The architecture features inherent high resolution (24-bit no missing codes, up to 21-bit effective resolution), high linearity (±0.01%), and high accuracy (±4 fF factory calibrated). The AD7745/AD7746 capacitance input range is ±4 pF (changing), while it can accept up to 17 pF common-mode capacitance (not changing), which can be balanced by a programmable on-chip, digital-tocapacitance converter (CAPDAC). The AD7745 has one capacitance input channel, while the AD7746 has two channels. Each channel can be configured as single-ended or differential. The AD7745/AD7746 are designed for floating capacitive sensors. For capacitive sensors with one plate connected to ground, the AD7747 is recommended. The parts have an on-chip temperature sensor with a resolution of 0.1°C and accuracy of ±2°C. The on-chip voltage reference and the on-chip clock generator eliminate the need for any external components in capacitive sensor applications. The parts have a standard voltage input, which together with the differential reference input allows easy interface to an external temperature sensor, such as an RTD, thermistor, or diode. APPLICATIONS Automotive, industrial, and medical systems for Pressure measurement Position sensing Level sensing Flowmeters Humidity sensing Impurity detection The AD7745/AD7746 have a 2-wire, I2C-compatible serial interface. Both parts can operate with a single power supply from 2.7 V to 5.25 V. They are specified over the automotive temperature range of –40°C to +125°C and are housed in a 16-lead TSSOP package. FUNCTIONAL BLOCK DIAGRAMS VDD TEMP SENSOR CLOCK GENERATOR VDD VIN(+) VIN(–) MUX CIN1(+) CIN1(–) 24-BIT Σ-∆ MODULATOR TEMP SENSOR AD7745 DIGITAL FILTER I2C SERIAL INTERFACE SDA SCL CLOCK GENERATOR AD7746 VIN(+) VIN(–) MUX CIN1(+) CIN1(–) 24-BIT Σ-∆ MODULATOR DIGITAL FILTER I2C SERIAL INTERFACE SDA SCL CIN2(+) CIN2(–) CONTROL LOGIC CALIBRATION CAP DAC RDY RDY CAP DAC VOLTAGE REFERENCE EXCB REFIN(+) REFIN(–) GND Figure 1. EXC1 05468-001 EXCITATION VOLTAGE REFERENCE EXCITATION EXC2 REFIN(+) REFIN(–) GND Figure 2. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. 05468-002 CAP DAC EXCA CONTROL LOGIC CALIBRATION CAP DAC AD7745/AD7746 TABLE OF CONTENTS Specifications..................................................................................... 3 Cap Gain Calibration Register.................................................. 19 Timing Specifications....................................................................... 5 Volt Gain Calibration Register ................................................. 19 Absolute Maximum Ratings............................................................ 6 Circuit Description......................................................................... 20 Pin Configurations and Function Descriptions ........................... 7 Overview ..................................................................................... 20 Typical Performance Characteristics ............................................. 8 Capacitance-to-Digital Converter ........................................... 20 Output Noise and Resolution Specifications .............................. 11 Excitation Source........................................................................ 20 Serial Interface ................................................................................ 12 CAPDAC ..................................................................................... 21 Read Operation........................................................................... 12 Single-Ended Capacitive Input................................................. 21 Write Operation.......................................................................... 12 Differential Capacitive Input .................................................... 21 AD7745/AD7746 Reset ............................................................. 13 Parasitic Capacitance to Ground.............................................. 22 General Call................................................................................. 13 Parasitic Resistance to Ground................................................. 22 Register Descriptions ..................................................................... 14 Parasitic Parallel Resistance ...................................................... 22 Status Register ............................................................................. 15 Parasitic Serial Resistance ......................................................... 23 Cap Data Register....................................................................... 15 Capacitive Gain Calibration ..................................................... 23 VT Data Register ........................................................................ 15 Capacitive System Offset Calibration ...................................... 23 Cap Set-Up Register ................................................................... 16 Internal Temperature Sensor .................................................... 23 VT Set-Up Register .................................................................... 16 External Temperature Sensor ................................................... 24 EXC Set-Up Register .................................................................. 17 Voltage Input............................................................................... 24 Configuration Register .............................................................. 18 VDD Monitor ................................................................................ 24 Cap DAC A Register................................................................... 19 Typical Application Diagram.................................................... 24 Cap DAC B Register................................................................... 19 Outline Dimensions ....................................................................... 25 Cap Offset Calibration Register................................................ 19 Ordering Guide .......................................................................... 25 REVISION HISTORY 4/05—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7745/AD7746 SPECIFICATIONS VDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; GND = 0 V; EXC = 32 kHz; EXC = ±VDD/2; –40°C to +125°C, unless otherwise noted. Table 1. Parameter CAPACITIVE INPUT Conversion Input Range Integral Nonlinearity (INL)2 No Missing Codes2 Resolution, p-p Resolution Effective Output Noise, rms Absolute Error3 Offset Error2, 4 System Offset Calibration Range2 Offset Drift vs. Temperature Gain Error5 Gain Drift vs. Temperature2 Allowed Capacitance to GND2 Power Supply Rejection Normal Mode Rejection Channel-to-Channel Isolation CAPDAC Full Range Resolution6 Drift vs. Temperature2 EXCITATION Frequency Voltage Across Capacitance Min Max ±4.096 ±0.01 24 16.5 19 2 ±4 32 ±1 –28 –1 0.02 –26 0.08 –24 60 1 0.3 65 55 70 17 24 21 164 26 0.1 ±0.5 ±2 Unit Test Conditions/Comments pF1 % of FSR Bit Bit Bit aF/√Hz fF1 aF1 Factory calibrated pF aF/°C % of FS ppm of FS/°C pF fF/V dB dB dB 28 pF fF ppm of FS/°C <±40 kHz V V V V mV 100 pF ±2 °C °C °C 32 ±VDD/8 ±VDD/4 ±VDD × 3/8 ±VDD/2 Average DC Voltage Across Capacitance Allowed Capacitance to GND2 TEMPERATURE SENSOR7 Resolution Error2 VOLTAGE INPUT7 Differential VIN Voltage Range Absolute VIN Voltage2 Integral Nonlinearity (INL) No Missing Codes2 Resolution, p-p Typ ±VREF 16 V V ppm of FS Bit Bits Output Noise 3 µV rms Offset Error Offset Drift vs. Temperature Full-Scale Error2, 9 ±3 15 0.025 µV nV/°C % of FS GND − 0.03 VDD + 0.03 ±15 ±3 24 0.1 Rev. 0| Page 3 of 28 Conversion time ≥ 62 ms Conversion time = 62 ms, see Table 5 Conversion time = 62 ms, see Table 5 See Table 5 25°C, VDD = 5 V, after offset calibration After system offset calibration, Excluding effect of noise4 25°C, VDD = 5 V See Figure 9 and Figure 10 50 Hz ± 1%, conversion time = 62 ms 60 Hz ± 1%, conversion time = 62 ms AD7746 only 7-bit CAPDAC Configurable via digital interface See Figure 11 VREF internal Internal temperature sensor External sensing diode8 VREF internal or VREF = 2.5 V Conversion time = 122.1 ms Conversion time = 62 ms See Table 6 and Table 7 Conversion time = 62 ms See Table 6 and Table 7 AD7745/AD7746 Parameter Full-Scale Drift vs. Temperature Min Typ 5 0.5 300 ±50 80 90 75 50 95 Max 1.169 1.17 5 0.1 GND − 0.03 2.5 Average VIN Input Current Analog VIN Input Current Drift Power Supply Rejection Power Supply Rejection Normal Mode Rejection Common-Mode Rejection INTERNAL VOLTAGE REFERENCE Voltage Drift vs. Temperature EXTERNAL VOLTAGE REFERENCE INPUT Differential REFIN Voltage2 Absolute REFIN Voltage2 Average REFIN Input Current Average REFIN Input Current Drift Common-Mode Rejection SERIAL INTERFACE LOGIC INPUTS (SCL, SDA) VIH Input High Voltage VIL Input Low Voltage Hysteresis Input Leakage Current (SCL) OPEN-DRAIN OUTPUT (SDA) VOL Output Low Voltage IOH Output High Leakage Current LOGIC OUTPUT (RDY) VOL Output Low Voltage VOH Output High Voltage VOL Output Low Voltage VOH Output High Voltage POWER REQUIREMENTS VDD-to-GND Voltage Test Conditions/Comments Internal reference External reference 1.171 V ppm/°C TA = 25°C VDD VDD + 0.03 V V nA/V pA/V/°C dB 400 ±50 80 2.1 0.8 Internal reference, VIN = VREF/2 External reference, VIN = VREF/2 50 Hz ± 1%, conversion time = 122.1 ms 60 Hz ± 1%, conversion time = 122.1 ms VIN = 1 V V V mV µA 150 ±0.1 ±1 0.4 V 0.1 1 µA ISINK = −6.0 mA VOUT = VDD 0.4 V V V V ISINK = 1.6 mA, VDD = 5 V ISOURCE = 200 µA, VDD = 5 V ISINK = 100 µA, VDD = 3 V ISOURCE = 100 µA, VDD = 3 V V V µA µA µA µA VDD = 5 V, nominal VDD = 3.3 V, nominal Digital inputs equal to VDD or GND VDD = 5 V VDD = 3.3 V Digital inputs equal to VDD or GND 4.0 0.4 VDD – 0.6 4.75 2.7 5.25 3.6 850 IDD Current IDD Current Power-Down Mode Unit ppm of FS/°C ppm of FS/°C nA/V pA/V/°C dB dB dB dB dB 750 700 0.5 2 1 Capacitance units: 1 pF = 10-12 F; 1 fF = 10-15 F; 1 aF = 10-18 F. Specification is not production tested, but is supported by characterization data at initial product release. 3 Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C. At different temperatures, compensation for gain drift over temperature is required. 4 The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter + system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF, the larger offset can be removed using CAPDACs. 5 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required. 6 The CAPDAC resolution is seven bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can further reduce the CIN offset or the unchanging CIN component. 7 The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance. 8 Using an external temperature sensing diode 2N3906, with nonideality factor nf = 1.008, connected as in Figure 41, with total serial resistance <100 Ω. 9 Full-scale error applies to both positive and negative full scale. 2 Rev. 0 | Page 4 of 28 AD7745/AD7746 TIMING SPECIFICATIONS VDD = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; –40°C to +125°C, unless otherwise noted. Table 2. Parameter SERIAL INTERFACE1, 2 SCL Frequency SCL High Pulse Width, tHIGH SCL Low Pulse Width, tLOW SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Hold Time (Start Condition), tHD;STA Set-Up Time (Start Condition), tSU;STA Data Set-Up Time, tSU;DAT Data Set-Up Time, tSU;DAT Set-Up Time (Stop Condition), tSU;STO Data Hold Time, tHD;DAT (Master) Bus-Free Time (Between Stop and Start Condition, tBUF) 2 0 0.6 1.3 Typ Max Unit 400 kHz µs µs µs µs µs µs µs µs µs µs µs 0.3 0.3 0.6 0.6 0.25 0.35 0.6 0 1.3 Test Conditions/Comments See Figure 3 After this period, the first clock is generated Relevant for repeated start condition VDD ≥ 3.0 V VDD < 3.0 V Sample tested during initial release to ensure compliance. All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Output load = 10 pF. tLOW tR tF tHD:STA SCL tHD:STA tHD:DAT tHIGH tSU:STA tSU:DAT tSU:STO SDA tBUF P S S Figure 3. Serial Interface Timing Diagram Rev. 0| Page 5 of 28 P 05468-003 1 Min AD7745/AD7746 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Positive Supply Voltage VDD to GND Voltage on any Input or Output Pin to GND ESD Rating (ESD Association Human Body Model, S5.1) Operating Temperature Range Storage Temperature Range Junction Temperature TSSOP Package θJA, (Thermal Impedance-to-Air) TSSOP Package θJC, (Thermal Impedance-to-Case) Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating −0.3 V to +6.5 V –0.3 V to VDD + 0.3 V 2000 V –40°C to +125°C –65°C to +150°C 150°C 128°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 14°C/W 215°C 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 28 AD7745/AD7746 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS RDY SCL 1 16 SDA 2 15 NC RDY 16 SDA 2 15 NC 14 VDD EXCA 3 13 GND TOP VIEW REFIN(+) 5 (Not to Scale) 12 VIN(–) EXCB 4 13 GND TOP VIEW REFIN(+) 5 (Not to Scale) 12 VIN(–) REFIN(–) 6 11 VIN(+) REFIN(–) 6 EXCA 3 EXCB 4 AD7745 14 VDD AD7746 11 VIN(+) 10 NC CIN1(–) 7 10 CIN2(–) CIN1(+) 8 9 NC CIN1(+) 8 9 NC = NO CONNECT 05468-004 CIN1(–) 7 NC = NO CONNECT Figure 4. AD7745 Pin Configuration (16-Lead TSSOP) CIN2(+) 05468-005 SCL 1 Figure 5. AD7746 Pin Configuration (16-Lead TSSOP) Table 4. Pin Function Descriptions Pin No. 1 Mnemonic SCL 2 RDY 3, 4 EXCA, EXCB 5, 6 REFIN(+), REFIN(–) 7 CIN1(–) 8 CIN1(+) 9, 10 (AD7745) 9 (AD7746) 10 (AD7746) 11, 12 NC 13 14 GND VDD 15 16 NC SDA CIN2(+) CIN2(–) VIN(+), VIN(–) Description Serial Interface Clock Input. Connects to the master clock line. Requires pull-up resistor if not already provided in the system. Logic Output. A falling edge on this output indicates that a conversion on enabled channel(s) has been finished and the new data is available. Alternatively, the status register can be read via the 2-wire serial interface and the relevant bit(s) decoded to query the finished conversion. If not used, this pin should be left as an open circuit. CDC Excitation Outputs. The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, these pins should be left as an open circuit. Differential Voltage Reference Input for the Voltage Channel (ADC). Alternatively, the on-chip internal reference can be used for the voltage channel. These reference input pins are not used for conversion on capacitive channel(s) (CDC). If not used, these pins can be left as an open circuit or connected to GND. CDC Negative Capacitive Input in Differential Mode. This pin is internally disconnected in single-ended CDC configuration. If not used, this pin can be left as an open circuit or connected to GND. CDC Capacitive Input (in Single-Ended Mode) or Positive Capacitive Input (in Differential Mode). The measured capacitance is connected between one of the EXC pins and one of the CIN pins. If not used, this pin can be left as an open circuit or connected to GND. Not Connected. This pin should be left as an open circuit. CDC Second Capacitive Input (in Single-Ended Mode) or Positive Capacitive Input (in Differential Mode). If not used, this pin can be left open circuit or connected to GND. CDC Negative Capacitive Input in Differential Mode. This pin is internally disconnected in a single-ended CDC configuration. If not used, this pin can be left as an open circuit or connected to GND. Differential Voltage Input for the Voltage Channel (ADC). These pins are also used to connect an external temperature sensing diode. If not used, these pins can be left as an open circuit or connected to GND. Ground Pin. Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example in combination with a 10 µF tantalum and a 0.1 µF multilayer ceramic. Not Connected. This pin should be left as an open circuit. Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided elsewhere in the system. Rev. 0| Page 7 of 28 AD7745/AD7746 TYPICAL PERFORMANCE CHARACTERISTICS 18 100 2.7V 3V 3.3V 5V 16 14 CAPACITANCE ERROR (fF) 60 40 12 10 8 6 4 2 05468-014 20 0 –5 –4 –3 –2 –1 0 1 2 3 4 05468-017 INL (ppm) 80 0 –2 0 5 50 100 150 200 250 300 350 400 500 450 CAPACITANCE CIN PIN TO GND (pF) INPUT CAPACITANCE (pF) Figure 6. Capacitance Input Integral Nonlinearity, VDD = 5 V, the Same Configuration as in Figure 31 Figure 9. Capacitance Input Error vs. Capacitance between CIN and GND. CIN(+) to EXC = 4 pF, CIN(−) to EXC = 0 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5 V, the Same Configuration as in Figure 33 2000 18 GAIN TC ≈ –26ppm/°C 16 1000 CAPACITANCE ERROR (fF) 0 –1000 –2000 –25 0 25 50 75 100 125 3V 3.3V 10 8 6 5V 4 2 05468-015 –3000 –50 2.7V 12 05468-018 GAIN ERROR (ppm) 14 0 150 –2 0 TEMPERATURE (°C) 50 100 150 200 250 300 350 400 500 450 CAPACITANCE CIN PIN TO GND (pF) Figure 7. Capacitance Input Offset Drift vs. Temperature, VDD = 5 V, CIN and EXC Pins Open Circuit Figure 10. Capacitance Input Error vs. Capacitance between CIN and GND, CIN(+) to EXC = 21 pF, CIN(−) to EXC = 23 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5 V, the Same Configuration as in Figure 34 100 5 75 2.7V 4 CAPACITANCE ERROR (fF) 25 0 –25 –50 –100 –50 –25 0 25 50 75 100 125 5V 3 3.3V 2 1 0 05468-016 –75 3V 05468-019 OFFSET ERROR (aF) 50 –1 150 0 TEMPERATURE (°C) 50 100 150 200 250 300 350 400 450 500 CAPACITANCE EXC PIN TO GND (pF) Figure 8. Capacitance Input Gain Drift vs. Temperature, VDD = 5 V, CIN(+) to EXC = 4 pF, the Same Configuration as in Figure 30 Figure 11. Capacitance Input Error vs. Capacitance between EXC and GND, CIN(+) to EXC = 21 pF, CIN(−) to EXC = 23 pF, VDD = 2.7 V, 3 V, 3.3 V, and 5 V, the Same Configuration as in Figure 34 Rev. 0 | Page 8 of 28 AD7745/AD7746 0 8 6 –2 CAPACITANCE ERROR (fF) 2 0 –2 3V –4 –6 2.7V –8 –4 –6 05468-028 –8 –10 –12 –250 –200 –150 –100 –50 0 50 100 150 200 05468-031 CAPACITANCE ERROR (fF) 4 –10 250 1 0 2 CIN LEAKAGE TO GND (nA) 3 4 5 6 7 SERIAL RESISTANCE (kΩ) Figure 12. Capacitance Input Error vs. Leakage Current to GND, CIN(+) to EXC = 4 pF, CIN(−) to EXC = 0 pF, VDD = 2.7 V and 3 V Figure 15. Capacitance Input Error vs. Serial Resistance, CIN(+) to EXC = 21 pF, CIN(−) to EXC = 23 pF, VDD = 5 V, the Same Configuration as in Figure 34. 0.2 8 6 0 CAPACITANCE ERROR (fF) 2 0 5V –2 –4 –6 –8 –0.2 –0.4 –0.6 –0.8 05468-030 3.3V –10 –12 –250 –200 –150 –100 –50 0 50 100 150 200 –1.0 2.5 250 05468-032 CAPACITANCE ERROR (fF) 4 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) CIN LEAKAGE TO GND (nA) Figure 16. Capacitance Input Power Supply Rejection (PSR), CIN(+) to EXC = 4 pF, the Same Configuration as in Figure 30 Figure 13. Capacitance Input Error vs. Leakage Current to GND, CIN(+) to EXC =4 pF, CIN(−) to EXC = 0 pF, VDD=3.3 V and 5 V 10 0.20 CAPDAC CODE DNL (pF) 0.1 0.01 05468-029 0.001 0.0001 1 10 100 1000 10000 0.10 0.05 0 –0.05 –0.10 –0.15 05468-033 CAPACITANCE ERROR (pF) 0.15 1 –0.20 100000 0 PARALLEL RESISTANCE (MΩ) 16 32 48 64 80 96 112 CAPDAC CODE Figure 14. Capacitance Input Error vs. Resistance in Parallel with Measured Capacitance Figure 17. CAPDAC Differential Nonlinearity (DNL) Rev. 0| Page 9 of 28 128 AD7745/AD7746 2.0 0 1.5 –20 1.0 GAIN (dB) ERROR (°C) –40 0.5 0 –60 –0.5 –80 –1.0 05468-034 –2.0 –50 –25 0 25 50 75 100 125 05468-037 –100 –1.5 –120 150 0 50 TEMPERATURE (°C) 100 150 200 250 300 350 400 INPUT SIGNAL FREQUENCY (Hz) Figure 21. Capacitance Channel Frequency Response, Conversion Time = 62 ms Figure 18. Internal Temperature Sensor Error vs. Temperature 1.0 0 0.5 –20 0 GAIN (dB) ERROR (°C) –40 –0.5 –1.0 –60 –1.5 –80 –2.0 05468-035 –3.0 –50 –25 0 25 50 75 100 125 05468-038 –100 –2.5 –120 150 0 50 TEMPERATURE (°C) –20 –40 –40 –60 –80 –100 –100 –120 400 500 600 300 350 400 –60 –80 300 250 700 800 900 05468-039 GAIN (dB) –20 05468-036 GAIN (dB) 0 200 200 Figure 22. Capacitance Channel Frequency Response, Conversion Time = 109.6 ms 0 100 150 INPUT SIGNAL FREQUENCY (Hz) Figure 19. External Temperature Sensor Error vs. Temperature 0 100 –120 0 1000 50 100 150 200 250 300 350 INPUT SIGNAL FREQUENCY (Hz) INPUT SIGNAL FREQUENCY (Hz) Figure 20. Capacitance Channel Frequency Response, Conversion Time = 11 ms Figure 23. Voltage Channel Frequency Response, Conversion Time = 122.1 ms Rev. 0 | Page 10 of 28 400 AD7745/AD7746 OUTPUT NOISE AND RESOLUTION SPECIFICATIONS The AD7745/AD7746 resolution is limited by noise. The noise performance varies with the selected conversion time. Table 5 shows typical noise performance and resolution for the capacitive channel. These numbers were generated from 1000 data samples acquired in continuous conversion mode, at an excitation of 32 kHz, ±VDD/2, and with all CIN and EXC pins connected only to the evaluation board (no external capacitors.) Table 6 and Table 7 show typical noise performance and resolution for the voltage channel. These numbers were generated from 1000 data samples acquired in continuous conversion mode with VIN pins shorted to ground. RMS noise represents the standard deviation and p-p noise represents the difference between minimum and maximum results in the data. Effective resolution is calculated from rms noise, and p-p resolution is calculated from p-p noise. Table 5. Typical Capacitive Input Noise and Resolution vs. Conversion Time Conversion Time (ms) 11.0 11.9 20.0 38.0 62.0 77.0 92.0 109.6 Output Data Rate (Hz) 90.9 83.8 50.0 26.3 16.1 13.0 10.9 9.1 –3dB Frequency (Hz) 87.2 79.0 43.6 21.8 13.8 10.5 8.9 8.0 RMS Noise (aF/√Hz) 4.3 3.1 1.8 1.6 1.5 1.5 1.5 1.5 RMS Noise (aF) 40.0 27.3 12.2 7.3 5.4 4.9 4.4 4.2 P-P Noise (aF) 212.4 137.7 82.5 50.3 33.7 28.3 27.8 27.3 Effective Resolution (Bits) 17.6 18.2 19.4 20.1 20.5 20.7 20.8 20.9 P-P Resolution (Bits) 15.2 15.9 16.6 17.3 17.9 18.1 18.2 18.2 Table 6. Typical Voltage Input Noise and Resolution vs. Conversion Time, Internal Voltage Reference Conversion Time (ms) 20.1 32.1 62.1 122.1 Output Data Rate (Hz) 49.8 31.2 16.1 8.2 –3dB Frequency (Hz) 26.4 15.9 8.0 4.0 RMS Noise (µV) 11.4 7.1 4.0 3.0 P-P Noise (µV) 62 42 28 20 Effective Resolution (Bits) 17.6 18.3 19.1 19.5 P-P Resolution (Bits) 15.2 15.7 16.3 16.8 Table 7. Typical Voltage Input Noise and Resolution vs. Conversion Time, External 2.5 V Voltage Reference Conversion Time (ms) 20.1 32.1 62.1 122.1 Output Data Rate (Hz) 49.8 31.2 16.1 8.2 –3dB Frequency (Hz) 26.4 15.9 8.0 4.0 RMS Noise (µV) 14.9 6.3 3.3 2.1 P-P Noise (µV) 95 42 22 15 Rev. 0| Page 11 of 28 Effective Resolution (Bits) 18.3 19.6 20.5 21.1 P-P Resolution (Bits) 15.6 16.8 17.7 18.3 AD7745/AD7746 SERIAL INTERFACE The AD7745/AD7746 supports an I2C-compatible 2-wire serial interface. The two wires on the I2C bus are called SCL (clock) and SDA (data). These two wires carry all addressing, control, and data information one bit at a time over the bus to all connected peripheral devices. The SDA wire carries the data, while the SCL wire synchronizes the sender and receiver during the data transfer. I2C devices are classified as either master or slave devices. A device that initiates a data transfer message is called a master, while a device that responds to this message is called a slave. To control the AD7745/AD7746 device on the bus, the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCL remains high. This indicates that the start byte follows. This 8-bit start byte is made up of a 7-bit address plus an R/W bit indicator. All peripherals connected to the bus respond to the start condition and shift in the next 8 bits (7-bit address + R/W bit). The bits arrive MSB first. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. An exception to this is the general call address, which is described later in this document. The idle condition is where the device monitors the SDA and SCL lines waiting for the start condition and the correct address byte. The R/W bit determines the direction of the data transfer. A Logic 0 LSB in the start byte means that the master writes information to the addressed peripheral. In this case the AD7745/AD7746 becomes a slave receiver. A Logic 1 LSB in the start byte means that the master reads information from the addressed peripheral. In this case, the AD7745/AD7746 becomes a slave transmitter. In all instances, the AD7745/AD7746 acts as a standard slave device on the I2C bus. The start byte address for the AD7745/AD7746 is 0x90 for a write and 0x91 for a read. READ OPERATION When a read is selected in the start byte, the register that is currently addressed by the address pointer is transmitted on to the SDA line by the AD7745/AD7746. This is then clocked out by the master device and the AD7745/AD7746 awaits an acknowledge from the master. If an acknowledge is received from the master, the address autoincrementer automatically increments the address pointer register and outputs the next addressed register content on to the SDA line for transmission to the master. If no acknowledge is received, the AD7745/AD7746 return to the idle state and the address pointer is not incremented. The address pointers’ auto-incrementer allow block data to be written or read from the starting address and subsequent incremental addresses. In continuous conversion mode, the address pointers’ autoincrementer should be used for reading a conversion result. That means, the three data bytes should be read using one multibyte read transaction rather than three separate single byte transactions. The single byte data read transaction may result in the data bytes from two different results being mixed. The same applies for six data bytes if both the capacitive and the voltage/temperature channel are enabled. The user can also access any unique register (address) on a oneto-one basis without having to update all the registers. The address pointer register contents cannot be read. If an incorrect address pointer location is accessed or, if the user allows the auto-incrementer to exceed the required register address, the following applies: • In read mode, the AD7745/AD7746 continues to output various internal register contents until the master device issues a no acknowledge, start, or stop condition. The address pointers’ auto-incrementer’s contents are reset to point to the status register at Address 0x00 when a stop condition is received at the end of a read operation. This allows the status register to be read (polled) continually without having to constantly write to the address pointer. • In write mode, the data for the invalid address is not loaded into the AD7745/AD7746 registers but an acknowledge is issued by the AD7745/AD7746. WRITE OPERATION When a write is selected, the byte following the start byte is always the register address pointer (subaddress) byte, which points to one of the internal registers on the AD7745/ AD7746. The address pointer byte is automatically loaded into the address pointer register and acknowledged by the AD7745/ AD7746. After the address pointer byte acknowledge, a stop condition, a repeated start condition, or another data byte can follow from the master. A stop condition is defined by a low-to-high transition on SDA while SCL remains high. If a stop condition is ever encountered by the AD7745/AD7746, it returns to its idle condition and the address pointer is reset to Address 0x00. If a data byte is transmitted after the register address pointer byte, the AD7745/AD7746 load this byte into the register that is currently addressed by the address pointer register, send an acknowledge, and the address pointer auto-incrementer automatically increments the address pointer register to the next internal register address. Thus, subsequent transmitted data bytes are loaded into sequentially incremented addresses. Rev. 0 | Page 12 of 28 AD7745/AD7746 If a repeated start condition is encountered after the address pointer byte, all peripherals connected to the bus respond exactly as outlined above for a start condition, that is, a repeated start condition is treated the same as a start condition. When a master device issues a stop condition, it relinquishes control of the bus, allowing another master device to take control of the bus. Hence, a master wanting to retain control of the bus issues successive start conditions known as repeated start conditions. GENERAL CALL When a master issues a slave address consisting of seven 0s with the eighth bit (R/W bit) set to 0, this is known as the general call address. The general call address is for addressing every device connected to the I2C bus. The AD7745/AD7746 acknowledge this address and read in the following data byte. If the second byte is 0x06, the AD7745/AD7746 are reset, completely uploading all default values. The AD7745/AD7746 do not respond to the I2C bus commands (do not acknowledge) during the default values upload for approximately 150 µs (max 200 µs). AD7745/AD7746 RESET To reset the AD7745/AD7746 without having to reset the entire I2C bus, an explicit reset command is provided. This uses a particular address pointer word as a command word to reset the part and upload all default settings. The AD7745/AD7746 do not respond to the I2C bus commands (do not acknowledge) during the default values upload for approximately 150 µs (max 200 µs). The AD7745/AD7746 do not acknowledge any other general call commands. The reset command address word is 0xBF. SCLOCK S 1–7 8 9 1–7 8 9 START ADDR R/W ACK SUBADDRESS ACK 1–7 DATA 8 9 P ACK STOP 05468-006 SDATA Figure 24. Bus Data Transfer S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) S = START BIT P = STOP BIT A(S) DATA A(S) P LSB = 1 LSB = 0 READ SEQUENCE DATA SUB ADDR A(S) S SLAVE ADDR A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) DATA A(M) A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER Figure 25. Write and Read Sequences Rev. 0| Page 13 of 28 DATA A(M) P 05468-007 WRITE SEQUENCE AD7745/AD7746 REGISTER DESCRIPTIONS The master can write to or read from all of the AD7745/ AD7746 registers except the address pointer register, which is a write-only register. The address pointer register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the address pointer register. After the part has been accessed over the bus and a read/write operation is selected, the address pointer register is set up. The address pointer register determines from or to which register the operation takes place. A read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. Table 8. Register Summary Register Address Pointer (Dec) (Hex) Bit 7 Bit 6 Bit 5 0 0 0 Dir Bit 4 Bit 3 Default Value EXCERR 0 0 Bit 2 Bit 1 Bit 0 RDY 1 RDYVT 1 RDYCAP 1 Status 0 0x00 R Cap Data H 1 0x01 R Capacitive channel data—high byte, 0x00 Cap Data M 2 0x02 R Capacitive channel data—middle byte, 0x00 Cap Data L 3 0x03 R Capacitive channel data—low byte, 0x00 VT Data H 4 0x04 R Voltage/temperature channel data—high byte, 0x00 VT Data M 5 0x05 R Voltage/temperature channel data—middle byte, 0x00 VT Data L 6 0x06 R Voltage/temperature channel data—low byte, 0x00 Cap Setup 7 0x07 R/W VT Setup 8 0x08 R/W EXC Setup 9 0x09 R/W Configuration 10 0x0A R/W Cap DAC A 11 0x0B R/W Cap DAC B 12 0x0C R/W Cap Offset H 13 0x0D R/W Capacitive offset calibration—high byte, 0x80 Cap Offset L 14 0x0E R/W Capacitive offset calibration—low byte, 0x00 Cap Gain H 15 0x0F R/W Capacitive gain calibration—high byte, factory calibrated Cap Gain L 16 0x10 R/W Capacitive gain calibration—low byte, factory calibrated Volt Gain H 17 0x11 R/W Voltage gain calibration—high byte, factory calibrated Volt Gain L 18 0x12 R/W Voltage gain calibration—low byte, factory calibrated 1 CAPEN 0 VTEN 0 CLKCTRL CIN21 0 VTMD1 0 EXCON CAPDIFF 0 VTMD0 0 EXCB 0 EXTREF 0 EXCB 0 VTFS1 1 DACAENA 0 DACBENB 0 0 VTFS0 0 0 CAPFS2 1 0 0 0 CAPFS1 CAPFS0 MD2 0 0 0 DACA—7-Bit Value 0x00 DACB—7-Bit Value 0x00 The CIN2 bit is relevant only for AD7746. The CIN2 bit should always be 0 on the AD7745. Rev. 0 | Page 14 of 28 0 0 EXCA 0 0 EXCA 0 VTSHORT 0 EXCLVL1 CAPCHOP 0 VTCHOP 0 EXCLVL0 1 MD1 0 1 MD0 0 AD7745/AD7746 The RDY pin reflects the status of the RDY bit. Therefore, the RDY pin high-to-low transition can be used as an alternative indication of the finished conversion. STATUS REGISTER Address Pointer 0x00, Read Only, Default Value 0x07 This register indicates the status of the converter. The status register can be read via the 2-wire serial interface to query a finished conversion. Table 9. Status Register Bit Map Bit Mnemonic Default Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 EXCERR 0 Bit 2 RDY 1 Bit 1 RDYVT 1 Bit 0 RDYCAP 1 Table 10. Bit 7-4 3 Mnemonic EXCERR 2 RDY 1 RDYVT 0 RDYCAP Description Not used, always read 0. EXCERR = 1 indicates that the excitation output cannot be driven properly. The possible reason can be a short circuit or too high capacitance between the excitation pin and ground. RDY = 0 indicates that conversion on the enabled channel(s) has been finished and new unread data is available. If both capacitive and voltage/temperature channels are enabled, the RDY bit is changed to 0 after conversion on both channels is finished. The RDY bit returns to 1 either when data is read or prior to finishing the next conversion. If, for example, only the capacitive channel is enabled, then the RDY bit reflects the RDYCAP bit. RDYVT = 0 indicates that a conversion on the voltage/temperature channel has been finished and new unread data is available. RDYCAP = 0 indicates that a conversion on the capacitive channel has been finished and new unread data is available. VT DATA REGISTER CAP DATA REGISTER 24 Bits, Address Pointer 0x01, 0x02, 0x03, Read-Only, Default Value 0x000000 24 Bits, Address Pointer 0x04, 0x05, 0x06, Read-Only, Default Value 0x000000 Capacitive channel output data. The register is updated after finished conversion on the capacitive channel, with one exception: When the serial interface read operation from the CAP DATA register is in progress, the data register is not updated and the new capacitance conversion result is lost. Voltage/temperature channel output data. The register is updated after finished conversion on the voltage channel or temperature channel, with one exception: When the serial interface read operation from the VT DATA register is in progress, the data register is not updated and the new voltage/temperature conversion result is lost. The stop condition on the serial interface is considered to be the end of the read operation. Therefore, to prevent data corruption, all three bytes of the data register should be read sequentially using the register address pointer auto-increment feature of the serial interface. To prevent losing some of the results, the CAP DATA register should be read before the next conversion on the capacitive channel is finished. The 0x000000 code represents negative full scale (–4.096 pF), the 0x800000 code represents zero scale (0 pF), and the 0xFFFFFF code represents positive full scale (+4.096 pF). The stop condition on the serial interface is considered to be the end of the read operation. Therefore, to prevent data corruption, all three bytes of the data register should be read sequentially using the register address pointer auto-increment feature of the serial interface. For voltage input, Code 0 represents negative full scale (–VREF), the 0x800000 code represents zero scale (0 V), and the 0xFFFFFF code represents positive full scale (+VREF). To prevent losing some of the results, the VT DATA register should be read before the next conversion on the voltage/ temperature channel is finished. For the temperature sensor, the temperature can be calculated from code using the following equation: Temperature (°C) = (Code/2048) − 4096 Rev. 0| Page 15 of 28 AD7745/AD7746 CAP SET-UP REGISTER Address Pointer 0x07, Default Value 0x00 Capacitive channel setup. Table 11. CAP Set-Up Register Bit Map Bit Mnemonic Default Bit 7 CAPEN 0 Bit 6 CIN2 0 Bit 5 CAPDIFF 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 CAPCHOP 0 Table 12. Bit 7 6 5 4-1 0 Mnemonic CAPEN CIN2 CAPDIFF CAPCHOP Description CAPEN = 1 enables capacitive channel for single conversion, continuous conversion, or calibration. CIN2 = 1 switches the internal multiplexer to the second capacitive input on the AD7746. DIFF = 1 sets differential mode on the selected capacitive input. These bits must be 0 for proper operation. The CAPCHOP bit should be set to 0 for the specified capacitive channel performance. CAPCHOP = 1 approximately doubles the capacitive channel conversion times and slightly improves the capacitive channel noise performance for the longest conversion times. VT SET-UP REGISTER Address Pointer 0x08, Default Value 0x00 Voltage/Temperature channel setup. Table 13. VT Set-Up Register Bit Map Bit Mnemonic Default Bit 7 VTEN 0 Bit 6 VTMD1 0 Bit 5 VTMD0 0 Bit 4 EXTREF 0 Bit 3 0 Bit 2 0 Bit 1 VTSHORT 0 Bit 0 VTCHOP 0 Table 14. Bit 7 6 5 Mnemonic VTEN VTMD1 VTMD0 4 EXTREF 3-2 1 0 VTSHORT VTCHOP = 1 Description VTEN = 1 enables voltage/temperature channel for single conversion, continuous conversion, or calibration. Voltage/temperature channel input configuration. VTMD1 VTMD0 Channel Input 0 0 Internal temperature sensor 0 1 External temperature sensor diode 1 0 VDD monitor 1 1 External voltage input (VIN) EXTREF = 1 selects an external reference voltage connected to REFIN(+), REFIN(–) for the voltage input or the VDD monitor. EXTREF = 0 selects the on-chip internal reference. The internal reference must be used with the internal temperature sensor for proper operation. These bits must be 0 for proper operation. VTSHORT = 1 internally shorts the voltage/temperature channel input for test purposes. VTCHOP = 1 sets internal chopping on the voltage/temperature channel. The VTCHOP bit must be set to 1 for the specified voltage/temperature channel performance. Rev. 0 | Page 16 of 28 AD7745/AD7746 EXC SET-UP REGISTER Address Pointer 0x09, Default Value 0x03 Capacitive channel excitation setup. Table 15. EXC Set-Up Bit Map Bit Mnemonic Default Bit 7 CLKCTRL 0 Bit 6 EXCON 0 Bit 5 EXCB 0 Bit 4 EXCB 0 Bit 3 EXCA 0 Bit 2 EXCA 0 Bit 1 EXCLVL1 0 Bit 0 EXCLVL0 0 Table 16. Bit 7 Mnemonic CLKCTRL 6 EXCON 5 4 EXCB EXCB 3 2 EXCA EXCA 1 0 EXCLVL1, EXCLVL0 Description The CLKCTRL bit should be set to 0 for the specified AD7745/AD7746 performance. CLKCTRL = 1 decreases the excitation signal frequency and the modulator clock frequency by factor of 2. This also increases the conversion time on all channels (capacitive, voltage, and temperature) by a factor of 2. When EXCON = 0, the excitation signal is present on the output only during capacitance channel conversion. When EXCON = 1, the excitation signal is present on the output during both capacitance and voltage/temperature conversion. EXCB = 1 enables EXCB pin as the excitation output. EXCB = 1 enables EXCB pin as the inverted excitation output. Only one of the EXCB or the EXCB bits should be set for proper operation. EXCA = 1 enables EXCA pin as the excitation output. EXCA = 1 enables EXCA pin as the inverted excitation output. Only one of the EXCA or the EXCA bits should be set for proper operation. Excitation Voltage Level. EXCLVL1 0 0 1 1 EXCLVL0 0 1 0 1 Voltage on Cap ±VDD/8 ±VDD/4 ±VDD × 3/8 ±VDD/2 Rev. 0| Page 17 of 28 EXC Pin Low Level VDD × 3/8 VDD × 1/4 VDD × 1/8 0 EXC Pin High Level VDD × 5/8 VDD × 3/4 VDD × 7/8 VDD AD7745/AD7746 CONFIGURATION REGISTER Address Pointer 0x0A, Default Value 0xA0 Converter update rate and mode of operation setup. Table 17. Configuration Register Bit Map Bit Mnemonic Default Bit 7 VTF1 0 Bit 6 VTF0 0 Bit 5 CAPF2 0 Bit 4 CAPF1 0 Bit 3 CAPF0 0 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 0 Table 18. Bit 7 6 Mnemonic VTF1 VTF0 5 4 3 CAPF2 CAPF1 CAPF0 2 1 0 MD2 MD1 MD0 Description Voltage/temperature channel digital filter setup—conversion time/update rate setup. The conversion times in this table are valid for the CLKCTRL = 0 in the EXC SETUP register. The conversion times are longer by a factor of two for the CLKCTRL = 1. VTCHOP = 1 VTF1 VTF0 Conversion Time (ms) Update Rate (Hz) –3 dB Frequency (Hz) 0 0 20.1 49.8 26.4 0 1 32.1 31.2 15.9 1 0 62.1 16.1 8.0 1 1 122.1 8.2 4.0 Capacitive channel digital filter setup—conversion time/update rate setup. The conversion times in this table are valid for the CLKCTRL = 0 in the EXC SETUP register. The conversion times are longer by factor of two for the CLKCTRL = 1. CAP CHOP = 0 CAPF2 CAPF1 CAPF0 Conversion Time (ms) Update Rate –3 dB Frequency (Hz) 0 0 0 11.0 90.9 87.2 0 0 1 11.9 83.8 79.0 0 1 0 20.0 50.0 43.6 0 1 1 38.0 26.3 21.8 1 0 0 62.0 16.1 13.1 1 0 1 77.0 13.0 10.5 1 1 0 92.0 10.9 8.9 1 1 1 109.6 9.1 8.0 Converter mode of operation setup. MD2 MD1 MD0 Mode 0 0 0 Idle 0 0 1 Continuous conversion 0 1 0 Single conversion 0 1 1 Power-Down 1 0 0 1 0 1 Capacitance system offset calibration 1 1 0 Capacitance or voltage system gain calibration 1 1 1 Rev. 0 | Page 18 of 28 AD7745/AD7746 CAP DAC A REGISTER Address Pointer 0x0B, Default Value 0x00 Capacitive DAC setup. Table 19. Cap DAC A Register Bit Map Bit Mnemonic Default Bit 7 DACAENA 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 DACA—7-Bit Value 0x00 Bit 1 Bit 0 Bit 1 Bit 0 Table 20. Bit 7 6-1 Mnemonic DACAENA DACA Description DACAENA = 1 connects capacitive DACA to the positive capacitance input. DACA value, Code 0x00 ≈ 0 pF, Code 0x7F ≈ full range. CAP DAC B REGISTER Address Pointer 0x0C, Default Value 0x00 Capacitive DAC setup. Table 21. Cap DAC B Register Bit Map Bit Mnemonic Default Bit 7 DACBENB 0 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 DACB—7-bit value 0x00 Table 22. Bit 7 6-1 Mnemonic DACBENB DACB Description DACBENB = 1 connects capacitive DACB to the negative capacitance input. DACB value, Code 0x00 ≈ 0 pF, Code 0x7F ≈ full range. CAP OFFSET CALIBRATION REGISTER CAP GAIN CALIBRATION REGISTER 16 Bits, Address Pointer 0x0D, 0x0E, Default Value 0x8000 16 Bits, Address Pointer 0x0F, 0x10, Default Value 0xXXXX The capacitive offset calibration register holds the capacitive channel zero-scale calibration coefficient. The coefficient is used to digitally remove the capacitive channel offset. The register value is updated automatically following the execution of a capacitance offset calibration. The capacitive offset calibration resolution (cap offset register LSB) is less than 32 aF; the full range is 1 pF. Capacitive gain calibration register. The register holds the capacitive channel full-scale factory calibration coefficient. On the AD7746, the register is shared by the two capacitive channels. On the AD7746, the register is shared by the two capacitive channels. If the capacitive channels need to be offset-calibrated individually, the host controller software should read the AD7746 capacitive offset calibration register values after performing the offset calibration on individual channels and then reload the values back to the AD7746 before executing conversion on a different channel. Voltage gain calibration register. The register holds the voltage channel full-scale factory calibration coefficient. VOLT GAIN CALIBRATION REGISTER 16 Bits, Address Pointer 0x11,0x12, Default Value 0xXXXX Rev. 0| Page 19 of 28 AD7745/AD7746 CIRCUIT DESCRIPTION VDD TEMP SENSOR CLOCK GENERATOR VDD VIN(+) VIN(–) MUX CIN1(+) CIN1(–) 24-BIT Σ-∆ MODULATOR TEMP SENSOR AD7745 DIGITAL FILTER I2C SERIAL INTERFACE SDA SCL CLOCK GENERATOR AD7746 VIN(+) VIN(–) MUX CIN1(+) CIN1(–) 24-BIT Σ-∆ MODULATOR I2C SERIAL INTERFACE DIGITAL FILTER SDA SCL CIN2(+) CIN2(–) CONTROL LOGIC CALIBRATION CAP DAC RDY CAP DAC RDY CAP DAC EXC1 REFIN(+) REFIN(–) 05468-001 EXCB GND VOLTAGE REFERENCE EXCITATION EXC2 REFIN(+) REFIN(–) Figure 26. AD7745 Block Diagram 05468-002 VOLTAGE REFERENCE EXCITATION GND Figure 27. AD7746 Block Diagram OVERVIEW CAPACITANCE TO DIGITAL CONVERTER (CDC) The AD7745/AD7746 core is a high precision converter consisting of a second order (Σ-Δ or charge balancing) modulator and a third order digital filter. It works as a CDC for the capacitive inputs and as a classic ADC for the voltage input or for the voltage from a temperature sensor. In addition to the converter, the AD7745/AD7746 integrates a multiplexer, an excitation source and CAPDACs for the capacitive inputs, a temperature sensor, a voltage reference for the voltage and temperature inputs, a complete clock generator, a control and calibration logic, and an I2C-compatible serial interface. The AD7745 has one capacitive input, while the AD7746 has two capacitive inputs. All other features and specifications are identical for both parts. CLOCK GENERATOR DATA CIN 24-BIT Σ-∆ MODULATOR DIGITAL FILTER CX EXC EXCITATION 05468-027 EXCA CONTROL LOGIC CALIBRATION CAP DAC Figure 28. CDC Simplified Block Diagram EXCITATION SOURCE The two excitation pins EXCA and EXCB are independently programmable. They are identically functional and therefore either of them can be used for the capacitive sensor excitation. On the 2-channel AD7746 using a separate excitation pin for each capacitive channel is recommended. CAPACITANCE-TO-DIGITAL CONVERTER Figure 28 shows the CDC simplified functional diagram. The measured capacitance CX is connected between the excitation source and the Σ-Δ modulator input. A square-wave excitation signal is applied on the CX during the conversion and the modulator continuously samples the charge going through the CX. The digital filter processes the modulator output, which is a stream of 0s and 1s containing the information in 0 and 1 density. The data from the digital filter is scaled, applying the calibration coefficients, and the final result can be read through the serial interface. The AD7745/AD7746 is designed for floating capacitive sensors. Therefore, both CX plates have to be isolated from ground. Rev. 0 | Page 20 of 28 AD7745/AD7746 CAPDAC The AD7745/AD7746 CDC full-scale input range is ±4.096 pF. For simplicity of calculation, however, the following text and diagrams use ±4 pF. The part can accept a higher capacitance on the input and the common-mode or offset (not-changing component) capacitance can be balanced by programmable on-chip CAPDACs. CAPDAC(+) The CAPDAC can be used for programmable shifting the input range. The example in Figure 31 shows how to use the full ±4 pF CDC span to measure capacitance between 0 pF to 8 pF. CAPDAC(+) 4pF CIN(+) CIN(–) CAPDIFF = 0 ± 4pF CDC 0x000000 ... 0xFFFFFF DATA CAPDAC(–) 0pF CX 0 ... 8pF EXC DATA CDC CIN(–) 05468-025 CIN(+) Figure 31. Using CAPDAC in Single-Ended Mode Figure 32 shows how to shift the input range further, up to 21 pF absolute value of capacitance connected to the CIN(+). 05468-010 CY EXC CAPDAC(+) 17pF CIN(+) Figure 29. Using a CAPDAC The CAPDAC can be understood as a negative capacitance connected internally to the CIN pin. There are two independent CAPDACs, one connected to the CIN(+) and the second connected to the CIN(–). The relation between the capacitance input and output data can be expressed as CAPDIFF = 0 CIN(–) ± 4pF CDC CAPDAC(–) 0pF CX 13 ... 21pF (17 ± 4pF) EXC DATA ≈ (C X − CAPDAC(+)) − (CY − CAPDAC(−)) Figure 32. Using CAPDAC in Single-Ended Mode DIFFERENTIAL CAPACITIVE INPUT The CAPDACs have a 7-bit resolution, monotonic transfer function, are well matched to each other, and have a defined temperature coefficient. The CAPDAC full range (absolute value) is not factory calibrated and can vary up to ±20% with the manufacturing process. See the Specifications section and typical performance characteristics in Figure 17. When configured for a differential mode (the CAPDIFF bit in the Cap Setup register set to 1), the AD7745/AD7746 CDC measures the difference between positive and negative capacitance input. The CAPDACs are shared by the two capacitive channels on the AD7746. If the CAPDACs need to be set individually, the host controller software should reload the CAPDAC values to the AD7746 before executing conversion on a different channel. SINGLE-ENDED CAPACITIVE INPUT When configured for a single-ended mode (the CAPDIFF bit in the Cap Setup register is set to 0), the AD7745/AD7746 CIN(–) pin is disconnected internally. The CDC (without using the CAPDACs) can measure only positive input capacitance in the range of 0 pF to 4 pF (see Figure 30). Each of the two input capacitances CX and CY between the EXC and CIN pins must be less than 4 pF (without using the CAPDACs) or must be less than 21 pF and balanced by the CAPDACs. Balancing by the CAPDACs means that both CX–CAPDAC(+) and CY–CAPDAC(–) are less than 4 pF. If the unbalanced capacitance between the EXC and CIN pins is higher than 4 pF, the CDC introduces a gain error, an offset error, and nonlinearity error. See the examples shown in Figure 33, Figure 34, and Figure 35. CAPDAC(+) OFF CIN(+) CAPDAC(+) OFF CIN(–) 0x800000 ... 0xFFFFFF DATA CIN(+) CAPDIFF = 0 CIN(–) 0 ... 4pF CDC CX 0 ... 4pF CAPDAC(–) OFF EXC CY 0 ... 4pF CAPDIFF = 1 ± 4pF CDC 0x000000 ... 0xFFFFFF DATA CAPDAC(–) OFF EXC 05468-024 CX 0 ... 4pF 0x000000 ... 0xFFFFFF DATA Figure 30. CDC Single-Ended Input Mode Rev. 0| Page 21 of 28 Figure 33. CDC Differential Input Mode 05468-020 CX 05468-026 CAPDAC(–) AD7745/AD7746 PARASITIC RESISTANCE TO GROUND CAPDAC(+) 17pF CIN(+) CY 15 ... 19pF (17 ± 2pF) RGND1 CIN CAPDAC(–) 17pF EXC CX Figure 34. Using CAPDAC in Differential Mode RGND2 EXC CAPDAC(+) 17pF Figure 37. Parasitic Resistance to Ground CIN(+) CAPDIFF = 1 CIN(–) ± 4pF CDC 0x000000 ... 0xFFFFFF DATA CAPDAC(–) 17pF CY 17pF 05468-011 CX 13 ... 21pF (17 ± 4pF) DATA CDC 05468-013 CX 15 ... 19pF (17 ± 2pF) CAPDIFF = 1 0x000000 ... 0xFFFFFF DATA 05468-021 CIN(–) ± 4pF CDC EXC The AD7745/AD7746 CDC result would be affected by a leakage current from the CX to ground, therefore the CX should be isolated from the ground. The influence of the leakage current varies with the power supply voltage. The following limits can be used as a guideline for the allowed leakage current or the equivalent resistance between the CX and ground (Figure 37). VDD ≈ 5 V: IGND < 150 nA (that is, RGND > 30 MΩ) Figure 35. Using CAPDAC in Differential Mode VDD ≥ 3 V: IGND < 60 nA (that is, RGND > 50 MΩ) PARASITIC CAPACITANCE TO GROUND CGND1 CIN CDC VDD ≥ 2.7 V: IGND < 30 nA (that is, RGND > 100 MΩ) A higher leakage current to ground results in a gain error, an offset error, and a nonlinearity error. See the typical performance characteristics shown in Figure 12 and Figure 13. DATA PARASITIC PARALLEL RESISTANCE CX CIN Figure 36. Parasitic Capacitance to Ground CX The CDC architecture used in the AD7745/AD7746 measures the capacitance CX connected between the EXC pin and the CIN pin. In theory, any capacitance CP to ground should not affect the CDC result (see Figure 36). The practical implementation of the circuitry in the chip implies certain limits and the result is gradually affected by capacitance to ground. See the allowed capacitance to GND in the specification table for CIN and excitation. Also see the typical performance characteristics shown in Figure 9, Figure 10, and Figure 11. CDC DATA RP EXC 05468-022 EXC 05468-012 CGND2 Figure 38. Parasitic Parallel Resistance The AD7745/AD7746 CDC measures the charge transfer between EXC pin and CIN pin. Any resistance connected in parallel to the measured capacitance CX (see Figure 38), such as the parasitic resistance of the sensor, also transfers charge. Therefore, the parallel resistor is seen as an additional capacitance in the output data. The equivalent parallel capacitance (or error caused by the parallel resistance) can be approximately calculated as CP = 1 RP × FEXC × 4 Where RP is the parallel resistance and CEXC is the excitation frequency. See the typical performance characteristics shown in Figure 14. Rev. 0 | Page 22 of 28 AD7745/AD7746 The offset calibration register is reloaded by the default value at power-on or after reset. Therefore, if the offset calibration is not repeated after each system power-up, the calibration coefficient value should be stored by the host controller and reloaded as part of the AD7745/AD7746 setup. RS1 CIN CDC DATA RS2 05468-023 CX EXC Figure 39. Parasitic Serial Resistance The AD7745/AD7746 CDC result is affected by a resistance in series with the measured capacitance. The total serial resistance, which refers to RS1 + RS2 on Figure 39, should be less than 1 kΩ for the specified performance. See typical performance characteristics shown in Figure 15. On the AD7746, the register is shared by the two capacitive channels. If the capacitive channels need to be offset calibrated individually, the host controller software should read the AD7746 capacitive offset calibration register values after performing the offset calibration on individual channels and then reload the values back to the AD7746 before executing a conversion on a different channel. INTERNAL TEMPERATURE SENSOR INTERNAL TEMPERATURE SENSOR CLOCK GENERATOR CAPACITIVE GAIN CALIBRATION The AD7745/AD7746 gain is factory calibrated for the full scale of ±4.096 pF in the production for each part individually. The factory gain coefficient is stored in a one-time programmable (OTP) memory and is copied to the capacitive gain register at power-up or after reset. The gain can be changed by executing a capacitance gain calibration mode, for which an external full-scale capacitance needs to be connected to the capacitance input, or by writing a user value to the capacitive gain register. This change would be only temporary and the factory gain coefficient would be reloaded back after power-up or reset. The part is tested and specified only for use with the default factory calibration coefficient. VDD N×I I ∆VBE 24-BIT Σ-∆ MODULATOR DIGITAL DATA FILTER AND SCALING VOLTAGE REFERENCE 05468-040 PARASITIC SERIAL RESISTANCE Figure 40. Internal Temperature Sensor The temperature sensing method used in the AD7745/AD7746 is to measure a difference in ∆VBE voltage of a transistor operated at two different currents (see Figure 40). The ∆VBE change with temperature is linear and can be expressed as ∆VBE = (n f ) KT × ln(N ) q where: CAPACITIVE SYSTEM OFFSET CALIBRATION The capacitive offset is dominated by the parasitic offset in the application, such as the initial capacitance of the sensor, any parasitic capacitance of tracks on the board, and the capacitance of any other connections between the sensor and the CDC. Therefore, the AD7745/AD7746 are not factory calibrated for capacitive offset. It is the user’s responsibility to calibrate the system capacitance offset in the application. Any offset in the capacitance input larger than ±1 pF should first be removed using the on-chip CAPDACs. The small offset within ±1 pF can then be removed by using the capacitance offset calibration register. One method of adjusting the offset is to connect a zero-scale capacitance to the input and execute the capacitance offset calibration mode. The calibration sets the midpoint of the ±4.096 pF range (that is, Output Code 0x800000) to that zero-scale input. K is Boltzmann’s constant (1.38 × 10–23). T is the absolute temperature in Kelvin. q is the charge on the electron (1.6 × 10–19 coulombs). N is the ratio of the two currents. nf is the ideality factor of the thermal diode. The AD7745/AD7746 uses an on-chip transistor to measure the temperature of the silicon chip inside the package. The Σ-Δ ADC converts the ∆VBE to digital, the data are scaled using factory calibration coefficients, thus the output code is proportional to temperature: Temperatur e(°C ) = Code − 4096 2048 The AD7745/AD7746 has a low power consumption resulting in only a small effect due to the part self-heating (less than 0.5°C at VDD = 5 V). Another method would be to calculate and write the offset calibration register value, the LSB is value 31.25 aF (4.096 pF/217). Rev. 0| Page 23 of 28 AD7745/AD7746 If the capacitive sensor can be considered to be at the same temperature as the AD7745/AD7746 chip, the internal temperature sensor can be used as a system temperature sensor. That means the complete system temperature drift compensation can be based on the AD7745/AD7746 internal temperature sensor without need for any additional external components. See the typical performance characteristics in Figure 18. VOLTAGE INPUT VDD ANALOG TO DIGITAL CONVERTER (ADC) CLOCK GENERATOR VIN(+) EXTERNAL TEMPERATURE SENSOR RTD DATA 24-BIT Σ-∆ MODULATOR VIN(–) DIGITAL FILTER VDD I ... N × I REFIN(+) CLOCK GENERATOR VOLTAGE REFERENCE RREF REFIN(–) 2N3906 ∆VBE RS1 VIN (+) RS2 VIN (–) 24-BIT Σ-∆ MODULATOR DIGITAL DATA FILTER AND SCALING Figure 42. Resistive Temperature Sensor Connected to the Voltage Input The AD7745/AD7746 Σ-Δ core can work as a high resolution (up to 21 ENOB) classic ADC with a fully differential voltage input. The ADC can be used either with the on-chip high precision, low drift, 1.17 V voltage reference, or an external reference connected to the fully differential reference input pins. 05468-041 VOLTAGE REFERENCE GND Figure 41. Transistor as an External Temperature Sensor The AD7745/AD7746 provide the option of using an external transistor as a temperature sensor in the system. The ∆VBE method, which is similar to the internal temperature sensor method, is used. However, it is modified to compensate for the serial resistance of connections to the sensor. Total serial resistance (RS1 + RS2 in Figure 41) up to 100 Ω is compensated. The VIN(–) pin must be grounded for proper external temperature sensor operation. The voltage and reference inputs are continuously sampled by a Σ-Δ modulator during the conversion. Therefore, the input source impedance should be kept low. See the application example in Figure 42. VDD MONITOR Along with converting external voltages, the AD7745/AD7746 Σ-Δ ADC can be used for monitoring the VDD voltage. The voltage from the VDD pin is internally attenuated by 6. The AD7745/AD7746 are factory calibrated for Transistor 2N3906 with the ideality factor nf = 1.008. See the typical performance characteristics shown in Figure 19. TYPICAL APPLICATION DIAGRAM 0.1µF + 3V/5V POWER SUPPLY 10µF 10kΩ VDD TEMP SENSOR CLOCK GENERATOR 10kΩ HOST SYSTEM AD7745 VIN(+) SDA VIN(–) MUX CIN1(+) 24-BIT Σ-∆ MODULATOR DIGITAL FILTER I2C SERIAL INTERFACE SCL CIN1(–) CONTROL LOGIC CALIBRATION CAP DAC RDY CAP DAC EXCA 05468-042 EXTERNAL TEMPERATURE SENSOR RT VOLTAGE REFERENCE EXCITATION REFIN(+) REFIN(–) GND Figure 43. Basic Application Diagram for a Differential Capacitive Sensor Rev. 0 | Page 24 of 28 05468-008 EXCB AD7745/AD7746 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 8° 0° SEATING PLANE 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 44. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model AD7745ARUZ1 AD7745ARUZ-REEL1 AD7745ARUZ-REEL71 AD7746ARUZ1 AD7746ARUZ-REEL1 AD7746ARUZ-REEL71 EVAL-AD7746EB 1 Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP Evaluation Board Z = Pb-free part. Rev. 0 | Page 25 of 28 Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 AD7745/AD7746 NOTES Rev. 0 | Page 26 of 28 AD7745/AD7746 NOTES Rev. 0 | Page 27 of 28 AD7745/AD7746 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C05468-0-4/05(0) Rev. 0 | Page 28 of 28