24-Bit Capacitance-to-Digital Converter with Temperature Sensor AD7747 Preliminary Technical Data FEATURES GENERAL DESCRIPTION Capacitance-to-digital converter New standard in single chip solutions Interfaces to single or differential grounded sensors Resolution down to 40 aF (that is, up to 18.5-bit ENOB) Accuracy: 8 fF Linearity: 0.01% Common-mode (not changing) capacitance up to 17 pF Full scale (changing) capacitance range ±8 pF Update rate: 5 Hz to 45 Hz Simultaneous 50 Hz and 60 Hz rejection at 8.1 Hz update Active shield for shielding sensor connection Temperature sensor on-chip Resolution: 0.1°C, accuracy: ±2°C Voltage input channel Internal clock oscillator The AD7747 is a high-resolution, Σ−∆ capacitance-to-digital converter (CDC). The capacitance to be measured is connected directly to the device inputs. The architecture features inherent high resolution (24-bit no missing codes, up to 18 bit effective resolution), high linearity (±0.01%), and high accuracy (±8 fF factory calibrated). The AD7747 capacitance input range is ±8 pF (changing), while it can accept up to 17 pF commonmode capacitance (not changing), which can be balanced by a programmable on-chip digital-to-capacitance converter (CAPDAC). The AD7747 is designed for single ended or differential capacitive sensors with one plate connected to ground. For floating (not grounded) capacitive sensors, the AD7745 or AD7746 are recommended. 2-wire serial interface (I2C®-compatible) Power 2.7 V to 5.25 V single-supply operation 1 mA current consumption Operating temperature: –40°C to +125°C 16-lead TSSOP package The part has an on-chip temperature sensor with a resolution of 0.1°C and accuracy of ±2°C. The on-chip voltage reference and the on-chip clock generator eliminate the need for any external components in capacitive sensor applications. The part has a standard voltage input, which together with the differential reference input allows easy interface to an external temperature sensor, such as an RTD, thermistor, or diode. APPLICATIONS The AD7747 has a 2-wire, I2C-compatible serial interface. The part can operate with a single power supply 2.7 V to 5.25 V. It is specified over the automotive temperature range of –40°C to +125°C and are housed in a 16-lead TSSOP package. Automotive, industrial, and medical systems for Pressure measurement Position sensing Proximity sensing Level sensing Flowmeters Impurity detection FUNCTIONAL BLOCK DIAGRAMS VDD TEMP SENSOR CLOCK GENERATOR AD7747 VIN(+) VIN(-) 24-BIT Σ -∆ MODULATOR MUX DIGITAL FILTER CIN1(+) CIN1(-) I2C SERIAL INTERFACE CONTROL LOGIC CALIBRATION SHLD SDA SCL RDY CAP DAC 1 EXCITATION VOLTAGE REFERENCE CAP DAC 2 REFIN(+) REFIN(-) GND Figure 1. Rev. PrC, 28. July 2006 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 © 2006 Analog Devices, Inc. All rights reserved. Preliminary Technical Data AD7747 TABLE OF CONTENTS Specifications..................................................................................... 3 VT Data Register ........................................................................ 13 Timing Specifications....................................................................... 5 Cap Set-Up Register................................................................... 14 Absolute Maximum Ratings............................................................ 6 VT Set-Up Register .................................................................... 14 Pin Configurations and Function Descriptions ........................... 7 EXC Set-Up Register.................................................................. 15 Typical Performance Characteristics ............................................. 8 Configuration Register .............................................................. 16 Output Noise and Resolution Specifications ................................ 9 Cap DAC A Register .................................................................. 17 Serial Interface ................................................................................ 10 Cap DAC B Register................................................................... 17 Read Operation........................................................................... 10 Cap Offset Calibration Register ............................................... 17 Write Operation.......................................................................... 10 Cap Gain Calibration Register.................................................. 17 AD7747 Reset ............................................................................. 11 Volt Gain Calibration Register ................................................. 17 General Call................................................................................. 11 Circuit Description ........................................................................ 18 Register Descriptions ..................................................................... 12 Typical Application Diagram.................................................... 18 Status Register ............................................................................. 13 Outline Dimensions ....................................................................... 19 Cap Data Register....................................................................... 13 REVISION HISTORY March 2005—Revision PrB: Preliminary sampling, chip rev.S2 July 2006—Revision PrC: Preliminary sampling, chip rev.S3 Rev. PrC | Page 2 of 20 Preliminary Technical Data AD7747 SPECIFICATIONS VDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; GND = 0 V; EXC = ±VDD/2; –40°C to +125°C, unless otherwise noted. Table 1. Parameter CAPACITIVE INPUT Conversion Input Range Integral Nonlinearity (INL)2 No Missing Codes2 Resolution, p-p Resolution Effective Output Noise, rms Absolute Error3 Offset Error2, 4 Min VOLTAGE INPUT7 Differential VIN Voltage Range Absolute VIN Voltage2 Integral Nonlinearity (INL) No Missing Codes2 Resolution, p-p Max ±8.192 ±0.01 24 16 18.5 15 ±8 TBD System Offset Calibration Range2 Offset Drift vs. Temperature Gain Error5 Gain Drift vs. Temperature2 Power Supply Rejection Normal Mode Rejection CAPDAC Full Range Resolution6 Drift vs. Temperature2 EXCITATION Frequency AC Voltage Across Capacitance Average DC Voltage Across Capacitance ACTIVE SHIELDING Allowed Capacitance to GND2 TEMPERATURE SENSOR7 Resolution Error2 Typ TBD 17 Unit Test Conditions/Comments pF1 % of FSR Bit Bit Bit aF/√Hz fF1 aF1 Factory calibrated Conversion time ≥ 124 ms Conversion time 124 ms, see Table 5 Conversion time 124 ms, see Table 5 See Table 5 25°C, VDD = 5 V, after offset calibration After system offset calibration, Excluding effect of noise4 TBD TBD –26 TBD TBD TBD pF aF/°C % of FS ppm of FS/°C fF/V dB dB 21 330 26 pF fF ppm of FS/°C 6-bit CAPDAC 16 ±VDD/2 TBD kHz V mV Configurable via digital interface 0.1 ±0.5 ±2 50 pF ±2 °C °C °C ±VREF 16 V V ppm of FS Bit Bits Output Noise 3 µV rms Offset Error Offset Drift vs. Temperature Full-Scale Error2, 9 Full-Scale Drift vs. Temperature ±3 15 0.025 5 0.5 µV nV/°C % of FS ppm of FS/°C ppm of FS/°C GND − 0.03 VDD + 0.03 ±15 ±3 24 0.1 Rev. PrC| Page 3 of 20 25°C, VDD = 5 V 50 Hz ± 1%, conversion time 124 ms 60 Hz ± 1%, conversion time 124 ms SHLD pin VREF internal Internal temperature sensor External sensing diode8 VREF internal or VREF = 2.5 V Conversion time = 122.1 ms Conversion time = 62 ms See Table 6 and Table 7 Conversion time = 62 ms See Table 6 and Table 7 Internal reference External reference Preliminary Technical Data AD7747 Parameter Average VIN Input Current Analog VIN Input Current Drift Power Supply Rejection Power Supply Rejection Normal Mode Rejection Common-Mode Rejection INTERNAL VOLTAGE REFERENCE Voltage Drift vs. Temperature EXTERNAL VOLTAGE REFERENCE INPUT Differential REFIN Voltage2 Absolute REFIN Voltage2 Average REFIN Input Current Average REFIN Input Current Drift Common-Mode Rejection SERIAL INTERFACE LOGIC INPUTS (SCL, SDA) VIH Input High Voltage VIL Input Low Voltage Hysteresis Input Leakage Current (SCL) OPEN-DRAIN OUTPUT (SDA) VOL Output Low Voltage Min Typ 300 ±50 80 90 75 50 95 Max 1.169 1.17 5 1.171 V ppm/°C 0.1 GND − 0.03 2.5 VDD VDD + 0.03 V V nA/V pA/V/°C dB 400 ±50 80 2.1 IOH Output High Leakage Current LOGIC OUTPUT (RDY) VOL Output Low Voltage VOH Output High Voltage VOL Output Low Voltage VOH Output High Voltage POWER REQUIREMENTS VDD-to-GND Voltage IDD Current IDD Current Power-Down Mode 0.1 TA = 25°C 0.4 V ISINK = −6.0 mA 1 µA VOUT = VDD 0.4 V V V V ISINK = 1.6 mA, VDD = 5 V ISOURCE = 200 µA, VDD = 5 V ISINK = 100 µA, VDD = 3 V ISOURCE = 100 µA, VDD = 3 V V V mA mA mA µA VDD = 5 V, nominal VDD = 3.3 V, nominal Digital inputs equal to VDD or GND VDD = 5 V VDD = 3.3 V Digital inputs equal to VDD or GND 0.4 VDD – 0.6 1 TBD TBD Internal reference, VIN = VREF/2 External reference, VIN = VREF/2 50 Hz ± 1%, conversion time = 122.1 ms 60 Hz ± 1%, conversion time = 122.1 ms VIN = 1 V ±1 4.0 4.75 2.7 Test Conditions/Comments V V mV µA 0.8 150 ±0.1 Unit nA/V pA/V/°C dB dB dB dB dB 5.25 3.6 TBD TBD 1 Capacitance units: 1 pF = 10-12 F; 1 fF = 10-15 F; 1 aF = 10-18 F. Specification is not production tested, but is supported by characterization data at initial product release. 3 Factory calibrated. The absolute error includes factory gain calibration error, integral nonlinearity error, and offset error after system offset calibration, all at 25°C. At different temperatures, compensation for gain drift over temperature is required. 4 The capacitive input offset can be eliminated using a system offset calibration. The accuracy of the system offset calibration is limited by the offset calibration register LSB size (32 aF) or by converter + system p-p noise during the system capacitive offset calibration, whichever is greater. To minimize the effect of the converter + system noise, longer conversion times should be used for system capacitive offset calibration. The system capacitance offset calibration range is ±1 pF, the larger offset can be removed using CAPDACs. 5 The gain error is factory calibrated at 25°C. At different temperatures, compensation for gain drift over temperature is required. 6 The CAPDAC resolution is six bits in the actual CAPDAC full range. Using the on-chip offset calibration or adjusting the capacitive offset calibration register can further reduce the CIN offset or the unchanging CIN component. 7 The VTCHOP bit in the VT SETUP register must be set to 1 for the specified temperature sensor and voltage input performance. 8 Using an external temperature sensing diode 2N3906, with nonideality factor nf = 1.008, connected as in Figure TBD, with total serial resistance <100 Ω. 9 Full-scale error applies to both positive and negative full scale. 2 Rev. PrC | Page 4 of 20 Preliminary Technical Data AD7747 TIMING SPECIFICATIONS VDD = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; –40°C to +125°C, unless otherwise noted. Table 2. Parameter SERIAL INTERFACE1, 2 SCL Frequency SCL High Pulse Width, tHIGH SCL Low Pulse Width, tLOW SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Hold Time (Start Condition), tHD;STA Set-Up Time (Start Condition), tSU;STA Data Set-Up Time, tSU;DAT Set-Up Time (Stop Condition), tSU;STO Data Hold Time, tHD;DAT (Master) Bus-Free Time (Between Stop and Start Condition, tBUF) 2 0 0.6 1.3 Typ Max Unit 400 kHz µs µs µs µs µs µs µs µs µs µs 0.3 0.3 0.6 0.6 0.1 0.6 0 1.3 Test Conditions/Comments See Figure 2 After this period, the first clock is generated Relevant for repeated start condition Sample tested during initial release to ensure compliance. All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Output load = 10 pF. tLOW tR tF tHD:STA SCL tHD:STA tHD:DAT tHIGH tSU:STA tSU:DAT tSU:STO SDA tBUF P S S Figure 2. Serial Interface Timing Diagram Rev. PrC| Page 5 of 20 P 05468-003 1 Min Preliminary Technical Data AD7747 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter Positive Supply Voltage VDD to GND Voltage on any Input or Output Pin to GND ESD Rating (ESD Association Human Body Model, S5.1) Operating Temperature Range Storage Temperature Range Junction Temperature TSSOP Package θJA, (Thermal Impedance-to-Air) TSSOP Package θJC, (Thermal Impedance-to-Case) Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating −0.3 V to +6.5 V –0.3 V to VDD + 0.3 V TBD V –40°C to +125°C –65°C to +150°C 150°C 128°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 14°C/W TBD°C TBD°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrC | Page 6 of 20 Preliminary Technical Data AD7747 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SCL 1 16 SDA RDY 2 15 NC SHLD 3 14 VDD TST 4 AD7747 13 GND REFIN(+) 5 TOP VIEW (Not to Scale) 12 VIN(-) REFIN(-) 6 11 VIN(+) CIN1(-) 7 10 NC CIN1(+) 8 9 NC Figure 3. AD7747 Pin Configuration (16-Lead TSSOP) Table 4. Pin Function Descriptions Pin No. 1 Mnemonic Description SCL 2 RDY 3 SHLD 4 TST Serial Interface Clock Input. Connects to the master clock line. Requires pull-up resistor if not already provided in the system. Logic Output. A falling edge on this output indicates that a conversion on enabled channel(s) has been finished and the new data is available. Alternatively, the status register can be read via the 2-wire serial interface and the relevant bit(s) decoded to query the finished conversion. If not used, this pin should be left as an open circuit. Capacitive input active AC shielding. To eliminate the CIN parasitic capacitance to ground, the SHLD signal can be used to for shielding the connection between the sensor and CIN. See the max allowed capacitance. If not used, this pin should be left as an open circuit. This pin must be left as an open circuit for proper operation. 5, 6 REFIN(+), REFIN(–) Differential Voltage Reference Input for the Voltage Channel (ADC). Alternatively, the on-chip internal reference can be used for the voltage channel. These reference input pins are not used for conversion on capacitive channel(s) (CDC). If not used, these pins can be left as an open circuit or connected to GND. 7 CIN1(–) 8 CIN1(+) 9, 10 11, 12 13 14 NC VIN(+), VIN(–) 15 16 NC SDA CDC Negative Capacitive Input in Differential Mode. This pin is internally disconnected in single-ended CDC configuration. If not used, this pin should be left as an open circuit. CDC capacitive input (in single ended mode) or positive capacitive input (in differential mode). The measured capacitance is connected between one of the CIN pins and GND. If not used, this pin should be left as an open circuit. Not Connected. These pins should be left as an open circuit. Differential Voltage Input for the Voltage Channel (ADC). These pins are also used to connect an external temperature sensing diode. If not used, these pins can be left as an open circuit or connected to GND. Ground Pin. Power Supply Voltage. This pin should be decoupled to GND, using a low impedance capacitor, for example in combination with a 10 µF tantalum and a 0.1 µF multilayer ceramic. Not Connected. This pin should be left as an open circuit. Serial Interface Bidirectional Data. Connects to the master data line. Requires a pull-up resistor if not provided elsewhere in the system. GND VDD Rev. PrC| Page 7 of 20 Preliminary Technical Data AD7747 TYPICAL PERFORMANCE CHARACTERISTICS Figure 4. Figure 7. Figure 5. Figure 8. Figure 6. Figure 9. Rev. PrC | Page 8 of 20 Preliminary Technical Data AD7747 OUTPUT NOISE AND RESOLUTION SPECIFICATIONS The AD7747 resolution is limited by noise. The noise performance varies with the selected conversion time. Table 6 and Table 7 show typical noise performance and resolution for the voltage channel. These numbers were generated from 1000 data samples acquired in continuous conversion mode with VIN pins shorted to ground. Table 5 shows typical noise performance and resolution for the capacitive channel. These numbers were generated from 1000 data samples acquired in continuous conversion mode, at an excitation of 16 kHz, ±VDD/2, and with all CIN and EXC pins connected only to the evaluation board (no external capacitors.) RMS noise represents the standard deviation and p-p noise represents the difference between minimum and maximum results in the data. Effective resolution is calculated from rms noise, and p-p resolution is calculated from p-p noise. Table 5. Typical Capacitive Input Noise and Resolution vs. Conversion Time Conversion Time (ms) 22.0 23.9 40.0 76.0 124.0 154.0 184.0 219.3 Output Data Rate (Hz) 45.5 41.9 25.0 13.2 8.1 6.5 5.4 4.6 –3dB Frequency (Hz) RMS Noise (aF/√Hz) RMS Noise (aF) P-P Noise (aF) Effective Resolution (Bits) P-P Resolution (Bits) TBD TBD TBD TBD TBD TBD 6.9 15 40 250 18.5 16.0 Table 6. Typical Voltage Input Noise and Resolution vs. Conversion Time, Internal Voltage Reference Conversion Time (ms) 20.1 32.1 62.1 122.1 Output Data Rate (Hz) 49.8 31.2 16.1 8.2 –3dB Frequency (Hz) 26.4 15.9 8.0 4.0 RMS Noise (µV) 11.4 7.1 4.0 3.0 P-P Noise (µV) 62 42 28 20 Effective Resolution (Bits) 17.6 18.3 19.1 19.5 P-P Resolution (Bits) 15.2 15.7 16.3 16.8 Table 7. Typical Voltage Input Noise and Resolution vs. Conversion Time, External 2.5 V Voltage Reference Conversion Time (ms) 20.1 32.1 62.1 122.1 Output Data Rate (Hz) 49.8 31.2 16.1 8.2 –3dB Frequency (Hz) 26.4 15.9 8.0 4.0 RMS Noise (µV) 14.9 6.3 3.3 2.1 P-P Noise (µV) 95 42 22 15 Rev. PrC| Page 9 of 20 Effective Resolution (Bits) 18.3 19.6 20.5 21.1 P-P Resolution (Bits) 15.6 16.8 17.7 18.3 Preliminary Technical Data AD7747 SERIAL INTERFACE The AD7747 supports an I2C-compatible 2-wire serial interface. The two wires on the I2C bus are called SCL (clock) and SDA (data). These two wires carry all addressing, control, and data information one bit at a time over the bus to all connected peripheral devices. The SDA wire carries the data, while the SCL wire synchronizes the sender and receiver during the data transfer. I2C devices are classified as either master or slave devices. A device that initiates a data transfer message is called a master, while a device that responds to this message is called a slave. To control the AD7747 device on the bus, the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-tolow transition on SDA while SCL remains high. This indicates that the start byte follows. This 8-bit start byte is made up of a 7-bit address plus an R/W bit indicator. All peripherals connected to the bus respond to the start condition and shift in the next 8 bits (7-bit address + R/W bit). The bits arrive MSB first. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as the acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. An exception to this is the general call address, which is described later in this document. The idle condition is where the device monitors the SDA and SCL lines waiting for the start condition and the correct address byte. The R/W bit determines the direction of the data transfer. A Logic 0 LSB in the start byte means that the master writes information to the addressed peripheral. In this case the AD7747 becomes a slave receiver. A Logic 1 LSB in the start byte means that the master reads information from the addressed peri-pheral. In this case, the AD7747 becomes a slave transmitter. In all instances, the AD7747 acts as a standard slave device on the I2C bus. The start byte address for the AD7747 is 0x90 for a write and 0x91 for a read. READ OPERATION When a read is selected in the start byte, the register that is currently addressed by the address pointer is transmitted on to the SDA line by the AD7747. This is then clocked out by the master device and the AD7747 awaits an acknowledge from the master. If an acknowledge is received from the master, the address autoincrementer automatically increments the address pointer register and outputs the next addressed register content on to the SDA line for transmission to the master. If no acknowledge is received, the AD7747 returns to the idle state and the address pointer is not incremented. The address pointers’ auto-incrementer allow block data to be written or read from the starting address and subsequent incremental addresses. In continuous conversion mode, the address pointers’ autoincrementer should be used for reading a conversion result. That means, the three data bytes should be read using one multibyte read transaction rather than three separate single byte transactions. The single byte data read transaction may result in the data bytes from two different results being mixed. The same applies for six data bytes if both the capacitive and the voltage/temperature channel are enabled. The user can also access any unique register (address) on a oneto-one basis without having to update all the registers. The address pointer register contents cannot be read. If an incorrect address pointer location is accessed or, if the user allows the auto-incrementer to exceed the required register address, the following applies: • In read mode, the AD7747 continues to output various internal register contents until the master device issues a no acknowledge, start, or stop condition. The address pointers’ auto-incrementer’s contents are reset to point to the status register at Address 0x00 when a stop condition is received at the end of a read operation. This allows the status register to be read (polled) continually without having to constantly write to the address pointer. • In write mode, the data for the invalid address is not loaded into the AD7747 registers but an acknowledge is issued by the AD7747. WRITE OPERATION When a write is selected, the byte following the start byte is always the register address pointer (subaddress) byte, which points to one of the internal registers on the AD7747. The address pointer byte is automatically loaded into the address pointer register and acknowledged by the AD7747. After the address pointer byte acknowledge, a stop condition, a repeated start condition, or another data byte can follow from the master. A stop condition is defined by a low-to-high transition on SDA while SCL remains high. If a stop condition is ever encountered by the AD7747, it returns to its idle condition and the address pointer is reset to Address 0x00. If a data byte is transmitted after the register address pointer byte, the AD7747 loads this byte into the register that is currently addressed by the address pointer register, send an acknowledge, and the address pointer auto-incrementer automatically increments the address pointer register to the next Rev. PrC | Page 10 of 20 Preliminary Technical Data AD7747 internal register address. Thus, subsequent transmitted data bytes are loaded into sequentially incremented addresses. GENERAL CALL When a master issues a slave address consisting of seven 0s with the eighth bit (R/W bit) set to 0, this is known as the general call address. The general call address is for addressing every device connected to the I2C bus. The AD7747 acknowledges this address and read in the following data byte. If a repeated start condition is encountered after the address pointer byte, all peripherals connected to the bus respond exactly as outlined above for a start condition, that is, a repeated start condition is treated the same as a start condition. When a master device issues a stop condition, it relinquishes control of the bus, allowing another master device to take control of the bus. Hence, a master wanting to retain control of the bus issues successive start conditions known as repeated start conditions. If the second byte is 0x06, the AD7747 is reset, completely uploading all default values. The AD7747 does not respond to the I2C bus commands (do not acknowledge) during the default values upload for approximately 150 µs (max 200 µs). AD7747 RESET The AD7747 does not acknowledge any other general call commands. To reset the AD7747 without having to reset the entire I2C bus, an explicit reset command is provided. This uses a particular address pointer word as a command word to reset the part and upload all default settings. The AD7747 does not respond to the I2C bus commands (do not acknowledge) during the default values upload for approximately 150 µs (max 200 µs). The reset command address word is 0xBF. SCLOCK S 1–7 8 9 1–7 8 9 START ADDR R/W ACK SUBADDRESS ACK 1–7 DATA 8 9 P ACK STOP 05468-006 SDATA Figure 10. Bus Data Transfer S SLAVE ADDR A(S) SUB ADDR A(S) DATA LSB = 0 READ SEQUENCE S SLAVE ADDR A(S) S = START BIT P = STOP BIT A(S) DATA A(S) P LSB = 1 SUB ADDR A(S) S SLAVE ADDR A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) DATA A(M) A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER Figure 11. Write and Read Sequences Rev. PrC| Page 11 of 20 DATA A(M) P 05468-007 WRITE SEQUENCE Preliminary Technical Data AD7747 REGISTER DESCRIPTIONS and a read/write operation is selected, the address pointer register is set up. The address pointer register determines from or to which register the operation takes place. A read/write operation is performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. The master can write to or read from all of the AD7747 registers except the address pointer register, which is a write-only register. The address pointer register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the address pointer register. After the part has been accessed over the bus Table 8. Register Summary Address Pointer Register (Dec) (Hex) Bit 7 Bit 6 Bit 5 Dir 0 0 0 Bit 4 Bit 3 Default Value 0 0 Bit 2 Bit 1 Bit 0 RDY 1 RDYVT 1 RDYCAP 1 Status 0 0x00 R Cap Data H 1 0x01 R Capacitive channel data—high byte, 0x00 Cap Data M 2 0x02 R Capacitive channel data—middle byte, 0x00 Cap Data L 3 0x03 R Capacitive channel data—low byte, 0x00 VT Data H 4 0x04 R Voltage/temperature channel data—high byte, 0x00 VT Data M 5 0x05 R Voltage/temperature channel data—middle byte, 0x00 VT Data L 6 0x06 R Voltage/temperature channel data—low byte, 0x00 Cap Setup 7 0x07 R/W VT Setup 8 0x08 R/W EXC Setup 9 0x09 R/W Configuration 10 0x0A R/W Cap DAC A 11 0x0B R/W Cap DAC B 12 0x0C R/W Cap Offset H 13 0x0D R/W Capacitive offset calibration—high byte, 0x80 Cap Offset L 14 0x0E R/W Capacitive offset calibration—low byte, 0x00 Cap Gain H 15 0x0F R/W Capacitive gain calibration—high byte, factory calibrated Cap Gain L 16 0x10 R/W Capacitive gain calibration—low byte, factory calibrated Volt Gain H 17 0x11 R/W Voltage gain calibration—high byte, factory calibrated Volt Gain L 18 0x12 R/W Voltage gain calibration—low byte, factory calibrated CAPEN 0 VTEN 0 0 VTFS1 1 DACAENA 0 DACBENB 0 0 VTMD1 0 0 VTFS0 0 0 0 CAPDIFF 0 VTMD0 0 0 CAPFS2 1 Rev. PrC | Page 12 of 20 0 EXTREF 0 0 CAPFS1 0 0 0 0 0 EXCDAC EXCEN 0 0 CAPFS0 MD2 0 0 DACA—6-Bit Value 0x00 DACB—6-Bit Value 0x00 0 VTSHORT 0 EXCLVL1 1 MD1 0 0 VTCHOP 0 EXCLVL0 1 MD0 0 Preliminary Technical Data AD7747 The RDY pin reflects the status of the RDY bit. Therefore, the RDY pin high-to-low transition can be used as an alternative indication of the finished conversion. STATUS REGISTER Address Pointer 0x00, Read Only, Default Value 0x07 This register indicates the status of the converter. The status register can be read via the 2-wire serial interface to query a finished conversion. Table 9. Status Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic Default 0 0 0 0 0 RDY 1 RDYVT 1 RDYCAP 1 Table 10. Bit 7-3 2 Mnemonic RDY 1 RDYVT 0 RDYCAP Description Not used, always read 0. RDY = 0 indicates that conversion on the enabled channel(s) has been finished and new unread data is available. If both capacitive and voltage/temperature channels are enabled, the RDY bit is changed to 0 after conversion on both channels is finished. The RDY bit returns to 1 either when data is read or prior to finishing the next conversion. If, for example, only the capacitive channel is enabled, then the RDY bit reflects the RDYCAP bit. RDYVT = 0 indicates that a conversion on the voltage/temperature channel has been finished and new unread data is available. RDYCAP = 0 indicates that a conversion on the capacitive channel has been finished and new unread data is available. CAP DATA REGISTER VT DATA REGISTER 24 Bits, Address Pointer 0x01, 0x02, 0x03, Read-Only, Default Value 0x000000 24 Bits, Address Pointer 0x04, 0x05, 0x06, Read-Only, Default Value 0x000000 Capacitive channel output data. The register is updated after finished conversion on the capacitive channel, with one exception: When the serial interface read operation from the CAP DATA register is in progress, the data register is not updated and the new capacitance conversion result is lost. Voltage/temperature channel output data. The register is updated after finished conversion on the voltage channel or temperature channel, with one exception: When the serial interface read operation from the VT DATA register is in progress, the data register is not updated and the new voltage/temperature conversion result is lost. The stop condition on the serial interface is considered to be the end of the read operation. Therefore, to prevent data corruption, all three bytes of the data register should be read sequentially using the register address pointer auto-increment feature of the serial interface. To prevent losing some of the results, the CAP DATA register should be read before the next conversion on the capacitive channel is finished. The 0x000000 code represents negative full scale (–8.192 pF), the 0x800000 code represents zero scale (0 pF), and the 0xFFFFFF code represents positive full scale (+8.192 pF). The stop condition on the serial interface is considered to be the end of the read operation. Therefore, to prevent data corruption, all three bytes of the data register should be read sequentially using the register address pointer auto-increment feature of the serial interface. For voltage input, Code 0 represents negative full scale (–VREF), the 0x800000 code represents zero scale (0 V), and the 0xFFFFFF code represents positive full scale (+VREF). To prevent losing some of the results, the VT DATA register should be read before the next conversion on the voltage/ temperature channel is finished. For the temperature sensor, the temperature can be calculated from code using the following equation: Temperature (°C) = (Code/2048) − 4096 Rev. PrC| Page 13 of 20 Preliminary Technical Data AD7747 CAP SET-UP REGISTER Address Pointer 0x07, Default Value 0x00 Capacitive channel setup. Table 11. CAP Set-Up Register Bit Map Bit Mnemonic Default Bit 7 CAPEN 0 Bit 6 0 Bit 5 CAPDIFF 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Table 12. Bit 7 6 5 4-0 Mnemonic CAPEN CAPDIFF - Description CAPEN = 1 enables capacitive channel for single conversion, continuous conversion, or calibration. This bit must be 0 for proper operation. DIFF = 1 sets differential mode on the selected capacitive input. These bits must be 0 for proper operation. VT SET-UP REGISTER Address Pointer 0x08, Default Value 0x00 Voltage/Temperature channel setup. Table 13. VT Set-Up Register Bit Map Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mnemonic Default VTEN 0 VTMD1 0 VTMD0 0 EXTREF 0 0 0 VTSHORT 0 VTCHOP 0 Table 14. Bit 7 6 5 Mnemonic VTEN VTMD1 VTMD0 4 EXTREF 3-2 1 0 VTSHORT VTCHOP = 1 Description VTEN = 1 enables voltage/temperature channel for single conversion, continuous conversion, or calibration. Voltage/temperature channel input configuration. VTMD1 VTMD0 Channel Input 0 0 Internal temperature sensor 0 1 External temperature sensor diode 1 0 VDD monitor 1 1 External voltage input (VIN) EXTREF = 1 selects an external reference voltage connected to REFIN(+), REFIN(–) for the voltage input or the VDD monitor. EXTREF = 0 selects the on-chip internal reference. The internal reference must be used with the internal temperature sensor for proper operation. These bits must be 0 for proper operation. VTSHORT = 1 internally shorts the voltage/temperature channel input for test purposes. VTCHOP = 1 sets internal chopping on the voltage/temperature channel. The VTCHOP bit must be set to 1 for the specified voltage/temperature channel performance. Rev. PrC | Page 14 of 20 Preliminary Technical Data AD7747 EXC SET-UP REGISTER Address Pointer 0x09, Default Value 0x03 Capacitive channel excitation setup. Table 15. EXC Set-Up Bit Map Bit Mnemonic Default Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 EXCDAC 0 Bit 2 EXCEN 0 Bit 1 EXCLVL1 1 Bit 0 EXCLVL0 1 Table 16. Bit 7-4 3 2 1 0 Mnemonic EXCDAC EXCEN EXCLVL1, EXCLVL0 Description These bits must be 0 for proper operation. CAPDAC excitation. This bit must be set to 1 for the proper capacitive channel operation CIN and AC SHLD excitation. This bit must be set to 1 for the proper capacitive channel operation Excitation Voltage Level. EXCLVL1 0 0 1 1 EXCLVL0 0 1 0 1 Voltage on Cap ±VDD/8 ±VDD/4 ±VDD × 3/8 ±VDD/2 Rev. PrC| Page 15 of 20 EXC Pin Low Level VDD × 3/8 VDD × 1/4 VDD × 1/8 0 EXC Pin High Level VDD × 5/8 VDD × 3/4 VDD × 7/8 VDD Preliminary Technical Data AD7747 CONFIGURATION REGISTER Address Pointer 0x0A, Default Value 0xA0 Converter update rate and mode of operation setup. Table 17. Configuration Register Bit Map Bit Mnemonic Default Bit 7 VTF1 0 Bit 6 VTF0 0 Bit 5 CAPF2 0 Bit 4 CAPF1 0 Bit 3 CAPF0 0 Bit 2 MD2 0 Bit 1 MD1 0 Bit 0 MD0 0 Table 18. Bit 7 6 Mnemonic VTF1 VTF0 Description Voltage/temperature channel digital filter setup—conversion time/update rate setup. VTCHOP = 1 5 4 3 2 1 0 CAPF2 CAPF1 CAPF0 MD2 MD1 MD0 VTF1 VTF0 Conversion Time (ms) Update Rate (Hz) 0 0 20.1 49.8 0 1 32.1 31.2 1 0 62.1 16.1 1 1 122.1 8.2 Capacitive channel digital filter setup—conversion time/update rate setup. –3 dB Frequency (Hz) 26.4 15.9 8.0 4.0 CAP CHOP = 0 CAPF2 CAPF1 CAPF0 Conversion Time (ms) 0 0 0 22.0 0 0 1 23.9 0 1 0 40.0 0 1 1 76.0 1 0 0 124.0 1 0 1 154.0 1 1 0 184.0 1 1 1 219.3 Converter mode of operation setup. MD2 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Update Rate 45.5 41.9 25.0 13.2 8.1 6.5 5.5 4.6 Mode Idle Continuous conversion Single conversion Power-Down Capacitance system offset calibration Capacitance or voltage system gain calibration Rev. PrC | Page 16 of 20 –3 dB Frequency (Hz) Preliminary Technical Data AD7747 CAP DAC A REGISTER Address Pointer 0x0B, Default Value 0x00 Capacitive DAC setup. Table 19. Cap DAC A Register Bit Map Bit Mnemonic Default Bit 7 DACAENA 0 Bit 6 Bit 5 Bit 4 0 Bit 3 Bit 2 DACA—6-Bit Value 0x00 Bit 1 Bit 0 Bit 1 Bit 0 Table 20. Bit 7 6 Mnemonic DACAENA - Description DACAENA = 1 connects capacitive DACA to the positive capacitance input. This bit must be 0 for proper operation. 5-1 DACA DACA value, Code 0x00 ≈ 0 pF, Code 0x3F ≈ full range. CAP DAC B REGISTER Address Pointer 0x0C, Default Value 0x00 Capacitive DAC setup. Table 21. Cap DAC B Register Bit Map Bit Bit 7 Mnemonic Default DACAENB 0 Bit 6 Bit 5 Bit 4 0 Bit 3 Bit 2 DACB—6-Bit Value 0x00 Table 22. Bit 7 6 Mnemonic DACBENB - Description DACBENB = 1 connects capacitive DACB to the negative capacitance input. This bit must be 0 for proper operation. 5-1 DACB DACB value, Code 0x00 ≈ 0 pF, Code 0x3F ≈ full range. CAP OFFSET CALIBRATION REGISTER CAP GAIN CALIBRATION REGISTER 16 Bits, Address Pointer 0x0D, 0x0E, Default Value 0x8000 16 Bits, Address Pointer 0x0F, 0x10, Default Value 0xXXXX The capacitive offset calibration register holds the capacitive channel zero-scale calibration coefficient. The coefficient is used to digitally remove the capacitive channel offset. The register value is updated automatically following the execution of a capacitance offset calibration. The capacitive offset calibration resolution (cap offset register LSB) is less than TBD aF; the full range is TBD pF. Capacitive gain calibration register. The register holds the capacitive channel full-scale factory calibration coefficient. VOLT GAIN CALIBRATION REGISTER 16 Bits, Address Pointer 0x11,0x12, Default Value 0xXXXX Voltage gain calibration register. The register holds the voltage channel full-scale factory calibration coefficient. Rev. PrC| Page 17 of 20 Preliminary Technical Data AD7747 CIRCUIT DESCRIPTION To eliminate the CIN parasitic capacitance to ground, the AD7747 SHLD signal can be used for shielding the connection between the sensor and CIN. The SHLD output is basically the same signal waveform as the excitation of the CIN pin, the SHLD is driven to the same voltage potential as the CIN pin. Therefore, there is no AC current between CIN and SHLD pins and any capacitance between these pins doesn't get involved in the CIN charge transfer. Ideally, the CIN to SHLD capacitance doesn't have any contribution to the AD7747 result. ACTIVE AC SHIELD CONCEPT The AD7747 measures capacitance between CIN and ground. That means any capacitance to ground on signal path between AD7747 CIN pin(s) and sensor is included in the AD7747 conversion result. The parasitic capacitance of the sensor connections can easily be in the same, if not even higher order than the capacitance of the sensor itself. If that parasitic capacitance is stable, it can be treated as a non-changing capacitive offset. However, the parasitic capacitance of sensor connections is often changing as result of mechanical movement, changing ambient temperature, ambient humidity, etc. These changes would be seen as drift in the conversion result and may significantly compromise the system accuracy. To get the best result, locate the AD7747 as close as possible to the capacitive sensor. Keep the connection between the sensor and AD7747 CIN pin and also the return path between sensor ground and the AD7747 GND pin short. Shield the PCB track to CIN pin and connect the shielding to the AD7747 SHLD pin. Also, if a shielded cable is used for sensor connection, the shield should be connected to the AD7747 SHLD pin. TYPICAL APPLICATION DIAGRAM 0.1uF + 10uF +3V / +5V POWER SUPPLY VDD TEMP SENSOR CLOCK GENERATOR HOST SYSTEM AD7747 VIN(+) SDA VIN(-) MUX 24-BIT Σ -∆ MODULATOR CIN1(+) CIN1(-) DIGITAL FILTER I2C SERIAL INTERFACE CONTROL LOGIC CALIBRATION SHLD CAP DAC 1 EXCITATION VOLTAGE REFERENCE CAP DAC 2 REFIN(+) REFIN(-) GND Figure 12. Basic Application Diagram for a Differential Capacitive Sensor Rev. PrC | Page 18 of 20 SCL RDY Preliminary Technical Data AD7747 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 SEATING PLANE 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 13. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Rev. PrC | Page 19 of 20 0.75 0.60 0.45 Preliminary Technical Data AD7747 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05469-0-7/06(PrC) Rev. PrC | Page 20 of 20