a FEATURES Broad Range Analog Variable Gain –2.5 dB to +42.5 dB 3 dB Cutoff Frequency of 500 MHz Gain Up and Gain Down Modes Linear-in-dB, Scaled 20 mV/dB Resistive Ground Referenced Input Nominal ZIN ⴝ 200 ⍀ On-Chip Square-Law Detector Single-Supply Operation: 2.7 V to 5.5 V APPLICATIONS Cellular Base Station Broadband Access Power Amplifier Control Loops Complete, Linear IF AGC Amplifiers High-Speed Data I/O GENERAL DESCRIPTION The AD8367 is a high-performance 45 dB variable gain amplifier with linear-in-dB gain control for use from low frequencies up to several hundred megahertz. The range, flatness, and accuracy of the gain response are achieved using Analog Devices’ X-AMP® architecture, the most recent in a series of powerful proprietary concepts for variable gain applications, which far surpasses what can be achieved using competing techniques. The input is applied to a 200 Ω resistive ladder network, having nine sections each of 5 dB loss, for a total attenuation of 45 dB. At maximum gain, the first tap is selected; at progressively lower gains, the tap moves smoothly and continuously toward higher attenuation values. The attenuator is followed by a 42.5 dB fixed gain feedback amplifier—essentially an operational amplifier with a gain bandwidth product of 100 GHz—and is very linear, even at high frequencies. The output third order intercept is +20 dBV at 100 MHz (+27 dBm re 200 Ω), measured at an output level of 1 V p-p with VS = 5 V. 500 MHz, Linear-in-dB VGA with AGC Detector AD8367 FUNCTIONAL BLOCK DIAGRAM VPSI ICOM VPSO ENBL AD8367 INPT ICOM 9-STAGE ATTENUATOR BY 5dB DECL BIAS HPFL gm CELLS VOUT GAUSSIAN INTERPOLATOR SQUARE LAW DETECTOR ICOM OCOM MODE GAIN DETO The analog gain-control interface is very simple to use. It is scaled at 20 mV/dB, and the control voltage, VGAIN, runs from 50 mV at –2.5 dB to 950 mV at +42.5 dB. In the inverse-gain mode of operation, selected by a simple pin-strap, the gain decreases from +42.5 dB at VGAIN = 50 mV to –2.5 dB at VGAIN = 950 mV. This inverse mode is needed in AGC applications, which are supported by the integrated square-law detector, whose set point is chosen to level the output to 354 mV rms, regardless of the waveshape. A single external capacitor sets up the loop averaging time. The AD8367 may be powered on or off by a voltage applied to the ENBL pin. When this voltage is at a logic LO, the total power dissipation drops to the milliwatt range. For a logic HI, the chip powers-up rapidly to its normal quiescent current of 26 mA at 25°C. The AD8367 is available in a 14-lead TSSOP package for the industrial temperature range of –40°C to +85°C. X-AMP is a registered trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD8367–SPECIFICATIONS Parameter (VS = 5 V, TA = 25ⴗC, System Impedance ZO = 200 ⍀, VMODE = 5 V, f = 10 MHz, unless otherwise noted.) Conditions Min OVERALL FUNCTION Frequency Range GAIN Range LF Pins INPT and ICOM To Avoid Input Overload From INPT to ICOM GAIN CONTROL INTERFACE Scaling Factor Pin GAIN VMODE = 5 V, 50 mV ≤ VGAIN ≤ 950 mV VMODE = 0 V, 50 mV ≤ VGAIN ≤ 950 mV 100 mV ≤ VGAIN ≤ 900 mV VGAIN = 0.95 V VGAIN = 0.05 V From 0 dB to 30 dB From 30 dB to 0 dB VGAIN = 0.5 V Small Signal Bandwidth OUTPUT STAGE Max Output Voltage Swing Output Source Resistance Output Centering Voltage1 Pin DETO POWER INTERFACE Supply Voltage Total Supply Current Pins VPSI, VPSO, ICOM, and OCOM CAGC 100 pF, 6 dB Gain Step 700 200 Unit 500 MHz dB Pin MODE Device in Negative Slope Mode of Operation Device in Positive Slope Mode of Operation ENABLE INTERFACE Enable Threshold Enable Response Time Pin ENBL Time Delay Following LO to HI Transition until Device Meets Full Specifications. ENBL at 5 V ENBL at 0 V –2– 225 mV p-p Ω +20 –20 ± 0.2 +42.5 –2.5 300 300 5 mV/dB mV/dB dB dB dB ns ns MHz 4.3 3.5 50 VS/2 V p-p V p-p Ω V 354 1 mV rms s 2.7 ENBL High, Maximum Gain, RL 200 Ω (Includes Load Current) ENBL Low –40°C ≤ TA ≤ +85°C MODE CONTROL INTERFACE Mode LO Threshold Mode HI Threshold Enable Input Bias Current 175 Pin VOUT RL = 1 kΩ RL = 200 Ω Series Resistance of Output Buffer SQUARE LAW DETECTOR Output Set Point AGC Small Signal Response Time Disable Current vs. Temperature Max 45 INPUT STAGE Maximum Input Input Resistance Gain Law Conformance Maximum Gain Minimum Gain VGAIN Step Response Typ 26 1.3 5.5 30 V mA 1.6 1.8 mA mA 1.2 1.4 V V 2.5 1.5 V s 27 32 A nA REV. 0 AD8367 Parameter f = 70 MHz Gain Conditions Min Maximum Gain Minimum Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Maximum Gain f1 70 MHz, f2 71 MHz, VGAIN 0.5 V Output 1 dB Compression Point VGAIN 0.5 V f = 140 MHz Gain Maximum Gain Minimum Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Maximum Gain f1 140 MHz, f2 141 MHz, VGAIN 0.5 V Output 1 dB Compression Point VGAIN 0.5 V f = 190 MHz Gain Maximum Gain Minimum Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Maximum Gain f1 190 MHz, f2 191 MHz, VGAIN 0.5 V Output 1 dB Compression Point VGAIN 0.5 V f = 240 MHz Gain Maximum Gain Minimum Gain Gain Scaling Factor Gain Intercept Noise Figure Output IP3 Maximum Gain f1 240 MHz, f2 241 MHz, VGAIN 0.5 V Output 1 dB Compression Point VGAIN 0.5 V NOTES 1 The output dc centering voltage is normally set at VS2 and can be adjusted by applying a voltage to DECL. Specifications subject to change without notice. REV. 0 –3– Typ Max Unit +42.5 –3.7 19.9 –5.6 6.2 27.5 20.5 8.5 1.5 dB dB mV/dB dB dB dBm dBV rms dBm dBV rms +43.5 –3.6 19.7 –5.3 7.4 24.5 17.5 8.4 1.4 dB dB mV/dB dB dB dBm dBV rms dBm dBV rms +43.5 –3.8 19.6 –5.3 7.5 23.9 16.9 8.4 1.4 dB dB mV/dB dB dB dBm dBV rms dBm dBV rms +43 –4.1 19.7 –5.2 7.6 24.6 17.6 8.1 1.1 dB dB mV/dB dB dB dBm dBV rms dBm dBV rms AD8367 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS Supply Voltage VPSO, VPSI . . . . . . . . . . . . . . . . . . . . . 5.5 V ENBL Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS + 200 mV MODE Select Voltage . . . . . . . . . . . . . . . . . . . . VS + 200 mV VGAIN Control Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 600 mV Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . 250 mW θJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W Maximum Junction Temperature . . . . . . . . . . . . . . . . 125°C Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . 300°C Pin *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PIN CONFIGURATION ICOM 1 14 ICOM ENBL 2 13 HPFL INPT 3 12 VPSI AD8367 MODE 4 11 DETO 6 9 DECL ICOM 7 8 OCOM VPSO TOP VIEW GAIN 5 (Not to Scale) 10 VOUT Mnemonic Description 1, 7, 14 ICOM Signal Common. Connect to low impedance ground. 2 ENBL A HI activates the device. 3 INPT Signal Input. 200 Ω to ground. 4 MODE Gain Direction Control. HI for Positive Slope; LO for Negative Slope. 5 GAIN Gain-Control Voltage Input 6 DETO Detector Output. Provides output current for RSSI function and AGC control. 8 OCOM Power Common. Connect to low impedance ground. 9 DECL Decoupling Pin. Can Be Used to Modify the Output Reference Level. 10 VOUT Signal Output. Generally will be ac-coupled. 11 VPSO Positive Supply Voltage. 2.7 V to 5.5 V. VPSI and VPSO are tied together internally with back-to-back PN junctions. They should be tied together externally and properly bypassed. 12 VPSI Positive Supply Voltage. 2.7 V to 5.5 V. 13 HPFL High-Pass Filter Connection. A capacitor to ground sets the corner frequency of the output offset control loop. ORDERING GUIDE Model Temperature Range Package Description Package Option AD8367ARU AD8367ARU-REEL-7 AD8367-EVAL AD8367ARU-REEL –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Tube, 14-Lead 7" Tape and Reel Evaluation Board 13" Tape and Reel RU-14 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8367 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 Typical Performance Characteristics–AD8367 10 50 +85 C 1V 0.9V 40 9 0.8V +25 C NOISE FIGURE – dB 0.7V 30 GAIN – dB 0.6V 0.5V 20 0.4V 0.3V 10 8 –40 C 7 6 0.2V 0.1V 0 –10 10 5 100 FREQUENCY – MHz 4 1000 70 90 190 130 150 170 FREQUENCY – MHz 110 210 230 250 TPC 4. NF (re 200 Ω) vs. Frequency at Maximum Gain TPC 1. Gain vs. Frequency for Values of VGAIN 45 60 40 50 35 MODE ⴝ 5V 10MHz 70MHz 140MHz 240MHz 25 20 15 NOISE FIGURE – dB GAIN – dB 30 MODE ⴝ 0V 10MHz 70MHz 140MHz 240MHz 10 5 40 30 20 10 0 –5 0 0.1 0.2 0.3 0.4 0.5 0.6 VGAIN – V 0.7 0.8 0.9 1.6 35 1.2 0.8 GAIN – dB –40 C 0.4 25 +25 C 20 0 +85 C 15 –0.4 10 –0.8 5 –1.2 0 –1.6 –5 0 0.1 0.2 0.3 0.4 0.5 0.6 VGAIN – V 0.7 0.8 0.9 0.3 0.4 0.5 0.6 VGAIN – V 0.7 0.8 0.9 1.0 37 10MHz 32 25 70MHz 20 27 140MHz 22 15 240MHz 10 17 5 12 0 –2.0 1.0 0 TPC 3. Gain Conformance at 70 MHz for T –40ⴗC, +25ⴗC, and +85ⴗC. REV. 0 0.2 30 OIP3 – dBV rms 2.0 LINEARITY ERROR – dB 45 40 0.1 TPC 5. NF (re 200 ) vs. VGAIN at 70 MHz TPC 2. Gain vs. VGAIN (Mode LO and Mode HI) 30 0 1.0 0.1 0.2 0.3 0.4 0.6 0.5 VGAIN – V 0.7 TPC 6. OIP3 vs. VGAIN –5– 0.8 0.9 7 1.0 OIP3 – dBm (re 200⍀) 0 AD8367 30 37 25 32 20 27 0 –10 22 10 17 OUTPUT IMD – dBc 15 OIP3 – dBm (re 200⍀) OIP3 – dBV rms –20 –30 240MHz –40 140MHz –50 70MHz 10MHz –60 12 5 –70 7 1000 –80 TPC 7. OIP3 vs. Frequency for VGAIN 500 mV 2 11 9 140MHz 0 7 200MHz –2 5 –4 3 –6 1 –8 0 0.1 0.2 0.3 0.4 0.5 0.6 VGAIN – V 0.7 0.8 0.9 OUTPUT 1dB COMPRESSION – dBV rms 10MHz 70MHz 11 3 10 2 9 1 8 0 7 –1 6 –2 5 –3 4 –4 3 –5 2 1000 OUTPUT IP3 – dBV rms 12 4 OUTPUT 1dB COMPRESSION – dBm (re 200⍀) OUTPUT 1dB COMPRESSION – dBV rms 0.3 0.4 0.5 VGAIN – V 0.6 0.7 0.8 0.9 11 2 9 0 7 –2 5 –4 3 –6 1 3.0 3.5 4.0 VS – V 4.5 5.0 –1 5.5 TPC 11. Output Compression Point vs. Supply Voltage at 70 MHz, VGAIN = 500 mV 5 100 FREQUENCY – MHz 0.2 4 –8 2.5 0 1.0 TPC 8. Output P1dB vs. VGAIN 10 0.1 TPC 10. IMD3 vs. Gain (VOUT 1 V p-p Composite) OUTPUT 1dB COMPRESSION – dBm (re 200⍀) OUTPUT 1dB COMPRESSION – dBV rms 4 0 OUTPUT 1dB COMPRESSION – dBm (re 200⍀) 100 FREQUENCY – MHz 25 32 20 27 15 22 10 17 5 12 0 2.5 TPC 9. Output P1dB vs. Frequency at VGAIN 500 mV 3.0 3.5 4.0 VS – V 4.5 5.0 OUTPUT IP3 – dBm (re 200⍀) 0 10 7 5.5 TPC 12. Output Third Order Intercept vs. Supply Voltage at 70 MHz, VGAIN = 500 mV –6– REV. 0 AD8367 250 0 200 –25 90 60 150 –47 100 –73 SERIES REACTANCE – ⍀ RESISTANCE – ⍀ 120 30 150 500mV 300mV 700mV 180 0 –95 50 210 0 0 100 200 300 FREQUENCY – MHz 330 –120 500 400 TPC 13. Input Resistance and Series Reactance vs. Frequency at VGAIN = 500 mV 240 300 270 90 TPC 16. Output Reflection Coefficient vs. Frequency from 10 MHz to 500 MHz for Multiple Values of VGAIN 60 120 0.5 VGAIN 30 150 0.4 0.3 VOUT 0 180 V –V 0.2 300mV 210 0.1 330 0 500mV 700mV 240 –0.1 300 –0.2 270 –0.3 TIME – 200ns/div TPC 14. Input Reflection Coefficient vs. Frequency from 10 MHz to 500 MHz for Multiple Values of VGAIN 70 20 65 15 TPC 17. VGA Time Domain Response (3 dB Step) 25 10 55 5 50 0 45 –5 40 –10 500 GAIN – dB 60 SERIES REACTANCE – ⍀ RESISTANCE – ⍀ 20 10nF 15 1nF 10pF 10 100pF 5 NO CAP 0 100 200 300 FREQUENCY – MHz 400 0 0.1 TPC 15. Output Resistance and Series Reactance vs. Frequency at VGAIN 500 mV REV. 0 1 10 100 1000 FREQUENCY – kHz 10000 100000 TPC 18. Gain vs. Frequency for Multiple Values of HPFL Capacitor at VGAIN = 500 mV –7– AD8367 1.0 1.5 10MHz 70MHz 140MHz 240MHz 70MHz 0.5 RSSI – V 0.6 0 0.5 –0.5 240MHz 0.4 –1.0 10MHz 0.3 –1.5 0.2 –2.0 0.1 –2.5 0 –60 VAGC 1.0 0.7 CAGC = 100pF V –V 140MHz LINEARITY ERROR – dB 0.8 0.7 0.8 2.0 0.9 –40 –30 –20 –10 VOUT 0.5 –3.0 –50 0.6 0.4 –2E–05 0 –1E–05 INPUT LEVEL – dBV rms TPC 19. AGC RSSI (Voltage on DETO Pin) vs. Input Power at 10 MHz, 70 MHz, 140 MHz, and 240 MHz 1.0 +85ⴗC RSSI – V TPC 22. AGC Time Domain Response (3 dB Step) 1.5 1.0 +25ⴗC 0.7 0.5 0.6 0 0.5 –0.5 –40ⴗC 0.4 –1.0 0.3 –1.5 0.2 –2.0 0.1 –2.5 LINEARITY ERROR – dB 0.8 –3.0 –50 –40 –30 –20 0 –10 19.0097 19.7297 19.9097 20.0897 GAIN SCALING – mV/dB INPUT LEVEL – dBV rms 1.0 2.5 0.9 2.0 0.8 1.5 RSSI – V 0.7 1.0 WCDMA 256QAM 0.6 64QAM 16QAM SINE 0.5 0.5 0 0.4 –0.5 IS95FWD 0.3 –1.0 0.2 –1.5 0.1 –2.0 –50 –40 –30 –20 INPUT LEVEL – dBV rms –10 20.2697 TPC 23. Gain Scaling Distribution at 70 MHz LINEARITY ERROR – dB TPC 20. AGC RSSI (Voltage on DETO Pin) vs. Input Power over Temperature at 70 MHz 0 –60 2E–05 1E–05 2.0 +25ⴗC –40ⴗC +85ⴗC 0.9 0 –60 0 TIME – sec –2.5 10 –6.4 TPC 21. AGC RSSI (Voltage on DETO Pin) vs. Input Power for Various Modulation Schemes –6.2 –6.0 –5.8 –5.6 –5.4 INTERCEPT – dB –5.2 –5.0 –4.8 TPC 24. Gain Intercept Distribution at 70 MHz –8– REV. 0 AD8367 44 The AD8367 is a variable gain single-ended IF amplifier based on Analog Devices’ patented X-AMP architecture. It offers accurate gain control with a 45 dB span and a 3 dB bandwidth of 500 MHz. It can be configured as a traditional VGA with 50 dB/V gain scaling or as an AGC amplifier by using the builtin rms detector. Figure 1 is a simplified block diagram of the amplifier. The main signal path consists of a voltage-controlled 0 dB to 45 dB variable attenuator followed by a 42.5 dB fixed gain amplifier. The AD8367 is designed to operate optimally in a 200 Ω impedance system. 40 36 1.2 0.8 GAIN – dB 28 0.4 24 0 20 –0.4 16 –0.8 12 –1.2 8 –1.6 HI MODE –2.0 0 INTEGRATOR OUTPUT BUFFER GAIN INTERPOLATOR 1.6 32 4 GAIN 2.0 50dB/V GAIN SLOPE LO MODE –4 LINEARITY ERROR – dB THEORY OF OPERATION –2.4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VGAIN – V gm gm 0dB gm –5dB –10dB VOUT gm Figure 2. The gain function can be either an increasing or decreasing function of VGAIN depending on the MODE pin. –45dB VOUT –42.5dB INPT The gain is a decreasing function of VGAIN when the MODE pin is low. Figure 2 also illustrates this mode which is described by 200⍀ Gain (dB) = 45 − 50 × VGAIN ATTENUATOR LADDER Figure 1. The Simplified Architecture This gain mode is required in AGC applications using the builtin square-law level detector. Input Attenuator and Gain Control The variable attenuator consists of a 200 Ω single-ended resistive ladder comprising nine 5 dB sections and an interpolator that selects the attenuation factor. Each tap point down the ladder network further attenuates the input signal by a fixed decibel factor. Gain control is achieved by sensing different tap points with variable transconductance stages. Based on the gain control voltage, an interpolator selects which stage(s) are active. For example, if only the first stage is active, the 0 dB tap point is sensed; if the last stage is active, the 45 dB tap point is sensed. Attenuation levels that fall between tap points are achieved by having neighboring gm stages active simultaneously, creating a weighted average of the discrete tap point attenuations. In this way, a smooth, monotonic attenuation function is synthesized that is linear-in-dB with a very precise scaling. The gain of the AD8367 can be an increasing or decreasing function of the control voltage, VGAIN, depending on whether the MODE pin is pulled up to the positive supply or down to ground. When the MODE pin is high, the gain increases with VGAIN as shown in Figure 2. The ideal linear-in-dB scaled transfer function is given by, Gain (dB) = 50 × VGAIN − 5 Input and Output Interfaces The AD8367 was designed to operate best in a 200 Ω impedance system. Its gain range, conformance law, noise and distortion assume that 200 Ω source and load impedances are used. Interfacing the AD8367 to other common impedances (from 50 Ω used at radio frequencies to 1 kΩ presented by data-converters) can be accomplished using resistive or reactive passive networks, whose design depends on specific system requirements such as bandwidth, return loss, noise figure and absolute gain range. The input impedance of the AD8367 is nominally 200 Ω, determined by the resistive ladder network. This presents a 200 Ω dc resistance to ground, and in cases where an elevated signal potential is used, ac coupling is necessary. The input signal level must not exceed 700 mV p-p to avoid overloading the input stage. The output impedance is determined by an internal 50 Ω damping resistor, as shown in the simplified schematic in Figure 3. VB1 (1) 50⍀ FROM INTEGRATOR VOUT VB2 where VGAIN is expressed in volts. Equation 1 contains the gain scaling factor of 50 dB/V (20 mV/dB) and the gain intercept of –5 dB which represents the extrapolated gain for VGAIN = 0 V. The gain ranges from –2.5 dB to 42.5 dB for VGAIN ranging from 50 mV to 950 mV. The deviation from (1), that is, the gain conformance error, is also illustrated in Figure 2. The ripples in the error are a result of the interpolation action between tap points. The AD8367 provides better than ±0.5 dB of conformance error over >40 dB gain range at 200 MHz and ± 1 dB at 400 MHz. REV. 0 (2) Figure 3. A 50 Ω Resistor is Added to the Output to Prevent Package Resonance –9– AD8367 Power and Voltage Metrics Output Centering Although power is the traditional metric used in the analysis of cascaded systems, most active circuit blocks fundamentally respond to voltage. The relationship between power and voltage is defined by the impedance level. When input and output impedance levels are the same, power gain and voltage gain are identical. However, when impedance levels change between input and output, they differ. Thus, one must be very careful to use the appropriate gain for system chain analyses. Quantities such as OIP3 are quoted in dBV rms as well as dBm referenced to 200 Ω. The dBV rms unit is defined as decibels relative to 1 V rms. In a 200 Ω environment, the conversion from dBV rms to dBm requires the addition of 7 dB to the dBV rms value. For example, a +2 dBV rms level corresponds to +9 dBm. The output level is centered midway between ground and the supply if the DECL pin is left floating. Alternatively, the output level may be set by driving the DECL pin with the desired reference level. As shown in Figure 5, the loop acts to suppress deviations from the reference at outputs below its corner frequency while not affecting signals above it. The maximum corner frequency with no external capacitor is 500 kHz. The corner frequency can be lowered arbitrarily by adding an external capacitor, CHP: Noise and Distortion Since the AD8367 consists of a passive variable attenuator followed by a fixed gain amplifier, the noise and distortion characteristics as a function of the gain voltage are easily predicted. The input-referred noise increases in proportion to the attenuation level. Figure 4 shows noise figure, NF, as a function of VGAIN for the MODE pin pulled high. The minimum NF of 7.5 dB occurs at maximum gain and increases 1 dB for every 1 dB reduction in gain. In receiver applications, the minimum NF should occur at the maximum gain where the received signal presumably is weak. At higher levels, a lower gain is needed, and the increased NF becomes less important. 60 f HP (kHz) = MAIN AMPLIFIER FROM INPUT VMID HPFL CHP 30 20 20 IIP3 10 10 The AD8367 contains a square-law detector that senses the output signal and compares it to a calibrated set-point of 354 mV rms which corresponds to a 1 V p-p sine wave. Any difference between the output and set-point generates a current which is integrated by an external capacitor, CAGC, connected from the DETO pin to ground, to provide an AGC control voltage. There is also an internal 5 pF capacitor on the DETO pin. 0 0 –10 –10 –20 –20 –30 0 0.1 0.2 0.3 0.4 0.5 0.6 VGAIN – V 0.7 0.8 0.9 AV ⴝ 1 RMS Detection NF – dB IIP3 – dBV 30 DECL Figure 5. The dc output level is centered to mid supply by a control loop whose corner frequency is determined by CHP. 50 40 VOUT gm NF 40 (3) A capacitor at pin DECL is recommended to decouple the reference level to which the output is centered. 60 50 10 C HP (nF)+ 0.02 –30 1.0 Figure 4. Noise Figure and Input Third Order Intercept vs. Gain (RSOURCE 200 Ω) The input-referred distortion varies in a similar manner to the noise. Figure 4 illustrates how the third-order intercept point at the input, IIP3, behaves as a function of VGAIN. The highest IIP3 of 20 dBV rms (27 dBm re 200 Ω) occurs at minimum gain. The IIP3 then decreases 1 dB for every 1 dB increase in gain. At lower levels, a degraded IIP3 is acceptable. Overall, the dynamic range, represented by the difference between IIP3 and NF, remains reasonably constant as a function of gain. The output distortion and compression are essentially independent of the gain. At low gains, when the input level is high, input overload may occur, causing premature distortion. The resulting voltage is used as an AGC bias. For this application, the MODE pin is pulled low and the DETO pin is tied to the GAIN pin. The output signal level is then regulated to 354 mV rms. The AGC bias represents a calibrated rms measure of the received signal strength (RSSI). Since in the AGC mode the output signal is forced to the 354 mV rms set-point (–9.02 dBV rms), Equation 2 can be recast to express the strength of the received signal, VIN-RMS, in terms of the AGC bias VDETO, VIN − RMS (dBV rms) = − 54.02 + 50 × VDETO (4) where –54.02 dBV rms –45 dB 9.02 dBV rms. For small changes in input signal level, VDETO responds with a characteristic single-pole time constant, τAGC, which is proportional to CAGC, τ AGC ( µs) = 10 × C AGC (nF) (5) where the internal 5 pF capacitor has been lumped with the external capacitor to give CAGC. –10– REV. 0 AD8367 APPLICATIONS 1 The AD8367 can be configured either as a variable-gain amplifier whose gain is controlled externally through the GAIN pin or as an AGC amplifier, using a supply voltage of 2.7 V to 5.5 V. The supply to the VPSO and VPSI pins should be decoupled using a low-inductance 0.1 F surface-mount ceramic capacitor, as close to the device as possible. Additional supply decoupling may be provided by a small series resistor. A 10 nF capacitor from pin DECL to OCOM is recommended to decouple the output reference voltage. 3 0.3333 RSOURCE 0.3333 1 3 Input and Output Matching ZIN The AD8367 is designed to operate in a 200 Ω impedance system. The output amplifier is a low output impedance voltage buffer with a 50 Ω damping resistor to desensitize it from load reactance and parasitics. The quoted performance includes the voltage division between the 50 Ω resistor and the 200 Ω load. The AD8367 can be reactively matched to an impedance other than 200 Ω using traditional step-up and step down matching networks or high quality transformers. Table I lists the 50 Ω S-parameters for the AD8367 at a VGAIN 750 mV. SERIES L SHUNT C –0.3333 –3 –1 fC ⴝ 140MHz, ZIN ⴝ 193.4 ⴚ j46.3⍀, ZLOAD ⴝ 229 ⴚ j8.8⍀ RSOURCE ⴝ 50⍀, RLOAD ⴝ 50⍀ Figure 6 illustrates an example where the AD8367 is matched to 50 Ω at 140 MHz. As shown in the Smith Chart, the input matching network shifts the input impedance from ZIN to 50 Ω with an insertion loss of less than 2 dB over a 5 MHz bandwidth. For the output network, the 50 Ω load is made to present 200 Ω to the AD8367 output. Table II provides the component values required for 50 Ω matching at several frequencies of interest. XSIN 120nH AD8367 XPIN 5pF RSOURCE 50⍀ ZIN VS CAC 0.1F ZOUT ZIN In situations where added loss and noise can be tolerated, a resistive pad can be used to provide broad-band near-matched impedances at the device terminals and the terminations. Minimum-loss L-pad networks are used on the evaluation board (see Figure 19) to allow easy interfacing to standard 50 Ω test equipment. Each pad introduces an 11.5 dB power loss (5.5 dB voltage loss). ZLOAD XPOUT 150nH 10 0.64⬔0° S21 S12 S22 8.5⬔177° −3 2 × 10 ⬔153° 0.02⬔11° −4 70 0.64⬔–1.5° 9.0⬔168° 5 × 10 ⬔106° 0.02⬔54° 140 0.63⬔–3.0° 10.0⬔152° 9 × 10−4⬔80° 0.06⬔88° 10.4⬔138° −4 9 × 10 ⬔147° 0.09⬔83° 10.8⬔125° −3 0.1⬔76° 190 240 0.63⬔–3.7° 0.62⬔–4.9° 1 × 10 ⬔148° Table II. Reactive Matching Components for a 50 Ω System, RS = 50 Ω, RLOAD = 50 Ω Frequency (MHz) XSIN REV. 0 RLOAD 50⍀ Figure 6. Reactive Matching Example for f 140 MHz Table I. S-Parameters for 50 Ω System for VS = 5 V, and VGAIN = 0.75 V Frequency (MHz) S11 XSOUT 13pF XPIN (pF) XSOUT (pF) XPOUT 10 1.5 H 120 180 1.8 H 70 220 nH 15 27 270 nH 140 120 nH 7 13 150 nH 190 82 nH 4 10 100 nH 240 68 nH 3 7 82 nH –11– AD8367 VGA Operation AGC Operation The AD8367 is a general-purpose VGA suitable for use in a wide variety of applications where voltage-control of gain is needed. While having a 500 MHz bandwidth, its use is not limited to high frequency signal processing. Its accurate, temperature- and supply-stable linear-in-dB scaling will be valuable wherever it is important to have a more dependable response to the control voltage than is usually offered by VGAs of this sort. For example, there is no preclusion to its use in speech-bandwidth systems. The AD8367 may be used as an AGC amplifier as shown in Figure 8. For this application, the accurate internal square-law detector is employed. The output of this detector is a current that varies in polarity depending on whether the rms value of the output is greater or less than its internally-determined “set-point” of 354 mV rms. This is 1 V p-p for sine-wave signals, but the peak amplitude for other signals, such as Gaussian noise, or those carrying complex modulation, will invariably be somewhat greater. However, for all waveforms having a crest factor of less than 5, and when using a supply voltage of 4.5 V to 5.5 V, the rms value will be correctly measured and delivered at VOUT. When using lower supplies, the rms value of VOUT is unaffected (the setpoint is determined by a band-gap reference) but the peak crest factor capacity is reduced. Figure 7 shows the basic connections. The capacitor CHP at Pin HPFL may be used to alter the high-pass corner frequency of the signal path, and is associated with the offset control loop that eliminates the inherent variation in the internal dc balance of the signal path as the gain is varied (“offset ripple”). This frequency should be chosen to be about a decade below the lowest frequency component of the signal. If made much lower than necessary, the offset loop will not be able to track the variations that occur when there are rapid changes in VGAIN. The control of offset is important even when the output is ac-coupled because of the potential reduction of the upper and lower voltage range at this pin. However, in many applications these components will be unnecessary, since an internal network provides a default high-pass corner of about 500 kHz. For CHP 1 nF, the modified corner is at ~10 kHz; it scales downward with increasing capacitance. TPC 18 shows representative response curves for the indicated component values. C1 1F VIN 1 ICOM ICOM 14 2 ENBL HPFL 13 3 VGAIN INPT AD8367 MODE VPSO 11 5 GAIN VOUT 10 6 DETO DECL ICOM C2 CHP, 0.1F 0.1F VP R5 4.7⍀ C3 0.1F C1 1F 1 VIN VPSI 12 4 7 R6 4.7⍀ The output of the detector is delivered to Pin DETO. The detector can source up to 60 µA and can sink up to 11 µA. For a sine-wave output signal, and under conditions where the AGC loop is settled, the detector output also takes the form of a sine-wave, but at twice the frequency and having a mean value of zero. If the input to the amplifier increases the mean of this current also increases, and charges the external loop filter capacitor CAGC toward more positive voltages. Conversely, a reduction in VOUT below the set-point of 354 mV rms causes this voltage to fall toward ground. The capacitor voltage is the AGC bias; this may be used as an RSSI (Received Signal Strength Indicator) output, and is scaled exactly as VGAIN, that is, 20 mV/dB. OCOM 9 8 C4, 0.1F VOUT VAGC CAGC 0.1F C5 10nF Figure 7. Basic Connections for Voltage-Controlled Gain Mode Modulated Gain Mode The AD8367 may be used as a means of modulating the signal level. It should be kept in mind, however, that the gain is a nonlinear (exponential) function of VGAIN; thus it is not suitable for normal amplitude-modulation functions. The small-signal bandwidth of the gain interface is ~5 MHz and the slew-rate is of the order of ± 500 dB/s. During gain slewing from close to minimum to maximum gain (or vice versa) the internal interpolation processes in an X-AMP-based VGA rapidly scan the full range of gain values. The gain and offset ripple associated with this process may cause transient disturbances in the output. Therefore, it is inadvisable to use high-amplitude pulse drives with rise and fall times below 200 ns. ICOM ICOM 14 2 ENBL 3 INPT HPFL 13 4 MODE VPSO 11 5 GAIN VOUT 10 6 DETO DECL 9 7 ICOM OCOM 8 AD8367 CHP, 10nF R6 4.7⍀ C2 0.1F VP R5 4.7⍀ C3 0.1F VPSI 12 C4, 0.1F VOUT C5 10nF Figure 8. Basic Connections for AGC Operation A valuable feature of using a square law detector is that the RSSI voltage is a true reflection of signal power, and may be converted to an absolute power measurement for any given source impedance. The AD8367 may thus be employed as a true-power meter, or decibel-reading ac voltmeter, as distinct from its basic amplifier function. The AGC mode of operation requires that the correct gain direction is chosen. Specifically, the gain must fall as VAGC increases to restore the needed balance against the set-point. Therefore, the MODE pin must be pulled low. This accurate leveling function is shown in Figure 9, where the rms output is held to within 0.1 dB of the set point for >35 dB range of input levels. The dynamics of this loop are controlled by CAGC acting in conjunction with an on-chip equivalent resistance RAGC of 10 kΩ which form an effective time-constant TAGC RAGC CAGC. The loop thus operates as a single-pole system with a loop bandwidth of 1/(2 TAGC). Because the gain control function is linear in decibels, this bandwidth is independent of absolute signal level. Figure 10 illustrates the loop dynamics for a 30 dB change in input signal level with CAGC 100 pF. –12– REV. 0 AD8367 In some cases, it may be found that, if driven into AGC overload, the AD8367 will require unusually long times to recover; that is, the voltage at DETO will remain at an abnormally high value and the gain will be at its lowest value. To avoid this situation, it is recommended that a clamp be placed on the DETO pin as shown in Figure 11. –1.2 –1.3 POUT – dBm (re 200⍀) –1.4 –1.5 –1.6 –1.7 1 –1.8 AD8367 2 13 –1.9 +VS 3 –2.0 0.5V –2.2 –50 –40 –30 –20 –10 PIN – dBm (re 200⍀) 10 0 Q1 2N2907 RA 12 4 MODE 11 5 GAIN 10 6 DETO 9 7 ICOM 8 VAGC RB –2.1 14 CAGC 0.1F Figure 9. Leveling Accuracy of the AGC Function Figure 11. External Clamp to Prevent AGC Overload. The resistive divider network, RA and RB, should be designed such that the base of Q1 is driven to 0.5 V. 1.0 VAGC 0.8 Modifying the AGC Set Point VAGC – V; VOUT – arb 0.6 If an AGC set point other than the internal one is desired, an external detector may be used. Figure 12 depicts a method that uses an external true-rms detector and error integrator to operate the AD8367 as a closed-loop AGC system with a user-settable operating level. 0.4 0.2 VOUT 0 –0.2 –0.4 –0.6 0 5 10 15 20 25 TIME – s 30 35 40 Figure 10. AGC Response to a 32 dB Step in Input Level (f 50 MHz) It is important to understand that RAGC does not act as if in shunt with CAGC. Rather, the error-correction process is that of a true integrator, to guarantee an output that is exactly equal in rms amplitude to the specified set-point. For large changes in input level, the integrating action of this loop will be most apparent. The slew rate of VAGC is determined by the peak output current from the detector and the capacitor. Thus, for a representative value of CAGC 3 nF, this rate is about 20 V rms or 10 dB/s, while the small-signal bandwidth is 1 kHz. Most AGC loops incorporating a true error-integrating technique have a common weakness. When driven from an increasingly larger signal, the AGC bias increases to reduce the gain. But eventually, the gain will fall to its minimum value, for which further increase in this bias will have no effect on the gain. That is, the voltage on the loop capacitor will be forced progressively higher because the detector output is a current, and the AGC bias is its integral. Consequently there will always be a precipitous increase in this bias voltage when the input to the AD8367 exceeds that value which overdrives the detector, and because the minimum gain is –2.5 dB, that will happen for all inputs +2.5 dB greater than the set-point of ~350 mV rms. If possible, the user should ensure that this limitation is preserved, preferably with a guard-band of 5 dB to 10 dB below overload. REV. 0 The AD8361 (U2) produces a dc output level which is proportional to the rms value of its input, taken as a sample of the AD8367 (U1) output. This dc voltage is compared to an externally-supplied setpoint voltage, and the difference is integrated by the AD820 (U3) to form the gain control voltage which is applied to the GAIN input of the AD8367 through the divider composed of R4 and R5. This divider is included in order to minimize overload recovery time of the loop by having the integrator saturate at a point that only slightly overdrives the gain control input of the AD8367. The scale factor at VAGC is influenced by the values of R4 and R5; for the values shown, the factor is 86 mV/dB. Note that in this circuit the AD8367’s MODE pin must be pulled high to obtain correct feedback polarity because the integrator inverts the polarity of the feedback signal. The relationship between set-point voltage and the rms output voltage of the AD8367 is as follows: VOUT − RMS = VSET × ( R1 + 225) 225 × 7.5 (6) where 225 is the input resistance of the AD8361 and 7.5 is its conversion gain. For R1 200 Ω, this reduces to VOUT –RMS VSET 0.25. Capacitor C2 sets the averaging time for the rms detector. This should be made long enough to provide sufficient smoothing of the detector’s output in the presence of the modulation on the RF signal. A level fluctuation of less than 1 dB (<5% to 10%) p-p at the AD8361’s output is a reasonable value. A considerably longer time-constant will needlessly lower the AGC bandwidth, while a short time-constant can degrade the accuracy of the true-rms measurement process. Components C1, R2, and R3 set the control loop’s bandwidth and stability. The maximum stable loop bandwidth will be limited by the rms detector’s averaging time constant as discussed above. –13– AD8367 10nF 10nF 10nF RF INPUT R6 66⍀ 1 ICOM ICOM 14 2 ENBL HPFL 13 3 INPT 4 MODE VPSO 11 5 GAIN 6 7 5V VOUT INTO A 200⍀ LOAD C2 0.27F 10nF 0.1F 1 VPOS SREF 8 2 IREF VRMS 7 VOUT 10 3 RFIN FLTR 6 DET0 DECL 9 4 PWDN COMM 5 ICOM OCOM 8 AD8367 VPSI 12 R1 200⍀ C5 0.1F U2 U1 C1 3.3nF AD820 Vg R3 82k⍀ VAGC R4 33k⍀ AD8361 4 6 R5 10k⍀ 20pF R2 150k⍀ 2 Vrms U3 0.1F 7 12k⍀ VSET 3 5V Figure 12. Example of Using an External Detector to Form an AGC Loop For an input signal consisting of a 4.096 MS/s QPSK modulated carrier, the relationship between VSET and the output power for this setup is shown in Figure 13. The exponential shape reflects the linear-in-magnitude response of the AD8361. The adjacent channel power ratio (ACPR) as a function of output power is illustrated in Figure 14. The minima occur where the distortion and integrated noise powers cross over. –20 –25 The component values shown in Figure 12 were chosen for a 64-QAM signal at 500 kS/s at a carrier frequency of 150 MHz. The response time of the loop as shown is roughly 5 ms for an abrupt input level change of 40 dB. Figure 15 shows the dynamic performance of the loop with a step-modulated CW signal applied to the input for a VSET of about 1 V. ACPR – dBc –30 –35 140MHz –40 380MHz –45 –50 10MHz 70MHz –55 –60 –20 –15 –10 –5 0 POUT – dBm Into 200⍀ 4.0 5 10 Figure 14. ACPR versus Output Power for QPSK Waveform (4.096 MS/s; 0.22; 1 User) 3.5 3.0 10MHz 1.0 VSET – V 2.5 Vg 380MHz 0.5 2.0 Vg – V; V OUT – arb 1.5 1.0 0.5 0 –20 –15 –10 –5 0 POUT – dBm Into 200⍀ 5 0.0 VOUT –0.5 –1.0 10 –1.5 Figure 13. AGC Set-Point Voltage vs. Output Power (QPSK: 4.096 MS/s; 0.22; 1 User) –2.0 0 0.005 0.010 0.015 0.020 0.025 TIME – sec 0.030 0.035 0.040 Figure 15. AGC Dynamic Response: 8367 AGC with an External Detector –14– REV. 0 AD8367 R7 10k⍀ SW2 TP3 MODE AD8367 LK1 R2 174⍀ J1 INPUT R1 57.6⍀ C1 1F TP4 GAIN 1 ICOM ICOM 14 2 ENBL HPFL 13 3 INPT VPSI 12 4 MODE 5 GAIN VOUT 10 6 DETO DECL 9 7 ICOM OCOM 8 SW1 CAGC 0.1F RHP, 0⍀ R6 4.7⍀ C2 0.1F TP1 VP R5 4.7⍀ C3 0.1F CHP, 10nF VPSO 11 J2 C5 10nF OUTPUT R4 174⍀ C4 0.1F R3 57.6⍀ Figure 16. Evaluation Board Schematic Table III. Suggested Component Values For External AGC Detector Circuit Modulation Type Rate Sym/s C1 F QPSK 1.23 M QPSK π/4 DQPSK C2 F R2 k⍀ R3 k⍀ 0.0022 0.033 150 62 4M 0.0022 0.015 150 39 24.3 K 0.033 0.68 150 51 64 QAM 100 K 0.015 1.5 150 51 64 QAM 500 K 0.0068 0.33 150 62 64 QAM 4M 0.0022 0.068 150 100 Evaluation Board Figure 16 shows the schematic of the AD8367 evaluation board. The board is powered by a single supply of 2.7 V to 5.5 V. Table IV details the various configuration options of the evaluation board. Figure 18. Silkscreen of Component Side Characterization Setup and Methods Minimum-loss L-pad matching networks were used to interface standard 50 Ω test equipment to the 200 Ω input impedance during the characterization process. Using a 57.6 Ω shunt resistor followed by a 174 Ω series resistor provides a broadband match between the 50 Ω test equipment and the 200 Ω device impedance as illustrated in Figure 19. The insertion loss of this network is 11.5 dB. AD8367 174⍀ 57.6⍀ 174⍀ 57.6⍀ Figure 19. Characterization Test Setup Figure 17. Layout of Component Side REV. 0 –15– AD8367 Table IV. Evaluation Board Configuration Options Function Default Condition TP1, TP2 Supply and Ground Vector Pins Not Applicable TP3, TP4 Mode and Gain Vector Pins Not Applicable SW1 VGA/AGC Select: Used to select VGA (position A) or AGC (position B) mode of operation. SW2 must be set for position A for AGC mode of operation. SW1 A SW2 MODE Select: Used to select positive or negative VGA slope. Set to position B for an increasing gain with VGAIN, position A for decreasing gain law. SW2 B LK1 Device Enable: When LK1 is installed, the ENBL pin is connected to the positive supply and the AD8367 is in operating mode. SW3 PWUP R1, R2 Input Interface: R1 and R2 are used to provide an L-pad impedancetransforming network. The broadband matching network transforms a 50 source to match a 200 Ω load with 11.5 dB of insertion loss. R1 57.6 Ω (Size 0603) R2 174 Ω (Size 0603) R3, R4, C4 Output Interface: R3 and R4 are used to transform a 50 Ω load termination to look like a 200 Ω load with 11.5 dB of insertion loss. The AC coupling capacitor, C4, can be increased to obtain a lower high-pass corner frequency. R3 57.6 Ω (Size 0603) R4 174 Ω (Size 0603) C4 0.1 F (Size 0603) C1, C2, C3, R5, R6 Power Supply Decoupling: The nominal supply decoupling consists of a 1 F capacitor to ground, a 4.7 Ω series resistor, and a 0.1 F capacitor to ground. The same de-coupling network should be used on both VPSI and VPSO supply lines. C1 1 F (Size 0603) R5 R6 4.7 Ω (Size 0805) C2 C3 0.1 F (Size 0603) C5 Internal Supply Decoupling: Capacitor C5 provides mid-supply decoupling. C5 10 nF (Size 0603) CHPFL Filter Capacitor: HPFL capacitor, sets the high pass corner frequency. CHPFL 0.1 F (Size 0805) RHP 0 Ω (Size 0603) CAGC AGC Filter Capacitor: Capacitor, CAGC, sets closed loop AGC response time. CAGC = 0.1 F (Size 0805) R7 Mode Pullup Resistor R7 10 kΩ (Size 0805) C02710–.8–10/01(0) Component OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead (TSSOP) (RU-14) 14 PRINTED IN U.S.A. 0.201 (5.10) 0.193 (4.90) 8 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 7 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) –16– 8ⴗ 0ⴗ 0.028 (0.70) 0.020 (0.50) REV. 0