a CDMA 3 V Transmitter IF Subsystem with Integrated Voltage Regulator AD6122 FEATURES Fully Compliant with IS98A and PCS Specifications Linear IF Amplifier –63 dB to +34 dB Linear-in-dB Gain Control Temperature-Compensated Gain Control Quadrature Modulator Modulates IFs from 50 MHz to 350 MHz Integral Low Dropout Regulator Accepts 2.9 V to 4.2 V Input from Battery Low Power 10.4 mA at Midgain <10 A Sleep Mode Operation Companion Receiver IF Chip Available (AD6121) APPLICATIONS CDMA, W-CDMA, AMPS and TACS Operation QPSK Transmitters GENERAL DESCRIPTION The AD6122 is a low power IF transmitter subsystem, specifically designed for CDMA applications. It consists of an I and Q modulator, a divide-by-two quadrature generator, high dynamic range IF amplifiers with voltage-controlled gain and a powerdown control input. An integral low dropout regulator allows operation from battery voltages from 2.9 V to 4.2 V. The gain control input accepts an external gain control voltage input from a DAC. It provides 97 dB of gain control with a nominal 75 dB/V scale factor. Either an internal or an external reference may be used to set the gain-control scale factor. The I and Q modulator accepts differential quadrature baseband inputs from a CDMA baseband converter. The local oscillator is injected at twice the IF frequency. A divide-by-two quadrature generator followed by dual polyphase filters ensures ± 1° quadrature accuracy. The modulator provides a common-mode reference output to bias the transmit DACs in the baseband converter to the same common-mode voltage as the modulator inputs, allowing dc coupling between the two ICs and thus eliminating the need to charge and discharge coupling capacitors. This allows the fastest power-up and power-down times for the AD6122 and CDMA baseband ICs. The AD6122 is fabricated using a 25 GHz f t silicon BiCMOS process and is packaged in a 28-lead SSOP and a 32-leadless LPCC chip scale package (5 mm × 5 mm). FUNCTIONAL BLOCK DIAGRAM VCC QUADRATURE MODULATOR OUTPUT ATTENUATOR IF AMPLIFIER INPUT QUADRATURE MODULATOR I INPUT IF AMPLIFIERS LOCAL OSCILLATOR INPUT TRANSMIT OUTPUT ⴜ2 AD6122 Q INPUT COMMON-MODE REFERENCE OUTPUT VPOS LOW DROPOUT REGULATOR POWER- POWERDOWN 1 DOWN 2 VREG GAIN CONTROL SCALE FACTOR TEMPERATURE COMPENSATION 1.23 V GAIN CONTROL GAIN CONTROL VOLTAGE REFERENCE REFERENCE INPUT OUTPUT VOLTAGE INPUT REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 (T = +25ⴗC, V AD6122–SPECIFICATIONS noted) NOTE: All powers shown in dBm are referred to 1 k⍀. A CC = +3.0 V, LO = 2 ⴛ IF, REFIN = 1.23 V, LDO Enabled, unless otherwise Specification Conditions MODULATOR LO = 260.76 MHz (2 × IF), 100 mV p-p 500 mV p-p Differential I and Q Inputs; Output Level Referred to a 1 kΩ Differential Load Output Level Output Third Order Harmonic I/Q Inputs Differential Input Voltage Bandwidth Resistance Quadrature Accuracy Amplitude Balance Output Referred Noise Modulator Common-Mode Reference LO Input Resistance LO Input Capacitance LO Carrier Leakage IF AMPLIFIER Noise Figure Input 1 dB Compression Point Input Third-Order Intercept Gain Flatness Input Capacitance Differential IF Input Resistance Differential IF Output Resistance Differential IF Output Capacitance GAIN CONTROL INTERFACE Gain Scaling Gain Scaling Linearity Minimum Gain Maximum Gain Gain Control Response Time Input Resistance at REFIN Input Resistance at VGAIN POWER-DOWN INTERFACE Logic Threshold High Logic Threshold Low Input Current for Logical High Turn-On Response Time Turn-Off Response Time LOW DROPOUT REGULATOR Min Max Unit –21 –50 dBm dBc 500 Differential Input at 260.38 MHz Differential Input at 260.38 MHz Bias I/Q Using MODCMREF 30 ±1 ± 0.1 –169 1.408 1.2 2.4 –40 mV p-p MHz kΩ ° dB dBm/Hz V kΩ pF dBc FIF = 130.38 MHz VGAIN = 2.5 V, 1 kΩ Differential Load VGAIN = 2.5 V VGAIN = 2.5 V IF ± 630 kHz Shunt Equivalent Model at 130.38 MHz Shunt Equivalent Model at 130.38 MHz Per Pin at 130.38 MHz Per Pin at 130.38 MHz 10 –32 –24 ± 0.25 2.3 680 4.2 2.0 dB dBm dBm dB pF Ω kΩ pF Using Internal Reference For a Typical Dynamic Range of 92 dB VGAIN = 0.5 V VGAIN = 2.5 V 90 dB Gain Change, Min Gain to Max Gain 75 ±3 –63 +34 0.7 10 109 dB/V dB/V dB dB µs MΩ kΩ Power-Up on Logical High 1.34 1.30 0.1 23 187 V V µA µs ns 2.9–4.2 2.70 200 1.23 V V mV V 2.7–5.0 10.4 7.8 V mA µA Differential –3 dB 20 0.9 MHz to 5.0 MHz Offsets Measure to Settling of AGC from Standby Mode To 200 µA Supply Current External PNP Pass Transistor, VCE SAT = –0.4 V Max, hFE = 100/300 Min/Max Input Range Nominal Output Dropout Voltage Reference Output POWER SUPPLY Supply Range Bypassing Internal LDO Supply Current Standby Current Typ VGAIN = 1.5 V (Unity Gain) OPERATING TEMPERATURE TMIN to TMAX –40 +85 °C Specifications subject to change without notice. –2– REV. B AD6122 ABSOLUTE MAXIMUM RATINGS 1 NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 28-lead SSOP Package: θJA = 115.25°C/W. Supply Voltage DVCC, IFVCC, TXVCC to DGND, IFGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . 600 mW Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C PIN CONFIGURATIONS LDOB 4 25 IFVCC LDOC 5 24 IFGND LDOC 2 DGND 7 AD6122 TOP VIEW NC IFVCC REFIN REFOUT 32 31 30 29 28 27 26 25 26 REFOUT LDOB 1 LDOGND 6 VGAIN 27 REFIN LDOE 3 PD1 28 VGAIN PD2 2 PD2 PD1 1 LPCC Package LDOE SSOP Package 23 IIPP LDOGND 3 22 IIPN LDOGND 4 24 IFGND 23 IFGND 22 IIPP 21 IIPN AD6122 Top View (Not to Scale) LOIPP 8 (Not to Scale) 21 MODCMREF LOIPN 9 20 QIPN LOIPP 6 19 QIPN DVCC 10 19 QIPP LOIPN 7 18 QIPP IFINP MODOPN 15 IFINN IFINN 16 IFINP IFGND 14 10 11 12 13 14 15 16 IFGND TXVCC 13 17 MODOPP 9 IFGND 17 MODOPN TXVCC TXOPN 12 DVCC 8 TXOPP 18 MODOPP 20 MODCMREF TXOPN TXOPP 11 DGND 5 NC = NO CONNECT ORDERING GUIDE Model Temperature Range Package Description AD6122ARS AD6122ARSRL AD6122ACP AD6122ACPRL –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Shrink Small Outline Package (SSOP) 28-Lead SSOP on Tape-and-Reel Chip Scale Package (LPCC) 32-Leadless LPCC on Tape-and-Reel CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6122 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –3– Package Option RS-28 CP-32 WARNING! ESD SENSITIVE DEVICE AD6122 PIN FUNCTION DESCRIPTIONS SSOP Pin # LPCC Pin # Pin Label Description Function 1 30 PD1 Power-Down 1 2 31 PD2 Power-Down 2 3 32 LDOE 4 1 LDOB 5 2 LDOC 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 3, 4 5 6 7 8 9 10 11 12, 13 14 15 16 17 18 19 20 LDOGND DGND LOIPP LOIPN DVCC TXOPP TXOPN TXVCC IFGND IFINN IFINP MODOPN MODOPP QIPP QIPN MODCMREF 22 23 24 25 26 21 22 23, 24 25 26 27 IIPN IIPP IFGND NC IFVCC REFOUT Low Dropout Regulator Pass Transistor Emitter Connection Low Dropout Regulator Pass Transistor Base Low Dropout Regulator Pass Transistor Collector Low Dropout Regulator Ground Digital Ground Local Oscillator “Positive” Input Local Oscillator “Negative” Input Digital VCC Transmit Output “Positive” Transmit Output “Negative” Transmit Output VCC IF Ground IF Input “Negative” IF Input “Positive” Modulator “Negative” If Output Modulator “Positive” Output Q Input “Positive” Q Input “Negative” Modulator Common-Mode Reference Out I Input “Negative” I Input “Positive” Ground No Connect IF VCC Gain Control Reference Output IF Amplifier Power-Down Control Input; CMOS Compatible; HIGH = Entire IC Powers Down, LOW = IF Amplifiers On. Modulator Power-Down Control Input; CMOS Compatible; HIGH = Modulator Off , LOW = Modulator On. Connects to Emitter of External PNP Pass Transistor and VCC. Connects to Base of External PNP Pass Transistor. 27 28 REFIN Gain Control Reference Input 28 29 VGAIN Gain Control Voltage Input –4– Connects to Collector of External PNP Pass Transistor. Ground. Ground. Connects to Local Oscillator; AC Coupled. Connects to Ground via Decoupling Capacitor. Connects to Digital Supply. Connects to Output Filter; AC Coupled. Connects to Output Filter; AC Coupled. Connects to LDO Output via Decoupling Network. Ground. IF “Negative” Input from LC Roofing Filter. IF “Positive” Input from LC Roofing Filter. Output Modulator Output to LC Roofing Filter. Modulator Output to LC Roofing Filter. Connects to Q “Positive” Output of Baseband IC. Connects to Q “Negative” Output of Baseband IC. Connects to CDMA Baseband Converter Tx DAC Common-Mode Reference Input. Connects to I “Negative” Output of Baseband IC. Connects to I “Positive” Output of Baseband IC. Connects to IF Ground. Connects to Decoupled Output of LDO Regulator. Provides 1.23 V Voltage Reference Output for DAC in CDMA Baseband Converter and REFIN. Accepts 1.23 V Reference Input from REFOUT or External Reference. Accepts Gain Control Input Voltage from External DAC. Max Gain = 2.5 V; Min Gain = 0.5 V. REV. B AD6122 Test Figures 0.1F +15V 8 VP 1 X1 2 X2 V–1 MUST BE EQUAL LENGTHS MODCMREF OUT A=1 3 Y1 7 IIPP 50⍀ 4 Y2 V–1 AD830 VN –15V I DATA AD6122 5 0.1F 50⍀ 0.1F +15V 1 X1 8 VP 2 X2 V–1 MODCMREF OUT A=1 3 Y1 7 IIPN 50⍀ 4 Y2 V–1 VREG OUT AD830 VN –15V 5 0.1F 0.1F 450⍀ MODOPP 0.1F +15V 1 X1 MUST BE EQUAL LENGTHS OUT A=1 3 Y1 7 10nF 450⍀ QIPP 0.1F VREG OUT 50⍀ 4 Y2 V–1 205⍀ MODOPN 8 VP 2 X2 V–1 MODCMREF 10nF AD830 VN –15V Q DATA 5 0.1F 50⍀ 0.1F +15V 8 VP 1 X1 2 X2 V–1 MODCMREF MODCMREF OUT A=1 3 Y1 7 QIPN 50⍀ 4 Y2 V–1 AD830 VN –15V 5 0.1F LOIPP LOIPN LO INPUT Figure 1. Quadrature Modulator’s Characterization Input and Output Impedance Matches REV. B –5– MOD_OUT AD6122 VREG OUT PULL-UP INDUCTORS CHOSEN FOR PEAK RESPONSE AT THE TEST FREQUENCY. 1:8 RF SOURCE 383⍀ 511⍀ IFINP 453⍀ TXOPP 10nF 0.1F 10nF 205⍀ 10nF 453⍀ TO SPECTRUM ANALYZER 4:1 IFINN 383⍀ TXOPN 10nF AD6122 0.1F VREG OUT Figure 2. IF Amplifier’s Characterization Input and Output Impedance Matches NOTE: RF CABLES FOR I AND Q PATHS MUST BE OF EQUAL LENGTH TEST BED MOTHERBOARD I DATA TEKTRONIX AFG2002 500mVp-p DIFFERENTIAL MOD OUT Q DATA R&S SMT03 I CHANNEL R&S FSEA20/30 SPECTRUM RF ANALYZER INPUT Q CHANNEL AUX MEAS PORT IFTX OUT LO INPUT RF IF IN RF SOURCE 1 TO RF SWITCHES R&S SMT03 HP34970A DATA ACQUISITION & SWITCH CONTROL RF RF SOURCE 2 HPE3610 POWER SUPPLY DC MEASUREMENTS & CONTROL BITS Figure 3. General Test Set –6– REV. B AD6122 VREG OUT PULL-UP INDUCTORS CHOSEN FOR PEAK RESPONSE AT THE TEST FREQUENCY. REACTIVE CONJUGATE MATCH NOISE SOURCE 1:8 IFINP 0.1F 453⍀ TXOPP 10nF 10nF 205⍀ 10nF 453⍀ 4:1 TO NOISE FILTER METER IFINN TXOPN 10nF AD6122 0.1F VREG OUT Figure 4. IF Amplifier’s Noise Figure Test Set HP8116A FUNCTION GEN. 4 kHz, 0.5V TO 2.5V SQ. WAVE AGC HP8116A FUNCTION GEN. ROHDE & SCHWARZ SMT03 4kHz, 0V TO 2.7V SQ. WAVE 100MHz, –30dBm IFIN PD1, PD2 TEKTRONIX TDS 744A ROHDE & SCHWARZ SMT03 100kHz, –30dBm IFIN IFOUT AD6122 TEST BED CH 2 WITH COAX CABLE 50⍀ IFOUT AD6122 TEST BED CH 2 WITH COAX CABLE 50⍀ b. Response Time from PD1 and PD2 Control to IF Output a. Response Time from Gain Control to IF Output Figure 5. Response Time Setup REV. B TEKTRONIX TDS 744A CH 1 WITH X10 PROBE CH 1 WITH X10 PROBE –7– AD6122 –Typical Performance Characteristics 1 –50 –60 30kHz 100kHz 2s UNIT dBm –49.18dBm 1 (T1) 130.67458918MHz CH PWR –33.92dBm –77.32dB ACP UP 77.46dB AVE LOW –30 A UNDESIRED SIDEBAND – dBc RBW VBW SWT REF LEV –40dBm –40 POWER – dBm –70 –80 –90 –100 –110 CL1 –120 CU1 –35 –40 –130 –45 50 –140 CENTER 130.38MHz 519kHz/DIV SPAN 5.19MHz MODULATOR OUTPUT – dBm REFERRED TO A 1k⍀ DIFFERENTIAL LOAD LO LEAKAGE – dBc 300 350 –10 –35 –40 –45 100 150 200 250 FREQUENCY – MHz 300 –15 –20 –25 –30 –35 –14.0 350 Figure 7. Modulator LO Leakage vs. Output Frequency –12.0 –10.0 –8.0 –6.0 MODULATOR, I = Q – dBV –4.0 –2.0 Figure 10. Modulator Gain: Input (dBV) vs. Output (dBm) –45 –15 –20 THIRD HARMONIC – dBc OUTPUT DESIRED SIDEBAND LEVEL – dBm REFERRED TO 1k⍀ 150 200 250 OUTPUT FREQUENCY – MHz Figure 9. Modulator Output Undesired Sideband vs. Output Frequency Figure 6. Spectral Plot at Modulator Outputs: ACPR –50 50 100 –25 –30 –50 –55 –60 –35 –40 50 100 150 200 250 OUTPUT FREQUENCY – MHz 300 –65 50 350 100 150 200 250 OUTPUT FREQUENCY – MHz 300 350 Figure 11. Modulator Third Harmonic Figure 8. Modulator Output Desired Sideband vs. Output Frequency Without Roofing Filter –8– REV. B AD6122 40 –24 –25 IIP3 – dBm Referred to 1k⍀ GAIN – dB With a 1k⍀ Load 20 0 TA = –40ⴗC –20 TA = +85ⴗC –40 –60 –26 –27 TA = +25ⴗC –80 0.5 1.0 1.5 VGAIN – V 2.0 –28 2.5 2.5 Figure 12. IF Amplifier Response Curve: Gain vs. VGAIN, TA = –40 °C, +25 °C, +85 °C 45 15 3.0 GAIN ERROR GAIN – dB 5 2.0 1.0 –5 –15 0 –25 –1.0 –2.0 –35 GAIN –45 –3.0 –55 –4.0 –65 –5.0 –75 0.5 0.9 1.3 1.7 VGAIN – V 2.1 IIP3 – dBm Referred to 1k⍀ 5.0 4.0 150 200 250 FREQUENCY – MHz 100 300 350 30.0 0 25.0 NOISE FIGURE – dB IIP3 – dBm Referred to 1k⍀ –25 Figure 16. IF Amplifier Input IP3 vs. Frequency 5.0 –5.0 –10.0 –15.0 20.0 133MHz 313MHz 15.0 238MHz 10.0 –20.0 0.9 1.3 1.7 VGAIN – V 2.1 5.0 –10.0 2.5 0 10.0 20.0 GAIN – dB 30.0 40.0 Figure 17. IF Amplifier Noise Figure vs. Gain Figure 14. IF Amplifier Input IP3 vs. VGAIN REV. B 3.7 –24 –26 50 –6.0 2.5 Figure 13. IF Amplifier Gain and Error vs. VGAIN –25.0 0.5 3.5 –23 ERROR FROM PREDICTED VALVE – dB 35 2.9 3.1 3.3 SUPPLY VOLTAGE – V Figure 15. IF Amplifier Input IP3 vs. Supply Voltage 6.0 25 2.7 –9– AD6122 18.0 TOTAL CURRENT CONSUMPTION – mA 40 VGAIN = 2.5V 20 VGAIN = 2.0V GAIN – dB 0 –20 VGAIN = 1.5V –40 VGAIN = 1.0V –60 16.0 14.0 12.0 10.0 VGAIN = 0.5V –80 50 100 150 200 250 FREQUENCY – MHz 300 8.0 0.5 350 Figure 18. IF Amplifier Gain vs. Frequency for VGAIN = 2.5 V, 2.0 V, 1.5 V, 1.0 V 1.5 VGAIN – V 2.0 2.5 Figure 19. Total Current Consumption vs. VGAIN RBW VBW SWT REF LEV –30dBm –30 –40 1 30kHz 300kHz 2s UNIT dBm –46.78dBm 1 (T1) 130.38000000MHz CH PWR –31.93dBm –66.95dB ACP UP AVE LOW –68.95dB –0.28 dB 1 (T1) 330.66132265kHz 1 –50 –60 POWER – dBm 1.0 A –70 –80 –90 –100 –110 CL1 CO CO CU1 –120 –130 CENTER 130.38MHz 600kHz/DIV SPAN 6MHz Figure 20. ACPR of Cascaded Modulator, 20 dB Pad and IF Amplifier: Spectral Plot –10– REV. B AD6122 VCC QUADRATURE MODULATOR OUTPUT ATTENUATOR IF AMPLIFIER INPUT QUADRATURE MODULATOR I INPUT IF AMPLIFIERS LOCAL OSCILLATOR INPUT TRANSMIT OUTPUT ⴜ2 AD6122 Q INPUT COMMON-MODE REFERENCE OUTPUT VPOS LOW DROPOUT REGULATOR POWERDOWN 1 GAIN CONTROL SCALE FACTOR VREG POWERDOWN 2 1.23 V REFERENCE OUTPUT GAIN CONTROL REFERENCE VOLTAGE INPUT TEMPERATURE COMPENSATION GAIN CONTROL VOLTAGE INPUT Figure 21. Block Diagram THEORY OF OPERATION IF Amplifiers and Gain Control The CDMA Transmitter IF Subsystem (Figure 21) consists of an I and Q modulator with a divide-by-two quadrature generator, high dynamic range IF amplifiers with voltage-controlled gain, a low dropout regulator and power-down control inputs. The IF amplifiers provide an 86 dB linear in dB gain control range. The input stage uses a differential, continuously variable attenuator based on Analog Devices’ patented X-AMP™ topology. This low noise attenuator consists of a differential R-2R ladder network, linear interpolator and a fixed gain amplifier. The IF amplifier’s input impedance is 1 kΩ differential. Similar to the I and Q modulator’s output, the IF amplifier’s output is a differential current, which will vary depending upon the gain control voltage. In order to achieve the specified gain, the output of the IF amplifiers should be loaded with a 1 kΩ differential load. I and Q Modulator The I and Q modulator accepts differential quadrature baseband inputs from CDMA baseband converters. The LO is injected at twice the IF frequency. A divide-by-two quadrature generator followed by dual polyphase filters ensures ± 1° quadrature accuracy (Figure 22). For 500 mV p-p differential I and Q input signals, the output power of the modulator will be –21 dBm referred to 1 kΩ when the output of the modulator is loaded with a 1 kΩ differential load. With the maximum input conditions stated above, the modulator outputs are a 225 µA p-p differential current; consequently, the output load will greatly affect the output power of the modulator. 2 ⴛ IF LO INPUT ⴜ2 I I POLYPHASE FILTERS 180ⴗ ⴜ2 The gain control circuits contain both temperature compensation circuitry and a choice of internal or external reference for adjusting the gain scale factor. The gain control input accepts an external gain control voltage input from a DAC. It provides 97 dB of gain control range with a nominal 75 dB/V scale factor. Q QUADRATURE OUTPUT TO MODULATOR Q Figure 22. Simplified Quadrature Generator Circuit The I and Q modulator also provides a common mode reference signal at the MODCMREF pin. This voltage is a dc voltage set to 1.408 V when a 2.7 V supply is used. It is used to dc bias the output of the DAC that provides I and Q inputs to the modulator. The external gain control input signal should be a clean signal. It is recommended to filter this signal in order to eliminate the noise that results from the DAC. If a noisy signal is used for the gain control voltage, VGAIN inband and adjacent channel noise peaking can occur at the output of the AD6122. A simple RC filter can be employed, but care should be taken with its design. If too big a resistor is used, a large voltage drop may occur across the resistor, resulting in lower gain than expected (as a result of a lower voltage reaching the AD6122). An RC filter with a 20 kHz bandwidth, employing a 1 kΩ resistor is appropriate. This results in an 8.2 nF capacitor. The resulting circuit is shown in Figure 23. Note that the input resistance at the VGAIN pin is approximately 100 kΩ. AD6122 1k⍀ 8.2nF VGAIN 109k⍀ Figure 23. Gain Voltage Filtering X-AMP is a trademark of Analog Devices, Inc. REV. B FROM BASEBAND CONVERTER –11– AD6122 The AD6122’s overall gain, expressed in decibels, is linear in dB with respect to the automatic gain control (AGC) voltage, VGAIN. Either REFOUT or an external reference voltage connected to REFIN may be used to set the voltage range for VGAIN. When the internal 1.23 V reference, REFOUT, is connected to REFIN , VGAIN will control the entire AGC range when it is typically set between 0.5 V and 2.5 V. Minimum gain occurs at minimum voltage on VGAIN and maximum gain occurs at maximum voltage on VGAIN. The maximum and minimum gain will not change with a change in voltage at REFIN. Rather, the slope of the gain curve will change as a result of a change in the required range for VGAIN. Figure 24 shows the piecewise linear approximation of the gain curve for the AD6122. GAIN – V/V MAXIMUM GAIN MINIMUM GAIN Figure 24. Piecewise Linear Approximation for the AD6122 Gain Curve Because the minimum and maximum gain from the AD6122 are constant, we can approximate the VGAIN range for a given REFIN voltage by using Equation 1. (GAIN – MinGain) × 1.6REFIN + 0.4 REFIN MaxGain – MinGain Table I. Operating Modes PD1 PD2 IF Amp Modulator 0 0 1 1 0 1 0 1 ON ON INVALID STATE OFF ON OFF INVALID STATE OFF Low Dropout Regulator The AD6122 incorporates an integrated low dropout regulator. The regulator accepts inputs from 2.9 V to 4.2 V and supplies a constant 2.7 V reference output at LDOC. The 2.7 V signal can be used to provide the dc voltages required for the DVCC, TXVCC and IFVCC dc supplies. In order to configure the low dropout regulator, an external pass transistor is required. A pnp bipolar junction transistor with a minimum hFE of 100 and a maximum hFE of 300 and a VCESAT of –0.4 V is required. In order to use the low dropout regulator, configure the transistor as shown in Figure 25. The 18 pF capacitor in Figure 25 is used for decoupling the 2.7 V dc signal. In addition to the low dropout regulator, a band-gap voltage reference produces a 1.23 V reference voltage at REFOUT. This reference voltage will be present whenever a 2.7 V dc signal is present on pin LDOC. This 1.23 V reference voltage can then be used to provide the gain reference signal required for REFIN and the reference voltage for the transmit DACs in a baseband converter. VGAIN – V VGAIN = up. The control is provided via two control pins, PD1 and PD2. Table I shows the operating modes of the AD6122. AD6122 (1) LDOE 2.9V – 4.2V Where MaxGain is the maximum gain (+34 dB) in dB, MinGain is the minimum gain (–63 dB) in dB, REFIN is the reference input voltage, in volts, VGAIN is the gain control voltage input, in volts, and GAIN is the particular gain, in dB, we would have for a given REFIN and VGAIN. Consequently, for any REFIN we choose, we can calculate the VGAIN range by solving Equation 1 for VGAIN. For example, in order to determine the VGAIN value for the maximum gain condition, given a 1.23 V REFIN, we can solve Equation 1 for VGAIN by substituting +34 dB for GAIN and MaxGain, –63 dB for MinGain and 1.23 V for REFIN. VGAIN can then be calculated to be 2.46 V, or approximately 2.5 V. For the minimum gain condition, we can determine the VGAIN value by substituting 34 dB for MaxGain, –63 dB for GAIN and MinGain and 1.23 V for REFIN. VGAIN can then be calculated to be 0.492 V or approximately 0.5 V. Power-Down Control PASS TRANSISTOR LDOB LDOC 2.7V 18pF REFOUT 1.23V Figure 25. Configuring the Low Dropout Regulator It is possible to bypass the low dropout regulator on the AD6122 and use an external regulator instead. In order to bypass the integrated low dropout regulator, connect pins LDOE, LDOB and LDOC together and then connect them all to the 2.7 V external regulator voltage. This configuration is shown in Figure 26. Even when the low dropout regulator is bypassed, the 1.23 V reference voltage at pin REFOUT is still present. The AD6122 can be operated with the IF amplifiers and quadrature modulator both powered up, both powered down or with the IF amplifiers powered up and the modulator powered down. The AD6122 cannot operate with only the modulator powered –12– REV. B AD6122 The attenuator is discussed in the next section entitled Measuring Adjacent Channel Protection Ratio (ACPR). AD6122 In order to confirm whether the roofing filter has been correctly designed, sweep the LO frequency and view the output of the IF amplifier on a spectrum analyzer. The signal should peak at the IF frequency if the inductor value is correct. The Q of the filter should be low enough so that variations in the parasitic capacitances should be negligible. LDOE FROM EXTERNAL VOLTAGE REGULATOR LDOB LDOC REFOUT 1.23V The value of inductor required will be a function of the IF frequency at which we are operating. The values of inductors used during characterization at Analog Devices are shown in Table II. Because the exact value will also be a function of printed circuit board layout, we will have to vary the value from those in Table II to those required for our board. Figure 26. Configuration for Bypassing the Low Dropout Regulator ROOFING FILTER Because the outputs of the AD6122 modulator are open collector, the parasitic capacitances seen at the output of the modulator, and inputs of the IF amplifiers, are high enough to create a low-pass filter, which may attenuate the IF signal. Consequently, the parasitic capacitance must be cancelled by using external inductors to form a parallel resonant circuit. The external inductors and the internal parasitic capacitors form what is known as the roofing filter, with the resonant frequency given by Equation 2. f0 = 1 (2) 2 π LCPAR where f0 is the IF frequency, in Hertz, CPAR is the total parasitic capacitance in Farads, and L is the value of external inductors, in henrys. The roofing filter may be composed of the pull-up inductors required on the open collector outputs of the I and Q modulator. This configuration is shown in Figure 27. The 10 nF capacitors are used for ac coupling. AD6122 MODOPP 2CPAR L/2 2CPAR L/2 MODOPN VCC 10nF PARALLEL RESONANT CIRCUIT 10nF IFINN IFINP 10nF ATTENUATOR Figure 27. Roofing Filter Configuration REV. B Table II. Roofing Filter Inductor Values IF Frequency (MHz) Value of Roofing Filter Inductor (nH) 50–125 126–200 201–275 276–350 470 150 68 27 It should be noted that the roofing filter is only required when cascading the output from the I/Q modulator to the input of the IF amplifiers. If we are driving into the IF amplifiers directly, no roofing filter is required, however, pull-up inductors are required in order to set the dc voltage of the open collector modulator outputs. MEASURING ADJACENT CHANNEL POWER RATIO (ACPR) At maximum IF gain and specified input conditions (500 mV p-p baseband inputs), the output of the I/Q modulator is 11 dB greater than the P1 dB (one dB compression point) of the IF amplifiers. This configuration maximizes the ratio of signal to LO feedthrough and also maximizes the signal to noise ratio. Once these ratios are maximized, we can attenuate the noise, signal and LO feedthrough without affecting the ratios. Therefore, attenuation is required between the I/Q modulator and the IF amplifiers. In order to determine exactly how much attenuation is required, we must recognize that ACPR is a function of the attenuation from the modulator outputs to the IF amplifier inputs. As a result, in order to determine how much attenuation is required, we must first know how good an ACPR performance is desired. If too much attenuation is applied, the ACPR will be very good, but, the IF amplifier’s output power level will be low, possibly resulting in poor signal to noise ratio and possibly requiring additional amplification external to the AD6122. An appropriate method that can be used to provide the correct amount of attenuation between the modulator outputs and the IF amplifier inputs is a simple differential voltage divider. The topology and its design equations are shown in Figure 28 and Equations 3 and 4. The input impedance of the IF amplifiers is typically 1 kΩ. As a result, if we design resistor R2 to be much less than 1 kΩ, we can neglect the effects of the IF amplifier’s input impedance on the attenuator. –13– AD6122 This circuit is very sensitive to parasitic capacitances. As a result, extra care should be taken to ensure minimum and equal printed circuit board transmission lines. We should also try to keep R2 small in order to minimize the effects of printed circuit board parasitic capacitance on loading the output of the pad. AD6122 MODOPP R1 MODOPN R1 IFINP R2 ZIN In conclusion, we have to develop a system-level ACPR budget for our radio, and from that budget determine how much ACPR performance we desire from the AD6122. We then need to implement the appropriate attenuation network to get that ACPR performance. RSHUNT >>R2 IFINN Figure 28. Pad Topology LEVEL DIAGRAM 1 1 R L = 20 log 1 1 + R1 R2 / 2 (3) Z IN = 2R1+ R2 (4) where L is the transducer loss (or loss through the pad) in dB and ZIN is the desired input resistance in ohms. Using these equations, we can design the attenuator circuit to provide whatever amount of attenuation we require. Figure 29 is provided to better understand the different voltage levels you can expect to see at different points of the AD6122. It represents the voltage and power levels expected for a maximum input condition of 500 mV p-p at the I and Q modulator and maximum gain in the IF amplifiers. When trying to make these measurements, a high impedance (10 MΩ) active FET probe (for example, the Tek P6204, from Tektronix) should be used to minimize the effects of loading the circuit with the probe. In order to produce these results, the attenuator is designed to have a 1 kΩ input impedance and the output of the IF amplifiers are loaded with 1 kΩ. The roofing filter is designed to resonate the parasitic capacitance at the IF frequency. MODULATORS I 500mV p-p DIFFERENTIAL LO ⴜ2 100mV p-p DIFFERENTIAL –21dBm (REFERRED TO 1k⍀) 252.1mV p-p DIFFERENTIAL –41dBm (REFERRED TO 1k⍀) 25.21mV p-p IF AMPLIFIERS DIFFERENTIAL MODOP TRANSMIT OUTPUT IFIN VCC Q 500mV p-p DIFFERENTIAL –7dBm (REFERRED TO 1k⍀) 1.263V p-p DIFFERENTIAL VGAIN = 2.5V GAIN = +34dB 1k⍀ 20dB ATTENUATOR ZOUT = 1k⍀ ZIN = 1k⍀ Figure 29. Level Diagram –14– REV. B AD6122 INPUT INTERFACES The AD6122 interfaces to CDMA baseband converters providing either IF or baseband outputs. The baseband input is provided by direct connection of the baseband converter’s baseband output to the baseband input of the AD6122 (Figure 30). The IF amplifier’s gain control is provided by connection of the transmit AGC DAC’s output on the baseband converter, through a low-pass filter to the VGAIN pin on the AD6122. PD1 PD2 VCC VGAIN TEMPERATURE COMPENSATION GAIN CONTROL SCALE FACTOR TX AGC DAC REFIN EXT REF IN LDOE LDOB LDOC REFOUT LOW DROPOUT REGULATOR IFVCC IFGND LDOGND IIPP DGND I OUTPUT Q LOIPP LOIPN IIPN I OUTPUT MODCMREF ⴜ2 I VCM REF IN QIPN Q OUTPUT Q OUTPUT QIPP DVCC MODOPP MODOPN AD6122 VCC VCC CDMA BASEBAND IC IFINP TXOPP TXOPN IFINN TXVCC IFGND Figure 30. Typical Connections to Baseband IC Using I and Q Inputs with SSOP Package REV. B –15– AD6122 The IF output port impedance match used during characterization at Analog Devices is as follows: AD6122 Evaluation Board The AD6122 Evaluation Board consists of an AD6122, I/O connectors, a 20-pin dual header, 2-pin headers and four AD830 high speed video difference amplifiers. It allows the user to evaluate the AD6122’s IF amplifier and modulator together or separately. Because the AD6122 may be used at any IF from 50 MHz to 350 MHz, pads are provided on the LOIPP input, TXOP output, MODOP output and IFIP inputs to allow the user to add matching networks. The board is configured for an IF frequency of 130.38 MHz when shipped. There is no difference between the configuration of the boards with the SSOP or LPCC package. AD6122 AD6122 1:8 383⍀ IFINP 511⍀ SIGNAL GENERATOR IFINN 383⍀ 1k⍀ Figure 31. IF Input Port Impedance Match Used During Characterization at ADI This is a broadband lossy match used for characterization over the 50 MHz to 350 MHz frequency range. All dBm references in the characterization data collected using this match are referenced to 1 kΩ. Note that the 1:8 ratio in Figure 31 is an impedance ratio and not a voltage ratio. 50⍀ 453⍀ SPECTRUM ANALYZER 1k⍀ Figure 32. IF Output Port Impedance Match Used During Characterization at ADI This is a broadband lossy output match for the 50 MHz to 350 MHz frequency range. The 4:1 ratio in Figure 32 is an impedance ratio and not a voltage ratio. In order to test the power-down modes of the AD6122, locate the two pin headers on the AD6122 evaluation boards labeled PD1 and PD2. By open-circuiting the pins labeled PD1, the IF amplifiers power down. By open-circuiting the pins labeled PD2, the modulator powers down. Note that the IF amplifiers and modulator are powered down unless the pins on the two pin headers, PD1 and PD2, are short circuited. 50⍀ 4:1 205⍀ TXOPN The AD830s are used to provide single-ended to differential conversion and the appropriate phase shift for the I and Q data input pins. As a result, a single-ended signal generator can be used to generate these signals. The IF input port impedance match used during characterization of the AD6122 at Analog Devices is as follows: 453⍀ TXOPP As shipped, the board is configured as follows: 1. J1 is open and J2 is shorted. This enables the LDO regulator. The external PNP transistor should remain in place even when the regulator is bypassed (the Pin LDOB is pulled up by the transistor). 2. X11, X25, X18 and X26 are shorted and X12, X14, X19 and X21 are opened in order to connect the output of the modulator to the input of the IF amplifiers. 3. L4 and L5, the roofing filter components are optimized for an IF frequency of 130.38 MHz. 4. R14, R15 and R16 set the attenuation between the modulator outputs and the IF amplifier inputs to 20 dB. 5. PD1 and PD2 are pulled low by the jumpers on the two pin headers. To power down the chip, set PD1 and PD2 high by removing the jumpers. In order to look at the modulator and IF amplifiers separately, disconnect the output of the modulator from the input of the IF amplifiers. This is accomplished by short circuiting X12, X14, X19 and X20 and open circuiting X11, X18, X25 and X26. –16– REV. B AD6122 Table III describes the high frequency signal connectors on the AD6122 customer sample boards. Table IV lists the connections for the 20-pin power-supply connector. Table III. Evaluation Board SMA Signal Connector Description Connector Description I CH I Modulator Input. 250 mV p-p into 50 Ω termination, dc coupled. The level shifting and phase splitting is done on board by the AD830 amplifiers. Table IV. 20-Pin Power Supply Connection Information Pin # Function 1 VPOS for AD6122; 2.9 V to 4.2 V using regulator; 2.7 V to 4.2 V bypassing regulator. VPOS for AD6122; 2.9 V to 4.2 V using regulator; 2.7 V to 3.6 V bypassing regulator. Ground. Ground. Ground. Regulated Output or Input Voltage; Connects to Pin 5 on AD6122. Ground. Ground. Ground. Ground. Ground. PD1; Power-Down 1 Input. Ground. 1.23 V Reference Voltage from AD6122. Ground. VGAIN; Gain Control Voltage Input. –15 V Supply for AD830 Differential Amplifier. +15 V Supply for AD830 Differential Amplifier. MODCMREF; common-mode reference output for baseband converter common-mode reference input. PD2; Power-Down 2 Input. 2 3 4 5 6 Q CH Q Modulator Input. 250 mV p-p into 50 Ω termination, ac coupled. The level shifting and phase splitting is done on board by the AD830 amplifiers. MODOP Modulator Output. The differential-to-single ended conversion is performed by a balun on the board. Impedance matched to 50 Ω for 130.38 MHz IF frequency. IFIP IF Amplifier Input. Single-ended-to-differential conversion performed by a balun on board. Impedance matched to 50 Ω for 130.38 MHz IF frequency. TXOP IF Amplifier Output. Differential-to-singleended conversion performed by a balun on board. Impedance matched to 50 Ω for 130.38 MHz IF frequency. LOIPP Local oscillator positive input at 2 × IF frequency. 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A schematic diagram of the evaluation board is on the next two pages. REV. B –17– AD6122 AD6122 PD1 PD2 J2 0⍀ VPOS 2.9V – 4.2V R12 0⍀ PD1 VGAIN PD2 REFIN C28 10nF VGAIN FMMT4403CT-ND LDOE REFOUT REFOUT C29 10nF Q1 J1 VREG OUT C23 18pF LDOB IFVCC LDOC IFGND IFVCC LDOGND IIPP IIPP DGND IIPN IIPN LOIPP MODCMREF LOIPN QIPN QIPN DVCC QIPP QIPP VREG OUT VREG OUT C1 10nF X2 0⍀ LOIPP X1 X3 X5 100nH TXOP X4 C24 0.1F 1:8 X6 3pF X8 C3 0⍀ 10nF X7 T1 VCC C2 10nF DVCC L2 220nH TXOPP MODCMREF X10 C4 0⍀ 10nF VCC TXVCC L3 220nH C25 10nF C26 10nF L4 180nH L5 180nH 8:1 MODOPP C8 10nF X9 TXOPN C27 10nF MODOPN TXVCC IFINP IFGND IFINN C10 10nF X11 0⍀ X13 X17 X14 L6 MODOP X15 4pF T2 X25 0⍀ C30 C11 10nF R14 = 442⍀ R15 = 100⍀ R16 = 442⍀ C9 10nF X12 X16 100nH R13 R14 R15 X18 0⍀ R16 X19 X26 0⍀ 8:1 X23 27nH IFIP X22 56nH X20 X24 X21 T3 Figure 33. Schematic Diagram of the Evaluation Board –18– REV. B AD6122 C15 0.1F C19 0.1F +15V +15V 8 1 2 MODCMREF SOIC PACKAGE U2 V–1 A=1 3 4 V–1 5 7 R7 50⍀ V–1 4 AD830 5 +15V A=1 3 V–1 8 1 U3 V–1 7 R8 50⍀ 2 TO IIPN U5 V–1 A=1 3 MODCMREF V–1 4 AD830 5 AD830 –15V C22 0.1F C18 0.1F TO DVCC TO IFVCC C6 18pF C5 18pF C7 18pF R1 10⍀ C13 0.01F P1 VREG OUT R2 10⍀ C12 0.01F R3 10⍀ C14 0.01F VPOS P2 1 2 3 4 5 6 L1 470nH 7 8 9 10 11 12 13 14 REFOUT R4 10k⍀ R5 10k⍀ PD1 15 16 VGAIN –15V 17 18 +15V MODCMREF 19 20 PD2 Figure 34. Schematic Diagram of the Evaluation Board –19– FROM VPOS 2.9V–4.2V VREG OUT NOTES: 1. TO USE THE LDO REGULATOR, SHORT J2 AND OPEN J1. 2. TO BYPASS THE REGULATOR, SHORT J1 AND OPEN J2 3. TO CONNECT THE OUTPUT OF THE MODULATOR TO THE INPUT OF THE IF AMP, SHORT J5 AND J6. TO TEST THE MODULATOR AND THE IF AMP SEPARATELY, OPEN J5 AND J6. 4. INDICATES A 50⍀ TRACE. REV. B TO QIPN 5 –15V TO TXVCC R11 50⍀ C21 0.1F 8 1 4 7 TO QIPP C20 0.1F R9 50⍀ +15V MODCMREF R10 50⍀ AD830 C17 0.1F 2 7 –15V QCH C16 0.1F R6 50⍀ A=1 3 MODCMREF –15V ICH U4 V–1 2 TO IIPP SOIC PACKAGE 8 1 PD1 PD2 AD6122 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C00946a–.5–6/00 (rev. B) 28-Lead SSOP (RS-28) 28 15 1 14 0.212 (5.38) 0.205 (5.21) 0.311 (7.9) 0.301 (7.64) 0.407 (10.34) 0.397 (10.08) 0.07 (1.79) 0.066 (1.67) 0.078 (1.98) PIN 1 0.068 (1.73) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 0.03 (0.762) 0.022 (0.558) 8° 0.015 (0.38) SEATING 0.009 (0.229) 0° 0.010 (0.25) PLANE 0.005 (0.127) 32-Leadless Chip Scale Package (LPCC) (CP-32) 0.205 (5.20) 0.197 (5.00) SQ 0.189 (4.80) 0.128 (3.25) 0.106 (2.70) SQ 0.049 (1.25) 25 32 1 24 0.015 (0.38) 0.012 (0.30) 0.009 (0.23) BOTTOM VIEW 17 PIN 1 INDICATOR 8 9 16 0.138 (3.50) BSC 0.018 (0.45) 0.016 (0.40) 0.014 (0.35) 0.039 (1.00) 0.035 (0.90) 0.031 (0.80) 0.010 (0.25) REF 0.020 (0.50) BSC 0.002 (0.05) 0.001 (0.02) 0.000 (0.00) PRINTED IN U.S.A. CONTROLLING DIMENSIONS ARE IN MILLIMETERS DIMENSIONS MEET JEDEC MO-220-VHHD-2 –20– REV. B