AD AD8273

Dual-Channel,
Audio Difference Amplifier
AD8273
FEATURES
FUNCTIONAL BLOCK DIAGRAM
+VS
Two gain settings
Gain of ½ (−6 dB)
Gain of 2 (+6 dB)
0.05% maximum gain error
10 ppm maximum gain drift
Excellent ac specifications
20 V/μs minimum slew rate
800 ns to 0.01% settling time
Low distortion: 0.004%, 20 Hz to 20 kHz
High accuracy dc performance
77 dB minimum CMRR
700 μV maximum offset voltage
14-lead SOIC package
Supply current: 2.5 mA maximum per channel
Supply range: ±2.5 V to ±18 V
11
2
12kΩ
6kΩ
12
13
3
6
12kΩ
6kΩ
12kΩ
6kΩ
12kΩ
6kΩ
14
10
5
4
–VS
8
06981-001
9
Figure 1.
APPLICATIONS
High performance audio
Instrumentation amplifier building blocks
Level translators
Automatic test equipment
Sin/Cos encoders
GENERAL DESCRIPTION
The AD8273 is a low distortion, dual-channel amplifier with
internal gain setting resistors. With no external components,
it can be configured as a high performance difference amplifier
(G = ½ or 2), inverting amplifier (G = ½ or 2), or noninverting
amplifier (G = 1½ or 3).
Table 1. Difference Amplifiers by Category
Low
Distortion
AD8270
AD8273
AMP03
High
Voltage
AD628
AD629
Single-Supply
Unidirectional
AD8202
AD8203
Single-Supply
Bidirectional
AD8205
AD8206
AD8216
The AD8273 operates on both single and dual supplies and only
requires 2.5 mA maximum supply current for each amplifier.
It is specified over the industrial temperature range of −40°C to
+85°C and is fully RoHS compliant.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD8273
TABLE OF CONTENTS
Features .............................................................................................. 1
Pin Configuration and Function Descriptions..............................5
Applications....................................................................................... 1
Typical Performance Characteristics ..............................................6
General Description ......................................................................... 1
Theory of Operation ...................................................................... 11
Functional Block Diagram .............................................................. 1
Configurations............................................................................ 11
Revision History ............................................................................... 2
Power Supplies ............................................................................ 11
Specifications..................................................................................... 3
Outline Dimensions ....................................................................... 13
Absolute Maximum Ratings............................................................ 4
Ordering Guide .......................................................................... 13
Maximum Power Dissipation ..................................................... 4
ESD Caution.................................................................................. 4
REVISION HISTORY
1/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
AD8273
SPECIFICATIONS
VS = ±15 V, VREF = 0 V, TA = 25°C, G = ½, RL = 2 kΩ, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Bandwidth
Slew Rate
Settling Time to 0.1%
Settling Time to 0.01%
Channel Separation
NOISE/DISTORTION 1
THD + Noise
Noise Floor, RTO 2
Output Voltage Noise (Referred to Output)
GAIN
Gain Error
Gain Drift
Gain Nonlinearity
INPUT CHARACTERISTICS
Offset 3
vs. Temperature
vs. Power Supply
Common-Mode Rejection Ratio
Input Voltage Range 4
Impedance 5
Differential
Common Mode 6
OUTPUT CHARACTERISTICS
Output Swing
Short-Circuit Current Limit
Capacitive Load Drive
Conditions
Min
Typ
Max
20
20
10 V step on output, CL = 100 pF
10 V step on output, CL = 100 pF
f = 1 kHz
670
750
130
f = 1 kHz, VOUT = 10 V p-p, 600 Ω load
20 kHz BW
f = 20 Hz to 20 kHz
f = 1 kHz
0.004
−106
3.5
26
−40°C to +85°C
VOUT = 10 V p-p, 600 Ω load
VOUT = 5 V p-p, 600 Ω load
2
200
50
Referred to output
−40°C to +85°C
VS = ±2.5 V to ±18 V
VCM = ±40 V, RS = 0 Ω, referred to input
100
3
2
86
77
−3VS + 4.5
VCM = 0 V
750
800
0.05
10
%
ppm/°C
ppm
ppm
700
μV
μV/°C
μV/V
dB
V
10
+3VS − 4.5
−VS + 1.5
kΩ
kΩ
+VS − 1.5
V
mA
mA
pF
pF
2.5
mA
+85
°C
100
60
200
1200
POWER SUPPLY
Supply Current (per Amplifier)
TEMPERATURE RANGE
Specified Performance
−40
1
MHz
V/μs
ns
ns
dB
%
dBu
μV rms
nV/√Hz
36
9
Sourcing
Sinking
G=½
G=2
Unit
Includes amplifier voltage and current noise, as well as noise of internal resistors.
dBu = 20 log (V rms /0.7746).
3
Includes input bias and offset current errors.
4
May also be limited by absolute maximum input voltage or by the output swing. See the Absolute Maximum Ratings section and Figure 9 through Figure 12 for
details.
5
Internal resistors are trimmed to be ratio matched but have ±20% absolute accuracy.
6
Common mode is calculated looking into both inputs. Common-mode impedance looking into only one input is 18 kΩ.
2
Rev. 0 | Page 3 of 16
AD8273
ABSOLUTE MAXIMUM RATINGS
MAXIMUM POWER DISSIPATION
Voltage at Any Input Pin
Differential Input Voltage
Current into Any Input Pin
Storage Temperature Range
Specified Temperature Range
Thermal Resistance
θJA
θJC
Package Glass Transition Temperature (TG)
Rating
±18 V
Observe
derating curve
40 V
40 V
3 mA
−65°C to +130°C
−40°C to +85°C
105°C/W
36°C/W
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The maximum safe power dissipation for the AD8273 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150°C, which is the glass transition temperature,
the plastic changes its properties. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the amplifiers. Exceeding a temperature of 150°C for an
extended period can result in a loss of functionality.
The AD8273 has built-in, short-circuit protection that limits the
output current to approximately 100 mA (see Figure 2 for more
information). While the short-circuit condition itself does not
damage the part, the heat generated by the condition can cause
the part to exceed its maximum junction temperature, with
corresponding negative effects on reliability.
2.0
TJ MAX = 150°C
θJA = 105°C/W
1.6
1.2
0.8
0.4
0
–50
–25
0
25
50
75
100
125
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
Rev. 0 | Page 4 of 16
06981-043
Parameter
Supply Voltage
Output Short-Circuit Current
MAXIMUM POWER DISSIPATION (W)
Table 3.
AD8273
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC 1
14
+6A
–12A 2
13
OUTA
12
–6A
+12A 3
AD8273
TOP VIEW
11 +VS
(Not to Scale)
+12B 5
10 –6B
–12B 6
9
OUTB
NC 7
8
+6B
NC = NO CONNECT
06981-020
–VS 4
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 7
2
3
4
5
6
8
9
10
11
12
13
14
Mnemonic
NC
−12A
+12A
−VS
+12B
−12B
+6B
OUTB
−6B
+VS
−6A
OUTA
+6A
Description
No Connect.
The 12 kΩ resistor connects to the negative terminal of Op Amp A.
The 12 kΩ resistor connects to the positive terminal of Op Amp A.
Negative Supply.
The 12 kΩ resistor connects to the positive terminal of Op Amp B.
The 12 kΩ resistor connects to the negative terminal of Op Amp B.
The 6 kΩ resistor connects to the positive terminal of Op Amp B.
Op Amp B Output.
The 6 kΩ resistor connects to the negative terminal of Op Amp B.
Positive Supply.
The 6 kΩ resistor connects to the negative terminal of Op Amp A.
Op Amp A Output.
The 6 kΩ resistor connects to the positive terminal of Op Amp A.
Rev. 0 | Page 5 of 16
AD8273
TYPICAL PERFORMANCE CHARACTERISTICS
VS = ±15 V, TA = 25°C, G = ½, difference amplifier configuration, unless otherwise noted.
500
N: 1641
MEAN: –9.5
SD: 228.4
100
400
300
SYSTEM OFFSET (µV)
HITS
80
60
40
200
100
0
–100
–200
–300
20
–250
0
250
REPRESENTATIVE SAMPLES
–500
–45 –30 –15 0
15 30 45
06981-036
–500
500
VOSO ±15V (µV/V)
Figure 4. Typical Distribution of System Offset Voltage,
G = ½, Referred to Output
100
GAIN ERROR (µV/V)
60
40
20
50
0
–50
–100
–150
–100
–50
0
50
100
150
CMRR ±15V (µV/V)
REPRESENTATIVE SAMPLES
–200
–45 –30 –15 0
15 30 45
06981-028
0
–150
60
75
90
06981-031
HITS
105 120
150
N: 1649
MEAN: –0.59
SD: 37.3
80
105 120
TEMPERATURE (°C)
Figure 5. Typical Distribution of CMRR, G = ½, Referred to Input
Figure 8. Gain Error vs. Temperature, Normalized at 25°C
50
70
G=½
0, +40
60
INPUT COMMON-MODE VOLTAGE (V)
50
40
30
20
10
0
–10
–20
–30
–40
–50
–60
40
30
–13.5, +26.5
+13.5, +26.5
–13.5, –26.5
+13.5, –26.5
20
10
0
–10
–20
–30
–40
0, –40
REPRESENTATIVE SAMPLES
–80
–45 –30 –15
0
15
30
45
60
75
90
105 120
TEMPERATURE (°C)
–50
–15
06981-029
CMRR (µV/V)
90
Figure 7. System Offset vs. Temperature, Normalized at 25°C,
Referred to Output
100
–70
75
Figure 6. CMRR vs. Temperature, Normalized at 25°C
–10
–5
0
5
OUTPUT VOLTAGE (V)
10
15
Figure 9. Input Common-Mode Voltage vs. Output Voltage,
Gain = ½, ±15 V Supplies
Rev. 0 | Page 6 of 16
06981-041
120
60
TEMPERATURE (°C)
06981-030
–400
0
AD8273
POSITIVE PSRR
9
POWER SUPPLY REJECTION (dB)
±5V SUPPLIES
12
+3.5, +7
6
–1, +4
3
+1, +2
±2.5V
SUPPLIES
0
–3
–1, –2
+1, –4
–6
–9
140
G=½
–3.5, +14
–3.5,–7
–12
–15
–18
–4
06981-003
INPUT COMMON-MODE VOLTAGE (V)
15
+3.5, –14
–3
–2
–1
0
1
2
3
120
100
80
60
40
20
0
4
NEGATIVE PSRR
1
10
100
OUTPUT VOLTAGE (V)
10k
100k
Figure 13. Power Supply Rejection vs. Frequency, G = ½, Referred to Output
50
32
G=2
±15V SUPPLY
–13.5, +36.25
30
MAXIMUM OUTPUT VOLTAGE (V p-p)
40
+13.5, +36.25
20
10
0
–10
–20
–30
+13.5, –36.25
–13.5, –36.25
–40
28
24
20
16
12
8
±5V SUPPLY
4
06981-006
0, +40
0, –40
–10
–5
0
5
OUTPUT VOLTAGE (V)
10
15
0
100
06981-042
1M
10M
10
G=2
–3.5, +6.125
G=2
±5V SUPPLIES
4
5
+3.5, +4.375
–1, +1.175
0
+1, +1.25
GAIN (dB)
2
±2.5V
SUPPLIES
0
–1, –1.25
–2
+1, –1.175
G=½
–5
–10
–3.5, –4.375
06981-005
–15
–6
–8
–4
100k
Figure 14. Maximum Output Voltage vs. Frequency
8
–4
10k
FREQUENCY (Hz)
Figure 11. Input Common-Mode Voltage vs. Output Voltage,
Gain = 2, ±15 V Supplies
6
1k
+3.5, –6.125
–3
–2
–1
0
1
2
3
–20
100
4
06981-007
–50
–15
INPUT COMMON-MODE VOLTAGE (V)
1M
FREQUENCY (Hz)
Figure 10. Input Common-Mode Voltage vs. Output Voltage,
Gain = ½, ±5 V and ±2.5 V Supplies
INPUT COMMON-MODE VOLTAGE (V)
1k
06981-021
18
1k
10k
100k
1M
FREQUENCY(Hz)
OUTPUT VOLTAGE (V)
Figure 15. Gain vs. Frequency
Figure 12. Input Common-Mode Voltage vs. Output Voltage,
Gain = 2, ±5 V and ±2.5 V Supplies
Rev. 0 | Page 7 of 16
10M
100M
AD8273
+VS
–40°C
+25°C
+VS – 3
GAIN = ½
80
60
+125°C
+VS – 6
–VS + 6
+125°C
+85°C
+25°C
–VS + 3
40
100
1k
10k
100k
1M
FREQUENCY (Hz)
–VS
20
40
60
80
100
Figure 19. Output Voltage vs. IOUT
ISHORT+
100
–40°C
0
CURRENT (mA)
Figure 16. Common-Mode Rejection vs. Frequency, Referred to Input
120
+85°C
CLOAD = 100pF
80
40
20
50mV/DIV
CURRENT (mA)
60
0
–20
–40
ISHORT–
–60
NO LOAD
600Ω
2kΩ
–120
–40
–20
0
20
40
60
80
100
120
1µs/DIV
06981-024
06981-008
–80
–100
TEMPERATURE (°C)
Figure 20. Small Signal Step Response, Gain = 2
Figure 17. Short-Circuit Current vs. Temperature
+85°C
+125°C
+VS – 2
–40°C
CLOAD = 100pF
+25°C
50mV/DIV
+VS – 4
0
–VS + 2
NO LOAD
+125°C
600Ω
2kΩ
–VS
–40°C +25°C
+85°C
200
1k
RLOAD (Ω)
10k
1µs/DIV
Figure 18. Output Voltage Swing vs. RLOAD, VS = ±15 V
Figure 21. Small Signal Step Response, Gain = ½
Rev. 0 | Page 8 of 16
06981-025
–VS + 4
06981-009
OUTPUT VOLTAGE SWING (V)
+VS
06981-023
OUTPUT VOLTAGE (V)
GAIN = 2
100
06981-022
COMMON-MODE REJECTION (dB)
120
AD8273
100
90
80
2.5V
5V
50mV/DIV
OVERSHOOT (%)
70
15V
60
18V
50
40
30
20
1µs/DIV
0
0
20
40
60
80
100
120
140
160
180
200
CAPACITANCE (pF)
Figure 22. Small Signal Pulse Response with 500 pF Capacitor Load, Gain = 2
06981-038
06981-026
10
Figure 25. Small Signal Overshoot vs. Capacitive Load,
G = ½, 600 Ω in Parallel with Capacitive Load
100
90
80
50mV/DIV
OVERSHOOT (%)
70
2.5V
60
15V
5V
50
18V
40
30
20
1µs/DIV
0
0
200
400
600
800
1000
1200
CAPACITANCE (pF)
Figure 23. Small Signal Pulse Response for 100 pF Capacitive Load,
Gain = ½
Figure 26. Small Signal Overshoot vs. Capacitive Load,
G = 2, No Resistive Load
100
100
80
80
5V
70
70
OVERSHOOT (%)
15V
60
18V
50
40
40
20
20
10
10
20
40
60
80
100
120
140
160
180
200
CAPACITANCE (pF)
5V 15V
50
30
0
2.5V
60
30
0
06981-037
OVERSHOOT (%)
90
2.5V
18V
0
200
400
600
800
1000
CAPACITANCE (pF)
Figure 24. Small Signal Overshoot vs. Capacitive Load, G = ½,
No Resistive Load
Figure 27. Small Signal Overshoot vs. Capacitive Load,
G = 2, 600 Ω in Parallel with Capacitive Load
Rev. 0 | Page 9 of 16
1200
06981-040
90
0
06981-039
06981-027
10
AD8273
0.1
2V/DIV
THD + N (%)
0.01
GAIN = ½
GAIN = 2
1µs/DIV
0.0001
20
200
2k
20k
FREQUENCY (Hz)
Figure 28. Large Signal Pulse Response Gain = ½
06981-011
06981-032
0.001
Figure 31. THD+N vs. Frequency, VOUT = 10 V p-p
06981-033
2V/DIV
VOLTAGE NOISE DENSITY (nV/√Hz)
10000
GAIN = 2
100
GAIN = ½
10
1
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 29. Large Signal Pulse Response, Gain = 2
Figure 32. Voltage Noise Density vs. Frequency, Referred to Output
40
35
G=2
+SR
1µV/DIV
25
20
–SR
G=½
15
5
0
–40
–20
0
20
40
60
80
100
120
1s/DIV
TEMPERATURE (°C)
Figure 30.Slew Rate vs. Temperature
Figure 33. 0.1 Hz to 10 Hz Voltage Noise, RTO
Rev. 0 | Page 10 of 16
06981–035
10
06981-010
SLEW RATE (V/µS)
30
06981-034
1µs/DIV
1000
AD8273
THEORY OF OPERATION
The resistors on the AD8273 are laser trimmed and tightly
matched. Specifications that depend on the resistor matching,
such as gain drift, common-mode rejection, and gain accuracy,
are better than can be achieved with standard discrete resistors.
The positive and negative input terminals of the AD8273
op amp are not pinned out intentionally. Keeping these nodes
internal means their capacitance is considerably lower than it
would be in discrete designs. Lower capacitance at these nodes
means better loop stability and improved common-mode
rejection vs. frequency.
–IN1
12
6kΩ
12kΩ
2
13
+IN1
–IN2
14
6kΩ
12kΩ
3
10
6kΩ
12kΩ
6
9
+IN2
8
6kΩ
12kΩ
OUT1
OUT2
5
06981-016
The AD8273 has two channels, each consisting of a high
precision, low distortion op amp and four trimmed resistors.
Although such a circuit can be built discretely, placing the
resistors on the chip offers advantages to board designers that
include better dc specifications, better ac specification, and
lower production costs.
VOUT = 2 (VIN+ − VIN−)
Figure 35. Difference Amplifier, G = 2
IN1
The internal resistors of the AD8273 lower production cost.
One part rather than several is placed on the board, which
improves both board build time and reliability.
2 12kΩ
14
6kΩ
12
13
6kΩ
OUT1
3 12kΩ
CONFIGURATIONS
IN2
6 12kΩ
8
6kΩ
10
9
6kΩ
OUT2
5 12kΩ
A stable dc voltage should be used to power the AD8273. Noise
on the supply pins can adversely affect performance. A bypass
capacitor of 0.1 μF should be placed between each supply pin
and ground, as close to each pin as possible. A tantalum
capacitor of 10 μF should also be used between each supply and
ground. It can be farther away from the AD8273 and typically
can be shared by other precision integrated circuits.
The AD8273 is specified at ±15 V, but it can be used with
unbalanced supplies as well, for example, −VS = 0 V, +VS = 20 V.
The difference between the two supplies must be kept below 36 V.
–IN1
2 12kΩ
6kΩ
13
VOUT = −½ VIN
Figure 36. Inverting Amplifier, G = ½
IN1
12
6kΩ
IN2
14
6kΩ
10
6kΩ
8
OUT1
12kΩ
2
13
3 12kΩ
5 12kΩ
12
06981-013
POWER SUPPLIES
12kΩ
OUT1
6
9
OUT2
6kΩ
VOUT = −2 VIN
–IN2
6kΩ
14
6 12kΩ
6kΩ
10
9
+IN2
5 12kΩ
VOUT = ½ (VIN+ − VIN−)
6kΩ
Figure 37. Inverting Amplifier, G = 2
OUT2
8
06981-012
+IN1
3 12kΩ
Figure 34. Difference Amplifier, G = ½
Rev. 0 | Page 11 of 16
06981-017
The AD8273 can be configured in several different ways; see
Figure 34 to Figure 41. Because these configurations rely on the
internal, matched resistors, these configurations have excellent
gain accuracy and gain drift.
AD8273
6kΩ
2 12kΩ
12
13
OUT1
3 12kΩ
6kΩ
14
6 12kΩ
6kΩ
10
9
IN1
6 12kΩ
IN2
8
VOUT = ½ VIN
6kΩ
12kΩ
9
6kΩ
OUT2
5 12kΩ
VOUT = 1½ VIN
2
13
10
Figure 40. Noninverting Amplifier, G = 1.5
Figure 38. Noninverting Amplifier, G = ½
12
6kΩ
OUT2
06981-015
IN2
6kΩ
OUT1
6kΩ
3 12kΩ
8
5 12kΩ
12
13
14
IN1
6kΩ
06981-014
2 12kΩ
12
6kΩ
12kΩ
OUT1
2
13
OUT1
3 12kΩ
14
6kΩ
12kΩ
3
10
6kΩ
12kΩ
6
9
IN1
14
6kΩ
10
6kΩ
OUT2
5 12kΩ
8
6kΩ
VOUT = 2 VIN
12kΩ
IN2
5
06981-019
IN2
8
VOUT = 3 VIN
Figure 39. Noninverting Amplifier, G = 2
12kΩ
6
9
OUT2
6kΩ
06981-018
IN1
Figure 41. Noninverting Amplifier, G = 3
Rev. 0 | Page 12 of 16
AD8273
OUTLINE DIMENSIONS
8.75 (0.3445)
8.55 (0.3366)
8
14
1
7
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
060606-A
4.00 (0.1575)
3.80 (0.1496)
Figure 42. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-14)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
AD8273ARZ 1
AD8273ARZ-R71
AD8273ARZ-RL1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
14-Lead SOIC_N
14-Lead SOIC_N, 7" Tape and Reel
14-Lead SOIC_N, 13" Tape and Reel
Z = RoHS Compliant Part.
Rev. 0 | Page 13 of 16
Package Option
R-14
R-14
R-14
AD8273
NOTES
Rev. 0 | Page 14 of 16
AD8273
NOTES
Rev. 0 | Page 15 of 16
AD8273
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06981-0-1/08(0)
Rev. 0 | Page 16 of 16