ETC AD532JD/+

a
Y2
+VS
FLEXIBILITY OF OPERATION
The AD532 multiplies in four quadrants with a transfer function of (X1 – X2)(Y1 – Y2)/10 V, divides in two quadrants with
a 10 V Z/(X1 – X2) transfer function, and square roots in one
quadrant with a transfer function of ±√ 10 V Z. In addition to
these basic functions, the differential X and Y inputs provide
significant operating flexibility both for algebraic computation and
transducer instrumentation applications. Transfer functions,
such as XY/10 V, (X2 – Y2)/10 V, ±X2/10 V, and 10 V Z/(X1 – X2),
are easily attained and are extremely useful in many modulation
and function generation applications, as well as in trigonometric
calculations for airborne navigation and guidance applications,
where the monolithic construction and small size of the AD532
offer considerable system advantages. In addition, the high
CMRR (75 dB) of the differential inputs makes the AD532
especially well qualified for instrumentation applications, as it
can provide an output signal that is the product of two transducergenerated input signals.
GND
AD532
–VS 3
AD532
12 Y2
TOP VIEW 11 VOS
(Not to Scale) 10
NC 5
GND
X2
NC 6
9
X2
X1 7
8
NC
X1
OUT
13 Y1
NC 4
TOP VIEW
(Not to Scale)
Z
–VS
Z
NC
+VS
3
2
1
20 19
Y1
OUT
NC = NO CONNECT
–VS 4
18 Y2
NC 5
17 NC
NC 7
AD532
TOP VIEW
(Not to Scale)
16 VOS
15 NC
14 GND
NC 8
X2
10 11 12 13
NC
9
NC
The AD532 is the first pretrimmed single chip monolithic multiplier/divider. It guarantees a maximum multiplying error of
± 1.0% and a ± 10 V output voltage without the need for any
external trimming resistors or output op amp. Because the
AD532 is internally trimmed, its simplicity of use provides design
engineers with an attractive alternative to modular multipliers,
and its monolithic construction provides significant advantages
in size, reliability and economy. Further, the AD532 can be used
as a direct replacement for other IC multipliers that require
external trim networks.
14 +VS
OUT 2
NC 6
PRODUCT DESCRIPTION
Z 1
VOS
Y1
X1
APPLICATIONS
Multiplication, Division, Squaring, Square Rooting
Algebraic Computation
Power Measurements
Instrumentation Applications
Available in Chip Form
PIN CONFIGURATIONS
NC
FEATURES
Pretrimmed to 1.0% (AD532K)
No External Components Required
Guaranteed 1.0% max 4-Quadrant Error (AD532K)
Diff Inputs for (X1 – X2) (Y1 – Y2)/10 V Transfer Function
Monolithic Construction, Low Cost
Internally Trimmed
Integrated Circuit Multiplier
AD532
NC = NO CONNECT
GUARANTEED PERFORMANCE OVER TEMPERATURE
The AD532J and AD532K are specified for maximum multiplying
errors of ± 2% and ± 1% of full scale, respectively at 25°C, and
are rated for operation from 0°C to 70°C. The AD532S has a
maximum multiplying error of ± 1% of full scale at 25°C; it is
also 100% tested to guarantee a maximum error of ± 4% at the
extended operating temperature limits of –55°C and +125°C. All
devices are available in either the hermetically-sealed TO-100
metal can, TO-116 ceramic DIP or LCC packages. J, K, and
S grade chips are also available.
ADVANTAGES OF ON-THE-CHIP TRIMMING OF THE
MONOLITHIC AD532
1. True ratiometric trim for improved power supply rejection.
2. Reduced power requirements since no networks across supplies are required.
3. More reliable since standard monolithic assembly techniques
can be used rather than more complex hybrid approaches.
4. High impedance X and Y inputs with negligible circuit loading.
5. Differential X and Y inputs for noise rejection and additional
computational flexibility.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD532–SPECIFICATIONS
(@ 25C, VS = 15 V, R ≥ 2 k VOS grounded, unless otherwise noted.)
Model
AD532J
Typ
Min
Max
Min
AD532K
Typ
Max
Min
AD532S
Typ
Max
Unit
MULTIPLIER PERFORMANCE
Transfer Function
Total Error (–10 V ≤ X, Y ≤ +10 V)
TA = Min to Max
Total Error vs. Temperature
Supply Rejection (± 15 V ± 10%)
Nonlinearity, X (X = 20 V p-p, Y = 10 V)
Nonlinearity, Y (Y = 20 V p-p, X = 10 V)
Feedthrough, X (Y Nulled,
X = 20 V p-p 50 Hz)
Feedthrough, Y (X Nulled,
Y = 20 V p-p 50 Hz)
Feedthrough vs. Temperature
Feedthrough vs. Power Supply
DYNAMICS
Small Signal BW (VOUT = 0.1 rms)
1% Amplitude Error
Slew Rate (VOUT 20 p-p)
Settling Time (to 2%, ∆VOUT = 20 V)
NOISE
Wideband Noise f = 5 Hz to 10 kHz
Wideband Noise f = 5 Hz to 5 MHz
OUTPUT
Output Voltage Swing
Output Impedance (f ≤ 1 kHz)
Output Offset Voltage
Output Offset Voltage vs. Temperature
Output Offset Voltage vs. Supply
INPUT AMPLIFIERS (X, Y, and Z)
Signal Voltage Range (Diff. or CM
Operating Diff)
CMRR
Input Bias Current
X, Y Inputs
X, Y Inputs TMIN to TMAX
Z Input
Z Input TMIN to TMAX
Offset Current
Differential Resistance
DIVIDER PERFORMANCE
Transfer Function (Xl > X2)
Total Error
(VX = –10 V, –10 V ≤ VZ ≤ +10 V)
(VX = –1 V, –10 V ≤ VZ ≤ +10 V)
SQUARE PERFORMANCE
(X1 – X 2 )(Y1 – Y 2 )
(X1 – X 2 )(Y1 – Y 2 )
(X1 – X 2 )(Y1 – Y 2 )
10 V
10 V
10 V
± 10
± 1.5
± 2.5
± 0.04
± 0.05
± 0.8
± 0.3
2.0
± 0.7
± 1.5
± 0.03
± 0.05
± 0.5
± 0.2
1.0
50
200
30
100
30
2.0
± 0.25
150
25
1.0
± 0.25
80
Total Error
SQUARE ROOTER PERFORMANCE
Transfer Function
Total Error (0 V ≤ VZ ≤ 10 V)
POWER SUPPLY SPECIFICATIONS
Supply Voltage
Rated Performance
Operating
Supply Current
Quiescent
PACKAGE OPTIONS
TO-116 (D-14)
TO-100 (H-10A)
LCC (E-20A)
1.0
4.0
0.04
%
%
%/°C
%/%
%
%
30
100
mV
25
1.0
± 0.25
80
mV
mV p-p/°C
mV/%
± 0.01
± 0.05
± 0.5
± 0.2
1
75
45
1
1
75
45
1
1
75
45
1
MHz
kHz
V/µs
µs
0.6
3.0
0.6
3.0
0.6
3.0
mV (rms)
mV (rms)
± 13
1
V
Ω
mV
mV/°C
mV/%
± 13
1
± 40
0.7
± 2.5
± 10
± 13
1
± 10
30
0.7
± 2.5
± 10
± 2.5
± 10
40
1.5
8
±5
± 25
± 0.1
10
10 V Z/(X1 – X2)
10 V Z/(X1 – X2)
±2
±4
±1
±3
4
1.5
8
±5
± 25
± 0.1
10
15
2
10 V
10 V
10 V
4
± 0.4
–√10 V Z
± 1.0
18
6
± 10
± 15
4
AD532JD
AD532JH
AD532KD
AD532KH
%
%
18
6
± 10
± 0.4
%
–√10 V Z
± 1.0
%
± 15
4
± 22
V
V
6
mA
AD532SD
AD532SH
AD532SE/883B
Specifications subject to change without notice.
THERMAL CHARACTERISTICS
Specifications shown in boldface are tested on all production units at final
electrical test. Results from those tests are used to calculate outgoing quality
levels. All min and max specifications are guaranteed, although only those shown
in boldface are tested on all production units.
H-10A: θJC = 25°C/W; θJA = 150°C/W
E-20A: θJC = 22°C/W; θJA = 85°C/W
D-14: θJC = 22°C/W; θJA = 85°C/W
–2–
µA
µA
µA
µA
µA
MΩ
2
(X1 – X 2 )
± 15
15
±1
±3
(X1 – X 2 )
–√10 V Z
± 1.5
4
10 V Z/(X1 – X2)
(X1 – X 2 )
± 10
V
dB
50
3
10
± 10
± 30
± 0.3
10
± 0.8
30
2.0
± 10
50
2
Transfer Function
± 0.5
REV. C
AD532
ORDERING GUIDE
CHIP DIMENSIONS AND BONDING DIAGRAM
Model
Temperature
Ranges
Package
Descriptions
Package
Options
AD532JD
AD532JD/+
AD532KD
AD532KD/+
AD532JH
AD532KH
AD532JCHIPS
AD532SD
AD532SD/883B
JM38510/13903BCA
AD532SE/883B
AD532SH
AD532SH/883B
JM38510/13903BIA
AD532SCHIPS
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
Header
Header
Chip
Side Brazed DIP
Side Brazed DIP
Side Brazed DIP
LCC
Header
Header
Header
Chip
D-14
D-14
D-14
D-14
H-10A
H-10A
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
0.107
(2.718)
VS
OUTPUT
Z
X1
0.062
(1.575)
D-14
D-14
D-14
E-20A
H-10A
H-10A
H-10A
VS
Y1
GND
X2
VOS
Y2
FUNCTIONAL DESCRIPTION
The functional block diagram for the AD532 is shown in Figure
1, and the complete schematic in Figure 2. In the multiplying
and squaring modes, Z is connected to the output to close the
feedback around the output op amp. (In the divide mode, it is
used as an input terminal.)
X1
VX
The X and Y inputs are fed to high impedance differential
amplifiers featuring low distortion and good common-mode
rejection. The amplifier voltage offsets are actively laser trimmed
to zero during production. The product of the two inputs is
resolved in the multiplier cell using Gilbert’s linearized transconductance technique. The cell is laser trimmed to obtain
VOUT = (X1 – X2)(Y1 – Y2)/10 volts. The built-in op amp is used
to obtain low output impedance and make possible self-contained
operation. The residual output voltage offset can be zeroed at
VOS in critical applications . . . otherwise the VOS pin should
be grounded.
X2
R
R
Z
X
Y1
VY
OUTPUT
Y2
10R
VOUT =
(X1 – X2) (Y1 – Y2)
10V
(WITH Z TIED TO OUTPUT)
Figure 1. Functional Block Diagram
X2
VS
R6
R2
R8
R16
R23
R27
Z
C1
Q2
Q1
Q7 Q8
Q14 Q15
Q16 Q17
Y1
X1
Q25
R22
R9
R1
R33
Q21
R20
R34
Q3
VOS
Q10
Q9
R13
Q4
R21
Q22 Q26
R3
R31
R30
R28
COM
Q6
Q11
R29
Q12
Q24
R32
R19
R11
R4
Y2
R5
R12
Q19
Q13
R15
R24 R25
R26
VS CAN
R18
Figure 2. Schematic Diagram
REV. C
Q27
Q20
R14
Q28
OUTPUT
Q23
Q18
R10
Q5
VOS
R
–3–
AD532
AD532 PERFORMANCE CHARACTERISTICS
AC FEEDTHROUGH
Multiplication accuracy is defined in terms of total error at
25°C with the rated power supply. The value specified is in
percent of full scale and includes XIN and YIN nonlinearities,
feedback and scale factor error. To this must be added such
application-dependent error terms as power supply rejection,
common-mode rejection and temperature coefficients (although
worst case error over temperature is specified for the AD532S).
Total expected error is the rms sum of the individual components since they are uncorrelated.
AC feedthrough is a measure of the multiplier’s zero suppression.
With one input at zero, the multiplier output should be zero
regardless of the signal applied to the other input. Feedthrough
as a function of frequency for the AD532 is shown in Figure 5. It
is measured for the condition VX = 0, VY = 20 V (p-p) and VY = 0,
VX = 20 V (p-p) over the given frequency range. It consists
primarily of the second harmonic and is measured in millivolts
peak-to-peak.
1000
FEEDTHROUGH mV
Accuracy in the divide mode is only a little more complex. To
achieve division, the multiplier cell must be connected in the
feedback of the output op amp as shown in Figure 13. In this
configuration, the multiplier cell varies the closed loop gain of the
op amp in an inverse relationship to the denominator voltage.
Thus, as the denominator is reduced, output offset, bandwidth
and other multiplier cell errors are adversely affected. The divide
error and drift are then ⑀m × 10 V/X1 – X2) where ⑀m represents
multiplier full-scale error and drift, and (X1–X2) is the absolute
value of the denominator.
Y FEEDTHROUGH
100
X FEEDTHROUGH
10
NONLINEARITY
Nonlinearity is easily measured in percent harmonic distortion.
The curves of Figures 3 and 4 characterize output distortion as
a function of input signal level and frequency respectively, with
one input held at plus or minus 10 V dc. In Figure 4 the sine
wave amplitude is 20 V (p-p).
1k
10k
100k
FREQUENCY Hz
1M
10M
Figure 5. Feedthrough vs. Frequency
COMMON-MODE REJECTION
1.0
PERCENT DISTORTION
1
100
XIN
The AD532 features differential X and Y inputs to enhance its
flexibility as a computational multiplier/divider. Common-mode
rejection for both inputs as a function of frequency is shown in
Figure 6. It is measured with X1 = X2 = 20 V (p-p), (Y1 – Y2) =
10 V dc and Y1 = Y2 = 20 V (p-p), (X1 – X2) = 10 V dc.
YIN
0.1
70
60
Y COMMON-MODE REJ
(X1X2) 10V
CMRR dB
50
0.01
1
2
3
6
7
9 10 11
8
4
5
PEAK SIGNAL AMPLITUDE Volts
12
13
14
Figure 3. Percent Distortion vs. Input Signal
40
30
20
100
10
0
100
PERCENT DISTORTION
X COMMON-MODE REJ
(Y1Y2) 10V
1k
10k
100k
FREQUENCY Hz
1M
10M
Figure 6. CMRR vs. Frequency
10
20V p-p SIGNAL
1.0
XIN
YIN
0.1
10
100
1k
10k
FREQUENCY Hz
100k
1M
Figure 4. Percent Distortion vs. Frequency
–4–
REV. C
AD532
POWER SUPPLY CONSIDERATIONS
1.0
Although the AD532 is tested and specified with ± 15 V dc
supplies, it may be operated at any supply voltage from ± 10 V
to ± 18 V for the J and K versions, and ± 10 V to ± 22 V for the
S version. The input and output signals must be reduced proportionately to prevent saturation; however, with supply voltages
below ± 15 V, as shown in Figure 9. Since power supply sensitivity is not dependent on external null networks as in other
conventionally nulled multipliers, the power supply rejection
ratios are improved from 3 to 40 times in the AD532.
AMPLITUDE Volts
RL 2k CL 1000pF
RL 2k CL 0pF
0.1
12
0.01
10M
100k
1M
FREQUENCY Hz
PEAK SIGNAL VOLTAGE Volts
10k
SATURATED OUTPUT
SWING
10
Figure 7. Frequency Response, Multiplying
DYNAMIC CHARACTERISTICS
The closed loop frequency response of the AD532 in the multiplier mode typically exhibits a 3 dB bandwidth of 1 MHz and
rolls off at 6 dB/octave thereafter. Response through all inputs is
essentially the same as shown in Figure 7. In the divide mode,
the closed loop frequency response is a function of the absolute
value of the denominator voltage as shown in Figure 8.
MAX X OR Y INPUT
FOR 1% LINEARITY
8
6
4
10
Stable operation is maintained with capacitive loads to 1000 pF
in all modes, except the square root for which 50 pF is a safe
upper limit. Higher capacitive loads can be driven if a 100 Ω
resistor is connected in series with the output for isolation.
12
14
16
18
20
POWER SUPPLY VOLTAGE Volts
22
Figure 9. Signal Swing vs. Supply
NOISE CHARACTERISTICS
All AD532s are screened on a sampling basis to assure that
output noise will have no appreciable effect on accuracy. Typical spot noise vs. frequency is shown in Figure 10.
5
VZ 0.1 VX SIN T
4
1.0
VX 10V
SPOT NOISE V/ Hz
AMPLITUDE Volts
10
VX 1V
VX 5V
0.1
10k
100k
1M
FREQUENCY Hz
10M
3
2
1
Figure 8. Frequency Response, Dividing
0
10
100
1k
FREQUENCY Hz
10k
Figure 10. Spot Noise vs. Frequency
REV. C
–5–
100k
AD532
APPLICATIONS CONSIDERATIONS
SQUARE
The performance and ease of use of the AD532 is achieved
through the laser trimming of thin-film resistors deposited
directly on the monolithic chip. This trimming-on-the-chip
technique provides a number of significant advantages in terms
of cost, reliability and flexibility over conventional in-package
trimming of off-the-chip resistors mounted or deposited on a
hybrid substrate.
First and foremost, trimming on the chip eliminates the need for
a hybrid substrate and the additional bonding wires that are
required between the resistors and the multiplier chip. By trimming more appropriate resistors on the AD532 chip itself, the
second input terminals that were once committed to external
trimming networks have been freed to allow fully differential
operation at both the X and Y inputs. Further, the requirement
for an input attenuator to adjust the gain at the Y input has been
eliminated, letting the user take full advantage of the high input
impedance properties of the input differential amplifiers. Thus, the
AD532 offers greater flexibility for both algebraic computation and
transducer instrumentation applications.
X1
X2
Z
AD532
+VS
–VS
Figure 12. Squarer Connection
The squaring circuit in Figure 12 is a simple variation of the
multiplier. The differential input capability of the AD532, however, can be used to obtain a positive or negative output response
to the input . . . a useful feature for control applications, as it
might eliminate the need for an additional inverter somewhere else.
DIVISION
Z
VOUT = 10VZ
X
X1
X2
X
Z
AD532
Y1
Y2 +VS
Z
X1
X2
AD532
Y1
Y2
VOUT
OUT
VOS
VOUT =
(OPTIONAL)
(X1 – X2) (Y1 – Y2)
10V
20k
+VS
–VS
Figure 11. Multiplier Connection
For operation as a multiplier, the AD532 should be connected
as shown in Figure 11. The inputs can be fed differentially to
the X and Y inputs, or single-ended by simply grounding the
unused input. Connect the inputs according to the desired
polarity in the output. The Z terminal is tied to the output to
close the feedback loop around the op amp (see Figure 1). The
offset adjust VOS is optional and is adjusted when both inputs are
zero volts to obtain zero out, or to buck out other system offsets.
VOUT
OUT
–VS
1k
(SF)
47k
10k
20k
(X0)
REPLACING OTHER IC MULTIPLIERS
MULTIPLICATION
VIN2
10V
20k
2.2k
APPLICATIONS
VOUT =
(OPTIONAL)
VIN
Finally, provision for fine trimming the output voltage offset has
been included. This connection is optional, however, as the
AD532 has been factory-trimmed for total performance as
described in the listed specifications.
Existing designs using IC multipliers that require external
trimming networks can be simplified using the pin-for-pin
replaceability of the AD532 by merely grounding the X2, Y2 and
VOS terminals. (The VOS terminal should always be grounded
when unused.)
VOUT
OUT
Y1
Y2 +VS VOS –VS
+VS
–VS
Figure 13. Divider Connection
The AD532 can be configured as a two-quadrant divider by
connecting the multiplier cell in the feedback loop of the op
amp and using the Z terminal as a signal input, as shown in
Figure 13. It should be noted, however, that the output error is
given approximately by 10 V ⑀m/(X1 – X2), where ⑀m is the total
error specification for the multiply mode; and bandwidth by
fm × (X1 – X2)/10 V, where fm is the bandwidth of the multiplier.
Further, to avoid positive feedback, the X input is restricted to
negative values. Thus for single-ended negative inputs (0 V to
–10 V), connect the input to X and the offset null to X2; for
single-ended positive inputs (0 V to +10 V), connect the input
to X2 and the offset null to X1. For optimum performance, gain
(S.F.) and offset (X0) adjustments are recommended as shown
and explained in Table I.
For practical reasons, the useful range in denominator input is
approximately 500 mV ≤ |(X1 – X2)| ≤ 10 V. The voltage offset
adjust (VOS), if used, is trimmed with Z at zero and (X1 – X2) at
full scale.
Table I. Adjust Procedure (Divider or Square Rooter)
DIVIDER
With:
Adjust
X
Scale Factor –10 V
X0 (Offset)
–1 V
Adjust
for:
Z
VOUT
+10 V –10 V
+0.1 V –1 V
SQUARE ROOTER
Adjust
With:
for:
Z
+10 V
+0.1 V
VOUT
–10 V
–1 V
Repeat if required.
–6–
REV. C
AD532
SQUARE ROOT
DIFFERENCE OF SQUARES
Z
X1
X2
VOUT = 10VZ
Z
AD532
Y1
Y2 +VS
OUT
VOUT
20k
Y
–VS
1k
(SF)
2.2k
47k
–Y
AD532
10k
VOUT
OUT
Y1
Y2 +VS VOS –VS
VOUT =
X2 – Y2
10V
(OPTIONAL)
20k
AD741KH
+VS
–VS
Figure 15. Differential of Squares Connection
–VS
Figure 14. Square Rooter Connection
The connections for square root mode are shown in Figure 14.
Similar to the divide mode, the multiplier cell is connected in
the feedback of the op amp by connecting the output back to
both the X and Y inputs. The diode D1 is connected as shown
to prevent latch-up as ZIN approaches 0 volts. In this case, the
VOS adjustment is made with ZIN = +0.1 V dc, adjusting VOS to
obtain –1.0 V dc in the output, VOUT = – √10 V Z. For optimum
performance, gain (S.F.) and offset (X0) adjustments are recommended as shown and explained in Table I.
REV. C
20k
Z
10k
20k
(X0)
+VS
X1
X2
X
–7–
The differential input capability of the AD532 allows for the
algebraic solution of several interesting functions, such as the
difference of squares, X2 – Y2/10 V. As shown in Figure 15, the
AD532 is configured in the square mode, with a simple unity
gain inverter connected between one of the signal inputs (Y)
and one of the inverting input terminals (–YIN) of the multiplier.
The inverter should use precision (0.1%) resistors or be otherwise trimmed for unity gain for best accuracy.
AD532
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.005 (0.13) MIN
C00502h–0–2/01 (rev. C)
Side-Brazed DIP
(D-14)
0.098 (2.49) MAX
14
8
0.310 (7.87)
0.220 (5.59)
1
7
PIN 1
0.785 (19.94) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.150
(3.81)
MAX
0.023 (0.58)
0.014 (0.36)
0.015 (0.38)
0.008 (0.20)
0.100 0.070 (1.78) SEATING
(2.54) 0.030 (0.76) PLANE
BSC
Leadless Chip Carrier
(E-20A)
0.358 (9.09)
0.342 (8.69)
SQ
0.095 (2.41)
0.075 (1.90)
TOP
VIEW
0.358
(9.09)
MAX
SQ
0.200 (5.08)
BSC
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.100 (2.54) BSC
0.015 (0.38)
MIN
3
4
19
18 20
0.028 (0.71)
0.022 (0.56)
1
BOTTOM
VIEW
0.050 (1.27)
BSC
8
14
13
9
45° TYP
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
0.150 (3.81)
BSC
Metal Can
(H-10A)
REFERENCE PLANE
0.160 (4.06)
0.110 (2.79)
0.250 (6.35) MIN
0.050 (1.27) MAX
0.370 (9.40)
0.335 (8.51)
0.335 (8.51)
0.305 (7.75)
6
8
4
0.045 (1.14)
0.010 (0.25)
0.045 (1.14)
0.027 (0.69)
9
3
2
0.040 (1.02) MAX
7
5
0.115
(2.92)
BSC
PRINTED IN U.S.A.
0.185 (4.70)
0.165 (4.19)
0.750 (19.05)
0.500 (12.70)
0.019 (0.48)
0.230 (5.84)
0.016 (0.41)
BSC
0.021 (0.53)
0.016 (0.41)
10
1
0.034 (0.86)
0.027 (0.69)
36° BSC
BASE & SEATING PLANE
–8–
REV. C