T UCT ROD ACEMEN at P E T L ® e E P t n r OL RE rt Ce m/tsc O B S E N D ED o p p o l Su MM sil.c ECO echnica w.inter R O T w N w Sheet January 1996, Rev B urData I L or act o cont -INTERS 8 1-88 EL4450 FN7168 Wideband Four-Quadrant Multiplier Features The EL4450 is a complete fourquadrant multiplier circuit. It offers wide bandwidth and good linearity while including a powerful output voltage amplifier, drawing modest supply current. • Complete four-quadrant multiplier with output amp— requires no extra components The EL4450 operates on ±5V supplies and has an analog input range of ±2V, making it ideal for video signal processing. AC characteristics do not vary over the ±5V to ±15V supply range. • Operates on ±5V to ±15V supplies The multiplier has an operational temperature range of -40°C to +85°C and are packaged in plastic 14-pin PDIP and SO. Applications • Good linearity of 0.3% • 90MHz bandwidth for both X and Y inputs • All inputs are differential • 400V/µs slew rate • Modulation/Demodulation • RMS computation Pinout • Real-time power computation • Nonlinearity correction/generation EL4450 (14-PIN PDIP, SO) TOP VIEW Ordering Information PART NUMBER 1 TEMP. RANGE PACKAGE PKG. NO. EL4450CN -40°C to +85°C 14-Pin PDIP MDP0031 EL4450CM -40°C to +85°C 14-Pin SO MDP0027 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL4450 Absolute Maximum Ratings (TA = 25°C) V+ VS VIN VIN IIN Positive Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 16.5V V+ to V- Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . .33V Voltage at any Input or Feedback . . . . . . . . . . . . . . . V+ to VDifference between Pairs of Inputs or Feedback. . . . . . . . .6V Current into any Input or Feedback Pin. . . . . . . . . . . . . . 4mA IOUT PD TA TS Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Maximum Power Dissipation . . . . . . . . . . . . . . . . See Curves Operating Temperature Range . . . . . . . . . . . .-40°C to +85°C Storage Temperature Range. . . . . . . . . . . . .-60°C to +150°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Open-Loop DC Electrical Specifications PARAMETER VDIFF Power Supplies at ±5V, TA = 25°C, VFB = VOUT. DESCRIPTION Differential Input Voltage—Clipping MIN TYP 1.8 2.0 V 1.0 V 0.2% nonlinearity VCM MAX UNITS Common-Mode Range of VDIFF = 0, VS = ±5V ±2.5 ±2.8 V VS = ±15V ±12.5 ±12.8 V VOS Input Offset Voltage 8 35 mV IB Input Bias Current 9 20 µA IOS Input Offset Current between XIN+ and XIN-, YIN+ and YIN-, REF and FB 0.5 4 µA Gain Gain Factor of VOUT = Gain × XIN+ × YIN 0.5 0.55 V/V2 NLx Nonlinearity of X Input; XIN between -1V and +1V 0.3 0.7 % NLy Nonlinearity of Y Input; YIN between -1V and +1V 0.2 0.35 % RIN Input resistance XIN+ to XIN-, YIN+ to YIN- 230 REF to FB 90 0.45 kΩ CMRR Common-Mode Rejection Ratio, XIN and YIN 70 90 dB PSRR Power-Supply Rejection Ratio, FB 60 72 dB VO Output Voltage Swing (VIN = 0, VREF Varied) VS = ±5V ±2.5 ±2.8 V VS = ±15V ±12.5 ±12.8 40 85 ISC Output Short-Circuit Current IS Supply Current, VS = ±15V 2 15.4 mA 18 mA EL4450 Closed-Loop AC Electrical Specifications PARAMETER Power Supplies at ±12V, TA = 25°C, RL = 500Ω, CL = 15pF. DESCRIPTION MIN TYP MAX UNITS BW, -3dB -3dB Small-Signal Bandwidth, X or Y 90 MHz BW, ±0.1dB 0.1dB Flatness Bandwidth 10 MHz Peaking Frequency Response Peaking 1.0 dB SR Slew Rate, VOUT between -2V and +2V 400 V/µs VN Input-Referred Noise Voltage Density 100 nV/Hz 300 Test Circuit Note: For typical performance curves, RF = 0, RG = ∞, VS = ±5V, RL = 500Ω, and CL = 15pF unless otherwise noted. Typical Performance Curves Transfer Function of X Input for Various Y Inputs 3 Transfer Function of Y Input for Various X Inputs EL4450 Typical Performance Curves Frequency Response for Various Feedback Divider Ratios X Input Frequency Response for Various Y DC Inputs Change in Bandwidth and Peaking vs Temperature 4 (Continued) Frequency Response for Various RL, CL VS = ±5V Y Input Frequency Response for Various X DC Inputs Total Harmonic Distortion of X Input vs Frequency Frequency Response for Various RL, CL VS = ±15V -3dB Bandwidth and Peaking vs Supply Voltage Total Harmonic Distortion of Y Input vs Frequency EL4450 Typical Performance Curves (Continued) Slew Rate vs Supply Voltage Slew Rate vs Die Temperature Input Voltage Noise vs Frequency Nonlinearity of X Input Bias Current vs Die Temperature Supply Current vs Die Temperature 5 CMRR vs Frequency Nonlinearity of Y Input Common-Mode Input Range vs Supply Voltage Supply Current vs Supply Voltage 14-Pin Package Power Dissipation vs Ambient Temperature EL4450 Applications Information The EL4450 is a complete four-quadrant multiplier with 90MHz bandwidth. It has three sets of inputs; a differential multiplying X-input, a differential multiplying Y-input, and another differential input which is used to complete a feedback loop with the output. Here is a typical connection: The gain of the feedback divider is H, and H = RG/(RG + RF). The transfer function of the part is: VOUT = AO × (1/2 × ((VINX+–VINX-) × (VINY+–VINY-)) + (VREF–VFB)). VFB is connected to VOUT through a feedback network, so VFB = H*VOUT. AO is the open-loop gain of the amplifier, and is about 600. The large value of AO drives: (1/2 × ((VINX+–VINX-) × (VINY+–VINY-)) + (VREF– VFB))→0. Rearranging and substituting for VREF: VOUT = (1/2 × ((VINX+–VINX-) × (VINY+–VINY-)) +VREF)/H, or VOUT = (XY/2 + VREF)/H Thus the output is equal to one-half the product of X and Y inputs and offset by VREF, all gained up by the feedback divider ratio. The EL4450 is stable for a direct connection between VOUT and FB, and the feedback divider may be used for higher output gain, although with the traditional loss of bandwidth. It is important to keep the feedback divider’s impedance at the FB terminal low so that stray capacitance does not diminish the loop’s phase margin. The pole caused by the parallel impedance of the feedback resistors and stray capacitance should be at least 150MHz; typical strays of 3pF thus require a feedback impedance of 360Ω or less. Alternatively, a small capacitor across RF can be used to create more of a frequency-compensated divider. The value of the capacitor should scale with the parasitic capacitance at the FB input. It is also practical to place small capacitors across both the feedback resistors (whose values maintain the desired gain) to swamp out parasitics. For instance, two 10pF capacitors across equal divider resistors for a maximum gain of 1 will dominate parasitic effects and allow a higher divider resistance. The REF pin can be used as the output’s ground reference, or for DC offsetting of the output, or it can be used to sum in another signal. Input Connections a metal probe) or an oscilloscope probe on the input will kill the oscillation. Normal high-frequency construction obviates any such problems, where the input source is reasonably close to the input. If this is not possible, one can insert series resistors of around to 51Ω to de-Q the inputs. Signal Amplitudes Signal input common-mode voltage must be between (V-) +2.5V and (V+) -2.5V to ensure linearity. Additionally, the differential voltage on any input stage must be limited to ±6V to prevent damage. The differential signal range is ±2V in the EL4450. The input range is substantially constant with temperature. The Ground Pin The ground pin draws only 6µA maximum DC current, and may be biased anywhere between (V-) +2.5V and (V+) -3.5V. The ground pin is connected to the IC’s substrate and frequency compensation components. It serves as a shield within the IC and enhances input stage CMRR over frequency, and if connected to a potential other than ground, it must be bypassed. Power Supplies The EL4450 works well on supplies from ±3V to ±15V. The supplies may be of different voltages as long as the requirements of the GND pin are observed (see the Ground Pin section for a discussion). The supplies should be bypassed close to the device with short leads. 4.7µF tantalum capacitors are very good, and no smaller bypasses need be placed in parallel. Capacitors as low as 0.01µF can be used if small load currents flow. Single-polarity supplies, such as +12V with +5V can be used, where the ground pin is connected to +5V and V- to ground. The inputs and outputs will have to have their levels shifted above ground to accommodate the lack of negative supply. The power dissipation of the EL4450 increases with power supply voltage, and this must be compatible with the package chosen. This is a close estimate for the dissipation of a circuit: PD =2*IS,max*VS + (VS–VO)*VO/RPAR where IS,max is the maximum supply current VS is the ± supply voltage (assumed equal) VO is the output voltage The input transistors can be driven from resistive and capacitive sources, but are capable of oscillation when presented with an inductive input. It takes about 80nH of series inductance to make the inputs actually oscillate, equivalent to four inches of unshielded wiring or about 6 of unterminated input transmission line. The oscillation has a characteristic frequency of 500MHz. Placing one’s finger (via 6 RPAR is the parallel of all resistors loading the output For instance, the EL4450 draws a maximum of 18mA. With light loading, RPAR→∞ and the dissipation with ±5V supplies is 180mW. The maximum supply voltage that the device can run on for a given PD and the other parameters is: VS,max = (PD + VO2/RPAR)/(2IS + VO/RPAR) EL4450 The maximum dissipation a package can offer is: PD,max = (TJ,max–TA,max)/θJA inputs between 200mVRMS and 1VRMS. The traditional use of the EL4450 as an AGC detector and control loop would be: Where TJ,max is the maximum junction temperature, 150°C for reliability, less to retain optimum electrical performance TA,max is the ambient temperature, 70°C for commercial and 85°C for industrial range θJA is the thermal resistance of the mounted package, obtained from data sheet dissipation curves The more difficult case is the SO-14 package. With a maximum junction temperature of 150°C and a maximum ambient temperature of 85°C, the 65°C temperature rise and package thermal resistance of 120°/W gives a dissipation of 542mW at 85°C. This allows the full maximum operating supply voltage unloaded, but reduced if loaded significantly. Output Loading The output stage is very powerful. It typically can source 85mA and sink 120mA. Of course, this is too much current to sustain and the part will eventually be destroyed by excessive dissipation or by metal traces on the die opening. The metal traces are completely reliable while delivering the 30mA continuous output given in the Absolute Maximum Ratings table in this data sheet, or higher purely transient currents. Gain accuracy degrades only 0.2% from no load to 100Ω load. Heavy resistive loading will degrade frequency response and video distortion for loads < 100Ω. Capacitive loads will cause peaking in the frequency response. If a capacitive load must be driven, a small-valued series resistor can be used to isolate it. 12Ω to 51Ω should suffice. A 22Ω series resistor will limit peaking to 2.5dB with even a 220pF load. Mixer Applications Because of its lower distortion levels, the Y input is the better choice for a mixer’s signal port. The X input would receive oscillator amplitudes of about 1V RMS maximum. Carrier suppression is initially limited by the offset voltage of the Y input, 20mV maximum, and is about 37dB worst-case. Better suppression can be obtained by nulling the offset of the X input. Similarly, nulling the offset of the Y input will improve signal-port suppression. Driving an input differentially will also maximize feedthrough suppression at frequencies beyond 10MHz. AC Level Detectors Square-law converters are commonly used to convert AC signals to DC voltages corresponding to the original amplitude in subsystems like automatic gain controls (AGCs) and amplitude-stabilized oscillators. Due to the controlled AC amplitudes, the inputs of the multiplier will see a relatively constant signal level. Best performance will be obtained for 7 FIGURE 1. TRADITIONAL AGC DETECTOR/DC FEEDBACK CIRCUIT The EL4450 simply provides an output equal to the square of the input signal and an integrator filters out the AC component, while comparing the DC component to an amplitude reference. The integrator output is the DC control voltage to the variable-gain sections of the AGC (not shown). If a negative polarity of reference is required, one of the multiplier input terminal pairs is reversed, inverting the multiplier output. Input bias current will cause input voltage offsets due to source impedances; putting a compensating resistor in series with the grounded inputs of the EL4450 will reduce this offset greatly. This control system will attempt to force: VIN,RMS2/4=VREF EL4450 FIGURE 2. SIMPLIFIED AGC DETECTOR/DC FEEDBACK CIRCUIT The extra op-amp can be eliminated by using this circuit (Figure 2). Here the internal op-amp of the EL4450 replaces the external amplifier. The feedback capacitor CF does not provide a perfect integration action; a zero occurs at a frequency of 1/2πRCF. This is canceled by including another RCF pair at the AGC control output. If the reference voltage must be negative, the resistor at pin 11 is connected to ground rather than the reference and pin 10 connected to the reference. An ECL comparator produces an output corresponding to the sign of the input, which when multiplied by the input produces an effective absolute-value function. The RC product connected to the X inputs simply emulates the time delay of the comparator to maintain circuit accuracy at higher frequencies. Nonlinear Function Generation The REF pin of the EL4450 can be used to sum in various quantities of polynomial function generators. For instance, The amplitude reference will have to support some AC currents flowing through R. If this is a problem, several changes can be made to eliminate it. The reference is connected to pin 10 and the resistor R connected to pin 11 reconnected to ground, and one of the multiplier input connections are reversed. Square-law detectors have a restricted input range, about 10:1, because the output rapidly disappears into the DC errors as signal amplitudes reduce. This circuit gives a multiplier output that is the absolute value of the input, thus increasing range to 100:1(Figure 3). FIGURE 3. ABSOLUTE-VALUE INPUT CIRCUITRY 8 EL4450 FIGURE 4. POLYNOMIAL FUNCTION GENERATOR this sum of REF allows a linear signal path which can have various amounts of squared signal added (Figure 4). the bandwidth of the circuit will reduce for smaller input signals (Figure 5). The polarity of the squared signal can be reversed by swapping one of the X or Y input pairs. The REF and FB terminals can also be used to implement division. The REF and FB pins also simplify feedback schemes that allow square-rooting. The output frequency response reduces for smaller values of VX, but is not affected by VREF(Figure 6). The diode and IPULLDOWN assure that the output will always produce the positive square-root of the input signal. IPULLDOWN should be large enough to assure that the diode be forward-biased for any load current. In this configuration, FIGURE 5. SQUARE-ROOTER FIGURE 6. DIVIDER CONNECTION 9 EL4450 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10