AD EVAL-ADMP441Z-FLEX

FEATURES
FUNCTIONAL BLOCK DIAGRAM
ADMP441
HARDWARE
CONTROL
SCK
SD
WS
09568-001
GND
GND
VDD
POWER
MANAGEMENT
I2S
SERIAL
PORT
L/R
ADC
FILTER
CHIPEN
Digital I²S interface with high precision 24-bit data
High SNR of 61 dBA
High sensitivity of −26 dBFS
Flat frequency response from 60 Hz to 15 kHz
Low current consumption of 1.4 mA
High PSR of −75 dBFS
Small 4.72 mm × 3.76 mm × 1 mm surface-mount package
Compatible with Sn/Pb and Pb-free solder processes
RoHS/WEEE compliant
GND
Data Sheet
Omnidirectional Microphone with
Bottom Port and I2S Digital Output
ADMP441
Figure 1.
Teleconferencing systems
Gaming consoles
Mobile devices
Laptops
Tablets
Security systems
BOTTOM
TOP
09568-015
APPLICATIONS
Figure 2. Isometric Views of ADMP441 Microphone Package
GENERAL DESCRIPTION
The ADMP4411 is a high performance, low power, digital output,
omnidirectional MEMS microphone with a bottom port. The
complete ADMP441 solution consists of a MEMS sensor, signal
conditioning, an analog-to-digital converter, antialiasing filters,
power management, and an industry standard 24-bit I2S interface. The I2S interface allows the ADMP441 to connect directly
to digital processors, such as DSPs and microcontrollers, without the need for an audio codec in the system.
1
The ADMP441 has a high SNR and high sensitivity, making it
an excellent choice for far field applications. The ADMP441 has
a flat wideband frequency response, resulting in natural sound
with high intelligibility. A built-in particle filter provides high
reliability.
The ADMP441 is available in a thin 4.72 mm × 3.76 mm ×
1 mm surface-mount package. It is reflow solder compatible
with no sensitivity degradation. The ADMP441 is halide free.
Protected by U.S. Patents 7,449,356; 7,825,484; 7,885,423; and 7,961,897. Other patents are pending.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
ADMP441
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Understanding Sensitivity ............................................................8 Applications....................................................................................... 1 Power Management ......................................................................8 Functional Block Diagram .............................................................. 1 Startup.............................................................................................8 General Description ......................................................................... 1 I2S Data Interface ..........................................................................8 Revision History ............................................................................... 2 Digital Filter Characteristics ..................................................... 10 Specifications..................................................................................... 3 Applications Information .............................................................. 11 I2S Digital Input/Output.............................................................. 4 Power Supply Decoupling ......................................................... 11 Timing Diagram ........................................................................... 4 Handling Instructions................................................................ 11 Absolute Maximum Ratings............................................................ 5 Supporting Documentation...................................................... 11 ESD Caution.................................................................................. 5 Layout and Design Recommendations........................................ 12 Pin Configuration and Function Descriptions............................. 6 Outline Dimensions ....................................................................... 13 Typical Performance Characteristics ............................................. 7 Ordering Guide .......................................................................... 13 Theory of Operation ........................................................................ 8 REVISION HISTORY
1/12—Rev. 0 to Rev. A
Changes to Circuit Note Title ....................................................... 11
Updated Outline Dimensions ....................................................... 13
Deleted Figure 18............................................................................ 13
10/11—Revision 0: Initial Version
Rev. A | Page 2 of 16
Data Sheet
ADMP441
SPECIFICATIONS
TA = 25°C, VDD = 2.4 V, SCK = 3.072 MHz, SPL = 104 dB (3.16 Pa rms), unless otherwise noted. All minimum and maximum
specifications are guaranteed. Typical specifications are not guaranteed.
Table 1.
Parameter
PERFORMANCE
Directionality
Sensitivity at 94 dB SPL 1
Signal-to-Noise Ratio
Equivalent Input Noise
Dynamic Range
Frequency Response 2
Symbol
Total Harmonic Distortion
Power Supply Rejection
Maximum Acoustic Input
Noise Floor
POWER SUPPLY
Supply Voltage
Supply Current
VDD = 1.8 V
Normal Mode
Standby
Power-Down
VDD = 3.3 V
Normal Mode
Standby
Power-Down
DIGITAL FILTER
Group Delay
THD
PSR
SNR
EIN
Test Conditions/Comments
Min
1 kHz, 104 dB SPL
20 kHz bandwidth, A-weighted
20 kHz bandwidth, A-weighted
Derived from EIN and maximum acoustic input
Low frequency –3 dB point
High frequency –3 dB point
Deviation limits from flat response within pass band
104 dB SPL
217 Hz, 100 mV p-p square wave superimposed on VDD
Peak
20 Hz to 20 kHz, A-weighted, rms
−29
VDD
IDD
Omni
−26
61
33
87
60
15
−3/+2
Max
Unit
−23
dBFS
dBA
dBA SPL
dB
Hz
kHz
dB
%
dBFS
dB SPL
dBFS
3
−75
120
−87
1.8
3.3
V
1.4
1.6
0.8
2
mA
mA
μA
2.2
2.5
0.8
4.5
mA
mA
μA
17.25/fS
359
1078
fS = 48 kHz
fS = 16 kHz
Pass-Band Ripple
Stop-Band Attenuation
Pass Band
Typ
±0.04
60
20.3
0.423 × fS
1
sec
μs
μs
dB
dB
kHz
The peak-to-peak amplitude is relative to peak-to-peak amplitude of 224 − 1. The stimulus is a 104 dB SPL sinusoid having rms amplitude of 3.1623 Pa. Sensitivity is
relative to 1 Pa.
2
See Figure 6 and Figure 8.
Rev. A | Page 3 of 16
ADMP441
Data Sheet
I²S DIGITAL INPUT/OUTPUT
–40°C < TA < +85°C, 1.8 V < VDD < 3.3 V, unless otherwise noted.
Table 2.
Parameter
DIGITAL INPUT
Voltage Input Low (L/R, WS, SCK)
Voltage Input High (L/R, WS, SCK)
SD DIGITAL OUTPUT
Voltage Output Low
Voltage Output Low
Voltage Output High
Voltage Output High
Voltage Output Low
Voltage Output Low
Voltage Output High
Voltage Output High
1
Symbol
Test Conditions/Comments
Min
VIL
VIH
0
0.7 × VDD
VOL
VOL
VOH
VOH
VOL
VOL
VOH
VOH
VDD = 1.8 V, ISINK = 0.25 mA
VDD = 1.8 V, ISINK = 0.7 mA
VDD = 1.8 V, ISINK = 0.7 mA
VDD = 1.8 V, ISINK = 0.25 mA
VDD = 3.3 V, ISINK = 0.5 mA
VDD = 3.3 V, ISINK = 1.7 mA
VDD = 3.3 V, ISINK = 1.7 mA
VDD = 3.3 V, ISINK = 0.5 mA
Limit 1
Max
Unit
0.25 × VDD
VDD
0.1 × VDD
0.3 × VDD
0.7 × VDD
0.9 × VDD
0.1 × VDD
0.3 × VDD
0.7 × VDD
0.9 × VDD
Limits based on characterization results; not production tested.
Table 3. Serial Data Port Timing Specifications
Parameter
tSCH
tSCL
tSCP
fSCK
tWSS
tWSH
fWS
Description
SCK high
SCK low
SCK period
SCK frequency
WS setup
WS hold
WS frequency
Min
50
50
312
0.5
0
20
7.8
Max
3.2
49.3
Unit
ns
ns
ns
MHz
ns
ns
kHz
TIMING DIAGRAM
tSCP
tSCH
SCK
tWSS
tSCL
tWSH
09568-103
WS
SD
Figure 3. Serial Data Port Timing
Rev. A | Page 4 of 16
V
V
V
V
V
V
V
V
V
V
Data Sheet
ADMP441
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage (VDD)
Sound Pressure Level
Mechanical Shock
Vibration
Operating Temperature Range
Digital Pin Input Voltage
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V to +3.6 V
160 dB
10,000 g
Per MIL-STD-883 Method
2007, Test Condition B
−40°C to +85°C
−0.3 V to VDD + 0.3 V or 3.6 V,
whichever is less
ESD CAUTION
CRITICAL ZONE
TL TO TP
tP
TP
TL
tL
TSMAX
TSMIN
tS
RAMP-DOWN
PREHEAT
09568-002
TEMPERATURE
RAMP-UP
t25°C TO PEAK
TIME
Figure 4. Recommended Soldering Profile Limits
Table 5. Recommended Soldering Profile Limits
Profile Feature
Average Ramp Rate (TL to TP)
Preheat
Minimum Temperature (TSMIN)
Maximum Temperature (TSMAX)
Time (TSMIN to TSMAX), tS
Ramp-Up Rate (TSMAX to TL)
Time Maintained Above Liquidous (tL)
Liquidous Temperature (TL)
Peak Temperature (TP)
Time Within 5°C of Actual Peak Temperature (tP)
Ramp-Down Rate
Time 25°C (t25°C) to Peak Temperature
Rev. A | Page 5 of 16
Sn63/Pb37
1.25°C/sec max
Pb-Free
1.25°C/sec max
100°C
150°C
60 sec to 75 sec
1.25°C/sec
45 sec to 75 sec
183°C
215°C +3°C/−3°C
20 sec to 30 sec
3°C/sec max
5 minute max
100°C
200°C
60 sec to 75 sec
1.25°C/sec
~50 sec
217°C
260°C +0°C/−5°C
20 sec to 30 sec
3°C/sec max
5 minute max
ADMP441
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADMP441
6 GND
WS 3
7 VDD
GND 5
L/R 4
SD 2
8 CHIPEN
9 GND
BOTTOM VIEW
(Not to Scale)
09568-003
SCK 1
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
Mnemonic
SCK
SD
Type
Input
Output
3
4
WS
L/R
Input
Input
5
6
7
8
GND
GND
VDD
CHIPEN
Ground
Ground
Power
Input
9
GND
Ground
Description
Serial Data Clock for I²S Interface.
Serial Data Output for I²S Interface. This pin tristates when not actively driving the appropriate
output channel. The SD trace should have a 100 kΩ pull-down resistor to discharge the line during
the time that all microphones on the bus have tristated their outputs.
Serial Data-Word Select for I²S Interface.
Left/Right Channel Select. When set low, the microphone outputs its signal in the left channel of
the I²S frame; when set high, the microphone outputs its signal in the right channel.
Ground. Connect to ground on the PCB.
Ground. Connect to ground on the PCB.
Power, 1.8 to 3.3 V. This pin should be decoupled to Pin 6 with a 0.1 μF capacitor.
Microphone Enable. When set low (ground), the microphone is disabled and put in power-down
mode. When set high (VDD), the microphone is enabled.
Ground. Connect to ground on the PCB.
Rev. A | Page 6 of 16
Data Sheet
ADMP441
TYPICAL PERFORMANCE CHARACTERISTICS
10
10
8
4
AMPLITUDE (dB)
SENSITIVITY (dB)
6
2
0
–2
–4
0
–10
–6
1k
10k
FREQUENCY (Hz)
0
–10
–20
–40
–50
–60
–70
1k
10k
09568-010
PSR (dB)
–30
FREQUENCY (Hz)
100
1k
10k
FREQUENCY (Hz)
Figure 8. Typical Frequency Response (Measured)
Figure 6. Frequency Response Mask
–80
100
–20
10
Figure 7. Typical Power Supply Rejection vs. Frequency
Rev. A | Page 7 of 16
09568-011
100
09568-009
–8
–10
50
ADMP441
Data Sheet
THEORY OF OPERATION
The ADMP441 is a high performance, low power, digital
output, omnidirectional MEMS microphone with a bottom
port. The complete ADMP441 solution consists of a MEMS
sensor, signal conditioning, an analog-to-digital converter, antialiasing filters, power management, and an industry standard
24-bit I2S interface.
The ADMP441 complies with the TIA-920 Telecommunications
Telephone Terminal Equipment Transmission Requirements for
Wideband Digital Wireline Telephones standard.
UNDERSTANDING SENSITIVITY
The casual user of digital microphones may have difficulty
understanding the sensitivity specification. Unlike an analog
microphone (whose specification is easily confirmed with an
oscilloscope), the digital microphone output has no obvious
unit of measure.
It is not recommended to supply active clocks (WS and SCK) to
the ADMP441 while there is no power supplied to VDD. Doing
this continuously turns on ESD protection diodes, which may
affect long-term reliability of the microphone.
I²S DATA INTERFACE
The slave serial data port’s format is I2S, 24-bit, twos complement. There must be 64 SCK cycles in each WS stereo frame, or
32 SCK cycles per data-word. The L/R control pin determines
whether the ADMP441 outputs data in the left or right channel.
For a stereo application, the SD pins of the left and right
ADMP441 microphones should be tied together as shown in
Figure 9. The format of a stereo I2S data stream is shown in
Figure 10. Figure 11 and Figure 12 show the formats of a mono
microphone data stream for left and right microphones,
respectively.
Data Output Mode
The output data pin (SD) is tristated when it is not actively
driving I2S output data. SD immediately tristates after the LSB
is output so that another microphone can drive the common
data line.
POWER MANAGEMENT
The ADMP441 has three different power states: normal
operation, standby mode, and power-down mode.
Normal Operation
The microphone becomes operational 218 clock cycles (85 ms
with SCK at 3.072 MHz) after initial power-up. The CHIPEN
pin then controls the power modes. The part is in normal operation mode when SCK is active and the CHIPEN pin is high.
The ADMP441 should not be transitioned from standby to
power-down mode, or vice versa. Standby mode is only
intended to be entered from the normal operation state.
It always takes 217 clock cycles to restart the ADMP441 after VDD
is applied.
The microphones have zero output for the first 218 SCK clock
cycles (85 ms with SCK at 3.072 MHz) following power-up.
Although the industry uses a standard specification of 94 dB
SPL, the ADMP441 test method applies a 104 dB SPL signal.
The higher sound pressure level reduces noise and improves
repeatability. The ADMP441 has excellent gain linearity, and
the sensitivity test result at 94 dB is derived with very high
confidence from the test data.
The microphone enters standby mode when the serial data
clock SCK stops and CHIPEN is high. Normal operation
resumes 214 clock cycles (5 ms with SCK at 3.072 MHz) after
SCK restarts.
The microphone enters power-down mode when CHIPEN is
low, regardless of the SCK operation. Normal mode operation
resumes 217 SCK clock cycles (43 ms with SCK at 3.072 MHz)
after CHIPEN returns high while SCK is active.
STARTUP
The ADMP441 has a nominal sensitivity of −26 dBFS at 1 kHz
with an applied sound pressure level of 94 dB. The units are in
decibels referred to full scale. The ADMP441 default full-scale
peak output word is 223 – 1 (integer representation), and
−26 dBFS of that scale is (223 − 1) × 10(−26/20) = 420,426. A pure
acoustic tone at 1 kHz having a 1 Pa rms amplitude results in an
output digital signal whose peak amplitude is 420,426.
Standby Mode
Power-Down Mode
The SD trace should have a pull-down resistor to discharge the
line during the time that all microphones on the bus have
tristated their outputs. A 100 kΩ resistor is sufficient for this, as
shown in Figure 9.
Data-Word Length
The output data-word length is 24 bits per channel. The
ADMP441 must always have 64 clock cycles for every stereo
data-word (fSCK = 64 × fWS).
Data-Word Format
The default data format is I2S (twos complement), MSB-first. In
this format, the MSB of each word is delayed by one SCK cycle
from the start of each half-frame.
Rev. A | Page 8 of 16
Data Sheet
ADMP441
FROM VOLTAGE
REGULATOR
(1.8V TO 3.3V)
SD
WS
SCK
SYSTEM MASTER
(DSP, MICROCONTROLLER,
CODEC)
0.1µF
VDD
0.1µF
VDD
CHIPEN
LEFT
L/R
ADMP441
VDD
VDD
SCK
SCK
WS
WS
SD
CHIPEN
RIGHT
SD
GND GND GND
09568-004
GND GND GND
L/R
ADMP441
100kΩ
Figure 9. System Block Diagram
WS
1
2
3
4
24
25
26
32
33
34
35
36
56
57
58
64
SD (24-BIT)
MSB
LSB
HIGH-Z
MSB
LEFT CHANNEL
LSB
HIGH-Z
RIGHT CHANNEL
HIGH-Z
09568-005
SCK (64 × fS)
Figure 10. Stereo Output I²S Format
WS
1
2
3
4
24
25
26
32
33
34
35
36
56
57
58
64
36
56
57
58
64
SCK (64 × fS)
MSB
LSB
HIGH-Z
09568-006
SD (24-BIT)
HIGH-Z
LEFT CHANNEL
Figure 11. Mono Output I²S Format Left Channel (L/R = 0)
WS
1
2
3
4
24
25
26
32
33
34
35
SD (24-BIT)
MSB
HIGH-Z
LSB
RIGHT CHANNEL
Figure 12. Mono Output I²S Format Right Channel (L/R = 1)
Rev. A | Page 9 of 16
HIGH-Z
09568-007
SCK (64 × fS)
ADMP441
Data Sheet
wide dynamic range. However, it does require a good quality
low-pass filter to eliminate the high frequency noise.
DIGITAL FILTER CHARACTERISTICS
The ADMP441 has an internal digital band-pass filter. A
high-pass filter eliminates unwanted low frequency signals.
A low-pass filter allows the user to scale the pass band with
the sampling frequency as well as perform required noise
reduction.
High Pass Filter
The ADMP441 incorporates a high-pass filter to remove unwanted
dc and very low frequency components. Table 7 shows the highpass characteristics for a nominal sampling rate of 48 kHz. The
cutoff frequency scales with changes in sampling rate.
Figure 13 shows the response of this digital low-pass filter
included in the microphone. The pass band of the filter extends
to 0.423 × fS and, in that band, has an unnoticeable 0.04 dB of
ripple. The high frequency cutoff of −6 dB occurs at 0.5 × fS. A
48 kHz sampling rate results in a pass band of 20.3 kHz and a
half amplitude corner at 24 kHz; the stop-band attenuation of
the filter is greater than 60 dB. Note that these filter specifications scale with sampling frequency.
0
–10
Table 7. High-Pass Filter Characteristics
–20
Attenuation
–3.0 dB
–0.5 dB
–0.1 dB
This digital filter response is in addition to the natural highpass response of the ADMP441 MEMS acoustic transducer that
has a −3 dB cutoff of 60 Hz.
MAGNITUDE (dB)
–30
–40
–50
–60
–70
–80
–90
–100
Low-Pass Filter
The analog-to-digital converter in the ADMP441 is a single-bit,
high order, sigma-delta (Σ-Δ) running at a high oversampling
ratio. The noise shaping of the converter pushes the majority of
the noise well above the audio band and gives the microphone a
Rev. A | Page 10 of 16
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
NORMALIZED FREQUENCY (fS)
Figure 13. Digital Low-Pass Filter Magnitude Response
1.0
09568-008
Frequency
3.7 Hz
10.4 Hz
21.6 Hz
Data Sheet
ADMP441
APPLICATIONS INFORMATION
POWER SUPPLY DECOUPLING
•
For best performance and to avoid potential parasitic artifacts,
placing a 0.1 μF ceramic type X7R or better capacitor between
Pin 7 (VDD) and ground is strongly recommended. The
capacitor should be placed as close to Pin 7 as possible.
•
The connections to each side of the capacitor should be as short
as possible, and the trace should stay on a single layer with no
vias. For maximum effectiveness, locate the capacitor equidistant
from the power and ground pins or, when equidistant placement
is not possible, slightly closer to the power pin. Thermal connections to the ground planes should be made on the far side of the
capacitor, as shown in Figure 14.
VDD
GND
Do not pick up the microphone with a vacuum tool that
makes contact with the bottom side of the microphone.
Do not pull air out of or blow air into the microphone port.
Do not use excessive force to place the microphone on
the PCB.
Reflow Solder
For best results, the soldering profile should be in accordance
with the recommendations of the manufacturer of the solder
paste used to attach the MEMS microphone to the PCB. It is
recommended that the solder reflow profile does not exceed the
limit conditions specified in Figure 4 and Table 5.
Board Wash
When washing the PCB, ensure that water does not make
contact with the microphone port. Blow-off procedures and
ultrasonic cleaning must not be used.
SUPPORTING DOCUMENTATION
CAPACITOR
Evaluation Board User Guide
UG-303, EVAL-ADMP441Z-FLEX: Bottom-Port I2S Output
MEMS Microphone Evaluation Board
TO GND
09568-012
TO VDD
Circuit Note
CN-0208, High Performance Digital MEMS Microphone's Simple
Interface to SigmaDSP Audio Processor with I2S Output
Figure 14. Recommended Power Supply Bypass Capacitor Layout
HANDLING INSTRUCTIONS
Application Notes
Pick-and-Place Equipment
AN-1112 Application Note, Microphone Specifications and
Terms Explained
The MEMS microphone can be handled using standard pickand-place and chip shooting equipment. Care should be taken
to avoid damage to the MEMS microphone structure as follows:
•
•
Use a standard pickup tool to handle the microphone.
Because the microphone hole is on the bottom of the
package, the pickup tool can make contact with any part
of the lid surface.
Use care during pick-and-place to ensure that no high
shock events above 10,000 g are experienced because such
events may cause damage to the microphone.
AN-1003 Application Note, Recommendations for Mounting and
Connecting Analog Devices, Inc., Bottom-Ported MEMS
Microphones
AN-1068 Application Note, Reflow Soldering of the MEMS
Microphone
AN-1124 Application Note, Recommendations for Sealing
Analog Devices, Inc., Bottom-Port MEMS Microphones from
Dust and Liquid Ingress
For additional information, visit www.analog.com/mic.
Rev. A | Page 11 of 16
ADMP441
Data Sheet
LAYOUT AND DESIGN RECOMMENDATIONS
1.05
(6×)
0.25 DIA.
(THRU HOLE)
2.66 (4×)
0.96
1.33 (2×)
1.56
09568-013
3.16
0.40 × 0.60
(8×)
DIMENSIONS SHOWN IN MILLIMETERS
Figure 15. Recommended Printed Circuit Board Land Pattern
(Dimensions shown in millimeters)
1.05
(6×)
0.20
1.05
2.66 (4×)
3.76
1.33 (2×)
1.6
1.07
0.350 × 0.550
(8×)
DIMENSIONS SHOWN IN MILLIMETERS
Figure 16. Recommended Printed Circuit Board Solder Paste Mask Pattern
(Dimensions shown in millimeters)
Rev. A | Page 12 of 16
09568-014
4.72
Data Sheet
ADMP441
OUTLINE DIMENSIONS
4.82
4.72
4.62
4.10 REF
PIN 1
REFERENCE
CORNER
0.40 × 0.60
(PINS 1-8)
0.30
1.07
1.05 BSC
1.56 DIA.
0.96 DIA.
3.86
3.76
3.66
1
4
2.66 BSC
5
3.14
REF
1.33 BSC
9
TOP VIEW
1.05
0.98
0.88
0.275
0.250 DIA.
0.225
6
BOTTOM VIEW
SIDE VIEW
12-19-2011-B
0.73 REF
0.24 REF
Figure 17. 9-Terminal Chip Array Small Outline No Lead Cavity [LGA_CAV]
4.72 mm × 3 .76 mm × 1 mm Body
(CE-9-1)
(Dimensions shown in millimeters)
ORDERING GUIDE
Model 1
ADMP441ACEZ-RL
ADMP441ACEZ-RL7
EVAL-ADMP441Z
EVAL-ADMP441Z-FLEX
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
9-Terminal LGA_CAV, 13” Tape and Reel
9-Terminal LGA_CAV, 7” Tape and Reel
Evaluation Board
Flex Evaluation Board
Z = RoHS Compliant Part.
This package option is halide-free.
Rev. A | Page 13 of 16
Package Option 2
CE-9-1
CE-9-1
Ordering Quantity
4,500
1,000
ADMP441
Data Sheet
NOTES
Rev. A | Page 14 of 16
Data Sheet
ADMP441
NOTES
Rev. A | Page 15 of 16
ADMP441
Data Sheet
NOTES
©2011–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09568-0-1/12(A)
Rev. A | Page 16 of 16