Dual 16-Bit, 1.0 GSPS D/A Converter Preliminary Technical Data AD9779 DAC that provides a sample rate of 1 GSPS, permitting multi carrier generation up to its Nyquist frequency. It includes features optimized for direct conversion transmit applications, including complex digital modulation and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators such as the AD8349. A serial peripheral interface (SPI) provides for programming many internal parameters and also enables read-back of status registers. The output current can be programmed over a range of 10mA to 30mA. The AD9779 is manufactured on an advanced 0.18µm CMOS process and operates from 1.8V and 3.3V supplies for a total power consumption of 950mW. It is supplied in a 100-lead QFP package. FEATURES • 1.8/3.3 V Single Supply Operation • Low power: 950mW (IOUTFS = 20 mA; fDAC = 1 GSPS, 4× Interpolation • DNL = ± 1.5 LSB, INL = ± 5.0 LSB • SFDR =82 dBc to fOUT = 100 MHz • ACLR = 87 dBc @ 80 MHz IF • CMOS data interface with Autotracking Input Timing • Analog Output: Adjustable 10-30mA (RL=25 Ω to 50 Ω) • 100-lead Exposed Paddle TQFP Package • Multiple Chip Synchronization Interface • 84dB Digital Interpolation Filter Stopband Attenuation • Digital Inverse Sinc Filter PRODUCT HIGHLIGHTS Ultra-low noise and Intermodulation Distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies. APPLICATIONS • Wireless Infrastructure Direct Conversion Transmit Diversity • Wideband Communications Systems: Point-to-Point Wireless, LMDS Single-ended CMOS interface supports a maximum input rate of 300 MSPS with 1x interpolation. Manufactured on a CMOS process, the AD9779 uses a proprietary switching technique that enhances dynamic performance. PRODUCT DESCRIPTION The current outputs of the AD9779 can be easily configured for various single-ended or differential circuit topologies. The AD9779 is a dual 16-bit high performance, high frequency FUNCTIONAL BLOCK DIAGRAM SYNC_O SYNC_I Delay Line DATACLK_OUT Delay Line Clock Generation/Distribution Clock Multiplier 2X/4X/8X Data Assembler P1D[15:0] IOUT1_P Sinc-1 I Latch 2X 2X 2X 2X 16-Bit IDAC 2X IOUT1_N n * Fdac/8 n = 1, 2, 3… 7 Q Latch CLK+ CLK- Complex Modulator IOUT2_P 2X 16-Bit QDAC P2D[15:0] Sinc-1 IOUT2_N Digital Controller 10 10 Serial Peripheral Interface Gain Reference & Bias Power-On Reset 10 Offset Offset VREF RSET AUX1_P AUX1_N AUX2_P AUX2_N SCLK CSB 10 SDO SDIO Gain Figure 1 Functional Block Diagram Rev. PrD Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved. AD9779 Preliminary Technical Data TABLE OF CONTENTS Specifications............................................................................................3 Instruction Byte .................................................................................12 DC SPECIFICATIONS ......................................................................3 Serial Interface Port Pin Descriptions ............................................12 DIGITAL SPECIFICATIONS............................................................4 MSB/LSB Transfers ...........................................................................13 AC SPECIFICATIONS.......................................................................4 Notes on Serial Port Operation .......................................................13 Pin Function Descriptions .....................................................................5 SPI Register Map ...............................................................................14 Pin Configuration....................................................................................6 Internal Reference/Full Scale Current Generation.......................22 Interpolation Filter Coefficients............................................................7 Auxiliary DACs..................................................................................22 INTERPOLATION Filter RESPONSE CURVES................................8 Power Down and Sleep Modes........................................................22 CHARACTERIZATION DATA ............................................................9 Internal PLL Clock Multiplier / Clock Distribution.....................23 General Description ..............................................................................12 Timing Information ..........................................................................23 Serial Peripheral Interface................................................................12 Interpolation Filter Architecture.....................................................25 General Operation of the Serial Interface......................................12 EvaLuation Board Schematics..............................................................27 REVISION HISTORY Revision PrA: Initial Version Revision PrB: Updated Page 1 Features, added eval board schematics, SPI register map, filter coefficients and filter response curves Revision PrC: Added characterization data, description of modulation modes, internal clock distribution architecture, timing information Revision PrD: Added more ac characterization data, power dissipation Rev. PrD | Page 2 of 34 Preliminary Technical Data AD9779 SPECIFICATIONS1 DC SPECIFICATIONS (VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED) Parameter Temp Test Level Min RESOLUTION ACCURACY TEMPERATURE DRIFT REFERENCE ANALOG SUPPLY VOLTAGES DIGITAL SUPPLY VOLTAGES POWER CONSUMPTION 16 Bits LSB ±5 Differential Nonlinearity (INL) Unit LSB Offset Error ± TBD % FSR Gain Error (With Internal Reference) ± TBD % FSR Full Scale Output Current Output Compliance Range Output Resistance 10 1.0 ± TBD 20 % FSR 30 TBD mA V kΩ pF Output Capacitance Offset TBD TBD Gain TBD ppm/°C Reference Voltage TBD Internal Reference Voltage Output Current VDDA33 VDDA18 VDDD33 VDDD18 VDDCLK 600 MSPS Standby Power 1.2 100 3.3 1.8 3.3 1.8 1.8 TBD TBD ppm/°C V nA V V V V V mW mW 3.13 1.70 3.13 1.70 1.70 Table 1: DC Specifications 1 Max ± 1.5 Integral Nonlinearity (DNL) Gain Error (Without Internal Reference) ANALOG OUTPUTS Typ Specifications subject to change without notice Rev. PrD | Page 3 of 34 ppm/°C 3.47 1.90 3.47 1.90 1.90 AD9779 Preliminary Technical Data DIGITAL SPECIFICATIONS (VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED) Parameter DAC CLOCK INPUT (CLK+, CLK-) SERIAL PERIPHERAL INTERFACE Temp Test Level Min Differential peak-to-peak Voltage Common Mode Voltage Maximum Clock Rate Maximum Clock Rate (SCLK) Maximum Pulse width high Maximum pulse width low Typ Max 800 400 1 40 TBD TBD Unit mV mV GSPS MHz ns ns Table 2: Digital Specifications AC SPECIFICATIONS (VDD33 = 3.3 V, VDD18 = 1.8 V, MAXIMUM SAMPLE RATE, UNLESS OTHERWISE NOTED) Parameter DYNAMIC PERFORMANCE SPURIOUS FREE DYNAMIC RANGE (SFDR) TWO-TONE INTERMODULATION DISTORTION (IMD) NOISE SPECTRAL DENSITY (NSD) WCDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER WCDMA SECOND ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER Temp Test Level Output Settling Time (tst) (to 0.025%) Output Rise Time (10% to 90%) Output Fall Time (90% to 10%) Output Noise (IoutFS=20mA) fDAC = 100 MSPS, fOUT = 20 MHz fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 70 MHz fDAC = 800 MSPS, fOUT = 70 MHz fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 60 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 100 MHz fDAC = 156 MSPS, fOUT = 60 MHz fDAC = 200 MSPS, fOUT = 80 MHz fDAC = 312 MSPS, fOUT = 100 MHz fDAC = 400 MSPS, fOUT = 100 MHz fDAC = 245.76 MSPS, fOUT = 20 MHz fDAC = 491.52 MSPS, fOUT = 100 MHz fDAC = 491.52 MSPS, fOUT = 200 MHz Min Typ TBD TBD TBD TBD 82 82 84 87 91 88 81 88 -158 -157 -159 -159 80 79 74 fDAC = 245.76 MSPS, fOUT = 60 MHz fDAC = 491.52 MSPS, fOUT = 100 MHz fDAC = 491.52 MSPS, fOUT = 200 MHz 78 80 76 Table 3: AC Specifications Rev. PrD | Page 4 of 34 Max Unit ns ns ns pA/rtHz dBc dBc dBc dBc dBc dBc dBc dBc dBm/Hz dBm/Hz dBm/Hz dBm/Hz dBc dBc dBc dBc dBc dBc Preliminary Technical Data AD9779 PIN FUNCTION DESCRIPTIONS Pin No. Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VDDC18 VDDC18 VSSC VSSC CLK+ CLKVSSC VSSC VDDC18 VDDC18 VSSC VSSC SYNC_I+ SYNC_IVSSD VDDD33 P1D<15> P1D<14> P1D<13> P1D<12> P1D<11> VSSD VDDD18 P1D<10> P1D<9> 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P1D<8> P1D<7> P1D<6> P1D<5> P1D<4> P1D<3> VSSD VDDD18 P1D<2> P1D<1> P1D<0> DATACLK_OUT VDDD33 TXENABLE P2D<15> P2D<14> P2D<13> VDDD18 VSSD P2D<12> P2D<11> P2D<10> P2D<9> P2D<8> P2D<7> Description Pin No. Name 1.8 V Clock Supply 1.8 V Clock Supply Clock Common Clock Common Differential Clock Input Differential Clock Input Clock Common Clock Common 1.8 V Clock Supply 1.8 V Clock Supply Clock Common Clock Common Differential Synchronization Input Differential Synchronization Input Digital Common 3.3 V Digital Supply Port 1 Data Input D15 (MSB) Port 1 Data Input D14 Port 1 Data Input D13 Port 1 Data Input D12 Port 1 Data Input D11 Digital Common 1.8 V Digital Supply Port 1 Data Input D10 Port 1 Data Input D9 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 P2D<6> P2D<5> VDDD18 VSSD P1D<4> P1D<3> P1D<2> P1D<1> P1D<0> VDDD18 VDDD33 SYNC_OSYNC_O+ VSSD PLL_LOCK SPI_SDO SPI_SDIO SPI_CLK SPI_CSB RESET IRQ VSS IPTAT VREF I120 Port 1 Data Input D8 Port 1 Data Input D7 Port 1 Data Input D6 Port 1 Data Input D5 Port 1 Data Input D4 Port 1 Data Input D3 Digital Common 1.8 V Digital Supply Port 1 Data Input D2 Port 1 Data Input D1 Port 1 Data Input D0 (LSB) Data Clock Output 3.3 V Digital Supply Transmit Enable Port 2 Data Input D15 (MSB) Port 2 Data Input D14 Port 2 Data Input D13 1.8 V Digital Supply Digital Common Port 2 Data Input D12 Port 2 Data Input D11 Port 2 Data Input D10 Port 2 Data Input D9 Port 2 Data Input D8 Port 2 Data Input D7 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VDDA33 VSSA VDDA33 VSSA VDDA33 VSSA VSSA IOUT2_P IOUT2_N VSSA AUX2_P AUX2_N VSSA AUX1_N AUX1_P VSSA IOUT1_N IOUT1_P VSSA VSSA VDDA33 VSSA VDDA33 VSSA VDDA33 Table 4: Pin Function Descriptions Rev. PrD | Page 5 of 34 Description Port 2 Data Input D6 Port 2 Data Input D5 1.8 V Digital Supply Digital Common Port 2 Data Input D4 Port 2 Data Input D3 Port 2 Data Input D2 Port 2 Data Input D1 Port 2 Data Input D0 (LSB) 1.8 V Digital Supply 3.3 V Digital Supply Differential Synchronization Output Differential Synchronization Output Digital Common PLL Lock Indicator SPI Port Data Output SPI Port Data Input/Output SPI Port Clock SPI Port Chip Select Bar Reset Interrupt Request Analog Common Reference Current Voltage Reference Output 120 µA Reference Current 3.3 V Analog Supply Analog Common 3.3 V Analog Supply Analog Common 3.3 V Analog Supply Analog Common Analog Common Differential DAC Current Output, Channel 2 Differential DAC Current Output, Channel 2 Analog Common Auxiliary DAC Voltage Output, Channel 2 Auxiliary DAC Voltage Output, Channel 2 Analog Common Auxiliary DAC Voltage Output, Channel 1 Auxiliary DAC Voltage Output, Channel 1 Analog Common Differential DAC Current Output, Channel 1 Differential DAC Current Output, Channel 1 Analog Common Analog Common 3.3 V Analog Supply Analog Common 3.3 V Analog Supply Analog Common 3.3 V Analog Supply AD9779 Preliminary Technical Data VDDA33 VSSA VDDA33 VSSA VDDA33 VSSA VSSA IOUT1_P IOUT1_N VSSA AUX1_P AUX1_N VSSA AUX2_N AUX2_P VSSA IOUT2_N IOUT2_P VSSA VSSA VDDA33 VSSA VDDA33 VSSA VDDA33 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PIN CONFIGURATION VDDC18 1 75 I120 VDDC18 2 74 VREF VSSC 3 73 IPTAT VSSC 4 72 VSS CLK+ 5 71 IRQ CLK- 6 70 RESET VSSC 7 69 SPI_CSB VSSC 8 68 SPI_CLK VDDC18 9 67 SPI_SDI VDDC18 10 66 SPI_SDO VSSC 11 65 PLL_LOCK VSSC 12 64 SYNC_I+ 13 SYNC_I- Analog Domain Digital Domain AD9779 VSSD 50 P2D<7> P2D<6> 49 51 P2D<8> 25 48 P1D<9> P2D<9> P2D<5> 47 52 P2D<10> 24 46 P1D<10> P2D<11> VDDD18 45 53 P2D<12> 23 44 VDDD18 VSSD VSSD 43 54 VDDD18 22 42 VSSD P2D<13> P2D<4> 41 55 P2D<14> 21 40 P1D<11> P2D<15> P2D<3> 39 56 TXEnable 20 38 P1D<12> VDDD33 P2D<2> 37 57 DCLK 19 36 P1D<13> P1D<0> P2D<1> 35 58 P1D<1> 18 34 P1D<14> P1D<2> P2D<0> 33 59 VDDD18 17 32 P1D<15> VSSD VDDD18 31 60 P1D<3> 16 30 VDDD33 P1D<4> VDDD33 29 61 P1D<5> 15 28 VSSD P1D<6> SYNC_O- P1D<7> 62 27 14 26 SYNC_O+ P1D<8> 63 Figure 2. Pin Configuration Rev. PrD | Page 6 of 34 Preliminary Technical Data AD9779 INTERPOLATION FILTER COEFFICIENTS Table 5: Halfband Filter 1 Lower Upper Coefficient Coefficient H(1) H(55) H(2) H(54) H(3) H(53) H(4) H(52) H(5) H(51) H(6) H(50) H(7) H(49) H(8) H(48) H(9) H(47) H(10) H(46) H(11) H(45) H(12) H(44) H(13) H(43) H(14) H(42) H(15) H(41) H(16) H(40) H(17) H(39) H(18) H(38) H(19) H(37) H(20) H(36) H(21) H(35) H(22) H(34) H(23) H(33) H(24) H(32) H(25) H(31) H(26) H(30) H(27) H(29) H(28) Integer Value -4 0 13 0 -34 0 72 0 -138 0 245 0 -408 0 650 0 -1003 0 1521 0 -2315 0 3671 0 -6642 0 20755 32768 Table 6: Halfband Filter 2 Lower Upper Coefficient Coefficient H(1) H(23) H(2) H(22) H(3) H(21) H(4) H(20) H(5) H(19) H(6) H(18) H(7) H(17) H(8) H(16) H(9) H(15) H(10) H(14) H(11) H(13) H(12) Integer Value -2 0 17 0 -75 0 238 0 -660 0 2530 4096 Table 7: Halfband Filter 3 Lower Upper Coefficient Coefficient H(1) H(15) H(2) H(14) H(3) H(13) H(4) H(12) H(5) H(11) H(6) H(10) H(7) H(9) H(8) Integer Value -39 0 273 0 -1102 0 4964 8192 Table 8: Inverse Sinc Filter Lower Upper Coefficient Coefficient H(1) H(9) H(2) H(8) H(3) H(7) H(4) H(6) H(5) Integer Value 2 -4 10 -35 401 Rev. PrD | Page 7 of 34 AD9779 Preliminary Technical Data INTERPOLATION FILTER RESPONSE CURVES 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -4 -3 -2 -1 0 1 2 3 4 Figure 3. AD9779 2x Interpolation, Low Pass Response to ±4x Input Data Rate (Dotted Lines Indicate 1dBRoll-Off) 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -4 -3 -2 -1 0 1 2 3 4 Figure 4. AD9779 4x Interpolation, Low Pass Response to ±4x Input Data Rate (Dotted Lines Indicate 1dBRoll-Off) 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -4 -3 -2 -1 0 1 2 3 4 Figure 5.AD9779 8x Interpolation, Low Pass Response to ±4x Input Data Rate (Dotted Lines Indicate 1dBRoll-Off) Rev. PrD | Page 8 of 34 Preliminary Technical Data AD9779 CHARACTERIZATION DATA 6 100 5 95 4 90 3 85 SFDR - dBm INL (LSBs) 2 1 0 -1 80 75 70 -2 65 -3 60 -4 55 F D ATA =100MSPS F D ATA =200MSPS F D ATA =160MSPS 50 -5 0 8192 16384 24576 32768 40960 49152 57344 65536 0 Code 20 40 60 80 100 Fout - MHz Figure 6. AD9779 Typical INL Figure 9. SFDR vs. FOUT, 2x Interpolation 2 100 F D ATA =125MSPS F D ATA =100MSPS 95 1.5 90 85 SFDR - dBm DNL (LSBs) 1 0.5 0 80 75 F D ATA =200MSPS 70 F D ATA =150MSPS 65 60 -0.5 55 50 -1 0 8192 16384 24576 32768 40960 49152 57344 65536 0 20 40 60 80 Code Fout - MHz Figure 7. AD9779 Typical DNL Figure 10. SFDR vs. FOUT, 4x Interpolation 100 100 F D ATA =160MSPS F D ATA =100MSPS F D ATA =200MSPS F D ATA =62.5MSPS 50MSPS 90 80 SFDR - dBm SFDR - dBm 90 70 60 80 75MSPS 70 100MSPS 60 50 0 20 40 60 80 100 Fout - M Hz 50 0 10 20 30 Fout - M Hz Figure 8. SFDR vs. FOUT, 1x Interpolation Figure 11. SFDR vs. FOUT, 8x Interpolation Rev. PrD | Page 9 of 34 40 50 AD9779 Preliminary Technical Data 100.0 F D ATA =200MSPS 100 90.0 90 IMD - dBc IMD - dBc 100MSPS 80.0 F D ATA =160MSPS 70.0 80 112.5MSPS 75MSPS 50MSPS 70 F D ATA =62.5MSPS 60 60.0 50 0 50 100 150 50.0 0 20 40 60 200 250 300 350 400 70 80 450 Fout - MHz 80 Figure 15. Third Order IMD vs. FOUT, 8x Interpolation Fout - MHz Figure 12. Third Order IMD vs. FOUT, 1x Interpolation 100.0 -150 F D ATA =200MSPS -152 NSD - dBm/Hz IMD - dBc 80.0 F D ATA =160MSPS 70.0 F D ATA =156MSPS F D ATA =78MSPS -154 90.0 -156 -158 -160 -162 F D ATA =200MSPS -164 -166 -168 60.0 -170 0 10 20 30 50.0 0 20 40 60 80 100 120 140 160 180 40 50 60 90 Fout - M Hz 200 Fout - MHz Figure 16. Noise Spectral Density vs. FOUT, 1x Interpolation Figure 13. Third Order IMD vs. FOUT, 2x Interpolation 100 -150 F D ATA =125MSPS F D ATA =156MSPS -152 90 -154 70 F D ATA =78MSPS -156 F D ATA =200MSPS 80 NSD - dBm /Hz IMD - dBc F D ATA =150MSPS F D ATA =100MSPS 60 50 -158 -160 -162 -164 -166 0 40 80 120 160 200 240 280 320 360 400 F D ATA =200MSPS -168 Fout - MHz -170 0 Figure 14. Third Order IMD vs. FOUT, 4x Interpolation 20 40 60 80 100 120 140 Fout - MHz Figure 17. Noise Spectral Density vs. FOUT, 2x Interpolation Rev. PrD | Page 10 of 34 160 180 Preliminary Technical Data AD9779 0.7 -90 8x Interpolation -85 F D ATA =122.88MSPS 0.6 4x Interpolation -75 4x Interpolation, Zero Stuffing 8x Interpolation, Zero Stuffing 0.5 2x Interpolation, Zero Stuffing -70 F D ATA =61.44MSPS -65 Power - W ACLR - dBc -80 -60 -55 0.4 2x Interpolation 1x Interpolation, Zero Stuffing 0.3 -50 1x Interpolation 0 20 40 60 80 100 120 140 160 180 200 220 0.2 240 260 280 300 Fout - M Hz 0.1 Figure 18. ACLR for 1st Adjacent Band WCDMA, 4x Interpolation. On-Chip Modulation is used to translate baseband signal to IF. 0 0 25 50 75 100 -85 150 175 200 225 250 Figure 21. Power Dissipation, Single DAC Mode F D ATA =122.88MSPS -80 ACLR - dBc 125 F DAT A (MSPS) -90 1.1 8x Interpolation,F DA C/4 Modulation -75 1 -70 8x Interpolation,F DA C/2 Modulation 0.9 8x Interpolation,F DA C/8 Modulation 4x Interpolation,F DA C/4 Modulation 8x Interpolation,Modulation off 4x Interpolation,F DA C/2 Modulation F D ATA =61.44MSPS -65 4x Interpolation,Modulation off 0.8 -60 -55 -50 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 Power - W 0.7 0.6 2x Interpolation, Zero Stuffing 4x Interpolation, Zero Stuffing 8x Interpolation, Zero Stuffing 2x Interpolation,F DA C/2 Modulation 2x Interpolation,Modulation off 0.5 1x Interpolation, Zero Stuffing 0.4 Fout - MHz Figure 19. ACLR for 2nd Adjacent Band WCDMA, 4x Interpolation. On-Chip Modulation is used to translate baseband signal to IF. 1x Interpolation 0.3 0.2 0.1 -90 0 -85 F D ATA =122.88MSPS 0 ACLR - dBc -80 25 50 75 100 125 150 175 200 225 250 F DATA (M SPS) -75 Figure 22. Power Dissipation, Dual DAC Mode -70 -65 0.16 F D ATA =61.44MSPS -60 0.14 -55 0.12 -50 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 Fout - M Hz 0.1 Power - W 0 Figure 20. ACLR for 3rd Adjacent Band WCDMA, 4x Interpolation. On-Chip Modulation is used to translate baseband signal to IF. 0.08 0.06 0.04 0.02 0 0 200 400 600 800 1000 FDAC - M SPS Figure 23. Power Dissipation of Inverse Sinc Filter Rev. PrD | Page 11 of 34 1200 AD9779 Preliminary Technical Data GENERAL DESCRIPTION The AD9779 combines many features which make it make it a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface with common quadrature modulators when designing single sideband transmitters. The speed and performance of the AD9779 allow wider bandwidths/more carriers to be synthesized than with previously available DACs. The digital engine in the AD9779 uses a breakthrough filter architecture that combines the interpolation with a digital quadrature modulator. This allows the AD9779 to do digital quadrature frequency up conversion. The AD9779 also has features which allow simplified synchronization with incoming data, and also allows multiple AD9779s to be synchronized. SPI_SDO (pin 66) SPI_SCLK (pin 68) Instruction Byte The instruction byte contains the information shown in Error! Reference source not found.. MSB I7 R/W Serial Peripheral Interface SPI_SDI (pin 67) The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9779 and the system controller. Phase 2 of the communication cycle is a transfer of 1, 2, 3, or 4 data bytes as determined by the instruction byte. Using one multibyte transfer is the preferred method. Single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte. I6 N1 I5 N0 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0 Table 9. SPI Instruction Byte AD9779 SPI PORT SPI_CSB (pin 69) Figure 24. AD9779 SPI Port The AD9779 serial port is a flexible, synchronous serial communications port allowing easy interface to many industrystandard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI® and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9779. Single or multiple byte transfers are supported, as well as MSB first or LSB first transfer formats. The AD9779’s serial interface port can be configured as a single pin I/O (SDIO) or two unidirectional pins for in/out (SDIO/SDO). General Operation of the Serial Interface There are two phases to a communication cycle with the AD9779. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9779, coincident with the first eight SCLK rising edges. The instruction byte provides the AD9779 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9779. A logic high on the CS pin, followed by a logic low, will reset the SPI port timing to the initial state of the instruction cycle. This is true regardless of the present state of the internal registers or the other signal levels present at the inputs to the SPI port. If the SPI port is in the midst of an instruction cycle or a data transfer cycle,none of the present data will be written. R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer will occur after the instruction byte write. Logic high indicates read operation. Logic 0 indicates a write operation. N1, N0, Bits 6 and 5 of the instruction byte, determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table 10. A4, A3, A2, A1, A0, Bits 4, 3, 2, 1, 0 of the instruction byte, determine which register is accessed during the data transfer portion of the communications cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9779 based on the LSBFIRST bit (REG00, bit 6). N1 0 0 1 1 N2 0 1 0 1 Description Transfer 1 Byte Transfer 2 Bytes Transfer 3 Bytes Transfer 4 Bytes Table 10. Byte Transfer Count Serial Interface Port Pin Descriptions SCLK—Serial Clock. The serial clock pin is used to synchronize data to and from the AD9779 and to run the internal state machines. SCLK’s maximum frequency is 20 MHz. All data input to the AD9779 is registered on the rising edge of SCLK. All data is driven out of the AD9779 on the falling edge of SCLK. CSB—Chip Select. Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. The SDO and SDIO pins will go to a high impedance state when this input is high. Chip select should stay low during the entire communication cycle. SDIO—Serial Data I/O. Data is always written into the AD9779 on Rev. PrD | Page 12 of 34 Preliminary Technical Data AD9779 SDO—Serial Data Out. Data is read from this pin for protocols that use separate lines for transmitting and receiving data. In the case where the AD9779 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. INSTRUCTION CYCLE DATA TRANSFER CYCLE CSB SCLK SDIO R/W N0 N1 A0 A1 A2 A3 A4 SDO D7 D6N D5N D30 D20 D10 D00 D7 D6N D5N D30 D20 D10 D00 03152-0-004 this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of register address 00h. The default is Logic 0, which configures the SDIO pin as unidirectional. MSB/LSB Transfers Figure 25. Serial Register Interface Timing MSB First When LSBFIRST = 1 (LSB first) the instruction and data bytes must be written from least significant bit to most significant bit. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte followed by multiple data bytes. The serial port internal byte address generator increments for each byte of the multibyte communication cycle. DATA TRANSFER CYCLE CSB SCLK SDIO A0 A1 A2 A3 A4 N1 N0 R/W D00 D10 D20 D4N D5N D6N D7N D00 D10 D20 D4N D5N D6N D7N SDO 03152-0-005 When LSBFIRST = 0 (MSB first) the instruction and data bytes must be written from most significant bit to least significant bit. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow in order from high address to low address. In MSB first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. INSTRUCTION CYCLE Figure 26. Serial Register Interface Timing LSB First tDS tSCLK CSB tPWH tPWL SCLK tDS SDIO tDH INSTRUCTION BIT 7 INSTRUCTION BIT 6 03152-PrD-006 The AD9779 serial port can support both most significant bit (MSB) first or least significant bit (LSB) first data formats. This functionality is controlled by register bit LSBFIRST (REG00, bit 6). The default is MSB first (LSBFIRST = 0). Figure 27. Timing Diagram for SPI Register Write CSB SCLK tDV SDIO SDO DATA BIT n DATA BIT n–1 Figure 28. Timing Diagram for SPI Register Read Notes on Serial Port Operation The AD9779 serial port configuration is controlled by REG00, bits 6 and 7 . It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. The same considerations apply to setting the software reset, RESET (REG00, bit 5). All registers are set to their default values EXCEPT REG00 and REG04 which remain unchanged. Use of only single byte transfers when changing serial port configurations or initiating a software reset is recommended to prevent unexpected device behavior. Rev. PrD | Page 13 of 34 03152-PrD-007 The AD9779 serial port controller data address will decrement from the data address written toward 0x00 for multibyte I/O operations if the MSB first mode is active. The serial port controller address will increment from the data address written toward 0x1F for multibyte I/O operations if the LSB first mode is active. AD9779 Preliminary Technical Data SPI Register Map Register Name Address Bit 7 Bit 6 LSB,MSB First Bit 5 Bit 4 Software Reset Power Down Mode Bit 3 00h 00 SDIO Bidirectional Digital Control Register 01h 01 Filter Interpolation Factor <1: 0> Filter Interpolation Mode <4:0> 02h 02 Data Format Real Mode 03h 03 Data Delay Mode <1:0> 04h 04 Sync Out Delay <3:0> 05h 05 Sync Enable Sync Driver Enable Dac Clock Offset <2:0> Interrupt Register 06h 06 Data Delay IRQ Sync Delay IRQ Cross Control IRQ PLL Control 07h 07 PLL Band Select <4:0> 08h 08 PLL Enable PLL Output Freq Divide <1:0> Misc. Control Register 09h 24 PLL Error Source PLL Ref Bypass I DAC Control Register 0Ah 09 IDAC Gain Adjustment <7:0> 0Bh 10 IDAC SLEEP 0Ch 11 Auxiliary DAC1 Data <7:0> 0Dh 12 Auxiliary DAC1 Sign 0Eh 13 QDAC Gain Adjustment <7;0> 0Fh 14 QDAC SLEEP Sync Control Aux 1 DAC Control Register Q DAC Control Register Inverse Sinc Enable Data Clock Delay <2:0> Bit 0 DATACLK Invert IQ Select Invert Zero Stuffing Enable 00h Q First 00h Data Window Delay <2:0> 00h 00h 00h Data Delay IRQ Enable PLL Loop Freq Divide <1:0> PLL Gain <2:0> Default 00h Sync Window Delay <3:0> Cross Control IRQ Enable 00h PLL Loop Cap Select <2:0> CFh PLL Loop Filter Pole/Zero <2:0> 37h PLL Bias <2:0> 38h Sync Delay IRQ Enable F9h IDAC Power Down Auxiliary DAC1 Current Direction Bit 1 PLL Lock Indicator Auto Power Down Enable Comm Register One Port Mode Bit 2 IDAC Gain Adjustment <9:8> 01h 00h Auxiliary DAC1 Sleep Auxiliary DAC1 Data <9:8> 00h F9h QDAC Sleep QDAC Gain Adjustment <9:8> Rev. PrD | Page 14 of 34 01h Preliminary Technical Data AD9779 10h 15 Auxiliary DAC2 Data <7:0> 11h 16 Auxiliary DAC2 Sign 12h 17 Cross Updel <7:0> 00h 13h 18 Cross Dndel <7:0> 00h 14h 19 Cross Clock Divide <3:0> 15h 20 Cross Run Analog Write 16h 23 Analog Write <7:0> Analog Control Register 17h 21 Mirror Roll Off <1:0> 18h 22 Stack Headroom Control<7:0> CAh Analog Status Register 19h 25 Analog Status <7:0> --h Test 1 Register 1Ah 26 MISR Enable Test 2 Register 1Bh 27 BIST<31:24> --h 1Ch 28 BIST<23:16> --h 1Dh 29 BIST<15:8> --h 1Eh 30 BIST<7:0> --h Aux 2 DAC Control Register Cross Register Auxiliary DAC2 Current Direction Cross Status MISR IQ Select 00h Auxiliary DAC2 Data <9:8> Auxiliary DAC2 Power Down Cross Wiggle Delay <3:0> Cross Done Cross Wiggle <2:0> 00h 00h Cross Step <1:0> 00h 00h Band Gap Trim <2:0> MISR Samples Internal Data Enable Table 11: SPI Register Map Rev. PrD | Page 15 of 34 Test Mode <2:0> 00h 00h AD9779 Register (hex) 00 Comm Register Preliminary Technical Data Bits 7 Name SDIO Bidirectional 6 LSB/MSB First 5 4 Software RESET Power Down Mode 3 Auto Power Down Enable PLL LOCK (read only) 1 01 Digital Path Filter Control 02 General Mode Control 03 Data Clock Delay 04 Synchronization Delay 05 Chip Sync and Data Delay Control 7:6 Filter Interpolation Rate 5:2 0 Control Halfband Filters 1,2,3 Zero Stuffing 7 Data Format 6 One Port Mode 5 Real Mode 3 Inverse Sinc Enable 2 DATACLK Invert 1 IQ Select Invert 0 Q First 7:6 Data Delay Mode 5:3 2:0 7 Data Clock Delay Data Window Delay Sync Output Delay Sync Window Delay Sync Enable 6 Sync Driver Enable 5:3 DAC Clock Offset 7:4 3:0 Function 0: Use SDIO pin as input data only 1: Use SDIO as both input and output data 0: First bit of serial data is MSB of data byte 1: First bit of serial data is LSB of data byte Bit must be written with a 1, then 0 to soft reset SPI register map 0: All circuitry is active 1: Disable all digital and analog circuitry, only SPI port is active Default 0 0 0 0 0 0: PLL is not locked 1: PLL is locked 00: 1x interpolation 01: 2x interpolation 10: 4x interpolation 11: 8x interpolation See Table 13 for filter modes 0: Zero stuffing off 1: Zero stuffing on 0: Signed binary 1: Unsigned binary 0: Both input data ports receive data 1: Data port 1 only receives data 0: Enable Q path for signal processing 1: Disable Q path data (clocks disabled) 0: Inverse sinc disabled 1: Inverse sinc disabled 0: Output DATACLK same phase as internal capture clock 1: Output DATACLK opposite phase as internal capture clock 0: TxEnable (pin 39) =1, routes input data to I channel TxEnable (pin 39) =0, routes input data to Q channel 1: TxEnable (pin 39) =1, routes input data to Q channel TxEnable (pin 39) =0, routes input data to I channel 0: First byte of data is always I data at beginning of transmit 1: First byte of data is always Q data at beginning of transmit 00: Manual, no error correction 01: Manual, continuous error correction 10: automatic, one pass check 11: automatic, continuous pass check Data Clock delay control Window delay control 0 00 0000 0 0 0 0 0 0 0 00 000 000 0000 0000 0: LVDS and synchronization rceiver logic off 1: LVDS and synchronization rceiver logic on 0: LVDS driver off 1: LVDS driver on 0 0 0 Rev. PrD | Page 16 of 34 Preliminary Technical Data 06 IRQ Status 7 6 5 3 2 1 07 PLL Band and Divide 7:3 2:0 08 PLL Enable and Charge Pump Control 09 Misc. Control 0A IDAC Gain 0B IDAC Gain and Control 0C Auxiliary DAC1 Gain 7 Data Delay Error (read only) Chip Synchronization Delay Error (read only) Cross Control Error (read only) Data Delay Error Enable Chip Synchronization Error Enable Cross Control Error Enable PLL Band Select See Table 14 for values. PLL Ripple Cap Adjust PLL Enable 6:5 PLL Output Divide Ratio 4:3 PLL Loop Feedback Divide Ratio 2:0 PLL Loop Filter Bandwidth Tuning Recommended Settings. See Table 14 for PLL Band Select values. PLL Error Bit Source 7 6 PLL Reference Bypass 5:3 VCO AGC Gain Control. See Table 14 for PLL Band Select values. 2:0 PLL Bias Current Level/Trim IDAC Gain Adjustment 7:0 7 IDAC Sleep 6 IDAC Power Down 1:0 IDAC Gain Adjustment Aux DAC1 Gain Adjustment 7:0 AD9779 0 0 0 0 0 0 11001 111 0: PLL off, DAC rate clock supplied by outside source 1: PLL on, DAC rate clock synthesized internally from data rate clock via PLL clock multiplier 00: Divide by 1 01: Divide by 2 10: Divide by 4 11: Divide by 8 00: Divide by 1 01: Divide by 2 10: Divide by 4 11: Divide by 8 000: PLL band select 00000-00111 100: PLL band select 01000-01111 110: PLL band select 10000-10111 111: PLL band select 11000-11111 0 0: Phase error detect 1: Range limit 0: Use PLL reference 1: Use DAC reference 000: PLL band select 00000-00111 100: PLL band select 01000-01111 110: PLL band select 10000-10111 111: PLL band select 11000-11111 0 01 10 111 0 111 000 (7:0) LSB slice of 10 bit gain setting word for IDAC 11111001 0: IDAC on 1: IDAC off 0: IDAC on 1: IDAC off (9:8) MSB slice of 10 bit gain setting word for IDAC 0 01 (7:0) LSB slice of 10 bit gain setting word for Aux DAC1 00000000 Rev. PrD | Page 17 of 34 0 AD9779 0D Auxiliary DAC1 Control and Data 0E QDAC Gain 0F QDAC Gain and Control 10 Auxiliary DAC2 Gain 11 Auxiliary DAC2 Control and Data 12 Cross Point Upper Delay 13 Cross Point Upper Delay 14 Wiggle Delay for Cross Point Control 15 Cross Point Control 16 Analog Write 17 Mirror Roll off and band gap Trim Preliminary Technical Data 7 Aux DAC1 Sign 6 Aux DAC1 Direction 5 Aux DAC1 Sleep 1:0 Aux DAC1 Gain Adjustment QDAC Gain Adjustment 7:0 7 QDAC Sleep 6 QDAC Power Down 1:0 QDAC Gain Adjustment Aux DAC2 Gain Adjustment 7:0 0 00 (7:0) LSB slice of 10 bit gain setting word for QDAC 11111001 0: QDAC on 1: QDAC off 0: QDAC on 1: QDAC off (9:8) MSB slice of 10 bit gain setting word for QDAC 0 01 (7:0) LSB slice of 10 bit gain setting word for Aux DAC2 00000000 0: Positive 1: Negative 0: Source 1: Sink 0: Aux DAC1 on 1: Aux DAC 1 off (9:8) MSB slice of 10 bit gain setting word for Aux DAC2 0 00 Value above zero for upper cross delay (bits 7,6, unused) 00000000 0 0 0 7 Aux DAC2 Sign 6 Aux DAC2 Direction 5 Aux DAC2 Sleep 1:0 7:0 Aux DAC2 Gain Adjustment Updelay 7:0 Dndelay Value below zero for lower cross delay (bits 7,6, unused) 00000000 7:3 Cross Control Clock Delay Wiggle Delay Cross Run Divide rate of CNTCLK by 2^(3:0), CNTCLK = 1/16 DAC clock rate 00000 Time step in 2^(Wiggle Delay) CNTCLK cycles 0: Disables Cross Control loop 1: Enables Cross Control loop 0: Control loop is lowering cross point 1: Control loop is raising cross point 0: Control loop is chnaging cross point value 1: Control loop is holding cross point value (2:0) Number of iterations allowed in control loop (1:0) Value to change cross point value per iteration (wiggle) Provides extra writeable control registers for analog circuit 000 0 2:0 7 6 Cross Status (read only) 5 Cross Done (read only) 4:2 1:0 7:0 Cross Wiggle Cross Step Analog Write 7:6 Mirror Roll off Frequency Band Gap Trim Temperature Characteristic 2:0 18 Output Stack headroom Control 19 Analog Status 0: Positive 1: Negative 0: Source 1: Sink 0: Aux DAC1 on 1: Aux DAC 1 off (9:8) MSB slice of 10 bit gain setting word for Aux DAC1 7:0 Analog Status 0 0 0 0 000 00 00000000 00 000 Output stack headroom control Overdrive (current density) trim (temperature packing) Reference offset from VDD3V (vcas centering) Provides extra status register for analog circuitry (unused, read only) Rev. PrD | Page 18 of 34 Preliminary Technical Data 1A MISR Control 1B MISR Signature Register 1 1C MISR Signature Register 2 1D MISR Signature Register 3 1E MISR Signature Register 4 AD9779 7 MISR Enable 6 MISR IQ Select 5 MISR Samples 3 Internal Data Enable 2:0 Test Mode 7:0 MISR Signature 0: MISR disabled 1: MISR Enabled 0: Read back I path signature 1: Read back Q path signature 0: MISR uses short sample period 1: MISR uses long sample period 0: Internal data generator off 1: Internal data generator on 000: Normal data port operation 001-111: To be defined test modes (31:24) Slice of 32 bit MISR signature 7:0 MISR Signature (23:16) Slice of 32 bit MISR signature 7:0 MISR Signature (15:8) Slice of 32 bit MISR signature 7:0 MISR Signature (7:0) Slice of 32 bit MISR signature Table 12: SPI RegisterDescription Rev. PrD | Page 19 of 34 0 0 0 0 000 AD9779 Preliminary Technical Data Interp. Factor <7:6> Filter Mode <5:2> Filter1 mode (Mode_F1) Nyquist Zone Passband F_low 8 00h 0 0 0 DC_odd 1 -0.05 0 0.05 8 01h 1 1 0 DC_even 2 0.0125 0.0625 0.1125 8 02h 2 2 1 F/8_odd 3 0.075 0.125 0.175 8 03h 3 3 2 F/8_even 4 0.1375 0.1875 0.2375 8 04h 0 4 2 2F/8_odd 5 0.2 0.25 0.3 8 05h 1 5 2 2F/8_even 6 0.2625 0.3125 0.3625 8 06h 2 6 3 3F/8_odd 7 0.325 0.375 0.425 8 07h 3 7 4 3F/8_even 8 0.3875 0.4375 0.4875 8 08h 0 0 4 -4F/8_even -8 0.45 0.5 0.55 8 09h 1 1 4 -4F/8_odd -7 0.5125 0.5625 0.6125 8 0Ah 2 2 5 -3F/8_even -6 0.575 0.625 0.675 8 0Bh 3 3 6 -3F/8_odd -5 0.6375 0.6875 0.7375 8 0Ch 0 4 6 -2F/8_even -4 0.7 0.75 0.8 8 0Dh 1 5 6 -2F/8_odd -3 0.7625 0.8125 0.8625 8 0Eh 2 6 7 -F/8_even -2 0.825 0.875 0.925 8 0Fh 3 7 0 -F/8_odd -1 0.8875 0.9375 0.9875 4 00h 0 0 OFF DC_odd 1 -0.1 0 0.1 4 01h 1 1 OFF DC_even 2 0.025 0.125 0.225 4 02h 2 2 OFF F/4_odd 3 0.15 0.25 0.35 4 03h 3 3 OFF F/4_even 4 0.275 0.375 0.475 4 04h 0 4 OFF -F/2_even -4 0.4 0.5 0.6 4 05h 1 5 OFF -F/2_odd -3 0.525 0.625 0.725 4 06h 2 6 OFF -F/4_even -2 0.65 0.75 0.85 4 07h 3 7 OFF -F/4_odd -1 0.775 0.875 0.975 2 00h 0 OFF OFF DC_odd 1 -0.2 0 0.2 2 01h 1 OFF OFF DC_even 2 0.05 0.25 0.45 2 02h 2 OFF OFF -F/2_even -1 0.3 0.5 0.7 2 03h 3 OFF OFF -F/2_odd -2 0.55 0.75 0.95 Filter2 mode (Mode_F2) Filter3 mode (Mode_F3) Modulation Table 13: Interpolation Filter Modes, see Reg 01, bits 5 :2 Rev. PrD | Page 20 of 34 Center F_High (Freq. Normalized to FDAC) In 8x interpolation, BW=0.0375(0.1* FDAC) Worst case: F/32 In 8x interpolation, BW=0.075-(0.2* FDAC) Worst case: F/16 In 2x Interpolation BW=0.15-0.4 FDAC Worst case: F/8 Preliminary Technical Data PLL Frequency Band Select AD9779 00110 (6) 1525 – 1597 PLL Band Select Value Frequency in MHz 00101 (5) 1560 – 1632 11111 (31) 804 – 850 00100 (4) 1594 – 1667 11110 (30) 827 – 875 00011 (3) 1629 – 1702 11101 (29) 850 – 899 00010 (2) 1665 – 1737 11100 (28) 875 – 925 00001 (1) 1700 – 1773 11011 (27) 899 – 951 00000 (0) 1735 – 1810 11010 (26) 925 – 977 11001 (25) 951 – 1005 11000 (24) 977 – 1032 10111 (23) 1004 – 1061 10110 (22) 1032 – 1089 10101 (21) 1060 – 1119 10100 (20) 1089 – 1149 10011 (19) 1118 – 1179 10010 (18) 1148 – 1210 10001 (17) 1176 – 1239 10000 (16) 1206 – 1270 01111 (15) 1237 – 1302 01110 (14) 1268 – 1334 01101 (13) 1299 – 1366 01100 (12) 1331 – 1399 01011 (11) 1363 – 1432 01010 (10) 1396 – 1466 01001 (9) 1425 – 1495 01000 (8) 1458 – 1529 00111 (7) 1492 – 1563 Table 14. VCO Frequency Range vs. PLL Band Select Value Rev. PrD | Page 21 of 34 AD9779 Preliminary Technical Data Internal Reference/Full Scale Current Generation Auxiliary DACs Full scale current on the AD9779 IDAC and QDAC can be set from 10 to 30ma. Initially, the 1.2V bandgap reference is used to set up a current in an external resistor connected to I120 (pin 75). A simplified block diagram of the AD9779 reference circuitry is given below in Figure 29. The recommended value for the external resistor is 10K Ω, which sets up an I REFERENCE in the resistor of 120µa. Internal current mirrors provide a current gain scaling, where IDAC or QDAC gain is a 10 bit word in the SPI port register (registers 0A, 0B, 0E, and 0F). The default value for the DAC gain registers gives an IFS of 20ma. Two auxiliary DACs are provided on the AD9779. The full scale output current on these DACs is derived from the 1.2V bandgap reference and external resistor. The gain scale from the reference amplifier to the DAC reference current for each aux DAC is 16.67. with the Aux DAC gain set to full scale (10 bit values, SPI reg 0C, 0D, 10, 11), this gives a full scale current of 2ma for Aux DAC1 and for Aux DAC2. Through these same SPI port registers, the Aux DACs can be turned off, their signs can be inverted (scale is reversed, 0-1024 gives IFS to 0), and they can be programmed for sourcing or sinking current. When sourcing current, the output compliance voltage is 0-1.5V, and when sinking current the output compliance voltage is 0.8-1.5V. VREF AD9779 IDAC gain 1.2V bandgap IDAC DAC full scale reference current current scaling I120 0.1µF QDAC QDAC gain 10KΩ Figure 29 . Reference Circuitry where IFS is equal to; The Aux DACs can be used for LO cancellation when the DAC output is followed by a quadrature. A typical DAC to Quadrature Modulator interface is given in Figure 31. Often, the input common mode voltage for the modulator is much higher than the output compliance range of the DAC, so that ac coupling is necessary. The input referred offset voltage of thee quadrature modulator can result in LO feed through on the modulator output, degrading system, performance. If the configuration of Figure 29 is used, the Aux DACs can be used to compensate for the input DC offset of the quad mod, thus reducing LO feedthrough. 1.2V ⎛ 27 ⎛ 6 ⎞⎞ × ⎜⎜ +⎜ × DAC gain ⎟ ⎟⎟ × 32 R 12 1024 ⎝ ⎠⎠ ⎝ AUX DAC1 35 IOUT1_P AUX1_P AUX1_N 30 IDAC IFS (ma) 25 Quad Mod I Inputs IOUT1_N 20 Quad Mod Q Inputs IOUT2_P 15 QDAC 10 IOUT2_N 5 AUX2_P 0 0 200 400 600 800 AUX2_N 1000 DAC gain code AUX DAC2 Figure 30. IFS vs. DAC Gain Code Figure 31. Typical Use of Auxiliary DACs Power Down and Sleep Modes The AD9779 has a variety of power down modes, so that the digital engine, main TxDACs, or auxiliary DACs can be powered down individually, or all at once. Via the SPI port, the main TxDACs can be placed in sleep or powered down modes. In sleep mode, the TxDAC output is turned off, thus reducing power dissipation. The reference remains powered on though, so that recovery from sleep mode is very fast. When the TxDAC is placed in Power Down mode, the TxDAC and 1.2V bandgap reference are turned off. This mode offers more substantial power savings than in sleep mode, but the time to turn on is much longer. The Auxiliary DACs also have the capability to be programmed via the SPI port into sleep mode. Rev. PrD | Page 22 of 34 Preliminary Technical Data AD9779 2. The power down bit (register 00h, bit 4) controls the power down function for the digital section of the AD9779. The power down function in bit 4 works in conjunction with TxEnable (pin 39) according to the following; PLL Disabled (reg 08h, bit 7=0) – The PLL enable switch in Figure 32 is connected to the Reference Clock Input. The differential reference clock input will be the DAC output sample rate and N3 will determine the interpolation rate. TxEnable = 0:PWDWN= 0: Flush data path with zeroes 1: Digital engine in power down state, DACs and reference are not affected. 1: Normal operation Internal PLL Clock Multiplier / Clock Distribution The internal clock structure on the AD9779 allows the user to drive the differential clock inputs with a clock at 1x or an integer multiple of the input data rate, or at the DAC output sample rate. A PLL internal to the AD9779 provides input clock multiplication and provides all of the internal clocks required for the interpolation filters and data synchronization. The internal clock architecture is shown in Figure 32. The reference clock is the differential clock at pins 5 and 6. This clock input can be run differentially, or singled ended by driving pin 5 with a clock signal, and biasing pin 6 to the mid swing point of the signal at pin 5. There are various configurations in which this clock architecture can be run; 1. Figure 32. Internal Clock Architecture of AD9779 Timing Information Figure 33 through Figure 35 show some of the various timing possibilities when the PLL is enabled. The combination of the settings of N2 and N3 means that the reference clock frequency may be a multiple of the actual input data rate. Figure 33 through Figure 35 show, respectively, what the timing looks like when N2/N3 = 1, 2, and 4. PLL Enabled (reg 08h, bit 7=1) – The PLL enable switch in Figure 32 is connected to the junction of the dividers N1 and N2. Divider N3 determines the interpolation rate of the DAC, and the ratio N2/N3 determines the ratio of Reference Clock/Input Data Rate. The VCO runs optimally over the range 804MHz to 1800MHz, so that N1 is used to keep the speed of the VCO in this range, even though the DAC sample rate may be lower. The loop filter components are entirely internal and no external compensation is necessary. Figure 36 shows the timing specifications for the AD9779 when the PLL is disabled. The reference clock is at the DAC output sample rate. In the example shown in Figure 36, if the PLL is disabled, the interpolation is 4x.. The set up and hold time for the input data are with respect to the rising edge of the reference clock which occurs just before the rising edge of the DATACLK out. Note that if reg 02h, bit2 is set, DATACLK out is inverted so the latching reference clock edge will occur just before the DATACLK out falling edge. Refe rence Clock tD DATA CLK out tS tH Input Data Figure 33. Timing Specifications for AD9779, PLL Enabled, Reference Clock = 1x Input Sample Rate Rev. PrD | Page 23 of 34 AD9779 Preliminary Technical Data Refe rence Clock tD DATA CLK out tS tH Input Data Figure 34. Timing Specifications for AD9779, PLL Enabled, Reference Clock = 2x Input Sample Rate Refe rence Clock tD DATA CLK out tS tH Input Data Figure 35. Timing Specifications for AD9779, PLL Enabled, Reference Clock = 4x Input Sample Rate Refe rence Clock tD DATA CLK out tS tH Input Data tS=-2.3ns typ tH=3.7ns typ tD=5.5ns typ Figure 36. Timing Specifications for AD9779, PLL Disabled, 4x Interpolation Using Data Delay to Meet Timing Requirements In order to meet strict timing requirements at input data rates of up to 250MSPS, the AD9779 has a fine timing feature. Fine timing adjustments can be made by programming values into the DATA CLOCK DELAY register (reg 03h, 5:3). By changing the values in this register, delay can be added to the default delay between the DACCLK in the DATACLK out. The effect of this is shown in Figure 37 and Figure 38. Figure 38. . Delay from DACCLK to DATACLK out with CLK DATA DELAY = 111 Figure 37. Delay from DACCLK to DATACLK out with CLK DATA DELAY = 000 The difference between the default delay of Figure 37 and the maximum delay shown in Figure 38 is the range programmable via the DATA CLK DELAY register. The resulting delays when programming DATA CLK DELAY between 000 and 111 are a linear extrapolation between these two figures. (typically 300ps400ps per increment to DATA CLK DELAY). Rev. PrD | Page 24 of 34 Preliminary Technical Data AD9779 Interpolation Filter Architecture 10 The AD9779 can provide up to 8× interpolation or disable the interpolation filters entirely. The coefficients of the low pass filters and the inverse sinc filter are given in Table 5, Table 6, Table 7, and Table 8. Spectral plots for the filter responses are given in Figure 3, Figure 4, and Figure 5. 0 -10 -20 -30 -40 With the interpolation filter and modulator combined, the incoming signal can be placed anywhere within the Nyquist region of the DAC output sample rate. Where the input signal is complex, this architecture allows modulation of the input signal to positive or negative Nyquist regions (refer to Table 13). -50 -60 -70 -80 -90 The Nyquist regions up to 4× the input data rate can be seen in Figure 39. -100 -4 -3× -2× -1× DC 1× 2× -1 0 1 2 3 4 10 4× 3× -2 Figure 41. Interpolation/Modulation Combination of -3fDAC/8 Filter in Odd Mode -8 -7 -6 -5 -4 -3 -2 -1 1 2 3 4 5 6 7 8 -4× -3 0 Figure 39. Nyquist Zones -10 -20 Figure 3, Figure 4 and Figure 5 show the low pass response of the digital filters with no modulation used. By turning on the modulation feature, the response of the digital filters can be tuned to any Nyquist zone within the DAC bandwidth. As an example, Figure 40 to Figure 46 show the odd mode filter responses (refer to Table 13 for odd/even mode filter responses). -30 -40 -50 -60 -70 -80 10 -90 0 -100 -4 -3 -2 -1 0 1 2 3 4 -10 Figure 42. Interpolation/Modulation Combination of -2fDAC/8 Filter in Odd Mode -20 -30 -40 10 -50 0 -60 -10 -70 -20 -80 -30 -90 -40 -100 -4 -3 -2 -1 0 1 2 3 -50 4 -60 -70 Figure 40. Interpolation/Modulation Combination of -4fDAC/8 Filter in Odd Mode -80 -90 -100 -4 -3 -2 -1 0 1 2 3 Figure 43. Interpolation/Modulation Combination of -1fDAC/8 Filter in Odd Mode Rev. PrD | Page 25 of 34 4 AD9779 Preliminary Technical Data 10 Even mode filter responses allow the passband to be centered around ±0.5, ±1.5, ±2.5 and ±3.5 FDATA. Switching from and odd mode response to an even mode filter response does not modulate the signal. Instead, the pass band is simply shifted. As an example, picture the response of Figure 46, and assume the signal in band is a complex signal over the bandwidth 3.2 to 3.3×FDATA. If the even mode filter response is then selected, the pass band will now be centered at 3.5×FDATA. However, the signal will still remain at the same place in the spectrum. The even/odd mode capability allows the passband to be placed anywhere in the DAC Nyquist bandwidth. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -4 -3 -2 -1 0 1 2 3 4 Figure 44. Interpolation/Modulation Combination of fDAC/8 Filter in Odd Mode 10 0 -10 -20 The AD9779 is a dual DAC with an internal complex modulator built into the interpolating filter response. The modulator can be set to a real or a complex mode by programming register 02h, bit 5. In the default mode, bit 5 is set to zero and the modulation is complex. The AD9779 then expects the real and the imaginary components of a complex signal at digital input ports one and two (I and Q respectively). The DAC outputs will then represent the real and imaginary components of the input signal, modulated by the complex carrier FDAC/2, FDAC/4 or FDAC/8. With Bit 5 set to one, the modulation is real. The Q channel is shut off and it’s value at the modulator inputs replaced with zero. The output spectrum at either the IDAC or the QDAC will then represent the signal at digital input port one, real modulated by the internal digital carrier (FDAC/2, FDAC/4 or FDAC/8). -30 -40 -50 -60 -70 -80 -90 -100 -4 -3 -2 -1 0 1 2 3 4 Figure 45. Interpolation/Modulation Combination of 2fDAC/8 Filter in Odd Mode 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -4 -3 -2 -1 0 1 2 3 4 Figure 46. Interpolation/Modulation Combination of 3fDAC/8 Filter in Odd Mode Rev. PrD | Page 26 of 34 Preliminary Technical Data AD9779 EVALUATION BOARD SCHEMATICS Figure 47. AD9779 Eval Board, Rev B , Power Supply Decoupling and SPI Interface Rev. PrD | Page 27 of 34 AD9779 Preliminary Technical Data Figure 48. AD9779 Eval Board, Rev B , Circuitry Local to AD9779 Rev. PrD | Page 28 of 34 Preliminary Technical Data AD9779 Figure 49. AD9779 Eval Board, RevB , AD8349 Quadrature Modulator Rev. PrD | Page 29 of 34 AD9779 Preliminary Technical Data Figure 50. AD9779 Eval Board, RevB , DAC Clock Interface Rev. PrD | Page 30 of 34 Preliminary Technical Data AD9779 Figure 51. AD9779 Eval Board, RevB , Input Port 1, Digital Input Buffers Rev. PrD | Page 31 of 34 AD9779 Preliminary Technical Data Figure 52. AD9779 Eval Board, RevB , Input Port 2, Digital Input Buffers Rev. PrD | Page 32 of 34 Preliminary Technical Data AD9779 Outline Dimensions Rev. PrD | Page 33 of 34 AD9779 Preliminary Technical Data ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model AD9779BSV AD9779/PCB Temperature Range -40°C to +85°C (Ambient) 25°C (Ambient) Description 100-Lead TQFP, Exposed Paddle Evaluation Board Table 15: Ordering Guide © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR05363–0–1/05(PrD) Rev. PrD | Page 34 of 34