AD AD7324BRUZ-REEL

4-Channel, Software-Selectable, True
Bipolar Input, 12-Bit Plus Sign ADC
AD7324
FEATURES
GENERAL DESCRIPTION
1
The AD7324 is a 4-channel, 12-bit plus sign, successive
approximation ADC designed on the iCMOS (industrial
CMOS) process. iCMOS is a process combining high voltage
silicon with submicron CMOS and complementary bipolar
technologies. It enables the development of a wide range of high
performance analog ICs capable of 33 V operation in a footprint
that no previous generation of high voltage parts could achieve.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can accept bipolar input signals while providing
increased performance, dramatically reduced power
consumption, and reduced package size.
The AD7324 can accept true bipolar analog input signals. The
AD7324 has four software-selectable input ranges, ±10 V, ±5 V,
±2.5 V, and 0 V to +10 V. Each analog input channel can be
independently programmed to one of the four input ranges.
The analog input channels on the AD7324 can be programmed
to be single-ended, true differential, or pseudo differential.
The ADC contains a 2.5 V internal reference. The AD7324 also
allows for external reference operation. If a 3 V reference is
applied to the REFIN/OUT pin, the AD7324 can accept a true
bipolar ±12 V analog input. Minimum ±12 V VDD and VSS
supplies are required for the ±12 V input range. The ADC has a
high speed serial interface that can operate at throughput rates
up to 1 MSPS.
FUNCTIONAL BLOCK DIAGRAM
VDD
REFIN/OUT
VCC
AD7324
2.5V
VREF
VIN0
VIN1
VIN2
VIN3
I/P
MUX
T/H
13-BIT
SUCCESSIVE
APPROXIMATION
ADC
DOUT
CONTROL LOGIC
AND REGISTERS
CHANNEL
SEQUENCER
SCLK
CS
DIN
VDRIVE
AGND
VSS
04864-001
12-bit plus sign SAR ADC
True bipolar input ranges
Software-selectable input ranges
±10 V, ±5 V, ±2.5 V, 0 V to +10 V
1 MSPS throughput rate
Four analog input channels with channel sequencer
Single-ended, true differential, and pseudo differential
analog input capability
High analog input impedance
Low power: 21 mW
Full power signal bandwidth: 22 MHz
Internal 2.5 V reference
High speed serial interface
Power-down modes
16-lead TSSOP package
iCMOS™ process technology
DGND
Figure 1.
PRODUCT HIGHLIGHTS
1.
The AD7324 can accept true bipolar analog input signals,
±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals.
2.
The four analog inputs can be configured as four singleended inputs, two true differential input pairs, two pseudo
differential inputs, or three pseudo differential inputs.
3.
1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™compatible interface.
4.
Low power, 30 mW maximum, at 1 MSPS throughput rate.
5.
Channel sequencer.
Table 1. Similar Products Selection Table
Device
Number
AD7329
AD7328
AD7327
AD7323
AD7322
AD7321
1
Throughput
Rate
250 kSPS
1000 kSPS
500 kSPS
500 kSPS
1000 kSPS
500 kSPS
Number of bits
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
12-bit plus sign
Number of
Channels
8
8
8
4
2
2
Protected by U.S. Patent No. 6,731,232.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2005 Analog Devices, Inc. All rights reserved.
AD7324
TABLE OF CONTENTS
Features .............................................................................................. 1
Control Register ......................................................................... 23
Functional Block Diagram .............................................................. 1
Sequence Register....................................................................... 25
General Description ......................................................................... 1
Range Register ............................................................................ 25
Product Highlights ........................................................................... 1
Sequencer Operation ..................................................................... 26
Revision History ............................................................................... 2
Reference ..................................................................................... 28
Specifications..................................................................................... 3
VDRIVE ............................................................................................ 28
Timing Specifications .................................................................. 7
Modes of Operation ....................................................................... 29
Absolute Maximum Ratings............................................................ 8
Normal Mode.............................................................................. 29
ESD Caution.................................................................................. 8
Full Shutdown Mode.................................................................. 29
Pin Configurations and Function Descriptions ........................... 9
Autoshutdown Mode ................................................................. 30
Typical Performance Characteristics ........................................... 10
Autostandby Mode..................................................................... 30
Terminology .................................................................................... 14
Power vs. Throughput Rate....................................................... 31
Theory of Operation ...................................................................... 16
Serial Interface ................................................................................ 32
Circuit Information.................................................................... 16
Microprocessor Interfacing........................................................... 33
Converter Operation.................................................................. 16
AD7324 to ADSP-218x.............................................................. 33
Analog Input Structure.............................................................. 17
AD7324 to ADSP-BF53x ........................................................... 33
Typical Connection Diagram ................................................... 19
Application Hints ........................................................................... 34
Analog Input ............................................................................... 19
Layout and Grounding .............................................................. 34
Driver Amplifier Choice............................................................ 21
Outline Dimensions ....................................................................... 35
Registers ........................................................................................... 22
Ordering Guide .......................................................................... 35
Addressing Registers .................................................................. 22
REVISION HISTORY
12/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
AD7324
SPECIFICATIONS
Unless otherwise noted, VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V to 3.0 V
internal/external, fSCLK = 20 MHz, fS = 1 MSPS, TA = TMAX to TMIN with VCC < 4.75 V, all specifications are typical.
Table 2.
Parameter 1
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR) 2
Signal-to-Noise + Distortion
(SINAD)2
Min
B Version
Typ
Max
76
72.5
75
dB
dB
dB
76
dB
dB
72.5
dB
72
Total Harmonic Distortion (THD)2
−80
−82
−77
−80
Peak Harmonic or Spurious Noise
(SFDR)2
dB
dB
dB
dB
−80
dB
−78
dB
dB
−82
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
Aperture Delay 3
Aperture Jitter3
Common-Mode Rejection Ratio
(CMRR)2
Channel-to-Channel Isolation2
Full Power Bandwidth
Unit
Test Conditions/Comments
FIN = 50 kHz sine wave
Differential mode
Single-ended/pseudo differential mode
Differential mode; ±2.5 V and ±5 V ranges
Differential mode; 0 V to 10 V and ±10 V ranges
Single-ended/pseudo differential mode; ±2.5 V and
±5 V ranges
Single-ended/pseudo differential mode; 0 V to +10 V
and ±10 V ranges
Differential mode; ±2.5 V and ±5 V ranges
Differential mode; 0 V to +10 V and ±10 V ranges
Single-ended/pseudo differential mode; ±2.5 V and
±5 V ranges
Single-ended/pseudo differential mode; 0 V to +10 V
and ±10 V ranges
Differential mode; ±2.5 V and ±5 V ranges
Differential mode; 0 V to +10 V and ±10 V ranges
Single-ended/pseudo differential mode; ±2.5 V and ±5 V
ranges
Single-ended/pseudo differential mode; 0 V to +10 V
and ±10 V ranges
fa = 50 kHz, fb = 30 kHz
−79
dB
−88
−90
7
50
−79
dB
dB
ns
ps
dB
Up to 100 kHz ripple frequency; see Figure 17
−72
22
5
dB
MHz
MHz
FIN on unselected channels up to 100 kHz; see Figure 14
At 3 dB
At 0.1 dB
Rev. 0 | Page 3 of 36
AD7324
Parameter 1
DC ACCURACY 4
Resolution
No Missing Codes
Min
B Version
Typ
Max
13
12-bit
plus sign
11-bit
plus sign
Integral Nonlinearity2
Differential mode
Bits
Single-ended/pseudo differential mode
±1.1
±1
LSB
LSB
LSB
−0.9/+1.5
LSB
±0.9
LSB
Differential mode
Single-ended/pseudo differential mode
Single-ended/pseudo differential mode
(LSB = FSR/8192)
Differential mode; guaranteed no missing codes to
13 bits
Single-ended mode; guaranteed no missing codes to
12 bits
Single-ended/psuedo differential mode
(LSB = FSR/8192)
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
Single-ended/pseudo differential mode
Differential mode
−0.7/+1
Offset Error2, 5
Offset Error Match2, 5
Gain Error2, 5
Gain Error Match2, 5
Positive Full-Scale Error2, 6
Positive Full-Scale Error Match2, 6
Bipolar Zero Error2, 6
Bipolar Zero Error Match2, 6
Negative Full-Scale Error2, 6
Negative Full-Scale Error Match2, 6
Test Conditions/Comments
All dc accuracy specifications are typical for 0 V to
10 V mode.
Bits
Bits
−0.7/+1.2
Differential Nonlinearity2
Unit
LSB
−4/+9
−7/+10
±0.6
±0.5
±8
±14
±0.5
±0.5
±4
±7
±0.5
±0.5
±8.5
±7.5
±0.5
±0.5
±4
±6
±0.5
±0.5
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Rev. 0 | Page 4 of 36
AD7324
Parameter 1
ANALOG INPUT
Input Voltage Ranges
(Programmed via Range
Register)
B Version
Typ
Min
Max
Unit
Test Conditions/Comments
±10
V
Reference = 2.5 V; see Table 6
VDD = 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V
±5
±2.5
0 to 10
V
V
V
±3.5
±6
±5
+3/−5
V
V
V
V
nA
nA
pF
pF
pF
pF
Pseudo Differential VIN(−)
Input Range
DC Leakage Current
±80
3
13.5
16.5
21.5
3
Input Capacitance3
REFERENCE INPUT/OUTPUT
Input Voltage Range
Input DC Leakage Current
Input Capacitance
Reference Output Voltage
Reference Output Voltage Error
@ 25°C
Reference Output Voltage
TMIN to TMAX
Reference Temperature
Coefficient
Reference Output Impedance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output
Capacitance3
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition
Time2, 3
Throughput Rate
2.5
3
±1
±5
V
μA
pF
V
mV
±10
mV
25
ppm/°C
10
2.5
3
7
VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V
VDD = 5 V min, VSS = − 5 V min, VCC = 2.7 V to 5.25 V
VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V
VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 40 and
Figure 41
Reference = 2.5 V; range = ±10 V
Reference = 2.5 V; range = ±5 V
Reference = 2.5 V; range = ±2.5 V
Reference = 2.5 V; range = 0 V to +10 V
VIN = VDD or VSS
Per channel, VIN = VDD or VSS
When in track, ±10 V range
When in track, ±5 V and 0 V to +10 V ranges
When in track, ±2.5 V range
When in hold, all ranges
ppm/°C
Ω
2.4
0.8
0.4
±1
10
VDRIVE −
0.2 V
0.4
±1
5
V
V
V
μA
pF
VCC = 4.75 V to 5.25 V
VCC = 2.7 to 3.6 V
VIN = 0 V or VDRIVE
V
ISOURCE = 200 μA
V
μA
pF
ISINK = 200 μA
Straight natural binary
Twos complement
Coding bit set to 1 in control register
Coding bit set to 0 in control register
800
305
ns
ns
16 SCLK cycles with SCLK = 20 MHz
Full-scale step input; see the Terminology section
1
770
MSPS
kSPS
See the Serial Interface section; VCC = 4.75 V to 5.25 V
VCC < 4.75 V
Rev. 0 | Page 5 of 36
AD7324
Parameter 1
POWER REQUIREMENTS
VDD
VSS
VCC
VDRIVE
Normal Mode (Static)
Normal Mode (Operational)
IDD
ISS
ICC and IDRIVE
Autostandby Mode (Dynamic)
IDD
ISS
ICC and IDRIVE
Autoshutdown Mode (Static)
IDD
ISS
ICC and IDRIVE
Full Shutdown Mode
IDD
ISS
ICC and IDRIVE
POWER DISSIPATION
Normal Mode (Operational)
Min
B Version
Typ
12
−12
2.7
2.7
Max
Unit
16.5
−16.5
5.25
5.25
V
V
V
V
mA
0.9
360
410
3.2
μA
μA
mA
200
210
1.3
μA
μA
mA
1
1
1
μA
μA
μA
1
1
1
μA
μA
μA
VDD/VSS = ±16.5 V, VCC/VDRIVE = 5.25 V
fSAMPLE = 1 MSPS
VDD = 16.5 V
VSS = −16.5 V
VCC/VDRIVE = 5.25 V
FSAMPLE = 250 kSPS
VDD = 16.5 V
VSS = −16.5 V
VCC/VDRIVE = 5.25 V
SCLK on or off
VDD = 16.5 V
VSS = −16.5 V
VCC/VDRIVE = 5.25 V
SCLK on or off
VDD = 16.5 V
VSS = −16.5 V
VCC/VDRIVE = 5.25 V
30
mW
mW
μW
VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V
VDD = 12 V, VSS = −12 V, VCC = 5 V
VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V
21
Full Shutdown Mode
Test Conditions/Comments
Digital inputs = 0 V or VDRIVE
See Table 6
See Table 6
See Table 6; typical specifications for VCC < 4.75 V
38.25
1
Temperature range is −40°C to +85°C.
See the Terminology section.
Sample tested during initial release to ensure compliance.
4
For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless
otherwise noted.
5
Unipolar 0 V to 10 V range with straight binary output coding.
6
Bipolar range with twos complement output coding.
2
3
Rev. 0 | Page 6 of 36
AD7324
TIMING SPECIFICATIONS
VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25, VREF = 2.5 V to 3.0 V Internal/External,
TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted. 1
Table 3.
Parameter
fSCLK
tCONVERT
tQUIET
t1
t2 2
t3
t4
t5
t6
t7
t8
t9
t10
tPOWER-UP
2
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
μs max
μs typ
Description
VDRIVE ≤ VCC
tSCLK = 1/fSCLK
Minimum time between end of serial read and next falling edge of CS
Minimum CS pulse width
CS to SCLK setup time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
Unipolar input range (0 V to 10 V)
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power up from autostandby
Power up from full shutdown/autoshutdown mode, internal reference
Power up from full shutdown/autoshutdown mode, external reference
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
When using VCC = 4.75 V to 5.25 V and the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to
50:50.
t1
CS
tCONVERT
t2
SCLK
t6
1
2
3
4
2 IDENTIFICATION BITS
t3
ADD1
DOUT
THREE- ZERO
t9
STATE
DIN
WRITE
REG
SEL1
ADD0
SIGN
5
t4
13
14
DB11
15
16
t5
t7
DB10
DB2
t8
DB1
DB0
t10
REG
SEL2
tQUIET
THREE-STATE
MSB
LSB
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 7 of 36
DON’T
CARE
04864-002
1
Limit at TMIN, TMAX
VCC < 4.75 V
VCC = 4.75 V to 5.25 V
50
50
14
20
16 × tSCLK
16 × tSCLK
75
60
12
5
25
20
45
35
26
14
57
43
0.4 × tSCLK
0.4 × tSCLK
0.4 × tSCLK
0.4 × tSCLK
13
8
40
22
10
9
4
4
2
2
750
750
500
500
25
25
AD7324
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted
Table 4.
Parameter
VDD to AGND, DGND
VSS to AGND, DGND
VDD to VCC
VCC to AGND, DGND
VDRIVE to AGND, DGND
AGND to DGND
Analog Input Voltage to AGND 1
Digital Input Voltage to DGND
Digital Output Voltage to GND
REFIN to AGND
Input Current to Any Pin
Except Supplies 2
Operating Temperature Range
Storage Temperature Range
Junction Temperature
TSSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
Pb-Free Temperature, Soldering
Reflow
ESD
Rating
−0.3 V to +16.5 V
+0.3 V to −16.5 V
VCC − 0.3 V to 16.5 V
−0.3 V to +7 V
−0.3 V to + 7 V
−0.3 V to +0.3 V
VSS −0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VCC + 0.3 V
±10 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +85°C
−65°C to +150°C
150°C
150.4°C/W
27.6°C/W
260(0)°C
2.5 kV
1
If the analog inputs are being driven from alternative VDD and VSS supply
circuitry, Schottky diodes should be placed in series with the AD7324’s VDD
and VSS supplies.
2
Transient currents of up to 100 mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 8 of 36
AD7324
CS 1
16
SCLK
DIN 2
15
DGND
DGND 3
AD7324
14
DOUT
AGND 4
TOP VIEW
(Not to Scale)
13
VDRIVE
12
VCC
6
11
VDD
VIN0 7
10
VIN2
VIN1 8
9
VIN3
REFIN/OUT 5
VSS
04864-003
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CS
2
DIN
3, 15
DGND
4
AGND
5
REFIN/OUT
6
7, 8, 10, 9
VSS
VIN0 to VIN3
11
12
VDD
VCC
13
VDRIVE
14
DOUT
16
SCLK
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on
the AD7324 and frames the serial data transfer.
Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the
register on the falling edge of SCLK (see the Reference section).
Digital Ground. Ground reference point for all digital circuitry on the AD7324. The DGND and AGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
Analog Ground. Ground reference point for all analog circuitry on the AD7324. All analog input signals
and any external reference signal should be referred to this AGND voltage. The AGND and DGND
voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a
transient basis.
Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the
AD7324. The nominal internal reference voltage is 2.5 V, which appears at the pin. A 680 nF capacitor
should be placed on the reference pin. Alternatively, the internal reference can be disabled and an
external reference applied to this input. On power-up, the external reference mode is the default
condition (see the Reference section).
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
Analog Input 0 to Analog Input 3. The analog inputs are multiplexed into the on-chip track-and-hold.
The analog input channel for conversion is selected by programming the Channel Address Bit ADD1
and ADD0 in the control register. The inputs can be configured as four single-ended inputs, two true
differential input pairs, two pseudo differential inputs, or three pseudo differential inputs. The configuration of the analog inputs is selected by programming the mode bits, Bit Mode 1 and Bit Mode 0, in
the control register. The input range on each input channel is controlled by programming the range
register. Input ranges of ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V can be selected on each analog input
channel when a +2.5 V reference voltage is used (see the Reference section).
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7324.
This supply should be decoupled to AGND. Specifications apply from VCC = 4.75 V to 5.25 V.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface
operates. This pin should be decoupled to DGND. The voltage at this pin may be different to that at VCC,
but it should not exceed VCC by more than 0.3 V.
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The
data stream consists of a leading ZERO bit, two channel identification bits, the sign bit, and 12 bits of
conversion data. The data is provided MSB first (see the Serial Interface section).
Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the
AD7324. This clock is also used as the clock source for the conversion process.
Rev. 0 | Page 9 of 36
AD7324
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0
4096 POINT FFT
VCC = VDRIVE = 5V
VDD, VSS = ±15V
TA = 25°C
INT/EXT 2.5V REFERENCE
±10V RANGE
FIN = 50kHz
SNR = 77.30dB
SINAD = 76.85dB
THD = –86.96dB
SFDR = –88.22dB
SNR (dB)
–40
–60
–80
0.6
0.4
INL ERROR (LSB)
–20
VCC = VDRIVE = 5V INT/EXT 2.5V REFERENCE
TA = 25°C
±10V RANGE
VDD, VSS = ±15V
+INL = +0.55LSB
–INL = –0.68LSB
0.8
0.2
0
–0.2
–0.4
–100
–0.6
–120
0
50
100
150
200
250
300
350
400
450
500
FREQUENCY (kHz)
04864-004
–1.0
–140
0
8192
1024
2048
3072
4096
5120
6144
7168
512
1536
2560
3584
4608
5632
6656
7680
CODE
04864-007
–0.8
Figure 7. Typical INL True Differential Mode
Figure 4. FFT True Differential Mode
1.0
0
–60
–80
–100
0.4
0.2
0
–0.2
–0.4
–0.8
–120
0
50
100
150
200
250
300
350
400
450
500
FREQUENCY (kHz)
04864-005
–1.0
1.0
1.0
0.8
0.8
0.6
0.6
0.4
INL ERROR (LSB)
0.4
0.2
0
–0.2
VCC = VDRIVE = 5V
TA = 25°C
VDD, VSS = ±15V
INT/EXT 2.5V REFERENCE
±10V RANGE
+DNL = +0.72LSB
–DNL = –0.22LSB
–0.4
–0.6
–0.8
0
8192
1024
2048
3072
4096
5120
6144
7168
512
1536
2560
3584
4608
5632
6656
7680
CODE
0.2
0
–0.2
VCC = VDRIVE = 5V
TA = 25°C
VDD, VSS = ±15V
–0.6
INT/EXT 2.5V REFERENCE
±10V RANGE
–0.8
+INL = +0.87LSB
–INL = –0.49LSB
–1.0
0
8192
1024
2048
3072
4096
5120
6144
7168
512
1536
2560
3584
4608
5632
6656
7680
CODE
–0.4
04864-006
DNL ERROR (LSB)
8192
1024
2048
3072
4096
5120
6144
7168
512
1536
2560
3584
4608
5632
6656
7680
CODE
Figure 8. Typical DNL Single-Ended Mode
Figure 5. FFT Single-Ended Mode
–1.0
0
Figure 6. Typical DNL True Differential Mode
Figure 9. Typical INL Single-Ended Mode
Rev. 0 | Page 10 of 36
04864-044
–140
VCC = VDRIVE = 5V
±10V RANGE
TA = 25°C
+DNL = +0.79LSB
–DNL = –0.38LSB
VDD, VSS = ±15V
INT/EXT 2.5V REFERENCE
–0.6
04864-043
–40
0.6
DNL ERROR (LSB)
–20
SNR (dB)
0.8
4096 POINT FFT
VCC = VDRIVE = 5V
VDD, VSS = ±15V
TA = 25°C
INT/EXT 2.5V REFERENCE
±10V RANGE
FIN = 50kHz
SNR = 74.67dB
SINAD = 74.03dB
THD = –82.68dB
SFDR = –85.40dB
AD7324
–50
0V TO +10V DIFF
0V TO +10V SE
70
±5V SE
–70
±10V DIFF
±5V DIFF
±2.5V DIFF
–80
0V TO +10V SE
±2.5V SE
65
±10V SE
±5V SE
0V TO +10V DIFF
60
–85
±2.5V SE
–90
VCC = 3V
VDD/VSS = ±12V
TA = 25°C
fS = 1MSPS
55
–95
1000
100
ANALOG INPUT FREQUENCY (kHz)
50
10
04864-008
–100
10
Figure 10. THD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 5 V VCC
Figure 13. SINAD vs. Analog Input Frequency for Single-Ended (SE) and
Differential Mode (Diff) at 3 V VCC
–50
–60
VCC = 3V
VDD/VSS = ±12V
TA = 25°C
fS = 1MSPS
CHANNEL-TO-CHANNEL ISOLATION (dB)
–50
–55
±10V SE
THD (dB)
–65
0V TO +10V DIFF
0V TO +10V SE
–70
±5V SE
–75
–80
±10V DIFF
±2.5V SE
–85
±5V DIFF
–90
–95
–55
VCC = 3V
–60
VCC = 5V
–65
–70
–75
–80
VDD/VSS = ±12V
SINGLE-ENDED MODE
fS = 1MSPS
TA = 25°C
50kHz ON SELECTED CHANNEL
–85
–90
±2.5V DIFF
100
1000
ANALOG INPUT FREQUENCY (kHz)
–95
04864-009
–100
10
200
±5V DIFF
75
NUMBER OF OCCURRENCES
±2.5V DIFF
±2.5V SE
0V TO +10V SE
65
±5V SE
±10V SE
0V TO +10V DIFF
60
VCC = 5V
VDD/VSS = ±12V
TA = 25°C
fS = 1MSPS
100
ANALOG INPUT FREQUENCY (kHz)
1000
8k
7k
Figure 12. SINAD vs. Analog Input Frequency for Single-Ended (SE) and
Differential Mode (Diff) at 5 V VCC
Rev. 0 | Page 11 of 36
500
600
VCC = 5V
VDD/VSS = ±12V
RANGE = ±10V
10k SAMPLES
TA = 25°C
6k
5k
4k
3k
2k
1k
04864-010
55
9469
9k
70
400
Figure 14. Channel-to-Channel Isolation
10k
±10V DIFF
300
FREQUENCY OF INPUT NOISE (kHz)
80
SINAD (dB)
100
0
Figure 11. THD vs. Analog Input Frequency for Single-Ended (SE) and True
Differential Mode (Diff) at 3 V VCC
50
10
1000
100
ANALOG INPUT FREQUENCY (kHz)
04864-011
–75
±2.5V DIFF
04864-012
THD (dB)
–65
75
±10V SE
0
0
–2
228
–1
303
0
1
0
2
CODE
Figure 15. Histogram of Codes, True Differential Mode
04864-013
–60
±10V DIFF ±5V DIFF
SINAD (dB)
–55
80
VCC = 5V
VDD/VSS = ±12V
TA = 25°C
fS = 1MSPS
AD7324
8k
2.0
7600
VCC = 5V
VDD/VSS = ±12V
RANGE = ±10V
10k SAMPLES
TA = 25°C
6k
1.5
INL = 500kSPS
5k
4k
3k
–1
0
1
11
0
2
3
–2.0
–55
–55
–60
–60
–65
–65
PSRR (dB)
VCC = 5V
–75
VCC = 3V
200
400
600
800
1000
1200
Figure 17. CMRR vs. Common-Mode Ripple Frequency
–75
VDD = 12V
–80
VSS = –12V
0
–55
DNL = 500kSPS
–60
–65
THD (dB)
DNL = 1MSPS
DNL = 1MSPS
–0.5
DNL = 500kSPS
±5V RANGE
VCC = VDRIVE = 5V
INTERNAL REFERENCE
SINGLE-ENDED MODE
5
7
9
11
13
15
±VDD/VSS SUPPLY VOLTAGE (V)
17
200
400
600
800
1000
19
VCC = VDRIVE = 5V
VDD/VSS = ±12V
TA = 25°C
INTERNAL REFERENCE
RANGE = ±10V AND ±2.5V
1200
RIN = 100Ω, ±10V RANGE
RIN = 2000Ω, ±10V RANGE
RIN = 50Ω,
±10V RANGE
–70 RIN = 1000Ω, ±10V RANGE
RIN = 4700Ω,
±2.5V RANGE
–75
RIN = 2000Ω,
±2.5V RANGE
–80
RIN = 1000Ω,
±2.5V RANGE
–85
RIN = 100Ω,
±2.5V RANGE
–90
RIN = 50Ω,
±2.5V RANGE
–95
10
04864-049
–1.5
–2.0
VCC = 3V
Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
1.0
DNL = 750kSPS
19
VCC = 5V
–50
–1.0
17
SUPPLY RIPPLE FREQUENCY (kHz)
DNL = 750kSPS
0
15
100mV p-p SINE WAVE ON EACH SUPPLY
NO DECOUPLING
SINGLE-ENDED MODE
fS = 1MSPS
–70
–100
2.0
0.5
13
–95
RIPPLE FREQUENCY (kHz)
1.5
11
–90
04864-055
0
9
–85
DIFFERENTIAL MODE
FIN = 50kHz
VDD/VSS = ±12V
fS = 1MSPS
TA = 25°C
–95
–100
7
Figure 19. INL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS
–50
–90
5
±VDD/VSS SUPPLY VOLTAGE (V)
–50
–85
±5V RANGE
VCC = VDRIVE = 5V
INTERNAL REFERENCE
SINGLE-ENDED MODE
INL = 1MSPS
04864-054
23
–2
04864-014
0
–3
Figure 16. Histogram of Codes, Single-Ended Mode
–80
INL = 750kSPS
–0.5
–1.5
CODE
CMRR (dB)
INL = 500kSPS
04864-050
1165
1k
–70
INL = 1MSPS
0
100
ANALOG INPUT FREQUENCY (kHz)
Figure 18. DNL Error vs. Supply Voltage at 500 kSPS, 750 kSPS, and 1 MSPS
1000
04864-015
1201
DNL ERROR (LSB)
0.5
–1.0
2k
0
INL = 750kSPS
1.0
INL ERROR (LSB)
NUMBER OF OCCURENCES
7k
Figure 21. THD vs. Analog Input Frequency for Various Source Impedances,
True Differential Mode
Rev. 0 | Page 12 of 36
AD7324
–50
VCC = VDRIVE = 5V
VDD/VSS = ±12V
TA = 25°C
INTERNAL REFERENCE
RANGE = ±10V AND ±2.5V
–60
THD (dB)
–65
RIN = 2000Ω, ±10V RANGE
RIN = 100Ω,
±10V RANGE
–70 RIN = 1000Ω, ±10V RANGE
RIN = 50Ω,
±10V RANGE
–75
RIN = 2000Ω,
±2.5V RANGE
–80
RIN = 1000Ω,
±2.5V RANGE
–85
RIN = 100Ω,
±2.5V RANGE
–90
RIN = 50Ω,
±2.5V RANGE
–95
10
100
INPUT FREQUENCY (kHz)
1000
04864-016
–55
Figure 22. THD vs. Analog Input Frequency for Various
Source Impedances, Single-Ended Mode
Rev. 0 | Page 13 of 36
AD7324
TERMINOLOGY
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (a point 1 LSB
below the first code transition) and full scale (a point 1 LSB
above the last code transition).
Offset Code Error
This applies to straight binary output coding. It is the deviation
of the first code transition (00 ... 000) to (00 ... 001) from the
ideal, that is, AGND + 1 LSB.
Offset Error Match
This is the difference in offset error between any two input
channels.
Gain Error
This applies to straight binary output coding. It is the deviation
of the last code transition (111 ... 110) to (111 ... 111) from the
ideal (that is, 4 × VREF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB)
after adjusting for the offset error.
Gain Error Match
This is the difference in gain error between any two input
channels.
Bipolar Zero Code Error
This applies when using twos complement output coding and a
bipolar analog input. It is the deviation of the midscale
transition (all 1s to all 0s) from the ideal input voltage, that is,
AGND − 1 LSB.
Negative Full-Scale Error
This applies when using twos complement output coding and
any of the bipolar analog input ranges. This is the deviation of
the first code transition (10 … 000) to (10 … 001) from the ideal
(that is, −4 × VREF + 1 LSB, −2 × VREF + 1 LSB, −VREF + 1 LSB)
after adjusting for the bipolar zero code error.
Negative Full-Scale Error Match
This is the difference in negative full-scale error between any
two input channels.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns into track mode after the
14th SCLK rising edge. Track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±1/2 LSB, after the end of a conversion.
For the ±2.5V range, the specified acquisition time is the time
required for the track-and-hold amplifier to settle to within ±1 LSB.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digitization process. The more levels, the smaller the quantization
noise. Theoretically, the signal to (noise + distortion) ratio for
an ideal N-bit converter with a sine wave input is given by
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
For a 13-bit converter, this is 80.02 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7324, it is defined as
Bipolar Zero Code Error Match
This refers to the difference in bipolar zero code error between
any two input channels.
Positive Full-Scale Error
This applies when using twos complement output coding and
any of the bipolar analog input ranges. It is the deviation of the
last code transition (011 … 110) to (011 … 111) from the ideal
(4 × VREF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB) after
adjusting for the bipolar zero code error.
Positive Full-Scale Error Match
This is the difference in positive full-scale error between any
two input channels.
THD (dB) = 20 log
V2 2 + V3 2 + V 4 2 + V5 2 + V6 2
V1
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, the
largest harmonic could be a noise peak.
Rev. 0 | Page 14 of 36
AD7324
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between any two channels. It is measured by applying a full-scale,
100 kHz sine wave signal to all unselected input channels and
determining the degree to which the signal attenuates in the
selected channel with a 50 kHz signal. Figure 14 shows the worstcase across all eight channels for the AD7324. The analog input
range is programmed to be the same on all channels.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa ± nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to 0. For example,
the second-order terms include (fa + fb) and (fa − fb), whereas
the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb),
and (fa − 2fb).
The AD7324 is tested using the CCIF standard where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second-order terms are usually distanced in
frequency from the original sine waves, whereas the third-order
terms are usually at a frequency close to the input frequencies.
As a result, the second- and third-order terms are specified
separately. The calculation of the intermodulation distortion is
per the THD specification, where it is the ratio of the rms sum
of the individual distortion products to the rms amplitude of
the sum of the fundamentals expressed in decibels.
PSR (Power Supply Rejection)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value (see the
Typical Performance Characteristics section).
CMRR (Common-Mode Rejection Ratio)
CMRR is defined as the ratio of the power in the ADC output at
full-scale frequency, f, to the power of a 100 mV sine wave
applied to the common-mode voltage of the VIN+ and VIN−
frequency, fS, as
CMRR (dB) = 10 log (Pf/PfS)
where Pf is the power at frequency f in the ADC output, and PfS
is the power at frequency fS in the ADC output (see Figure 17).
Rev. 0 | Page 15 of 36
AD7324
THEORY OF OPERATION
The AD7324 is a fast, 4-channel, 12-bit plus sign, bipolar input,
serial A/D converter. The AD7324 can accept bipolar input ranges
that include ±10 V, ±5 V, and ±2.5 V; it can also accept a 0 V to
+10 V unipolar input range. A different analog input range can
be programmed on each analog input channel via the on-chip
registers. The AD7324 has a high speed serial interface that can
operate at throughput rates up to 1 MSPS.
The AD7324 requires VDD and VSS dual supplies for the high voltage
analog input structures. These supplies must be equal to or greater
than the analog input range. See Table 6 for the requirements of
these supplies for each analog input range. The AD7324 requires
a low voltage 2.7 V to 5.25 V VCC supply to power the ADC core.
Table 6. Reference and Supply Requirements
for Each Analog Input Range
Selected Analog
Input Range (V)
±10
±5
±2.5
0 to +10
Reference
Voltage (V)
2.5
3.0
2.5
3.0
2.5
3.0
2.5
3.0
Full-Scale
Input Range (V)
±10
±12
±5
±6
±2.5
±3
0 to +10
0 to +12
AVCC (V)
3/5
3/5
3/5
3/5
3/5
3/5
3/5
3/5
Minimum
VDD/VSS (V)
±10
±12
±5
±6
±5
±5
+10/AGND
+12/AGND
To meet the specified performance specifications when the
AD7324 is configured with the minimum VDD and VSS supplies
for a chosen analog input range, the throughput rate should be
decreased from the maximum throughput range (see the
Typical Performance Characteristics section). Figure 18 and
Figure 19 show the change in INL and DNL as the VDD and VSS
voltages are varied. When operating at the maximum throughput
rate, as the VDD and VSS supply voltages are reduced, the INL
and DNL error increases. However, as the throughput rate is
reduced with the minimum VDD and VSS supplies, the INL and
DNL error is reduced.
Figure 31 shows the change in THD as the VDD and VSS supplies
are reduced. At the maximum throughput rate, the THD degrades
significantly as VDD and VSS are reduced. It is therefore necessary
to reduce the throughput rate when using minimum VDD and
VSS supplies so that there is less degradation of THD and the
specified performance can be maintained. The degradation is
due to an increase in the on resistance of the input multiplexer
when the VDD and VSS supplies are reduced.
The analog inputs can be configured as four single-ended
inputs, two true differential input pairs, two pseudo differential
inputs, or three pseudo differential inputs. Selection can be
made by programming the mode bits, Mode 0 and Mode 1, in
the control register.
The serial clock input accesses data from the part and provides
the clock source for the successive approximation ADC. The
AD7324 has an on-chip 2.5 V reference. However, the AD7324
can also work with an external reference. On power-up, the
external reference operation is the default option. If the internal
reference is the preferred option, the user must write to the
reference bit in the control register to select the internal
reference operation.
The AD7324 also features power-down options to allow power
saving between conversions. The power-down modes are
selected by programming the on-chip control register as
described in the Modes of Operation section.
CONVERTER OPERATION
The AD7324 is a successive approximation analog-to-digital
converter built around two capacitive DACs. Figure 23 and
Figure 24 show simplified schematics of the ADC in singleended mode during the acquisition and conversion phases,
respectively. Figure 25 and Figure 26 show simplified
schematics of the ADC in differential mode during acquisition
and conversion phases, respectively. The ADC is composed of
control logic, a SAR, and capacitive DACs. In Figure 23 (the
acquisition phase), SW2 is closed and SW1 is in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor array acquires the signal on the input.
CAPACITIVE
DAC
VIN0
B
COMPARATOR
CS
A SW1
SW2
CONTROL
LOGIC
AGND
04864-017
CIRCUIT INFORMATION
Figure 23. ADC Acquisition Phase (Single-Ended)
When the ADC starts a conversion (Figure 24), SW2 opens and
SW1 moves to Position B, causing the comparator to become
unbalanced. The control logic and the charge redistribution
DAC are used to add and subtract fixed amounts of charge from
the capacitive DAC to bring the comparator back into a
balanced condition. When the comparator is rebalanced, the
conversion is complete. The control logic generates the ADC
output code.
Rev. 0 | Page 16 of 36
AD7324
The ideal transfer characteristic for the AD7324 when twos
complement coding is selected is shown in Figure 27. The ideal
transfer characteristic for the AD7324 when straight binary
coding is selected is shown in Figure 28.
CAPACITIVE
DAC
AGND
011...111
011...110
ADC CODE
Figure 24. ADC Conversion Phase (Single-Ended)
Figure 25 shows the differential configuration during the
acquisition phase. For the conversion phase, SW3 opens and
SW1 and SW2 move to Position B (Figure 26). The output
impedances of the source driving the VIN+ and VIN− pins must
be matched; otherwise, the two inputs will have different
settling times, resulting in errors.
CAPACITIVE
DAC
111...111
111...110
CONTROL
LOGIC
SW3
CS
VREF
CAPACITIVE
DAC
Figure 25. ADC Differential Configuration During Acquisition Phase
111...000
011...111
000...010
000...001
000...000
CAPACITIVE
DAC
VIN–
COMPARATOR
CS
B
A SW1
A SW2
B
–FSR/2 + 1LSB
+FSR/2 – 1LSB BIPOLAR RANGES
AGND + 1LSB
+FSR – 1LSB
UNIPOLAR RANGE
ANALOG INPUT
Figure 28. Straight Binary Transfer Characteristic (Bipolar Ranges)
SW3
CONTROL
LOGIC
ANALOG INPUT STRUCTURE
CS
VREF
CAPACITIVE
DAC
04864-020
VIN+
+FSR/2 – 1LSB BIPOLAR RANGES
+FSR – 1LSB
UNIPOLAR RANGE
ANALOG INPUT
Figure 26. ADC Differential Configuration During Conversion Phase
Output Coding
The AD7324 default output coding is set to twos complement.
The output coding is controlled by the coding bit in the control
register. To change the output coding to straight binary coding,
the coding bit in the control register must be set. When
operating in sequence mode, the output coding for each
channel in the sequence is the value written to the coding bit
during the last write to the control register.
The analog inputs of the AD7324 can be configured as singleended, true differential, or pseudo differential via the control
register mode bits (see Table 10). The AD7324 can accept true
bipolar input signals. On power-up, the analog inputs operate as
four single-ended analog input channels. If true differential or
pseudo differential is required, a write to the control register is
necessary after power-up to change this configuration.
Figure 29 shows the equivalent analog input circuit of the
AD7324 in single-ended mode. Figure 30 shows the equivalent
analog input structure in differential mode. The two diodes
provide ESD protection for the analog inputs.
VDD
Transfer Functions
D
VIN0
The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is
dependent on the analog input range selected.
C1
Full-Scale Range/8192 Codes
20 V
10 V
5V
10 V
D
VSS
Table 7. LSB Sizes for Each Analog Input Range
Input Range
±10 V
±5 V
±2.5 V
0 V to +10 V
04864-022
B
AGND – 1LSB
Figure 27. Twos Complement Transfer Characteristic (Bipolar Ranges)
ADC CODE
VIN–
A SW1
A SW2
–FSR/2 + 1LSB
AGND + 1LSB
COMPARATOR
CS
B
100...010
100...001
100...000
04864-019
VIN+
000...001
000...000
111...111
04864-021
CONTROL
LOGIC
SW2
R1
C2
04864-023
A SW1
04864-018
COMPARATOR
CS
B
VIN0
Figure 29. Equivalent Analog Input Circuit (Single-Ended)
LSB Size
2.441 mV
1.22 mV
0.61 mV
1.22 mV
Rev. 0 | Page 17 of 36
AD7324
VDD
D
VIN+
C1
R1
The AD7324 enters track mode on the 14th SCLK rising edge.
When running the AD7324 at a throughput rate of 1 MSPS with
a 20 MHz SCLK signal, the ADC has approximately
C2
D
1.5 SCLK + t8 + tQUIET
VSS
to acquire the analog input signal. The ADC goes back into
hold mode on the CS falling edge.
VDD
C1
D
VSS
R1
C2
04864-024
D
VIN–
Figure 30. Equivalent Analog Input Circuit (Differential)
Care should be taken to ensure that the analog input does not
exceed the VDD and VSS supply rails by more than 300 mV.
Exceeding this value causes the diodes to become forward
biased and to start conducting into either the VDD supply rail or
VSS supply rail. These diodes can conduct up to 10 mA without
causing irreversible damage to the part.
As the VDD/VSS supply voltage is reduced, the on resistance of
the input multiplexer increases. Therefore, based on the
equation for tACQ, it is necessary to increase the amount of
acquisition time provided to the AD7324 and, hence, decrease
the overall throughput rate. Figure 31 shows that if the
throughput rate is reduced when operating with minimum VDD
and VSS supplies, the specified THD performance is maintained.
–50
VCC = VDRIVE = 5V
INTERNAL REFERENCE
TA = 25°C
FIN = 10kHz
±5V RANGE
SE MODE
–55
–60
THD (dB)
–65
In Figure 29 and Figure 30, Capacitor C1 is typically 4 pF and
can primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of the input
multiplexer and the track-and-hold switch. Capacitor C2 is the
sampling capacitor; its capacitance varies depending on the
analog input range selected (see the Specifications section).
–70
–75
1MSPS
–80
750kSPS
–85
–90
Track-and-Hold Section
The track-and-hold on the analog input of the AD7324 allows
the ADC to accurately convert an input sine wave of full-scale
amplitude to 13-bit accuracy. The input bandwidth of the trackand-hold is greater than the Nyquist rate of the ADC. The
AD7324 can handle frequencies up to 22 MHz.
th
The track-and-hold enters its tracking mode on the 14 SCLK
rising edge after the CS falling edge. The time required to
acquire an input signal depends on how quickly the sampling
capacitor is charged. With 0 source impedance, 305 ns is
sufficient to acquire the signal to the 13-bit level. The
acquisition time required is calculated using the following
formula:
tACQ = 10 × ((RSOURCE + R) C)
where C is the sampling capacitance and R is the resistance seen
by the track-and-hold amplifier looking back on the input. For
the AD7324, the value of R includes the on resistance of the
input multiplexer and is typically 300 Ω. RSOURCE should include
any extra source impedance on the analog input.
5
7
9
11
13
15
17
19
±VDD/VSS SUPPLIES (V)
04864-051
500kSPS
–95
Figure 31. THD vs. ±VDD/VSS Supply Voltage at 500 kSPS, 750 kSPS,
and 1 MSPS
Unlike other bipolar ADCs, the AD7324 does not have a
resistive analog input structure. On the AD7324, the bipolar
analog signal is sampled directly onto the sampling capacitor.
This gives the AD7324 high analog input impedance. An
approximation for the analog input impedance can be
calculated from the following formula:
Z = 1/(fS × CS)
where fS is the sampling frequency, and CS is the sampling
capacitor value.
CS depends on the analog input range chosen (see the
Specifications section). When operating at 1 MSPS, the analog
input impedance is typically 75 kΩ for the ±10V range. As the
sampling frequency is reduced, the analog input impedance
further increases. As the analog input impedance increases the
current required to drive the analog input therefore decreases.
Rev. 0 | Page 18 of 36
AD7324
V+
TYPICAL CONNECTION DIAGRAM
Figure 32 shows a typical connection diagram for the AD7324.
In this configuration, the AGND pin is connected to the analog
ground plane of the system, and the DGND pin is connected to
the digital ground plane of the system. The analog inputs on the
AD7324 can be configured to operate in single-ended, true
differential, or pseudo differential mode. The AD7324 can operate
with either an internal or external reference. In Figure 32, the
AD7324 is configured to operate with the internal 2.5 V reference.
A 680 nF decoupling capacitor is required when operating with
the internal reference.
The VCC pin can be connected to either a 3 V supply voltage or a
5 V supply voltage. The VDD and VSS are the dual supplies for the
high voltage analog input structures. The voltage on these pins
must be equal to or greater than the highest analog input range
selected on the analog input channels (see Table 6). The VDRIVE
pin is connected to the supply voltage of the microprocessor.
The voltage applied to the VDRIVE input controls the voltage of
the serial interface. VDRIVE can be set to 3 V or 5 V.
+15V
+
10µF
10µF
VDD1
+
AGND
V–
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 33. Single-Ended Mode Typical Connection Diagram
True Differential Mode
The AD7324 can have a total of two true differential analog
input pairs. Differential signals have some benefits over singleended signals, including better noise immunity based on the
device’s common-mode rejection and improvements in
distortion performance. Figure 34 defines the configuration of
the true differential analog inputs of the AD7324.
VIN+
VCC +2.7V TO +5.25V
AD73241
+3V SUPPLY
10µF +
0.1µF
1ADDITIONAL
AD7324
DOUT
µC/µP
SCLK
DIN
DGND
REFIN/OUT
VSS1
SERIAL
INTERFACE
AGND
+
10µF
1MINIMUM
VDD AND VSS SUPPLY VOLTAGES
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
04864-025
–15V
0.1µF
PINS OMITTED FOR CLARITY.
Figure 34. True Differential Inputs
CS
680nF
04864-026
VSS
VIN–
VDRIVE
ANALOG INPUTS
±10V, ±5V, ±2.5V
0V TO +10V
VDD VCC
AD73241
0.1µF
VCC
VIN0
VIN1
VIN2
VIN3
VIN+
04864-027
0.1µF
5V
The amplitude of the differential signal is the difference
between the signals applied to the VIN+ and VIN− pins in
each differential pair (VIN+ − VIN−). VIN+ and VIN− should
be simultaneously driven by two signals of equal amplitude,
dependent on the input range selected, that are 180° out of
phase. Assuming the ±4 × VREF mode, the amplitude of the
differential signal is −20 V to +20 V p-p (2 × 4 × VREF),
regardless of the common mode.
The common mode is the average of the two signals
Figure 32. Typical Connection Diagram
(VIN+ + VIN−)/2
ANALOG INPUT
Single-Ended Inputs
The AD7324 has a total of four analog inputs when operating in
single-ended mode. Each analog input can be independently
programmed to one of the four analog input ranges. In applications
where the signal source is high impedance, it is recommended
to buffer the signal before applying it to the ADC analog inputs.
Figure 33 shows the configuration of the AD7324 in singleended mode.
and is therefore the voltage on which the two input signals
are centered.
This voltage is set up externally, and its range varies with
reference voltage. As the reference voltage increases, the
common-mode range decreases. When driving the differential
inputs with an amplifier, the actual common mode range is
determined by the amplifier’s output swing. If the differential
inputs are not driven from an amplifier, the common-mode
range is determined by the supply voltage on the VDD supply pin
and the VSS supply pin.
When a conversion takes place, the common mode is rejected,
resulting in a noise-free signal of amplitude −2 × (4 × VREF) to
+2 × (4 × VREF) corresponding to Digital Codes −4096 to +4095.
Rev. 0 | Page 19 of 36
AD7324
5
8
±5V RANGE
±2.5V
RANGE
VCOM RANGE (V)
2
6
±5V RANGE
0
–2
–3
±10V
RANGE
±2.5V
RANGE
±10V
RANGE
0
–2
–4
–6
04864-045
VCC = 3V
VREF = 3V
–6
±16.5V VDD/VSS
±12V VDD/VSS
Figure 35. Common-Mode Range for VCC = 3 V and REFIN/OUT = 3 V
±5V RANGE
±2.5V
RANGE
VCC = 5V
VREF = 2.5V
±16.5V VDD/VSS
±12V VDD/VSS
Pseudo Differential Inputs
±5V RANGE
6
VCOM RANGE (V)
–8
Figure 38. Common-Mode Range for VCC = 5 V and REFIN/OUT = 2.5 V
8
4
±5V RANGE
±10V
RANGE
2
–4
–5
±2.5V
RANGE
4
1
–1
±10V
RANGE
04864-048
3
VCOM RANGE (V)
4
±10V
RANGE
±5V RANGE
±2.5V
RANGE
±2.5V
RANGE
2
±10V
RANGE
0
–2
04864-046
VCC = 5V
VREF = 3V
–4
±16.5V VDD/VSS
±12V VDD/VSS
Figure 36. Common-Mode Range for VCC = 5 V and REFIN/OUT = 3 V
6
The AD7324 can have two pseudo differential pairs or three
pseudo differential inputs referenced to a common VIN− pin.
The VIN+ inputs are coupled to the signal source and must have
an amplitude within the selected range for that channel as
programmed in the range register. A dc input is applied to the
VIN− pin. The voltage applied to this input provides an offset for
the VIN+ input from ground or a pseudo ground. Pseudo
differential inputs separate the analog input signal ground from
the ADC ground, allowing cancellation of dc common-mode
voltages. Figure 39 shows the AD7328 configured in pseudo
differential mode.
When a conversion takes place, the pseudo ground corresponds
to Code −4096 and the maximum amplitude corresponds to
Code +4095.
V+
4
±5V RANGE
5V
±5V RANGE
VIN+
0
–6
±10V
RANGE
±10V
±2.5V
RANGE RANGE
VIN–
VSS
±2.5V
RANGE
V–
VCC = 3V
VREF = 2.5V
–8
±16.5V VDD/VSS
±12V VDD/VSS
1ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 37. Common-Mode Range for VCC = 3 V and REFIN/OUT = 2.5 V
04864-028
–2
–4
VDD VCC
AD73241
04864-047
VCOM RANGE (V)
2
Figure 39. Pseudo Differential Inputs
Figure 40 and Figure 41 show the typical voltage range on the
VIN− pin for the different analog input ranges when configured
in the pseudo differential mode.
For example, when the AD7324 is configured to operate in
pseudo differential mode and the ±5 V range is selected with
±16.5 V VDD/VSS supplies and 5 V VCC, the voltage on the VIN−
pin can vary from −6.5 V to +6.5 V.
Rev. 0 | Page 20 of 36
AD7324
8
6
4
The driver amplifier must be able to settle for a full-scale step to
a 13-bit level, 0.0122%, in less than the specified acquisition
time of the AD7324. An op amp such as the AD8021 meets this
requirement when operating in single-ended mode. The
AD8021 needs an external compensating NPO type of
capacitor. The AD8022 can also be used in high frequency
applications where a dual version is required. For lower
frequency applications, op amps such as the AD797, AD845,
and AD8610 can be used with the AD7324 in single-ended
mode configuration.
±5V RANGE
±5V RANGE
±2.5V
RANGE
±10V
RANGE
±2.5V
RANGE
2
0
–2
±10V
RANGE
–6
–8
0V TO +10V
RANGE
VCC = 5V
VREF = 2.5V
±16.5V VDD/VSS
0V TO +10V
RANGE
±12V VDD/VSS
Differential operation requires that VIN+ and VIN− be
simultaneously driven with two signals of equal amplitude that
are 180° out of phase. The common mode must be set up
externally to the AD7324. The common-mode range is
determined by the REFIN/OUT voltage, the VCC supply voltage,
and the particular amplifier used to drive the analog inputs.
Differential mode with either an ac input or a dc input provides
the best THD performance over a wide frequency range. Because
not all applications have a signal preconditioned for differential
operation, there is often a need to perform the single-ended-todifferential conversion.
04864-039
–4
Figure 40. Pseudo Input Range with VCC= 5 V
4
±5V RANGE
2
±5V RANGE
±2.5V
RANGE
0
–4
±10V
RANGE
±2.5V
RANGE
0V TO +10V
RANGE
–6
This single-ended-to-differential conversion can be performed
using an op amp pair. Typical connection diagrams for an op
amp pair are shown in Figure 42 and Figure 43. In Figure 42,
the common-mode signal is applied to the noninverting input
of the second amplifier.
±10V
RANGE
0V TO +10V
RANGE
VCC = 3V
VREF = 2.5V
–8
±16.5V VDD/VSS
±12V VDD/VSS
04864-040
–2
1.5kΩ
VIN
Figure 41. Pseudo Input Range with VCC = 3 V
3kΩ
V+
DRIVER AMPLIFIER CHOICE
In applications where the harmonic distortion and signal-tonoise ratio are critical specifications, the analog input of the
AD7324 should be driven from a low impedance source. Large
source impedances significantly affect the ac performance of the
ADC and can necessitate the use of an input buffer amplifier.
1.5kΩ
1.5kΩ
1.5kΩ
V–
10kΩ
04864-029
VCOM
20kΩ
Figure 42. Single-Ended-to-Differential Configuration with the AD845
442Ω
VIN
442Ω
AD8021
V+
442Ω
442Ω
442Ω
442Ω
Due to the programmable nature of the analog inputs on the
AD7324, the choice of op amp used to drive the inputs is a
function of the particular application and depends on the input
configuration and the analog input voltage ranges selected.
V–
AD8021
100Ω
04864-030
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of THD that can be
tolerated in the application. The THD increases as the source
impedance increases and performance degrades. Figure 21 and
Figure 22 show graphs of the THD vs. the analog input
frequency for various source impedances. Depending on the
input range and analog input configuration selected, the
AD7324 can handle source impedances of up to 4.7 kΩ before
the THD starts to degrade.
Figure 43. Single-Ended-to-Differential Configuration with the AD8021
Rev. 0 | Page 21 of 36
AD7324
REGISTERS
The AD7324 has three programmable registers, the control register, the sequence register, and the range register. These registers are writeonly registers.
ADDRESSING REGISTERS
A serial transfer on the AD7324 consists of 16 SCLK cycles. The three MSBs on the DIN line during the 16 SCLK transfer are decoded to
determine which register is addressed. The three MSBs consist of the write bit, Register Select 1 bit, and Register Select 2 bit. The register
select bits are used to determine which of the three on-board registers is selected. The write bit determines if the data on the DIN line
following the register select bits loads into the addressed register. If the write bit is 1, the bits load into the register addressed by the
register select bits. If the write bit is 0, the data on the DIN line does not load into any register.
Table 8. Decoding Register Select Bits and Write Bit
Write
0
1
Register Select 1
0
0
Register Select 2
0
0
1
0
1
1
1
1
Comment
Data on the DIN line during this serial transfer is ignored.
This combination selects the control register. The subsequent 12 bits are loaded into
the control register.
This combination selects the range register. The subsequent 8 bits are loaded into the
range register.
This combination selects the sequence register. The subsequent 4 bits are loaded into
the sequence register.
Rev. 0 | Page 22 of 36
AD7324
CONTROL REGISTER
The control register is used to select the analog input channel, analog input configuration, reference, coding, and power mode. The
control register is a write-only, 12-bit register. Data loaded on the DIN line corresponds to the AD7324 configuration for the next
conversion. If the sequence register is being used, data should be loaded into the control register after the range register and the sequence
register have been initialized. The bit functions of the control register are shown in Table 9 (the power-up status of all bits is 0).
MSB
15
Write
14
Register Select 1
13
Register Select 2
12
ZERO
11
ADD1
10
ADD0
9
Mode 1
8
Mode 0
7
PM1
6
PM0
5
Coding
1
Ref
3
Seq1
2
Seq2
1
ZERO
LSB
0
0
Table 9. Control Register Details
Bit
12, 1
11, 10
Mnemonic
ZERO
ADD1, ADD0
9, 8
Mode 1, Mode 0
7, 6
5
PM1, PM0
Coding
4
Ref
3, 2
Seq1, Seq2
Description
A 0 must be written to this bit to ensure correct operation of the device
These two channel address bits are used to select the analog input channel for the next conversion if the
sequencer is not being used. If the sequencer is being used, the two channel address bits are used to
select the final channel in a consecutive sequence.
These two mode bits are used to select the configuration of the four analog input pins, VIN0 to VIN3. These
pins are used in conjunction with the channel address bits. On the AD7324, the analog inputs can be
configured as four single-ended inputs, two true differential input pairs, two pseudo differential inputs, or
three pseudo differential inputs (see Table 10).
The power management bits are used to select different power mode options on the AD7324 (see Table 11).
This bit is used to select the type of output coding the AD7324 uses for the next conversion result. If
coding = 0, the output coding is twos complement. If coding = 1, the output coding is straight binary.
When operating in sequence mode, the output coding for each channel is the value written to the coding
bit during the last write to the control register.
The reference bit is used to enable or disable the internal reference. If Ref = 0, the external reference is
enabled and used for the next conversion, and the internal reference is disabled. If Ref = 1, the internal
reference is used for the next conversion. When operating in sequence mode, the reference used for each
channel is the value written to the Ref bit during the last write to the control register.
The Sequence 1 and Sequence 2 bits are used to control the operation of the sequencer (see Table 12).
The four analog input channels can be configured as three pseudo differential analog inputs, two pseudo differential inputs, two true
differential input pairs, or four single-ended analog inputs.
Table 10. Analog Input Configuration Selection
Channel Address Bits
ADD1
ADD0
0
0
0
1
1
0
1
1
Mode 1 = 1, Mode 0 = 1
3 Pseudo Differential I/Ps
VIN+
VIN−
VIN0
VIN3
VIN1
VIN3
VIN2
VIN3
Not a valid selection
Mode 1 = 1, Mode 0 = 0
2 Fully Differential I/Ps
VIN+
VIN−
VIN0
VIN1
VIN0
VIN1
VIN2
VIN3
VIN2
VIN3
Rev. 0 | Page 23 of 36
Mode 1 = 0, Mode 0 =1
2 Pseudo Differential I/Ps
VIN+
VIN−
VIN0
VIN1
VIN0
VIN1
VIN2
VIN3
VIN2
VIN3
Mode 1 = 0, Mode 0 = 0
4 Single-Ended I/Ps
VIN+
VIN−
VIN0
AGND
VIN1
AGND
VIN2
AGND
VIN3
AGND
AD7324
Table 11. Power Mode Selection
PM1
1
PM0
1
1
0
0
1
0
0
Description
Full Shutdown Mode. In this mode, all internal circuitry on the AD7324 is powered down. Information in the control register
is retained when the AD7324 is in full shutdown mode.
Autoshutdown Mode. The AD7324 enters autoshutdown on the 15th SCLK rising edge when the control register is updated.
All internal circuitry is powered down in autoshutdown.
Autostandby Mode. In this mode, all internal circuitry is powered down excluding the internal reference. The AD7324 enters
autostandby mode on the 15th SCLK rising edge after the control register is updated.
Normal Mode. All internal circuitry is powered up at all times.
Table 12. Sequencer Selection
Seq1
0
Seq2
0
0
1
1
0
1
1
Sequence Type
The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the
control register, selects the next channel for conversion.
Uses sequence of channels that were previously programmed in the sequence register for conversion. The AD7324 starts
converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted, the
AD7324 keeps converting the sequence. The range for each channel defaults to the range previously written into the
range register.
Used in conjunction with the channel address bits in the control register. This allows continuous conversions on a
consecutive sequence of channels, from Channel 0 up to and including a final channel selected by the channel address bits
in the control register. The range for each channel defaults to the range previously written into the range register.
The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the
control register, selects the next channel for conversion.
Rev. 0 | Page 24 of 36
AD7324
SEQUENCE REGISTER
The sequence register on the AD7324 is a 4-bit, write-only register. Each of the four analog input channels has one corresponding bit in
the sequence register. To select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequence register.
MSB
16
Write
15
Register Select 1
14
Register Select 2
13
VIN0
12
VIN1
11
VIN2
10
VIN3
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
LSB
1
0
RANGE REGISTER
The range register is used to select one analog input range per analog input channel. It is an 8-bit, write-only register with two dedicated
range bits for each of the analog input channels from Channel 0 to Channel 3. There are four analog input ranges, ±10 V, ±5 V, ±2.5 V, and
0 V to +10 V. A write to the range register is selected by setting the write bit to 1 and the register select bits to 0 and 1. After the initial write to
the range register occurs, each time an analog input is selected, the AD7324 automatically configures the analog input to the appropriate
range, as indicated by the range register. The ±10 V input range is selected by default on each analog input channel (see Table 13).
MSB
16
Write
15
Register Select 1
14
Register Select 2
13
VIN0A
12
VIN0B
11
VIN1A
10
VIN1B
9
VIN2A
Table 13. Range Selection
VINxA
0
0
1
1
VINxB
0
1
0
1
Description
This combination selects the ±10 V input range on VINx.
This combination selects the ±5 V input range on VINx.
This combination selects the ±2.5 V input range on VINx.
This combination selects the 0 V to +10 V input range on VINx.
Rev. 0 | Page 25 of 36
8
VIN2B
7
VIN3A
6
VIN3B
5
0
4
0
3
0
2
0
LSB
1
0
AD7324
SEQUENCER OPERATION
POWER ON.
CS
DIN: WRITE TO RANGE REGISTER TO SELECT THE RANGE
FOR EACH ANALOG INPUT CHANNEL.
DOUT: CONVERSION RESULT FROM CHANNEL 0, ± 10V
RANGE, SINGLE-ENDED MODE.
CS
DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE
ANALOG INPUT CHANNELS TO BE INCLUDED IN
THE SEQUENCE.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
SINGLE-ENDED MODE, RANGE SELECTED IN
RANGE REGISTER.
CS
DIN: WRITE TO CONTROL REGISTER TO START THE
SEQUENCE, Seq1 = 0, Seq2 = 1.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
SINGLE-ENDED MODE, RANGE SELECTED IN
RANGE REGISTER.
CS
DIN: TIE DIN LOW/WRITE BIT = 0 TO CONTINUE TO CONVERT
THROUGH THE SEQUENCE OF CHANNELS.
CS
DOUT: CONVERSION RESULT FROM FIRST CHANNEL IN
THE SEQUENCE.
DIN: WRITE TO CONTROL
REGISTER TO STOP THE
SEQUENCE, Seq1 = 0, Seq2 = 0.
STOPPING
A SEQUENCE.
DOUT: CONVERSION RESULT
FROM CHANNEL IN SEQUENCE.
DIN TIED LOW/WRITE BIT = 0.
CONTINUOUSLY CONVERT
ON THE SELECTED SEQUENCE
OF CHANNELS.
SELECTING A NEW SEQUENCE.
CS
DIN: WRITE TO SEQUENCE REGISTER TO SELECT THE
NEW SEQUENCE.
04864-031
DOUT: CONVERSION RESULT FROM CHANNEL X IN
THE FIRST SEQUENCE.
Figure 44. Programmable Sequence Flowchart
The AD7324 can be configured to automatically cycle through
a number of selected channels using the on-chip sequence
register with the Seq1 bit and the Seq2 bit in the control register.
Figure 44 shows how to program the AD7324 register to
operate in sequence mode.
After power-up, all of the three on-chip registers contain default
values. Each analog input has a default input range of ±10 V. If
different analog input ranges are required, a write to the range
register is required. This is shown in the first serial transfer of
Figure 44.
This initial serial transfer is only necessary if input ranges other
than the default ranges are required. After the analog input ranges
are configured, a write to the sequence register is necessary to
select the channels to be included in the sequence. Once the
channels for the sequence have been selected, the sequence can
be initiated by writing to the control register and setting Seq1 to
0 and Seq2 to 1. The AD7324 continues to convert the selected
sequence without interruption provided that the sequence register
remains unchanged, and Seq1 = 0 and Seq2 = 1 in the control
register.
Rev. 0 | Page 26 of 36
AD7324
If a change to the range register is required during a sequence, it
is necessary to first stop the sequence by writing to the control
register and setting Seq1 to 0 and Seq2 to 0. Next, the write to
the range register should be completed to change the required
range. The previously selected sequence should then be initiated
again by writing to the control register and setting Seq1 to 0 and
Seq2 to 1. The ADC converts on the first channel in the
sequence.
The AD7324 can be configured to convert a sequence of
consecutive channels (see Figure 45). This sequence begins by
converting on Channel 0 and ends with a final channel as
selected by Bit ADD1 to Bit ADD0 in the control register. In
this configuration, there is no need for a write to the sequence
register. To operate the AD7324 in this mode, set Seq1 to 1 and
Seq2 to 0 in the control register, and then select the final channel
in the sequence by programming Bit ADD1 to Bit ADD0 in the
control register.
Once the control register is configured to operate the AD7324
in this mode, the DIN line can be held low, or the write bit can
be set to 0. To return to traditional multichannel operation, a
write to the control register to set Seq1 to 0 and Seq2 to 0 is
necessary.
When the Seq1 and Seq2 are both set to 0, or when both are set
to 1, the AD7324 is configured to operate in traditional multichannel mode, where a write to Channel Address Bit ADD1 to
Bit ADD0 in the control register selects the next channel for
conversion.
POWER ON.
CS
DIN: WRITE TO RANGE REGISTER TO SELECT THE RANGE
FOR ANALOG INPUT CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 0, ± 10V
RANGE, SINGLE-ENDED MODE.
CS
DIN: WRITE TO CONTROL REGISTER TO SELECT THE FINAL
CHANNEL IN THE CONSECUTIVE SEQUENCE, SET Seq1 = 1
AND Seq2 = 0. SELECT OUTPUT CODING FOR SEQUENCE.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
RANGE SELECTED IN RANGE REGISTER,
SINGLE-ENDED MODE.
CS
DIN: WRITE BIT = 0 OR DIN LINE HELD LOW TO CONTINUE TO
CONVERT THROUGH THE SEQUENCE OF
CONSECUTIVE CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 0,
RANGE SELECTED IN RANGE REGISTER.
CS
DIN: WRITE BIT = 0 OR DIN LINE HELD LOW TO CONTINUE
THROUGH SEQUENCE OF CONSECUTIVE CHANNELS.
DOUT: CONVERSION RESULT FROM CHANNEL 1,
RANGE SELECTED IN RANGE REGISTER.
STOPPING
A SEQUENCE.
DIN TIED LOW/WRITE BIT = 0.
CONTINUOUSLY CONVERT
ON CONSECUTIVE SEQUENCE
OF CHANNELS.
CS
DOUT: CONVERSION RESULT
FROM CHANNEL IN SEQUENCE.
Figure 45. Flowchart for Consecutive Sequence of Channels
Rev. 0 | Page 27 of 36
04864-032
DIN: WRITE TO CONTROL
REGISTER TO STOP THE
SEQUENCE, Seq1 = 0, Seq2 = 0.
AD7324
REFERENCE
The AD7324 can operate with either the internal 2.5 V on-chip
reference or an externally applied reference. The internal reference
is selected by setting the Ref bit in the control register to 1. On
power-up, the Ref bit is 0, selecting the external reference for the
AD7324 conversion. Suitable reference sources for the AD7324
include AD780, AD1582, ADR431, REF193, and ADR391.
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When operating the AD7324
in internal reference mode, the 2.5 V internal reference is available
at the REFIN/OUT pin, which should be decoupled to AGND
using a 680 nF capacitor. It is recommended that the internal
reference be buffered before applying it elsewhere in the system.
The internal reference is capable of sourcing up to 90 μA.
On power-up, if the internal reference operation is required for
the ADC conversion, a write to the control register is necessary
to set the Ref bit to 1. During the control register write, the
conversion result from the first initial conversion is invalid. The
reference buffer requires 500 μs to power up and charge the
680 nF decoupling capacitor during the power-up time.
The AD7324 is specified for a 2.5 V to 3 V reference range.
When a 3 V reference is selected, the ranges are ±12 V, ±6 V,
±3 V, and 0 V to +12 V. For these ranges, the VDD and VSS supply
must be equal to or greater than the maximum analog input
range selected, see Table 6.
VDRIVE
The AD7324 has a VDRIVE feature to control the voltage at which
the serial interface operates. VDRIVE allows the ADC to easily
interface to both 3 V and 5 V processors. For example, if the
AD7324 is operated with a VCC of 5 V, the VDRIVE pin can be
powered from a 3 V supply. This allows the AD7324 to accept
large bipolar input signals with low voltage digital processing.
Rev. 0 | Page 28 of 36
AD7324
MODES OF OPERATION
The AD7324 has several modes of operation that are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements. The mode of
operation of the AD7324 is controlled by the power management bits, Bit PM1 and Bit PM0, in the control register as shown
in Table 11. The default mode is normal mode, where all internal
circuitry is fully powered up.
The AD7324 remains fully powered up at the end of the
conversion if both PM1 and PM0 contain 0 in the control
register.
To complete the conversion and access the conversion result
16 serial clock cycles are required. At the end of the conversion,
CS can idle either high or low until the next conversion.
NORMAL MODE
Once the data transfer is complete, another conversion can be
initiated after the quiet time, tQUIET, has elapsed.
(PM1 = PM0 = 0)
FULL SHUTDOWN MODE
This mode is intended for the fastest throughput rate
performance, with the AD7324 being fully powered up at all
times. Figure 46 shows the general operation of the AD7324
in normal mode.
(PM1 = PM0 = 1)
In this mode, all internal circuitry on the AD7324 is powered
down. The part retains information in the registers during full
shutdown. The AD7324 remains in full shutdown mode until
the power management bits, Bit PM1 and Bit PM0, in the
control register are changed.
The conversion is initiated on the falling edge of CS, and the
track-and-hold enters hold mode as described in the Serial
Interface section. Data on the DIN line during the 16 SCLK
transfer is loaded into one of the on-chip registers if the write
bit is set. The register is selected by programming the register
select bits (see Figure 46).
A write to the control register with PM1 = 1 and PM0 = 1 places
the part into full shutdown mode. The AD7324 enters full shutdown mode on the 15th SCLK rising edge rising edge once the
control register is updated.
CS
1
If a write to the control register occurs while the part is in full
shutdown mode with the power management bits, Bit PM1 and
Bit PM0, set to 0 (normal mode), the part begins to power up
on the 15th SCLK rising edge once the control register is
updated. Figure 47 shows how the AD7324 is configured to exit
full shutdown mode. To ensure the AD7324 is fully powered up,
tPOWER-UP for full shutdown mode should elapse before the next
CS falling edge
16
SCLK
DIN
04864-035
LEADING ZERO, 2 CHANNEL I.D. BITS, SIGN BIT +
CONVERSION RESULT
DOUT
DATA INTO CONTROL/SEQUENCE/RANGE REGISTER
Figure 46. Normal Mode
PART IS IN FULL
SHUTDOWN
THE PART IS FULLY POWERED UP
ONCE tPOWER-UP HAS ELAPSED
PART BEGINS TO POWER UP ON THE 15TH
SCLK RISING EDGE AS PM1 = PM0 = 0
tPOWER-UP
CS
1
16
16
1
SDATA
DIN
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER
DATA INTO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
PM1 = 0, PM0 = 0
TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0
IN CONTROL REGISTER
Figure 47. Exiting Full Shutdown Mode
Rev. 0 | Page 29 of 36
04864-041
SCLK
AD7324
AUTOSHUTDOWN MODE
(PM1 = 1, PM0 = 0)
Once the autoshutdown mode is selected, the AD7324 automatically enters shutdown on the 15th SCLK rising edge. In
autoshutdown mode, all internal circuitry is powered down. The
AD7324 retains information in the registers during autoshutdown.
The track-and-hold is in hold mode during autoshutdown. On
the rising CS edge, the track-and-hold, which was in hold during
shutdown, returns to track as the AD7324 begins to power up.
The power-up from autoshutdown is 500 μs.
When the control register is programmed to transition to
autoshutdown mode, it does so on the 15th SCLK rising edge.
Figure 48 shows the part entering autoshutdown mode. Once in
autoshutdown mode, the CS signal must remain low to keep the
part in autoshutdown mode. The AD7324 automatically begins to
power up on the CS rising edge. The tPOWER-UP for autoshutdown
is required before a valid conversion, initiated by bringing the
CS signal low, can take place. Once this valid conversion is
complete, the AD7324 powers down again on the 15th SCLK
rising edge. The CS signal must remain low again to keep the
part in autoshutdown mode.
As is the case with the autoshutdown mode, the AD7324 enters
standby on the 15th SCLK rising edge once the control register is
updated (see Figure 48). The part retains information in the
registers during standby. Once in autostandby mode, the CS
signal must remain low to keep the part in autostandby mode.
The AD7324 remains in standby until it receives a CS rising
edge. The ADC begins to power up on the CS rising edge. On
the CS rising edge, the track-and-hold, which was in hold mode
while the part was in standby, returns to track. The power-up
time from standby is 700 ns.
The user should ensure that 700 ns have elapsed before bringing
CS low to attempt a valid conversion. Once this valid conversion
is complete, the AD7324 again returns to standby on the 15th SCLK
rising edge. The CS signal must remain low to keep the part in
standby mode.
Figure 48 shows the part entering autoshutdown mode. The
sequence of events is the same when entering autostandby
mode. In Figure 48, the power management bits are configured
for autoshutdown. For autostandby mode, the power
management bits, PM1 and PM0, should be set to 0 and 1,
respectively.
AUTOSTANDBY MODE
(PM1 = 0, PM0 =1)
In autostandby mode, portions of the AD7324 are powered
down, but the on-chip reference remains powered up. The
reference bit in the control register should be 1 to ensure that
the on-chip reference is enabled. This mode is similar to
autoshutdown, but allows the AD7324 to power up much faster.
This allows faster throughput rates to be achieved.
PART BEGINS TO POWER
UP ON CS RISING EDGE
PART ENTERS SHUTDOWN MODE
ON THE 15TH RISING SCLK EDGE
AS PM1 = 1, PM0 = 0
CS
1
THE PART IS FULLY POWERED UP
ONCE tPOWER-UP HAS ELAPSED
tPOWER-UP
15 16
1
15 16
SCLK
DIN
VALID DATA
VALID DATA
DATA INTO CONTROL REGISTER
DATA INTO CONTROL REGISTER
04864-042
SDATA
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
PM1 = 1, PM0 = 0
Figure 48. Entering Autoshutdown/Autostandby Mode
Rev. 0 | Page 30 of 36
AD7324
20
POWER VS. THROUGHPUT RATE
18
16
12
20MHz SCLK
8
VARIABLE SCLK
6
4
VCC = 3V
VDD/VSS = ±12V
TA = 25°C
INTERNAL REFERENCE
2
0
100
200
300
400
500
600
700
800
900 1000 1100
THROUGHPUT RATE (kSPS)
04864-052
AVERAGE POWER (mW)
20MHz SCLK
12
10
8
6
4
VCC = 5V
VDD/VSS = ±12V
TA = 25°C
INTERNAL REFERENCE
2
0
0
100
200
300
400
500
600
700
800
900
THROUGHPUT RATE (kHz)
Figure 50. Power vs. Throughput Rate with 5 V VCC
10
0
VARIABLE SCLK
14
Figure 49. Power vs. Throughput Rate with 3 V VCC
Rev. 0 | Page 31 of 36
1000
04864-053
AVERAGE POWER (mW)
The power consumption of the AD7324 varies with throughput
rate. The static power consumed by the AD7324 is very low, and
a significant power savings can be achieved as the throughput
rate is reduced. Figure 49 and Figure 50 shows the power vs.
throughput rate for the AD7324 at a VCC of 3 V and 5 V,
respectively. Both plots clearly show that the average power
consumed by the AD7324 is greatly reduced as the sample
frequency is reduced. This is true whether a fixed SCLK value is
used or if it is scaled with the sampling frequency. Figure 49 and
Figure 50 show the power consumption when operating in
normal mode for a fixed 20 MHz SCLK and a variable SCLK
that scales with the sampling frequency.
AD7324
SERIAL INTERFACE
Figure 51 shows the timing diagram for the serial interface of
the AD7324. The serial clock applied to the SCLK pin provides
the conversion clock and controls the transfer of information to
and from the AD7324 during a conversion.
The CS signal initiates the data transfer and the conversion
process. The falling edge of CS puts the track-and-hold into
hold mode and takes the bus out of three-state. Then the analog
input signal is sampled. Once the conversion is initiated,
it requires 16 SCLK cycles to complete.
The track-and-hold goes back into track mode on the 14th SCLK
rising edge. On the 16th SCLK falling edge, the DOUT line returns
to three-state. If the rising edge of CS occurs before 16 SCLK cycles
have elapsed, the conversion is terminated, and the DOUT line
returns to three-state. Depending on where the CS signal is brought
high, the addressed register may be updated.
Data is clocked into the AD7324 on the SCLK falling edge. The
3 MSBs on the DIN line are decoded to select which register is
being addressed. The control register is a 12-bit register. If the
control register is addressed by the 3 MSBs, the data on the DIN
line is loaded into the control on the 15th SCLK rising edge. If the
sequence register or the range register is addressed, the data on
the DIN line is loaded into the addressed register on the 11th SCLK
falling edge.
Conversion data is clocked out of the AD7324 on each SCLK
falling edge. Data on the DOUT line consists of a leading ZERO
bit, two channel identifier bits, a sign bit, and a 12-bit conversion
result. The channel identifier bits are used to indicate which
channel corresponds to the conversion result. The leading ZERO
bit is clocked out on the CS falling edge, and the first channel
identifier bit is clocked out on the first SCLK falling edge.
t1
CS
tCONVERT
t2
1
2
3
4
2 IDENTIFICATION BITS
t3
DOUT
THREE- ZERO
STATE
DIN
ADD1
WRITE
ADD0
SIGN
t4
13
14
DB11
15
16
t5
t7
DB10
DB2
t8
DB1
DB0
t10
t9
REG
SEL1
5
REG
SEL2
tQUIET
THREE-STATE
MSB
LSB
DON’T
CARE
Figure 51. Serial Interface Timing Diagram (Control Register Write)
Rev. 0 | Page 32 of 36
04864-036
SCLK
t6
AD7324
MICROPROCESSOR INTERFACING
The serial interface on the AD7324 allows the part to be directly
connected to a range of different microprocessors. This section
explains how to interface the AD7324 with some common
microcontroller and DSP serial interface protocols.
AD7324 TO ADSP-218x
The ADSP-21xx family of DSPs interface directly to the AD7324
without requiring glue logic. The VDRIVE pin of the AD7324 takes
the same supply voltage as that of the ADSP-21xx. This allows
the ADC to operate at a higher supply voltage than its serial
interface. The SPORT0 on the ADSP-21xx should be configured
as shown in Table 14.
Table 14. SPORT0 Control Register Setup
Description
Alternative framing
Active low frame signal
Right justify data
16-bit data word
Internal serial clock
Frame every word
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3, an
SCLK of 2 MHz is obtained, and eight master clock periods elapse
for every one SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs occur between interrupts and,
subsequently, between transmit instructions. This situation leads
to nonequidistant sampling because the transmit instruction
occurs on an SCLK edge. If the number of SCLKs between
interrupts is an integer of N, equidistant sampling is implemented
by the DSP.
AD7324 TO ADSP-BF53x
The connection diagram is shown in Figure 52. The ADSP-21xx
has TFS0 and RFS0 tied together. TFS0 is set as an output, and
RFS0 is set as an input. The DSP operates in alternative framing
mode, and the SPORT0 control register is set up as described in
Table 14. The frame synchronization signal generated on the
TFS is tied to CS and, as with all signal processing applications,
requires equidistant sampling. However, as in this example, the
timer interrupt is used to control the sampling rate of the ADC
and under certain conditions equidistant sampling cannot be
achieved.
The ADSP-BF53x family of DSPs interface directly to the
AD7324 without requiring glue logic, as shown in Figure 53.
The SPORT0 Receive Configuration 1 register should be set up
as outlined in Table 15.
ADSP-BF53x1
AD73241
SCLK
CS
RFS0
DIN
DT0
DOUT
DR0
VDRIVE
ADSP-21xx1
AD73241
SCLK
RSCLK0
VDD
1ADDITIONAL PINS OMITTED FOR CLARITY.
SCLK0
04864-038
Setting
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
SLEN = 1111
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
The frequency of the serial clock is set in the SCLKDIV register.
When the instruction to transmit with TFS is given (AX0 = TX0),
the state of the serial clock is checked. The DSP waits until the
SCLK has gone high, low, and high again before starting the
transmission. If the timer and SCLK are chosen, so that the
instruction to transmit occurs on or near the rising edge of SCLK,
data can be transmitted immediately or at the next clock edge.
Figure 53. Interfacing the AD7324 to the ADSP-BF53x
CS
TFS0
RFS0
DIN
DT0
DOUT
DR0
Table 15. SPORT0 Receive Configuration 1 Register
VDD
1ADDITIONAL PINS OMITTED FOR CLARITY.
04864-037
VDRIVE
Figure 52. Interfacing the AD7324 to the ADSP-21xx
The timer registers are loaded with a value that provides an
interrupt at the required sampling interval. When an interrupt
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and, hence, the
reading of data.
Setting
RCKFE = 1
LRFS = 1
RFSR = 1
IRFS = 1
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
TFSR = RFSR = 1
Rev. 0 | Page 33 of 36
Description
Sample data with falling edge of RSCLK
Active low frame signal
Frame every word
Internal RFS used
Receive MSB first
Zero fill
Internal receive clock
Receive enable
16-bit data-word
AD7324
APPLICATION HINTS
LAYOUT AND GROUNDING
The printed circuit board that houses the AD7324 should be
designed so that the analog and digital sections are confined to
certain areas of the board. This design facilitates the use of
ground planes that can easily be separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally best. All AGND pins on the AD7324
should be connected to the AGND plane. Digital and analog
ground pins should be joined in only one place. If the AD7324
is in a system where multiple devices require an AGND and
DGND connection, the connection should still be made at only
one point. A star point should be established as close as possible
to the ground pins on the AD7324.
Good connections should be made to the power and ground
planes. This can be done with a single via or multiple vias for
each supply and ground pin.
Avoid running digital lines under the AD7324 device because
this couples noise onto the die. However, the analog ground
plane should be allowed to run under the AD7324 to avoid
noise coupling. The power supply lines to the AD7324 device
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
To avoid radiating noise to other sections of the board,
components, such as clocks, with fast switching signals should
be shielded with digital ground and never run near the analog
inputs. Avoid crossover of digital and analog signals. To reduce
the effects of feedthrough within the board, traces should be
run at right angles to each other. A microstrip technique is the
best method, but its use may not be possible with a doublesided board. In this technique, the component side of the board
is dedicated to ground planes, and signals are placed on the
other side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 μF tantalum capacitors in parallel with
0.1 μF capacitors to AGND. To achieve the best results from
these decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 μF capacitors should have a low effective series resistance
(ESR) and low effective series inductance (ESI), such as is
typical of common ceramic and surface mount types of
capacitors. These low ESR, low ESI capacitors provide a low
impedance path to ground at high frequencies to handle
transient currents due to internal logic switching.
Rev. 0 | Page 34 of 36
AD7324
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.65
BSC
0.30
0.19
COPLANARITY
0.10
0.20
0.09
8°
0°
SEATING
PLANE
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 54. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions show in millimeters
ORDERING GUIDE
Model
AD7324BRUZ 1
AD7324BRUZ-REEL1
AD7324BRUZ-REEL71
EVAL-AD7324CB 2
EVAL-CONTROL BRD2 3
1
2
3
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
Evaluation Board
Controller Board
Package Option
RU-16
RU-16
RU-16
Z = Pb-free part.
This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.
This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete
evaluation kit, the particular ADC evaluation board (for example, EVAL-AD7324CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the relevant
evaluation board technical note for more information.
Rev. 0 | Page 35 of 36
AD7324
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04864–0–12/05(0)
Rev. 0 | Page 36 of 36