AD ADUC812BS-REEL

a
MicroConverter™, Multichannel
12-Bit ADC with Embedded FLASH MCU
ADuC812
APPLICATIONS
FEATURES
Intelligent Sensors (IEEE 1451.2-Compatible)
ANALOG I/O
Battery Powered Systems (Portable PCs, Instruments,
8-Channel, High Accuracy 12-Bit ADC
Monitors)
On-Chip, 40 ppm/C Voltage Reference
Transient Capture Systems
High Speed 200 kSPS
DAS and Communications Systems
DMA Controller for High Speed ADC-to-RAM Capture
Two 12-Bit Voltage Output DACs
GENERAL DESCRIPTION
On-Chip Temperature Sensor Function
The ADuC812 is a fully integrated 12-bit data acquisition
MEMORY
system incorporating a high performance self-calibrating
8K Bytes On-Chip Flash/EE Program Memory
multichannel ADC, two 12-bit DACs and programmable 8-bit
640 Bytes On-Chip Flash/EE Data Memory
(8051-compatible) MCU on a single chip.
On-Chip Charge Pump (No Ext. VPP Requirements)
256 Bytes On-Chip Data RAM
The programmable 8051-compatible core is supported by
16M Bytes External Data Address Space
8K bytes Flash/EE program memory, 640 bytes Flash/EE data
64K Bytes External Program Address Space
memory and 256 bytes data SRAM on-chip.
8051-COMPATIBLE CORE
Additional MCU support functions include Watchdog Timer,
12 MHz Nominal Operation (16 MHz Max)
Power Supply Monitor and ADC DMA functions. 32 ProgramThree 16-Bit Timer/Counters
mable I/O lines, I2C-compatible, SPI and Standard UART
32 Programmable I/O lines
Serial Port I/O are provided for multiprocessor interfaces and
High Current Drive Capability—Port 3
I/O expansion.
Nine Interrupt Sources, Two Priority Levels
Normal, idle and power-down operating modes for both the
POWER
MCU core and analog converters allow for flexible power manSpecified for 3 V and 5 V Operation
agement schemes suited to low power applications. The part is
Normal, Idle and Power-Down Modes
specified for 3 V and 5 V operation over the industrial temperaON-CHIP PERIPHERALS
ture range and is available in a 52-lead, plastic quad flatpack
UART Serial I/O
package.
2-Wire (I 2C ®-Compatible) and SPI ® Serial I/O
Watchdog Timer
Power Supply Monitor
FUNCTIONAL BLOCK DIAGRAM
P0.0
P0.7
P1.0
P2.0
P2.7
P3.0
P3.7
BUF
AIN0 (P1.0)
AIN7 (P1.7)
P1.7
AIN
MUX
T/H
ADC
CONTROL
AND
CALIBRATION
LOGIC
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
ADuC812
12-BIT
DAC0
DAC0
DAC
CONTROL
BUF
12-BIT
DAC1
DAC1
T0 (P3.4)
MICROCONTROLLER
2.5V
REF
TEMP
SENSOR
8051-COMPATIBLE
MICROCONTROLLER
POWER SUPPLY
MONITOR
8K BYTES FLASH/EE
PROGRAM MEMORY
WATCHDOG
TIMER
640 BYTES FLASH/EE
DATA MEMORY
ON-CHIP SERIAL
DOWN LOADER
3 16-BIT
TIMER/COUNTERS
2-WIRE
SERIAL I/O
SPI
BUF
VREF
256 8 USER
RAM
OSC
MUX
UART
CREF
T1 (P3.5)
T2 (P1.0)
T2EX (P1.1)
INT0 (P3.2)
INT1 (P3.3)
ALE
PSEN
EA
RESET
AVDD
AGND
DVDD
DGND
XTAL XTAL TxD RxD SCLOCK MOSI/ MISO
1
2 (P3.0) (P3.1)
SDATA (P3.3)
I2C is a registered trademark of Philips Corporation.
MicroConverter is a trademark of Analog Devices, Inc.
SPI is a registered trademark of Motorola Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1, 2
(AV = DV = +3.0 V or +5.0 V 10%, V = 2.5 V Internal Reference,
ADuC812–SPECIFICATIONS
MCLKIN = 16.0 MHz, DAC V Load to AGND; R = 10 k, C = 100 pF. All specifications T = T to T , unless otherwise noted.)
DD
OUT
Parameter
ADC CHANNEL SPECIFICATIONS
DC ACCURACY3, 4
Resolution
Integral Nonlinearity
Differential Nonlinearity
CALIBRATED ENDPOINT ERRORS5, 6
Offset Error
Offset Error Match
Gain Error
Gain Error Match
USER SYSTEM CALIBRATION7
Offset Calibration Range
Gain Calibration Range
L
DD
L
REF
A
MIN
ADuC812BS
VDD = 5 V
VDD = 3 V
Units
12
± 1/2
± 1.5
± 1.5
±1
Bits
LSB typ
LSB max
LSB typ
LSB typ
12
± 1/2
± 1.5
±1
±5
±1
1
±6
±1
1.5
±2
1.5
LSB max
LSB typ
LSB typ
LSB max
LSB typ
LSB typ
±5
± 2.5
±5
± 2.5
% of VREF typ
% of VREF typ
±2
1
ANALOG INPUT
Input Voltage Ranges
Leakage Current
Input Capacitance
TEMPERATURE SENSOR9
Voltage Output at +25°C
Voltage TC
DAC CHANNEL SPECIFICATIONS
DC ACCURACY10
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Full-Scale Error
Full-Scale Mismatch
ANALOG OUTPUTS
Voltage Range_0
Voltage Range_1
Resistive Load
Capacitive Load
Output Impedance
ISINK
Test Conditions/Comments
fSAMPLE = 100 kHz
fSAMPLE = 100 kHz
fSAMPLE = 200 kHz
fSAMPLE = 100 kHz. Guaranteed No
Missing Codes at 5 V
fIN = 10 kHz Sine Wave
fSAMPLE = 100 kHz
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)8
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
MAX
70
–78
–78
70
–78
–78
dB typ
dB typ
dB typ
0 to VREF
± 10
±1
20
0 to VREF
+1
20
Volts
µA max
µA typ
pF max
600
–3.0
600
–3.0
mV typ
mV/°C typ
12
±3
± 0.5
± 50
± 25
± 25
± 10
± 0.5
12
±3
±1
± 10
± 0.5
Bits
LSB typ
LSB typ
mV max
mV typ
mV max
mV typ
% typ
0 to VREF
0 to VDD
10
100
0.5
50
0 to VREF
0 to VDD
10
100
0.5
50
V typ
V typ
kΩ typ
pF typ
Ω typ
µA typ
± 25
–2–
Measured On-Chip via a Typical
± 0.5 LSB (610 µV) Accurate ADC
Guaranteed 12-Bit Monotonic
% of Full-Scale on DAC1
REV. 0
ADuC812
Parameter
ADuC812BS
VDD = 5 V
VDD = 3 V
Units
Test Conditions/Comments
DAC AC CHARACTERISTICS
Voltage Output Settling Time
15
15
µs typ
10
10
nV sec typ
Full-Scale Settling Time to
Within 1/2 LSB of Final Value
1 LSB Change at Major Carry
2.3/VDD
150
2.45/2.55
2.5
40
2.3/VDD
150
V min/max
kΩ typ
V min/max
V typ
ppm/°C typ
Digital-to-Analog Glitch Energy
REFERENCE INPUT/OUTPUT
REFIN Input Voltage Range
Input Impedance
REFOUT Output Voltage
REFOUT Tempco
FLASH/EE MEMORY PERFORMANCE
CHARACTERISTICS11, 12
Endurance
2.5
40
10,000
50,000
10
50,000
Cycles min
Cycles typ
Years min
WATCHDOG TIMER
CHARACTERISTICS
Oscillator Frequency
64
64
kHz typ
POWER SUPPLY MONITOR
CHARACTERISTICS
Power Supply Trip Point Accuracy
± 2.5
Data Retention
± 1.0
DIGITAL INPUTS
Input High Voltage (VINH)
Input Low Voltage (VINL)
Input Leakage Current (Port 0, EA)
2.4
0.8
± 10
±1
± 1.0
V min
V max
µA max
µA typ
±1
Logic 1 Input Current
(All Digital Inputs)
± 10
±1
Logic 0 Input Current (Port 1, 2, 3)
–80
–40
Logic 1-0 Transition Current (Port 1, 2, 3) –700
–400
Input Capacitance
10
REV. 0
% of Selected
Nominal Trip
Point Voltage
max
% of Selected
Nominal Trip
Point Voltage
typ
±1
–40
–400
10
–3–
µA max
µA typ
µA max
µA typ
µA max
µA typ
pF typ
VIN = 0 V or VDD
VIN = 0 V or VDD
VIN = VDD
VIN = VDD
VIL = 450 mV
VIL = 2 V
VIL = 2 V
ADuC812–SPECIFICATIONS1, 2
Parameter
ADuC812BS
VDD = 5 V
VDD = 3 V
Units
Test Conditions/Comments
DIGITAL OUTPUTS
Output High Voltage (VOH)
2.4
V min
VDD = 4.5 V to 5.5 V
ISOURCE = 80 µA
VDD = 2.7 V to 3.3 V
ISOURCE = 20 µA
4.0
Output Low Voltage (VOL)
ALE, PSEN, Ports 0 and 2
Port 3
Floating State Leakage Current
Floating State Output Capacitance
POWER REQUIREMENTS13, 14, 15
IDD Normal Mode16
IDD Idle Mode
IDD Power-Down Mode17
0.4
0.2
0.4
0.2
± 10
±5
10
42
32
26
8
25
18
15
7
50
5
2.6
0.2
0.2
±5
10
16
12
3
17
6
2
50
5
V typ
V max
V typ
V max
V typ
µA max
µA typ
pF typ
ISINK = 1.6 mA
ISINK = 1.6 mA
ISINK = 8 mA
ISINK = 8 mA
mA max
mA typ
mA typ
mA typ
mA max
mA typ
mA typ
mA typ
µA max
µA typ
MCLKIN = 16 MHz
MCLKIN = 16 MHz
MCLKIN = 12 MHz
MCLKIN = 1 MHz
MCLKIN = 16 MHz
MCLKIN = 16 MHz
MCLKIN = 12 MHz
MCLKIN = 1 MHz
NOTES
1
Specifications apply after calibration.
2
Temperature range –40°C to +85°C.
3
Linearity is guaranteed during normal MicroConverter Core operation.
4
Linearity may degrade when programming or erasing the 640 Byte Flash/EE space during ADC conversion times due to on-chip charge pump activity.
5
Measured in production at V DD = 5 V after Software Calibration Routine at +25°C only.
6
User may need to execute Software Calibration Routine to achieve these specifications, which are configuration dependent.
7
The offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADuC812 can compensate.
8
SNR calculation includes distortion and noise components.
9
The temperature sensor will give a measure of the die temperature directly, air temperature can be inferred from this result.
10
DAC linearity is calculated using:
reduced code range of 48 to 4095, 0 to V REF range
reduced code range of 48 to 3995, 0 to V DD range
DAC output load = 10 kΩ and 50 pF.
11
Flash/EE Memory Performance Specifications are qualified as per JEDEC Specification A103 (Data Retention) and JEDEC Draft Specification All7 (Endurance).
12
Endurance Cycling is evaluated under the following conditions:
Mode
= Byte Programming, Page Erase Cycling
Cycle Pattern
= 00Hex to FFHex
Erase Time
= 20 ms
Program Time
= 100 µs
13
IDD at other MCLKIN frequencies is typically given by:
Normal Mode (V DD = 5 V):
IDD = (1.6 × MCLKIN) + 6
Normal Mode (V DD = 3 V):
IDD = (0.8 × MCLKIN) + 3
Idle Mode (V DD = 5 V):
IDD = (0.75 × MCLKIN) + 6
Idle Mode (V DD = 3 V):
IDD = (0.25 × MCLKIN) + 3
Where MCLKIN is the oscillator frequency in MHz and resultant I DD values are in mA.
14
IDD Currents are expressed as a summation of analog and digital power supply currents during normal MicroConverter operation.
15
IDD is not measured during Flash/EE program or erase cycles; I DD will typically increase by 10 mA during these cycles.
16
Analog IDD = 2 mA (typ) in normal operation (internal V REF, ADC and DAC peripherals powered on).
17
EA = Port0 = DV DD, XTAL1 (Input) tied to DV DD, during this measurement.
Typical specifications are not production tested, but are supported by characterization data at initial product release.
Specifications subject to change without notice.
Please refer to User Guide, Quick Reference Guide, Application Notes and Silicon Errata Sheet at www.analog.com/microconverter for additional information.
–4–
REV. 0
ADuC812
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
PSEN
EA
P0.0/AD0
ALE
P0.1/AD1
P0.3/AD3
P0.2/AD2
DVDD
DGND
P0.7/AD7
P0.6/AD6
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DVDD to DGND, AVDD to AGND . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to DGND . . . . . –0.3 V, DVDD + 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V, DVDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, AVDD + 0.3 V
Analog Inputs to AGND . . . . . . . . . . . . –0.3 V, AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
P0.5/AD5
P0.4/AD4
(TA = +25°C unless otherwise noted)
52 51 50 49 48 47 46 45 44 43 42 41 40
P1.0/ADC0/T2 1
P1.1/ADC1/T2EX 2
39 P2.7/A15/A23
PIN 1
IDENTIFIER
38 P2.6/A14/A22
37 P2.5/A13/A21
P1.2/ADC2 3
P1.3/ADC3 4
AVDD 5
36 P2.4/A12/A20
35 DGND
AGND 6
CREF 7
34 DVDD
33 XTAL2 (OUTPUT)
ADuC812
TOP VIEW
(Not to Scale)
VREF 8
DAC0 9
DAC1 10
32 XTAL1 (INPUT)
31 P2.3/A11/A19
30 P2.2/A10/A18
P1.4/ADC4 11
29 P2.1/A9/A17
P1.5/ADC5/SS 12
P1.6/ADC6 13
28 P2.0/A8/A16
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
27 SDATA/MOSI
P3.7/RD
SCLOCK
P3.6/WR
P3.4/T0
P3.5/T1/CONVST
DGND
P3.2/INT0
P3.3/INT1/MISO
DVDD
P3.0/RxD
P3.1/TxD
P1.7/ADC7
RESET
14 15 16 17 18 19 20 21 22 23 24 25 26
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
ADuC812BS
–40°C to +85°C
52-Lead Plastic Quad Flatpack
S-52
QuickStart™ Development System
Eval-ADuC812QS
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADuC812 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. 0
–5–
WARNING!
ESD SENSITIVE DEVICE
ADuC812
PIN FUNCTION DESCRIPTIONS
Mnemonic
Type Function
DVDD
AVDD
CREF
VREF
P
P
I
I/O
AGND
P1.0–P1.7
G
I
ADC0–ADC7
T2
I
I
T2EX
I
SS
SDATA
SCLOCK
MOSI
MISO
DAC0
DAC1
RESET
I
I/O
I/O
I/O
I/O
O
O
I
P3.0–P3.7
I/O
RxD
TxD
INT0
I/O
O
I
INT1
I
T0
T1
CONVST
I
I
I
WR
RD
XTAL2
XTAL1
DGND
P2.0–P2.7
(A8–A15)
(A16–A23)
O
O
O
I
G
I/O
PSEN
O
Digital Positive Supply Voltage, +3 V or +5 V nominal.
Analog Positive Supply Voltage, +3 V or +5 V nominal.
Decoupling pin for on-chip reference. Connect 0.1 µF between this pin and AGND.
Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the
reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this
appears at the pin (once the ADC or DAC peripherals are enabled). This pin can be overdriven by an external reference.
Analog Ground. Ground Reference point for the analog circuitry.
Port 1 is an 8-bit Input Port only. Unlike other Ports, Port 1 defaults to Analog Input Mode, to configure
any of these Port Pins as a digital input, write a “0” to the port bit. Port 1 pins are multifunction and share
the following functionality.
Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR.
Timer 2 Digital Input. Input to Timer/Counter 2. When Enabled, Counter 2 is incremented in response to
a 1 to 0 transition of the T2 input.
Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for
Counter 2.
Slave Select input for the SPI interface.
User selectable, I2C-Compatible Input/Output pin or SPI Data Input/Output pin.
Serial Clock pin for I2C-Compatible or SPI serial interface clock.
SPI Master Output/Slave Input Data I/O pin for SPI interface.
Master Input/Slave Output Data I/O pin for SPI Serial Interface.
Voltage Output from DAC0.
Voltage Output from DAC1.
Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the
device.
Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 3
pins being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also
contain various secondary functions which are described below.
Receiver Data Input (asynchronous) or Data Input/ Output (synchronous) of serial (UART) port.
Transmitter Data Output (asynchronous) or Clock Output (synchronous) of serial (UART) port.
Interrupt 0, programmable edge or level triggered Interrupt input, which can be programmed to one of two
priority levels. This pin can also be used as a gate control input to Timer 0.
Interrupt 1, programmable edge or level triggered Interrupt input, which can be programmed to one of two
priority levels. This pin can also be used as a gate control input to Timer 1.
Timer/Counter 0 Input.
Timer/Counter 1 Input.
Active low Convert Start Logic input for the ADC block when the external Convert start function is enabled. A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion.
Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory.
Read Control Signal, Logic Output. Enables the external data memory to Port 0.
Output of the inverting oscillator amplifier.
Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
Digital Ground. Ground reference point for the digital circuitry.
Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are
pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 2
pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits
the high order address bytes during fetches from external program memory and middle and high order
address bytes during accesses to the external 24-bit external data memory space.
Program Store Enable, Logic Output. This output is a control signal that enables the external program
memory to the bus during external fetch operations. It is active every six oscillator periods except during
external data memory accesses. This pin remains high during internal program execution. PSEN can also be
used to enable serial download mode when pulled low through a resistor on power-up or RESET.
–6–
REV. 0
ADuC812
Mnemonic
Type Function
ALE
O
EA
I
P0.7–P0.0
(A0–A7)
I/O
Address Latch Enable, Logic Output. This output is used to latch the low byte (and middle byte for 24-bit
address space accesses) of the address into external memory during normal operation. It is activated every
six oscillator periods except during an external data memory access.
External Access Enable, Logic Input. When held high, this input enables the device to fetch code from
internal program memory locations 0000H to 1FFFH. When held low this input enables the device to fetch
all instructions from external program memory.
Port 0 is an 8-bit open drain bidirectional I/O port. Port 0 pins that have 1s written to them float and in that
state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data bus
during accesses to external program or data memory. In this application it uses strong internal pull-ups
when emitting 1s.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise +distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
TERMINOLOGY
ADC SPECIFICATIONS
Integral Nonlinearity
This is the maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
1/2 LSB below the first code transition and full scale, a point
1/2 LSB above the last code transition.
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (0000 . . . 000)
to (0000 . . . 001) from the ideal, i.e., +1/2 LSB.
DAC SPECIFICATIONS
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error.
Full-Scale Error
This is the deviation of the last code transition from the ideal
AIN voltage (Full Scale – 1.5 LSB) after the offset error has
been adjusted out.
Voltage Output Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
REV. 0
Total Harmonic Distortion is the ratio of the rms sum of the
harmonics to the fundamental.
Digital to Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV sec.
–7–
ADuC812
ADuC812 ARCHITECTURE, MAIN FEATURES
The ADuC812 is a highly integrated high accuracy 12-bit data
acquisition system. At its core, the ADuC812 incorporates a high
performance 8-bit (8051-Compatible) MCU with on-chip reprogrammable nonvolatile Flash/EE program memory controlling a
multichannel (8-input channels), 12-bit ADC.
The chip incorporates all secondary functions to fully support the
programmable data acquisition core. These secondary functions
include User Flash/EE Data Memory, Watchdog Timer (WDT),
Power Supply Monitor (PSM) and various industry-standard
parallel and serial interfaces.
The lower 128 bytes of internal data memory are mapped as
shown in Figure 2. The lowest 32 bytes are grouped into four
banks of eight registers addressed as R0 through R7. The next
16 bytes (128 bits) above the register banks form a block of bit
addressable memory space at bit addresses 00H through 7FH.
The SFR space is mapped in the upper 128 bytes of internal
data memory space. The SFR area is accessed by direct addressing only and provides an interface between the CPU and all onchip peripherals. A block diagram showing the programming
model of the ADuC812 via the SFR area is shown in Figure 3.
7FH
ADuC812 MEMORY ORGANIZATION
As with all 8051-compatible devices, the ADuC812 has separate
address spaces for Program and Data memory as shown in Figure 1. Also as shown in Figure 1, an additional 640 Bytes of
Flash/EE Data Memory are available to the user. The Flash/EE
Data Memory area is accessed indirectly via a group of control
registers mapped in the Special Function Register (SFR) area.
30H
2FH
BIT-ADDRESSABLE SPACE
(BIT ADDRESSES 0–7FH)
BANKS
SELECTED
VIA
BITS IN PSW
20H
1FH
11
18H
PROGRAM MEMORY SPACE
READ ONLY
17H
10
10H
FFFFFFH
0FH
4 BANKS OF 8 REGISTERS
R0–R7
01
EXTERNAL
PROGRAM
MEMORY
SPACE
08H
07H
00
RESET VALUE OF
STACK POINTER
00H
Figure 2. Lower 128 Bytes of Internal RAM
2000H
EA = 1
INTERNAL
8K BYTE
FLASH/EE
PROGRAM
MEMORY
8K BYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE PROGRAM
MEMORY
1FFFH
0000H
EA = 0
EXTERNAL
PROGRAM
MEMORY
SPACE
DATA MEMORY SPACE
READ/WRITE
9FH
(PAGE 159)
8051COMPATIBLE
CORE
FFFFFFH
640-BYTE
ELECTRICALLY
REPROGRAMMABLE
NONVOLATILE
FLASH/EE DATA
MEMORY
128-BYTE
SPECIAL
FUNCTION
REGISTER
AREA
640 BYTES
FLASH/EE DATA
MEMORY
ACCESSED
INDIRECTLY
VIA SFR
CONTROL REGISTERS
00H
OTHER ON-CHIP
PERIPHERALS
TEMPERATURE
SENSOR
2 12-BIT DACs
SERIAL I/O
PARALLEL I/O
WDT
PSM
(PAGE 0)
INTERNAL
DATA MEMORY
SPACE
FFH
UPPER
128
80H
7FH
LOWER
128
00H
ACCESSIBLE
BY
INDIRECT
ADDRESSING
ONLY
ACCESSIBLE
BY
DIRECT
AND
INDIRECT
ADDRESSING
FFH
SPECIAL
FUNCTION
REGISTERS
ACCESSIBLE
BY DIRECT
ADDRESSING
ONLY
80H
SELF-CALIBRATING
8-CHANNEL
HIGH SPEED
12-BIT ADC
EXTERNAL
DATA
MEMORY
SPACE
(24-BIT
ADDRESS
SPACE)
Figure 3. ADuC812 Programming Model
ADC CIRCUIT INFORMATION
General Overview
The ADC conversion block incorporates a 5 µs, 8-channel,
12-bit, single supply A/D converter. This block provides the
user with multichannel mux, track/hold, on-chip reference,
calibration features and A/D converter. All components in this
block are easily configured via a 3-register SFR interface.
000000H
The A/D converter consists of a conventional successiveapproximation converter based around a capacitor DAC. The
converter accepts an analog input range of 0 to +VREF. A high
precision, low drift and factory calibrated 2.5 V reference is
Figure 1. ADuC812 Program and Data Memory Maps
–8–
REV. 0
ADuC812
Table I. ADCCON1 SFR Bit Designations
provided on-chip. The internal reference may be overdriven via
the external VREF pin. This external reference can be in the
range 2.3 V to AVDD.
Single step or continuous conversion modes can be initiated in
software or, alternatively, by applying a convert signal to an
external Pin 25 (CONVST). Timer 2 can also be configured
to generate a repetitive trigger for ADC conversions. The ADC
may be configured to operate in a DMA Mode whereby the
ADC block continuously converts and captures samples to an
external RAM space without any interaction from the MCU
core. This automatic capture facility can extend through a
16 MByte external Data Memory space.
The ADuC812 is shipped with factory programmed calibration
coefficients that are automatically downloaded to the ADC on
power-up, ensuring optimum ADC performance. The ADC
core contains internal Offset and Gain calibration registers, a
software calibration routine is provided to allow the user to
overwrite the factory programmed calibration coefficients if
required, thus minimizing the impact of endpoint errors in the
users target system.
Bit
Location
Bit
Mnemonic
ADCCON1.7
ADCCON1.6
MD1
MD0
The mode bits (MD1, MD0)
select the active operating mode
of the ADC as follows:
MD1 MD0 Active Mode
0
0
ADC powered down.
0
1
ADC normal mode
1
0
ADC powered down
if not executing a
conversion cycle.
1
1
ADC standby if not
executing a conversion cycle.
ADCCON1.5
ADCCON1.4
CK1
CK0
ADCCON1.3
ADCCON1.2
AQ1
AQ0
ADCCON1.1
T2C
ADCCON1.0
EXC
The ADC clock divide bits (CK1,
CK0) select the divide ratio for
the master clock used to generate
the ADC clock. An ADC conversion will require 16 ADC
clocks in addition to the selected
number of acquisition clocks (see
AQ0/AQ1 below). The divider
ratio is selected as follows:
CK1 CK0 MCLK Divider
0
0
1
0
1
2
1
0
4
1
1
8
The ADC acquisition select bits
(AQ1, AQ0) select the time available for the input track/hold
amplifier to acquire the input
signal and is selected as follows:
AQ1 AQ0 #ADC Clks
0
0
1
0
1
2
1
0
3
1
1
4
Note: for analog input source
impedances of <8 kΩ, the default
AQ0/AQ1 selection of 00, i.e., 1
Acquisition Clock will suffice. For
source impedances greater than
this, it is recommended that you
increase the acquisition clock
selection to 2, 3 or 4 clocks.
The Timer 2 conversion bit (T2C)
is set to enable the Timer 2 overflow bit to be used as the ADC
convert start trigger input.
The external trigger enable bit
(EXC) is set to allow the external
Pin 23 (CONVST) to be used as
the active low convert start input.
This input should be an active low
pulse (100 ns minimum pulsewidth)
at the required sample rate.
A voltage output from an on-chip temperature sensor proportional to absolute temperature can also be routed through the
front-end ADC multiplexor (effectively a 9th ADC channel
input) facilitating a temperature sensor implementation.
ADC Transfer Function
The analog input range for the ADC is 0 V to VREF. For this
range, the designed code transitions occur midway between
successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs,
5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight
binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when
VREF = 2.5 V. The ideal input/output transfer characteristic for
the 0 to VREF range is shown in Figure 4.
OUTPUT
CODE
111...111
111...110
111...101
111...100
1LSB =
FS
4096
000...011
000...010
000...001
000...000
0V 1LSB
+FS
–1LSB
VOLTAGE INPUT
Figure 4. ADuC812 ADC Transfer Function
SFR Interface to ADC Block
The ADC operation is fully controlled via three SFRs, namely:
ADCCON1 – (ADC Control SFR #1)
The ADCCON1 register controls conversion and acquisition
times, hardware conversion modes and power-down modes as
detailed below.
SFR Address:
SFR Power-On Default Value:
Bit Addressable:
MD1
REV. 0
MD0
CK1
CK0
EFH
20H
NO
AQ1
AQ0
T2C
Description
Note: In standby mode the ADC V REF circuits are maintained on, while in
powered down mode all ADC peripherals are powered down thus minimizing
current consumption. Typical ADC current consumption is 1.6 mA at V DD = 5 V.
EXC
–9–
ADuC812
ADCCON2 – (ADC Control SFR #2)
ADCCON3 – (ADC Control SFR #3)
The ADCCON2 register controls ADC channel selection and
conversion modes as detailed below.
The ADCCON3 register gives user software an indication of
ADC busy status.
SFR Address:
SFR Power On Default Value:
Bit Addressable:
SFR Address:
SFR Power On Default Value:
Bit Addressable:
D8H
00H
YES
ADCI DMA CCONV SCONV
CS3 CS2 CS1 CS0
F5H
00H
NO
BUSY RSVD RSVD RSVD CTYP CAL1 CAL0 CALST
Table II. ADCCON2 SFR Bit Designations
Table III. ADCCON3 SFR Bit Designations
Bit
Location
Bit
Mnemonic Description
ADCCON2.7
ADCI
ADCCON2.6
ADCCON2.5
ADCCON2.4
ADCCON2.3
ADCCON2.2
ADCCON2.1
ADCCON2.0
DMA
CCONV
SCONV
CS3
CS2
CS1
CS0
The ADC interrupt bit (ADCI) is
set by hardware at the end of a
single ADC conversion cycle or at
the end of a DMA block conversion. ADCI is cleared by hardware
when the PC vectors to the ADC
Interrupt Service Routine.
The DMA mode enable bit (DMA)
is set by the user to initiate a preconfigured ADC DMA mode operation. A more detailed description of
this mode is given below.
The continuous conversion bit
(CCONV) is set by the user to
initiate the ADC into a continuous
mode of conversion. In this mode
the ADC starts converting based on
the timing and channel configuration already set up in the ADCCON
SFRs, the ADC automatically starts
an other conversion once a previous
conversion cycle has completed.
The single conversion bit
(SCONV) is set by the user to
initiate a single conversion cycle.
The SCONV bit is automatically
reset to “0” on completion of the
single conversion cycle.
The channel selection bits (CS3-0)
allow the user to program the
ADC channel selection under
software control. Once a conversion is initiated the channel
converted will be that pointed to
by these channel selection bits. In
DMA mode the channel selection
is derived from the channel ID
written to the external memory.
CS3 CS2 CS1 CS0 CH#
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
Temp Sensor
1
X
X
X
Other
Combinations
1
1
1
1
DMA STOP
Bit
Location
Bit
Mnemonic Description
ADCCON3.7 BUSY
The ADC busy status bit (BUSY)
is a read-only status bit that is set
during a valid ADC conversion or
calibration cycle. Busy is automatically cleared by the core at the
end of conversion or calibration.
ADCCON3.6
ADCCON3.5
ADCCON3.4
ADCCON3.3
ADCCON3.2
ADCCON3.1
ADCCON3.0
ADCCON3.0–3.6 are reserved
(RSVD) for internal use. These
bits will read as zero and should
only be written as zero by user
software.
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
ADC Internal Reference
If the internal reference is being used, both the VREF and CREF
pins should be decoupled with 100 nF capacitors to AGND.
These decoupling capacitors should be placed very close to the
VREF and CREF pins. For specified performance, it is recommended that when using an external reference, this reference
should be between 2.3 V and the analog supply AVDD.
If the internal reference is required for use external to the
MicroConverter, it should be buffered at the VREF pin and a
100 nF capacitor should be connected from this pin to AGND.
The internal 2.5 V is factory calibrated to an absolute accuracy
of 2.5 V ± 50 mV. It should also be noted that the internal VREF
will remain powered down until either of the DACs or the ADC
peripheral blocks are powered on by their respective enable bits.
Calibration
The ADC block also has four associated calibration SFRs.
These SFR’s drive calibration logic ensuring optimum performance from the 12-bit ADC at all times. As part of the poweron reset configuration, these SFRs are configured automatically
and transparently from factory programmed calibration constants. In many applications use of factory programmed calibration constants will suffice; however, these calibration SFRs may
be overwritten by user code to further compensate for systemdependent offset and gain errors.
Calibration Overview
The ADC block incorporates calibration hardware that ensures
optimum performance from the ADC at all times. The calibration modes are exercised as part of the ADuC812 internal factory
final test routines. The factory calibration results are stored in
Flash memory and are automatically downloaded on any poweron-reset event to initialize the ADC calibration registers. In
–10–
REV. 0
ADuC812
many applications this autocalibration download function suffices. Alternatively, a device calibration can be easily initiated by
user software to compensate for significant changes in operating
conditions (CLK frequency, analog input range, reference voltage and supply voltages).
00000AH
This in-circuit software calibration feature allows the user to
remove various system and reference related errors (whether it
be internal or external reference) and to make use of the full
dynamic range of the ADC by adjusting the analog input range
of the part for a specific system. Contact Analog Devices, Inc.
for further details on the implementation of the software calibration routine in your applications.
Once configured via the ADCCON 1-3 SFRs (shown previously) the ADC will convert the analog input and provide an
ADC 12-bit result word in the ADCDATAH/L SFRs. The top
four bits of the ADCDATAH SFR will be written with the
channel selection bits to identify the channel result. The format
of the ADC 12-bit result word is shown in Figure 5.
1
1
STOP COMMAND
0
0
1
1
REPEAT LAST CHANNEL
FOR A VALID STOP
CONDITION
0
0
1
1
CONVERT ADC CH#3
1
0
0
0
CONVERT TEMP SENSOR
0
1
0
1
CONVERT ADC CH#5
0
0
1
0
CONVERT ADC CH#2
Figure 6. Typical DMA External Memory Preconfiguration
At the end of ADC DMA Mode, the external data memory
contains the new ADC conversion results as shown in Figure 7.
It should be noted that the channel selection bits are still present
in the result words to identify the individual conversion results.
ADCDATAH SFR
HIGH 4 BITS OF
ADC RESULT WORD
00000AH
ADCDATAL SFR
LOW 8 BITS OF THE
ADC RESULT WORD
Figure 5. ADC Result Format
ADC DMA Mode
The on-chip ADC has been designed to run at a maximum speed
of one sample every 5 µs (i.e., 200 kHz sampling rate). Therefore,
in an interrupt driven routine the user software is required to service the interrupt, read the ADC result and store the result for
further post processing, all within 5 µs otherwise the next ADC
sample could be lost. In applications where the ADuC812 cannot sustain the interrupt rate, an ADC DMA Mode is provided.
The ADC DMA Mode is enabled via the DMA enable bit
(ADCCON2.6), which allows the ADC to sample continuously
as per configuration in ADCCON SFRs. Each sample result is
written into an external Static RAM (mapped in the data memory
space) without any interaction from the ADuC812 core. This
mode ensures the ADuC812 can capture a contiguous sample
stream even at full speed ADC update rates.
000000H
1
1
1
1
STOP COMMAND
0
0
1
1
NO CONVERSION
RESULT WRITTEN HERE
0
0
1
1
CONVERSION RESULT
FOR ADC CH#3
1
0
0
0
CONVERSION RESULT
FOR TEMP SENSOR
0
1
0
1
CONVERSION RESULT
FOR ADC CH#5
0
0
1
0
CONVERSION RESULT
FOR ADC CH#2
Figure 7. Typical External Memory Configuration Post
ADC DMA Operation
Micro Operation during ADC DMA Mode
During ADC DMA mode the MicroConverter core is free to
continue code execution, including general housekeeping and
communication tasks. However, it should be noted that MCU
core accesses to Ports 0 and 2 (which, of course, are being used
by the DMA controller) are gated “OFF” during ADC DMA
mode of operation. This means that even though the instruction
that accesses the external Ports 0 or 2 will appear to execute, no
data will be seen at these external port pins as a result.
Before enabling ADC DMA mode the user must first configure
the external SRAM to which the ADC samples will be written.
This consists of writing the required ADC DMA channels into
the channel ID bits (the top four bits) in the external SRAM. A
typical preconfiguration of external memory is shown in Figure 6.
The MicroConverter core is interrupted once the requested
block of DMA data has been captured and written to external
memory allowing the service routine for this interrupt to postprocess the data without any real time, timing constraints.
Once the external data memory has been preconfigured, the
DMA address pointer (DMAP, DMAH and DMAL) SFRs are
written. These SFRs should be written with the DMA start
address in external memory. In Figure 6, for example, the DMA
start address is 000000H. The 3-byte start address should be
written in the following order: DMAL, DMAH and DMAP.
The end of a DMA table is signified by writing “1111” into the
channel selection bits field.
REV. 0
1
The DMA Enable bit (ADCCON2.6, DMA) can now be set to
initiate the DMA conversion and transfer of the results sequentially into external memory. Remember that the DMA mode
will only progress if the user has preconfigured the ADC
conversion time and trigger modes via the ADCCON1 and 2
SFRs. The end of DMA conversion is signified by the ADC
interrupt bit ADCCON2.7.
ADC MODES OF OPERATION
Typical Operation
CH–ID
TOP 4 BITS
000000H
1
SFR Interface to the DAC Block
The ADuC812 incorporates two 12-bit DACs on-chip. DAC
operation is controlled via a single control special function
register and four data special function registers, namely:
DAC0L/DAC1L – Contains the lower 8-bit DAC byte.
DAC0H/DAC1H – Contains the high 4-bit DAC byte.
DACCON
– Contains general purpose control bits
required for DAC0 and DAC1 operation.
–11–
ADuC812
In normal mode of operation each DAC is updated when the
low DAC nibble (DACxL) SFR is written. Both DACs can be
updated simultaneously using the SYNC bit in the DACCON
SFR.
NONVOLATILE FLASH MEMORY
Flash Memory Overview
In 8-bit mode of operation, the 8-bit byte written to the DACxL
registers is automatically routed to the top 8 bits of each 12-bit
DAC. The bit designations of the DACCON SFR are shown
below in Table IV.
SFR Address:
SFR Power On Default Value:
Bit Addressable:
FDH
04H
NO
Because Flash technology is based on a single transistor cell
architecture, a Flash memory array, like EPROM can be
implemented to achieve the space efficiencies or memory
densities required by a given design.
Table IV. DACCON SFR Bit Designations
Bit
Mnemonic Description
DACCON.7
MODE
DACCON.6
DACCON.5
RNG1
RNG0
Like EEPROM, Flash memory can be programmed in-system at
a byte level, although it must be erased first; the erase being
performed in sector blocks. Thus, Flash memory is often and
more correctly referred to as Flash/EE memory.
The DAC MODE bit sets the
overriding operating mode for
both DACs.
Set to “1” = 8-bit mode (Write 8
bits to DACxL SFR.
Set to “0” = 12-bit mode.
EPROM
TECHNOLOGY
DAC1 range select bit.
Set to “1” = DAC1 range 0–VDD.
Set to “0” = DAC1 range 0–VREF.
DAC0 range select bit.
Set to “1” = DAC0 range 0–VDD.
Set to “0” = DAC0 range 0–VREF.
DACCON.4
CLR1
DAC1 clear bit.
Set to “0” = DAC1 output forced
to 0 V.
Set to “1” = DAC1 output
normal.
DACCON.3
CLR0
DAC0 clear bit.
Set to “0” = DAC0 output forced
to 0 V.
Set to “1” = DAC0 output normal.
DACCON.2
SYNC
DAC0/1 update synchronization
bit.
When set to “1” the DAC outputs
update as soon as the DACxL
SFRs are written.
The user can simultaneously update both DACs by first updating
the DACxL/H SFRs while SYNC
is “0.”
DACCON.1
PD1
DACCON.0
PD0
Flash memory is the newest type of nonvolatile memory
technology and is based on a single transistor cell architecture.
This technology is basically an outgrowth of EPROM
technology and was developed through the late 1980s.
Flash memory takes the flexible in-circuit reprogrammable
features of EEPROM and combines them with the space
efficient/density features of EPROM (see Figure 8).
MODE RNG1 RNG0 CLR1 CLR0 SYNC PD1 PD0
Bit
Location
The ADuC812 incorporates Flash memory technology on-chip
to provide the user with a nonvolatile, in-circuit reprogrammable, code and data memory space.
Both DACs will then update
simultaneously when the SYNC
bit is set to “1.”
DAC1 Power-Down Bit.
Set to “1” = Power-On DAC1.
Set to “0” = Power-Off DAC1.
EEPROM
TECHNOLOGY
IN-CIRCUIT
REPROGRAMMABLE
SPACE EFFICIENT/
DENSITY
FLASH/EE MEMORY
TECHNOLOGY
Figure 8. Flash Memory Development
Overall, Flash/EE memory represents a step closer towards
the ideal memory device that includes nonvolatility, in-circuit
programmability, high density and low cost. Incorporated in
the ADuC812, Flash/EE memory technology allows the user to
update program code space in-circuit without the need to
replace one-time programmable (OTP) devices at remote
operating nodes.
Flash/EE Memory and the ADuC812
The ADuC812 provides two arrays of Flash/EE memory for
user applications.
8K bytes of Flash/EE Program space are provided on-chip to
facilitate code execution without any external discrete ROM
device requirements. The program memory can be programmed
using conventional third party memory programmers. This array
can also be programmed in-circuit, using the serial download
mode provided.
A 640-Byte Flash/EE Data Memory space is also provided onchip. This may be used by the user as a general purpose nonvolatile scratchpad area. User access to this area is via a group of
six SFRs. This space can be programmed at a byte level, although it must first be erased in 4-byte sectors.
Using the Flash/EE Program Memory
This 8K Byte Flash/EE Program Memory array is mapped
into the lower 8K bytes of the 64K bytes program space addressable by the ADuC812 and will be used to hold user code
in typical applications.
DAC0 Power-Down Bit.
Set to “1” = Power-On DAC0.
Set to “0” = Power-Off DAC0.
–12–
REV. 0
ADuC812
The program memory array can be programmed in one of two
modes, namely:
+5V
VDD
Serial Downloading (In-Circuit Programming)
PROGRAM
DATA
(D0–D7)
P0
GND
ADuC812
As part of its factory boot code, the ADuC812 facilitates serial
code download via the standard UART serial port. Serial download mode is automatically entered on power-up if the external
pin, PSEN, is pulled low through an external resistor as shown
in Figure 9. Once in this mode, the user can download code to
the program memory array while the device is sited in its target
application hardware. A PC serial download executable is provided as part of the ADuC812 QuickStart development system.
PROGRAM MODE
(SEE TABLE V)
P3
PROGRAM
ADDRESS
(A0–A13)
(P2.0 = A0)
(P1.7 = A13)
P1
PSEN
GND
VDD
P2
RST
XTAL1
WRITE ENABLE
STROBE
ALE
XTAL2
Figure 10. Flash/EE Memory Parallel Programming
The Serial Download protocol is detailed in a MicroConverter
Applications Note available from ADI.
Table V shows the normal parallel programming modes that can
be configured using Port 3 bits.
Table V. Flash Memory Parallel Programing Modes
PULL PSEN LOW DURING RESET TO
CONFIGURE THE ADuC812
FOR SERIAL DOWNLOAD MODE
ADuC812
Port Pins
.7 .6 .5
(P3.0–P3.7)
.4 .3 .2
.1
.0
Programming Mode
1
X
X
X
0
0
0
1
1
X
X
X
0
0
1
1
1
X X X
1
X X X
1
X X X
1
X X X
Any Other Code
0
0
1
1
1
1
0
0
0
1
0
1
1
1
1
1
Erase Flash Program
Erase Flash User
Read Manufacture and
Chip ID
Program Byte
Read Byte
Reserved
Reserved
Redundant
Using the Flash/EE Data Memory
The user Flash/EE data memory array consists of 640 bytes that
are configured into 160 (00H to 9FH), 4-byte pages as shown in
Figure 11.
PSEN
1k
Figure 9. Flash/EE Memory Serial Download Mode
Programming
9FH
BYTE 1
BYTE 2
BYTE 3
BYTE 4
00H
BYTE 1
BYTE 2
BYTE 3
BYTE 4
Parallel Programming
The parallel programming mode is fully compatible with conventional third party Flash or EEPROM device programmers. A
block diagram of the external pin configuration required to
support parallel programming is shown in Figure 10. In this
mode Ports P0, P1 and P2 operate as the external data and
address bus interface, ALE operates as the Write Enable strobe
and Port P3 is used as a general configuration port that configures the device for various program and erase operations during
parallel programming. The high voltage (12 V) supply required
for Flash programming is generated using on-chip charge pumps
to supply the high voltage program lines.
REV. 0
Figure 11. User Flash/EE Memory Configuration
As with other user peripherals the interface to this memory
space is via a group of registers mapped in the SFR space. A
group of four data registers (EDATA1-4) are used to hold the
4-byte page data just accessed. EADRL is used to hold the 8-bit
address of the page to be accessed. Finally, ECON is an 8-bit
control register that may be written with one of five Flash/EE
memory access commands to enable various read, write, erase
and verify modes.
–13–
ADuC812
Flash/EE Memory Write and Erase Times
A block diagram of the SFR registered interface to the User
Flash/EE Memory array is shown in Figure 12.
FUNCTION:
HOLDS THE 8-BIT PAGE
ADDRESS POINTER
9FH
The typical program/erase times for the User Flash/EE Memory
are:
Erase Full Array (640 Bytes)
Erase Single Page (4 Bytes)
Program Page (4 Bytes)
Read Page (4 Bytes)
FUNCTION:
HOLDS THE 4-BYTE
PAGE WORD
BYTE 1 BYTE 2 BYTE 3 BYTE 4
–
–
–
–
20 ms
20 ms
250 µs
Within Single Instruction Cycle
Using the Flash/EE Memory Interface
EADRL
As with all Flash/EE memory architectures, the array can be programmed in system at a byte level, although it must be erased
first; the erasure being performed in page blocks (4-byte pages
in this case).
EDATA1 (BYTE 1)
EDATA2 (BYTE 2)
EDATA3 (BYTE 3)
EDATA4 (BYTE 4)
00H
A typical access to the Flash/EE array will involve setting up the
page address to be accessed in the EADRL SFR, configuring the
EDATA1-4 with data to be programmed to the array (the
EDATA SFRs will not be written for read accesses) and finally
writing the ECON command word which initiates one of the
five modes shown in Table VI.
BYTE 1 BYTE 2 BYTE 3 BYTE 4
ECON COMMAND
INTERPRETER LOGIC
FUNCTION:
HOLDS COMMAND WORD
ECON
FUNCTION:
INTERPRETS THE FLASH
COMMAND WORD
It should be noted that a given mode of operation is initiated as
soon as the command word is written to the ECON SFR. At
this time the core microcontroller operation on the ADuC812
is idled until the requested Program/Read or Erase mode is
completed.
Figure 12. User Flash/EE Memory Control and
Configuration
ECON—Flash/EE Memory Control SFR
This SFR acts as a command interpreter and may be written
with one of five command modes to enable various read, program and erase cycles as detailed in Table VI:
Table VI. ECON–Flash/EE Memory Control Register
Command Modes
Command Byte
Command Mode
01H
READ COMMAND
Results in four bytes being read into
EDATA 1–4 from memory page location
contained in EADRL .
WRITE COMMAND
Results in four bytes (EDATA 1–4) being
written to memory page location in EADRL.
This write command assumes the designated “write” page has been pre-erased.
RESERVED COMMAND
“DO NOT USE”
VERIFY COMMAND
Allows the user to verify if data in EDATA
1–4 is contained in page location designated
by EADRL. A subsequent read of the
ECON SFR will result in a “zero” being
read if the verification is valid, a nonzero
value will be read to indicate an invalid
verification.
ERASE COMMAND
Results in an erase of the 4-byte page
designated in EADRL.
ERASE-ALL COMMAND
Results in erase of the full user memory
160-page (640 bytes) array.
RESERVED COMMANDS
Commands reserved for future use.
02H
03H
04H
05H
06H
07H to FFH
In practice, this means that even though the Flash/EE memory
mode of operation is typically initiated with a 2 machine cycle
MOV instruction (to write to the ECON SFR), the next
instruction will not be executed until the Flash/EE operation
is complete (250 µs or 20 ms later). This means that the core
will not respond to Interrupt requests until the Flash/EE
operation is complete, although the core peripheral functions
like Counter/Timers will continue to count and time as configured
throughout this pseudo-idle period.
ERASE-ALL
Although the 640-byte User Flash/EE array is shipped from the
factory pre-erased, i.e., Byte locations set to FFH, it is nonetheless good programming practice to include an erase-all routine
as part of any configuration/setup code running on the ADuC812.
An “ERASE-ALL” command consists of writing “06H” to the
ECON SFR, which initiates an erase of all 640 byte locations in
the Flash/EE array. This command coded in 8051 assembly
would appear as:
MOV ECON, #06H
; Erase all Command
; 20 ms Duration
PROGRAM A BYTE
In general terms, a byte in the Flash/EE array can only be
programmed if it has previously been erased. To be more specific, a byte can only be programmed if it already holds the value
FFH. Because of the Flash/EE architecture this erasure must
happen at a page level, therefore a minimum of four bytes (1 page)
will be erased when an erase command is initiated.
A more specific example of the Program-Byte process is shown
graphically in Figure 13. In this example the user will write F3H
into the second byte on Page 03H of the User Flash/EE Memory
space.
However, Page 03H already contains four bytes of valid data,
and as the user is only required to modify one of these bytes, the
full page must be first read so that this page can then be erased
without the existing data being lost.
–14–
REV. 0
ADuC812
06H
05H
04H
03H
02H
01H
00H
A5H
A5H
A5H
A5H
A5H
A5H
A5H
32H
32H
32H
32H
32H
32H
32H
05H
05H
05H
05H
05H
05H
05H
0DH
0DH
0DH
0DH
0DH
0DH
0DH
06H
05H
04H
03H
02H
01H
00H
A5H
A5H
A5H
FFH
A5H
A5H
A5H
32H
32H
32H
FFH
32H
32H
32H
05H
05H
05H
FFH
05H
05H
05H
0DH
0DH
0DH
FFH
0DH
0DH
0DH
06H
05H
04H
03H
02H
01H
00H
A5H
A5H
A5H
A5H
A5H
A5H
A5H
32H
32H
32H
32H
F3H
32H
32H
05H
05H
05H
05H
05H
05H
05H
0DH
0DH
0DH
0DH
0DH
0DH
0DH
0DH
05H
32H
A5H
EDATA4
EDATA3
EDATA2
EDATA1
0DH
05H
F3H
A5H
EDATA4
EDATA3
EDATA2
EDATA1
ERASE
0DH
05H
F3H
A5H
EDATA4
EDATA3
EDATA2
EDATA1
The new byte is then written to the EDATA2 SFR, followed by
an ERASE cycle that will ensure this page is erased before the
new page data EDATA1-4 is written back into memory.
READ PAGE 03H
MOV EADRL, #03H ;SET P PAGE
POINTER
MOV ECON, #01H ;INITIATE READ
MODE
If the user attempts to initiate a PROGRAM cycle (ECON
set to 02H) without an ERASE cycle (ECON set to 05H),
then only bit locations set to a “1” would be modified, i.e., the
Flash/EE memory byte location must be pre-erased to allow a
valid write access to the array. It should also be noted that the
time durations for an ERASE-ALL command (640 bytes) and
that for an ERASE page command (four bytes) are identical,
i.e., 20 ms.
WRITE NEW BYTE
TO EDATA2
MOV EDATA2, #0F3H ;WRITE NEW
BYTE
This example coded in 8051 assembly would appear as :
ERASE PAGE 03H
AND WRITE NEW DATA
TO PAGE 03H
MOV ECON, #05
;ERASE PAGE
MOV ECON, #02H ;PROGRAM
PAGE
MOV
MOV
MOV
MOV
MOV
EADRL, #03H
ECON, #01H
EDATA2, #0F3H
ECON, #02H
ECON, #05H
WRITE
INTERRUPT SYSTEM
Figure 13. User Flash/EE Memory Program Byte Example
POWER SUPPLY
MONITOR
The ADuC812 provides nine interrupt sources with two priority
levels. Interrupt priority within a given level is shown in descending order of priority in Figure 14, which gives a general
overview of the interrupt sources and illustrates the request and
control flags. The interrupt vector addresses for corresponding
interrupts are also included in Table VII.
HIGH PRIORITY
PSMI
PSCON.5
EXTERNAL INT0
P3.2
EPSM
IE2.1
LOW PRIORITY
IE0
TCON.1
ITO
TCON.0
END OF ADC
OR ADC DMA
MODE CONVERSION
EX0
IE1.0
PX0
IP.0
EADC
IE1.6
PADC
IP.6
ET0
IE1.1
PT0
IP.1
EX1
IE1.2
PX1
IP.2
ET1
IE1.3
PT1
IP.3
ESI
IE2.0
PSI
IP.7
ES
IE1.4
PS
IP.4
ET2
IE1.5
PT2
ADCI
AC2.7
TIMER 0
OVERFLOW
TF0
TCON.5
EXTERNAL INT1
P3.3
IE1
TCON.3
IT1
TCON.2
TIMER 1
OVERFLOW
TF1
TCON.7
I2CCON.0
I2CI
SPI/I2C
PORT
=1
ISPI
SPICON.7
SCON.0
RI
=1
UART
TI
TIMER 2
OVERFLOW
SCON.1
T2CON.7
TF2
=1
P1.1/T2EX
EXF2
EXEN.2
T2CON.6
T2CON.3
Figure 14. Interrupt Request Sources
REV. 0
; Set Page Pointer
; Read Page Command
; Write New Byte
; Erase Page Command
; Program Page Command
–15–
IP.5
ADuC812
Table VII. Interrupt Vector Addresses
Interrupt
Interrupt Name
Interrupt
Vector
Address
PSMI
IE0
ADCI
TF0
IE1
TF1
I2CI/ISPI
RI/TI
TF2/EXF2
Power Supply Monitor
External INT0
End of ADC Conversion
Timer 0 Overflow
External INT1
Timer 1 Overflow
Serial Interrupt
UART Interrupt
Timer 2 Interrupt
43H
03H
33H
0BH
13H
1BH
3BH
23H
2BH
Priority
Within
Level
1
2
3
4
5
6
7
8
9
Bit
Location
Bit
Mnemonic
IE.1
ET0
IE.0
EX0
Description
The Timer 0 Overflow Interrupt
Enable bit (ET0) is set to “1” to
enable the Timer 0 interrupt.
The INT0 Interrupt Enable bit
(EX0) is set to “1” to enable the
external INT0 interrupt
IE2 – (Interrupt Enable 2 SFR )
The IE2 register enables two additional interrupt sources.
SFR Address:
SFR Power On Default Value:
Bit Addressable:
A9H
00H
NO
Use of Interrupts
NU
To use any of the interrupts on the ADuC812, the following
three steps must be taken.
NU
NU
NU
Three SFRs are used to enable and set priority for the various
interrupts. The bit designations of these SFRs are shown in
Tables VIII, IX and X. It should be noted that while IE and IP
SFRs are bit addressable, IE2 is byte addressable only.
IE – (Interrupt Enable SFR)
Bit
Location
Bit
Mnemonic
IE2.7
IE2.6
IE2.5
IE2.4
IE2.3
IE2.2
IE2.1
NU
NU
NU
NU
NU
NU
EPSM
IE2.0
ESI
The IE register enables the interrupt system and seven interrupt
sources.
EA
EADC
ET2
ES
A8H
00H
YES
ET1
EX1
ET0
EX0
Table VIII. Interrupt Enable (IE) SFR Bit Designations
Bit
Location
Bit
Mnemonic
IE.7
EA
IE.6
IE.5
EADC
ET2
IE.4
ES
IE.3
ET1
IE.2
EX1
Description
The Global Interrupt Enable bit
(EA) must be set to “1” before any
interrupt source will be recognized
by the core. EA is set to “0” to disable all interrupts.
The ADC Interrupt Enable bit
(EADC) is set to “1” to enable the
ADC interrupt.
The Timer 2 Overflow Interrupt
Enable bit (ET2) is set to “1” to
enable the Timer 2 interrupt.
The UART Serial Port Interrupt
Enable bit (ES) is set to “1” to enable the UART Serial Port Interrupt.
The Timer 1 Overflow Interrupt
Enable bit (ET1) is set to “1” to
enable the Timer 1 interrupt.
The INT1 Interrupt Enable bit
(EX1) is set to “1” to enable the
external INT1 interrupt.
NU
EPSM ESI
Table IX. Interrupt Enable 2 (IE2) SFR Bit Designations
1. Locate the interrupt service routine at the corresponding
Vector Address of that interrupt. See Table VII above.
2. Set the EA (enable all) bit in the IE SFR to “1.”
3. Set the corresponding individual interrupt bit in the IE
or IE2 SFR to “1.”
SFR Address:
SFR Power On Default Value:
Bit Addressable:
NU
Description
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
The Power Supply Monitor
Interrupt enable bit is set to “1”
to enable the PSM Interrupt.
The SPI/I2C Interrupt Enable bit
(ESI) is set to “1” to enable the
SPI or I2C interrupt.
IP – (Interrupt Priority SFR )
The IP register sets one of two main priority levels for the various interrupt sources. Set the corresponding bit to “1” to configure interrupt as high priority and to “0” to configure interrupt
as low priority.
SFR Address:
SFR Power On Default Value:
Bit Addressable:
PS1 PADC
PT2
PS
B8H
00H
YES
PT1
PX1
PT0
PX0
Table X. Interrupt Priority (IP) SFR Bit Designations
Bit
Location
Bit
Mnemonic
IP.7
IP.6
IP.5
IP.4
PSI
PADC
PT2
PS
IP.3
IP.2
PT1
PX1
IP.1
IP.0
PT0
PX0
–16–
Description
Sets SPI/I2C Interrupt Priority
Sets ADC Interrupt Priority
Sets Timer 2 Interrupt Priority
Sets UART Serial Port Interrupt
Priority
Sets Timer 1 Interrupt Priority
Sets External INT1 Interrupt
Priority
Sets Timer 0 Interrupt Priority
Sets External INT0 Interrupt
Priority
REV. 0
ADuC812
In “Counter” function, the TLx register is incremented by a
1-to-0 transition at its corresponding external input pin, T0, T1
or T2.
ON-CHIP PERIPHERALS
The following sections give a brief overview of the various secondary peripherals also available on-chip. A quick reference to
the various SFR configuration registers used to control these
peripheral functions is given on the following pages.
ON-CHIP MONITORS
PARALLEL I/O PORTS 0–3
The ADuC812 uses four general purpose data ports to exchange
data with external devices. In addition to performing general
purpose I/O, some ports are capable of external memory operations; others are multiplexed with an alternate function for the
peripheral features on the device. In general, when a peripheral
sharing a port pin is enabled, that pin may not be used as a
general purpose I/O pin.
Ports 0, 2 and 3 are bidirectional while Port 1 is an input only
port. All ports contain an output latch and input buffer, the I/O
Ports will also contain an output driver. Read and Write accesses
to Port 0–3 pins are performed via their corresponding special
function registers.
Port pins on Ports 0, 2 and 3 can be independently configured
as digital inputs or digital outputs via the corresponding port
SFR bits. Port 1 pins however, can be configured as digital
inputs or analog inputs only, Port 1 digital output capability is
not supported on this device.
The ADuC812 integrates two on-chip monitor functions to
minimize code or data corruption during catastrophic programming or other external system faults. Again, both monitor functions are fully configurable via the SFR space.
WATCHDOG TIMER
The purpose of the watchdog timer is to generate a device reset
within a reasonable amount of time if the ADuC812 enters an
erroneous state, possibly due to a programming error, electrical
noise or RFI. The Watchdog function can be permanently disabled by clearing WDE (Watchdog Enable) bit in the Watchdog
Control (WDCON) SFR. When enabled, the watchdog circuit
will generate a system reset if the user program fails to refresh
the watchdog within a predetermined amount of time. The
watchdog reset interval can be adjusted via the SFR prescale bits
from 16 to 204 ms.
POWER SUPPLY MONITOR
The Power Supply Monitor generates an interrupt when
the analog (AVDD) or digital (DVDD) power supplies to the
ADuC812 drop below one of five user-selectable voltage trip
points from 2.6 V to 4.6 V The interrupt bit will not be cleared
until the power supply has returned above the trip point for at
least 256 ms.
SERIAL I/O PORTS
UART Interface
The serial port is full duplex, meaning it can simultaneously
transmit and receive. It is also receive-buffered, meaning it can
commence reception of a second byte before a previously received byte has been read from the receive register. However, if
the first byte still hasn't been read by the time reception of the
second byte is complete, one of the bytes will be lost.
The physical interface to the serial data network is via Pins
RxD(P3.0) and TxD(P3.1) and the serial port can be configured
into one of four modes of operation.
Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is an industry standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and received simultaneously. The
system can be configured for Master or Slave operation.
This monitor function ensures that the user can save working
registers to avoid possible data corruption due to the low supply
condition, and that code execution will not resume until a “safe”
supply level has been well established. The supply monitor is
also protected against spurious glitches triggering the interrupt
circuit.
QuickStart DEVELOPMENT SYSTEM
The QuickStart Development System is a full featured, low cost
development tool suite supporting the ADuC812. The system
consists of the following PC-based (Win95-compatible) hardware and software development tools.
Code Development: Full Assembler and C Compiler
(2K Code Limited)
Code Functionality: ADSIM812, Windows Code Simulator
Code Download: FLASH/EE UART-Serial Downloader
Code Debug: Serial Port Debugger
Misc: System includes CD-ROM documentation, power supply
and serial port cable.
I2C-Compatible Serial Interface
The ADuC812 supports a 2-wire serial interface mode that is
I2C-compatible. This interface can be configured to be a Software Master or Hardware Slave and is multiplexed with the SPI
serial interface port.
TIMERS/COUNTERS
The ADuC812 has three 16-bit Timer/Counters, namely: Timer 0,
Timer 1 and Timer 2. The Timer/Counter hardware has been
included on-chip to relieve the processor core of the overhead
inherent in implementing timer/counter functionality in software. Each Timer/Counter consists of two 8-bit registers THx
and TLx (x = 0, 1 and 2). All three can be configured to operate
either as timers or event counters.
In “Timer” function, the TLx register is incremented every
machine cycle. Thus one can think of it as counting machine
cycles. Since a machine cycle consists of 12 oscillator periods,
the maximum count rate is 1/12 of the oscillator frequency.
Figure 15. Typical QuickStart System Configuration
REV. 0
–17–
ADuC812
SPECIAL FUNCTION REGISTERS
All registers except the program counter and the four general purpose register banks, reside in the special function register (SFR)
area. The SFR registers include control, configuration and data registers that provide an interface between the CPU and other onchip peripherals.
Figure 16 shows a full SFR memory map and SFR contents on Reset; NOT USED indicates unoccupied SFR locations. Unoccupied
locations in the SFR address space are not implemented; i.e., no register exists at this location. If an unoccupied location is read, an
unspecified value is returned. SFR locations reserved for on-chip testing are shaded (RESERVED) and should not be accessed by
user software.
ISPI
WCOL
SPE
SP1M
CPOL
CPHA
SPR1
SPR0
FFH
0 FEH
0 FDH
0 FCH
0 FBH
0 FAH
0 F9H
0 F8H
0
F7H
0 F6H
0 F5H
0 F4H
0 F3H
0 F2H
F1H
0 F0H
0
MDO
EFH
E7H
MDE
0 EEH
0 E6H
ADCI
DFH
PS1
BFH
RD
B7H
EA
0 DCH
I2CM
0 EBH
PT2
0 BDH
T1
1 B5H
EADC
ET2
PS
0 BCH
T0
1 B4H
ES
CS2
RS0
CS1
OV
XEN
0 CBH
WDR1
0 C3H
PT1
0 BBH
PX1
0 BAH
INT1
1 B3H
INT0
1 B2H
ET1
EX1
P
CNT2
C9H
WDR2
0 C2H
0
0 D0H
0
CAP2
0 C8H
WDS
C1H
0
WDE
0 C0H
PT0
B9H
1 B1H
0
RxD
1
EX0
AFH
AEH
ADH
ACH
0 ABH
0 AAH
A9H
0 A8H
0
A7H
A6H
A5H
1 A4H
1 A3H
1 A2H
1 A1H
1 A0H
1
SM0
SM1
SM2
9FH
0 9EH
0 9DH
97H
0 96H
0 95H
REN
TB8
RB8
0 9BH
0 9AH
0 99H
0 94H
0 93H
0 92H
0 91H
SS/
TF1
TR1
TF0
T1
0 9CH
TR0
IE1
IT1
R1
0 98H
T2EX
0
T2
0 90H
IE0
0
IT0
8FH
0 8EH
0 8DH
0 8CH
0 8BH
0 8AH
0 89H
0 88H
0
87H
1 86H
1 85H
1 84H
1 83H
1 82H
1 81H
1 80H
1
SFR MAP KEY:
E8H
FAH
00H
DAC1L
FBH
00H
DAC1H
FCH
00H
DACCON
FDH
F1H
00H
RESERVED
F2H
20H
RESERVED
F3H
00H
RESERVED
F4H
00H
RESERVED
F5H
RESERVED
E0H
RESERVED
00H
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
00H
PSW1
D0H
RESERVED
B0H
RESERVED
A8H
NOT USED
A0H
98H
90H
B9H
88H
IE2
00H
A9H
80H
BAH
52H
PSMCON
00H
RCAP2H
CBH
00H
NOT USED
DMAP
D4H
TL2
CCH
ETIM2
BBH
04H
00H
ETIM3
TH2
CDH
RESERVED
RESERVED
RESERVED
RESERVED
00H
RESERVED
C9H
EDATA1
BCH
RESERVED
00H
00H
EDARL
C6H
EDATA2
BDH
00H
EDATA3
BEH
RESERVED
00H
00H
EDATA4
BFH
00H
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
NOT USED
00H
NOT USED
FFH
00H
SBUF
99H
I2CDAT
00H
NOT USED
9AH
00H
NOT USED
I2CADD
9BH
00H
NOT USED
FFH
00H
TMOD
89H
P01
BITS
00H
ETIM1
00H
NOT USED
TCON1
BITS
RESERVED
FFH
P11, 2
BITS
RCAP2L
DMAH
D3H
C4H
SCON1
BITS
00H
NOT USED
ECON
00H
P21
BITS
DMAL
CAH
IE1
BITS
20H
DFH DCH
00H
00H
P31
BITS
DAH
D2H
IP1
B8H
00H
00H
WDCON1
C0H
D9H
00H
T2CON1
C8H
BITS
00H
ADCCON1
00H
D8H
BITS
SPIDAT
F7H
EFH
BITS
BITS
NOT USED
04H
00H
ACC1
BITS
DAC0H
00H
ADCOFSL3 ADCOFSH3 ADCGAINL3 ADCGAINH3 ADCCON3
00H
I2CCON1
BITS
PX0
1 B0H
ET0
F0H
BITS
DAC0L
00H F9H
B1
BITS
0
0 B8H
TxD
F8H
ADCCON21 ADCDATAL ADCDATAH
CS0
FI
TR2
0
0 D8H
D1H
0 CAH
0
0 E0H
D9H
0 D2H
I2CI
0 E8H
E1H
0 DAH
0 D3H
NOT
USED
0 C4H
CS3
I2CTX
E9H
0 E2H
0 DBH
TCLK
0 CCH
I2CRS
0 EAH
0 E3H
RSI
0 D4H
PRE0
0 C5H
WR
1 B6H
0 E4H
RCLK
0 CDH
PADC
0 BEH
0 ECH
F0
0 D5H
PRE1
0 C6H
MDI
CCONV SCONV
0 DDH
EXF2
0 CEH
PRE2
C7H
0 E5H
AC
0 D6H
TF2
CFH
0 EDH
DMA
0 DEH
CY
D7H
MCO
SPICON1
BITS
FFH
TL0
00H
SP
81H
8AH
00H
TL1
8BH
DPL
07H
82H
00H
00H
DPH
83H
00H
TH0
8CH
00H
DPP
84H
00H
TH1
8DH
04H
RESERVED
RESERVED
PCON
87H
00H
THESE BITS ARE CONTAINED IN THIS BYTE.
MNEMONIC
SFR ADDRESS
IE0
89H
TCON
IT0
0 88H
0
88H
DEFAULT VALUE
00H
MNEMONIC
DEFAULT VALUE
SFR ADDRESS
SFR NOTES:
1SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE.
2THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT,
THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE
PORT PINS, WRITE A '0' TO THE CORRESPONDING PORT 1 SFR BIT.
COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES.
3CALIBRATION
Figure 16. Special Function Register Locations and Reset Values
–18–
REV. 0
ADuC812
ADCCON1
ADC CONTROL REGISTER #1
ADCCON3
ADC CONTROL REGISTER #3
ADCCON1.7 ADC POWER CONTROL BITS
ADCCON1.6 [SHTDN, NORM, AUTOSHTDN,
AUTOSTBY]
ADCCON1.5 CONVERSION TIME = 16/ADCCLK
ADCCON1.4 ADCCLK = MCLK/[1, 2, 4, 8]
ADCCON1.3 ACQUISITION TIME SELECT BITS
ADCCON1.2 ACQ TIME = [1, 2, 3, 4]/ADCCLK
ADCCON1.1 TIMER2 CONVERT ENABLE
ADCCON1.0 EXTERNAL CONVST ENABLE
ADCCON3.7 BUSY INDICATOR FLAG
(0 = ADC NOT ACTIVE)
ADCCON3.6 THIS BIT MUST CONTAIN ZERO
ADCCON3.5 THIS BIT MUST CONTAIN ZERO
ADCCON3.4 THIS BIT MUST CONTAIN ZERO
ADCCON3.3 THIS BIT MUST CONTAIN ZERO
ADCCON3.2 THIS BIT MUST CONTAIN ZERO
ADCCON3.1 THIS BIT MUST CONTAIN ZERO
ADCCON3.0 THIS BIT MUST CONTAIN ZERO
ADCCON2
ADCDATAH
ADC DATA REGISTERS
ADCDATAL
ADCI
DMA
CCONV
SCONV
CS3
CS2
CS1
CS0
ADC CONTROL REGISTER #2
ADC INTERRUPT FLAG
DMA MODE ENABLE
CONTINUOUS CONVERSION ENABLE BIT
SINGLE CONVERSION START BIT
INPUT CHANNEL SELECT BITS
0000–0111 = ADC0–ADC7
1XXX = TEMPERATURE SENSOR
1111 = "HALT" COMMAND
(IN DMA MODE ONLY)
DMAP, DMAH, DMAL DMA ADDRESS POINTER
ADCGAINH ADC GAIN
ADCGAINL CALIBRATION COEFFICIENTS
ADCOFSH
ADCOFSL
DACCON
DACCON.7
DACCON.6
DACCON.5
DACCON.4
DACCON.3
DACCON.2
DACCON.1
DACCON.0
DAC CONTROL REGISTER
MODESELECT (0 = 12 BIT, 1 = 8 BIT)
DAC1 RANGE SELECT (0 = VREF, 1 = VDD)
DAC0 RANGE SELECT (0 = VREF, 1 = VDD)
CLEAR DAC1
(0 = 0V, 1 = NORMAL OPERATION)
CLEAR DAC0
(0 = 0V, 1 = NORMAL OPERATION)
SYNCHRONOUS UPDATE
(1 = ASYNCHRONOUS)
POWERDOWN DAC1 (0 = OFF, 1 = ON)
POWERDOWN DAC0 (0 = OFF, 1 = ON)
DAC1H, DAC1L DAC1 DATA REGISTERS
DAC0H, DAC0L DAC0 DATA REGISTERS
ADC OFFSET
CALIBRATION COEFFICIENTS
Figure 17. ADC and DAC—Control and Configuration SFRs
P0
PORT0 REGISTER (ALSO A0–A7 & D0–D7)
P1
PORT1 REGISTER (ANALOG & DIGITAL INPUTS)
TIMER/COUNTER 2 CAPTURE/RELOAD TRIGGER
TIMER/COUNTER 2 EXTERNAL INPUT
T2EX
T2
P2
P3
RD
WR
T1
T0
INT1
INT0
TxD
RxD
PORT2 REGISTER (ALSO A8–A15 & A16–A23)
PORT3 REGISTER
EXTERNAL DATA MEMORY READ STROBE
EXTERNAL DATA MEMORY WRITE STROBE
TIMER/COUNTER 1 EXTERNAL INPUT
TIMER/COUNTER 0 EXTERNAL INPUT
EXTERNAL INTERRUPT 1
EXTERNAL INTERRUPT 0
SERIAL PORT TRANSMIT DATA LINE
SERIAL PORT RECEIVE DATA LINE
SCON SERIAL COMMUNICATIONS CONTROL REGISTER
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
UART MODE CONTROL BITS BAUD RATE:
00 - 8 BIT SHIFT REGISTER FOSC/12
01 - 8 BIT UART
TIMER OVERFLOW
RATE/32 (2)
10 - 9 BIT UART
FOSC/64 (2)
11 - 9 BIT UART
TIMER OVERFLOW
RATE/32 (2)
IN MODES 2&3, ENABLES MULTIPROCESSOR
COMMUNICATION
RECEIVE ENABLE CONTROL BIT
IN MODES 2&3, 9TH BIT TRANSMITTED
IN MODES 2&3, 9TH BIT RECEIVED
TRANSMIT INTERRUPT FLAG
RECEIVE INTERRUPT FLAG
SBUF
PCON
PCON.7
PCON.4
PCON.3
PCON.2
PCON.1
PCON.0
PSW
SERIAL PORT BUFFER REGISTER
POWER CONTROL REGISTER
DOUBLE BAUD RATE CONTROL
ALE DISABLE
(0 = NORMAL, 1 = FORCES ALE HIGH)
GENERAL PURPOSE FLAG
GENERAL PURPOSE FLAG
POWER-DOWN CONTROL BIT
(RECOVERABLE WITH HARD RESET)
IDLE-MODE CONTROL
(RECOVERABLE WITH ENABLED
INTERRUPT)
RS0
OV
F1
P
PROGRAM STATUS WORD
CARRY FLAG
AUXILIARY CARRY FLAG
GENERAL PURPOSE FLAG 0
REGISTER BANK SELECT
CONTROL BITS
ACTIVE REGISTER BANK = [0, 1, 2, 3]
OVERFLOW FLAG
GENERAL PURPOSE FLAG 1
PARITY OF ACC
DPP
DATA POINTER PAGE
CY
AC
F0
RS1
DPH, DPL (DPTR) DATA POINTER
ACC
ACCUMULATOR
B
SP
STACK POINTER
WDCON WATCHDOG TIME
PRE2
PRE1
PRE0
WDR1
WDR2
WDS
WDE
CONTROL REGISTER
WATCHDOG TIMEOUT SELECTION BITS
TIMEOUT = [16, 32, 64, 128, 256, 512, 1024,
2048] ms
WATCHDOG TIMER REFRESH BITS
SET SEQUENTIALLY TO REFRESH
WATCHDOG
WATCHDOG STATUS FLAG
WATCHDOG ENABLE
PSMCON POWER SUPPLY MONITOR
CONTROL REGISTER
PSMCON.7 (NOT USED)
PSMCON.6 PSM STATUS BIT
(1 = NORMAL/0 = FAULT)
PSMCON.5 PSM INTERRUPT BIT
PSMCON.4 TRIP POINT SELECT BITS
PSMCON.3 [4.63V, 4.37V, 3.08V, 2.93V, 2.63V]
PSMCON.2
PSMCON.1 AVDD/DVDD FAULT INDICATOR
(1 = ADD/0 = DVDD)
PSMCON.0 PSM POWERDOWN CONTROL
(1 = ON/0 = OFF)
ECON DATA FLASH MEMORY
COMMAND REGISTER
01h READ
04h VERIFY
02h WRITE
05h ERASE
03h (RESERVED) 06h ERASE ALL
EADRL DATA FLASH MEMORY
ADDRESS REGISTER
EDATA1, EDATA2, EDATA3, EDATA4
DATA FLASH DATA REGISTERS
ETIM1, ETIM2, ETIM3
FLASH TIMING REGISTERS
Figure 18. 8051 Core, On-Chip Monitors and Flash/EE Data Memory SFRs
REV. 0
–19–
ADuC812
IE
TCON
EA
TF1
INTERRUPT ENABLE REGISTER #1
ENABLE INTURRUPTS
(0 = ALL INTERRUPTS DISABLED)
EADC ENABLE ADCI (ADC INTERRUPT)
ET2
ENABLE TF2/EXF2
(TIMER2 OVERFLOW INTERRUPT)
ES
ENABLE RI/TI (SERIAL PORT INTERRUPT)
ET1
ENABLE TF1 (TIMER1 OVERFLOW INTERRUPT)
EX1
ENABLE IE1 (EXTERNAL INTERRUPT 1)
ET0
ENABLE TFO (TIMER0 OVERFLOW INTERRUPT)
EX0
ENABLE IE0 (EXTERNAL INTERRUPT 0)
IE2
IE2.1
IE2.0
INTERRUPT ENABLE REGISTER #2
ENABLE PSMI
(POWER SUPPLY MONITOR INTERRUPT)
ENABLE ISPI/I2CI
(SERIAL INTERFACE INTERRUPT)
IP
INTERRUPT PRIORITY REGISTER
PRIORITY OF ISI/ISPI
(SERIAL INTERFACE INTERRUPT)
PADC PRIORITY OF ADCI (ADC INTERRUPT)
PT2
PRIORITY OF TF2/EXF2
(TIMER2 OVERFLOW INTERRUPT)
PS
PRIORITY OF RI/TI (SERIAL PORT INTERRUPT)
PT1
PRIORITY OF TF1
(TIMER1 OVERFLOW INTERRUPT)
PX1
PRIORITY OF IE1 (EXTERNAL INT1)
PT0
PRIORITY OF TF0
(TIMER0 OVERFLOW INTERRUPT)
PX0
PRIORITY OF IE0 (EXTERNAL INT0)
PSI
TMOD
TIMER MODE REGISTER
GATE CONTROL BIT (0 = IGNORE INTx)
COUNTER/TIMER SELECT BIT (0 = TIMER)
TIMER MODE SELECTON BITS
[13 BIT T, 16 BIT T/C, 8 BIT T/C RELOAD,
2 8 BIT T]
(UPPER NIBBLE = TIMER1, LOWER NIBBLE = TIMER2)
TMOD.3/.7
TMOD.2/.6
TMOD.1/.5
TMOD.0/.4
TR1
TF0
TR0
IE1
IT1
IE0
IT0
TIMER CONTROL REGISTER
TIMER1 OVERFLOW FLAG
(AUTO CLEARED ON VECTOR TO ISR)
TIMER1 RUN CONTROL (0 = OFF, 1 = RUN)
TIMER0 OVERFLOW FLAG
(AUTO CLEARED ON VECTOR TO ISR)
TIMER0 RUN CONTROL (0 = OFF, 1 = RUN)
EXTERNAL INT1 FLAG
(AUTO CLEARED ON VECTOR TO ISR)
IE1 TYPE (0 = LEVEL TRIG, 1 = EDGE TRIG)
EXTERNAL INT0 FLAG
(AUTO CLEARED ON VECTOR TO ISR)
IE0 TYPE (0 = LEVEL TRIG, 1 = EDGE TRIG)
SPICON
ISPI
WCOL
SPE
SPIM
CPOL
CPHA
SPR1
SPR0
SPI CONTROL REGISTER
SPI INTERRUPT
(SET AT END OF SPI TRANSFER)
WRITE COLLISION ERROR FLAG
SPI ENABLE
(0 = DISABLE, ALSO ENABLES SPI)
MASTER MODE SELECT (0 = SLAVE)
CLOCK POLARITY SELECT
(0 = SCLK IDLES LOW)
CLOCK PHASE SELECT
(0 = LEADING EDGE LATCH)
SPI BITRATE SELECT BITS
BITRATE = FOSC / [4, 8, 32, 64]
TH0, TL0 TIMER0 REGISTERS
SPIDAT
TH1, TL1 TIMER1 REGISTERS
I2CCON
T2CON
MDO
MDE
TIMER2 CONTROL REGISTER
TF2
OVERFLOW FLAG
EXF2
EXTERNAL FLAG
RCLK RECEIVE CLOCK ENABLE
(0 = TIMER1 USED FOR RxD CLK)
TCLK TRANSMIT CLOCK ENABLE
(0 = TIMER1 USED FOR TxD CLK)
EXEN2 EXTERNAL ENABLE
(0 = IGNORE T2EX, 1 = CAP/RL)
TR2
RUN CONTROL (0 = STOP, 1 = RUN)
CNT2 TIMER/COUNTER SELECT
(0 = TIMER, 1 = COUNTER)
CAP2 CAPTURE/RELOAD SELECT
(0 = RELOAD, 1 = CAPTURE)
MCO
MDI
I2CM
I2CRS
I2CTX
I2CI
SPI DATA REGISTER
I2C CONTROL REGISTER
MASTER MODE SDATA OUTPUT BIT
MASTER MODE SDATA OUTPUT
ENABLE
MASTER MODE SCLK BIT
MASTER MODE SDATA INPUT BIT
MASTER MODE SELECT
SERIAL PORT RESET
TRANSMISSION DIRECTION STATUS
SERIAL INTERFACE INTERRUPT
I2CADD
I2C ADDRESS REGISTER
I2CDAT
I2C DATA REGISTER
TH2, TL2 TIMER2 REGISTER
RCAP2H, RCAP2L TIMER2 CAPTURE/RELOAD
Figure 19. Interrupt, Timer, SPI and I 2C Control SFRs
–20–
REV. 0
ADuC812
TIMING SPECIFICATIONS1, 2, 3 AV
DD
= DVDD = +3.0 V or 5.0 V 10%. All specifications TA = TMIN to TMAX unless otherwise noted.
Parameter
Min
CLOCK INPUT (External Clock Driven XTAL1)
XTAL1 Period
tCK
XTAL1 Width Low
tCKL
XTAL1 Width High
tCKH
tCKR
XTAL1 Rise Time
XTAL1 Fall Time
tCKF
tCYC4
ADuC812 Machine Cycle Time
12 MHz
Typ
Max
83.33
Variable Clock
Min
Typ
Max
62.5
20
20
20
20
1000
20
20
20
20
1
12tCK
Units
Figure
ns
ns
ns
ns
ns
µs
20
20
20
20
20
NOTES
1
AC inputs during testing are driven at DV DD – 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at V IH min for a Logic 1 and V IL max for
a Logic 0.
2
For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the
loaded V OH/VOL level occurs.
3
CLOAD for Port0, ALE, PSEN outputs = 100 pF; C LOAD for all other outputs = 80 pF unless otherwise noted.
4
ADuC812 Machine Cycle Time is nominally defined as MCLKIN/12.
tCKR
tCKH
tCKL
tCKF
tCK
Figure 20. XTAL 1 Input
VCC – 0.5V
0.45V
0.2VCC + 0.9V
TEST POINTS
0.2VCC – 0.1V
VLOAD – 0.1V
VLOAD
VLOAD + 0.1V
TIMING
REFERENCE
POINTS
Figure 21. Timing Waveform Characteristics
REV. 0
–21–
VLOAD – 0.1V
VLOAD
VLOAD – 0.1V
ADuC812
Parameter
12 MHz
Min
Max
Variable Clock
Min
Max
127
43
53
2tCK – 40
tCK – 40
tCK – 30
Units
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
22
22
22
22
22
22
22
22
22
22
22
22
EXTERNAL PROGRAM MEMORY
tLHLL
tAVLL
tLLAX
tLLIV
tLLPL
tPLPH
tPLIV
tPXIX
tPXIZ
tAVIV
tPLAZ
tPHAX
ALE Pulsewidth
Address Valid to ALE Low
Address Hold After ALE Low
ALE Low to Valid Instruction In
ALE Low to PSEN Low
PSEN Pulsewidth
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction Float After PSEN
Address to Valid Instruction In
PSEN Low to Address Float
Address Hold After PSEN High
234
4tCK – 100
53
205
tCK – 30
3tCK – 45
145
3tCK – 105
0
0
59
312
25
tCK – 25
5tCK – 105
25
0
0
MCLK
tLHLL
ALE (O)
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
PSEN (O)
PORT 0 (I/O)
tPXIZ
tPLAZ
tLLAX
tPXIX
INSTRUCTION
(IN)
PCL (OUT)
tAVIV
PORT 2 (O)
tPHAX
PCH
Figure 22. External Program Memory Read Cycle
–22–
REV. 0
ADuC812
Parameter
12 MHz
Min
Max
Variable Clock
Min
Max
400
43
48
6tCK – 100
tCK – 40
tCK – 35
Units
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
23
23
23
23
23
23
23
23
23
23
23
23
EXTERNAL DATA MEMORY READ CYCLE
tRLRH
tAVLL
tLLAX
tRLDV
tRHDX
tRHDZ
tLLDV
tAVDV
tLLWL
tAVWL
tRLAZ
tWHLH
RD Pulsewidth
Address Valid After ALE Low
Address Hold After ALE Low
RD Low to Valid Data In
Data and Address Hold After RD
Data Float After RD
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RD or WR Low
Address Valid to RD or WR Low
RD Low to Address Float
RD or WR High to ALE High
252
5tCK – 165
0
0
97
517
585
300
200
203
3tCK – 50
4tCK – 130
0
123
43
2tCK –70
8tCK – 150
9tCK – 165
3tCK + 50
0
6tCK – 100
tCK – 40
MCLK
ALE (O)
tWHLH
PSEN (O)
tLLDV
tLLWL
tRLRH
RD (O)
tAVWL
tRLDV
tAVLL
tRHDZ
tLLAX
tRHDX
tRLAZ
PORT 0 (I/O)
A0–A7 (OUT)
DATA (IN)
tAVDV
PORT 2 (O)
A16–A23
A8–A15
Figure 23. External Data Memory Read Cycle
REV. 0
–23–
ADuC812
Parameter
12 MHz
Min
Max
Variable Clock
Min
Max
Units
Figure
400
43
48
200
203
33
433
33
43
6tCK – 100
tCK – 40
tCK – 35
3tCK – 50
4tCK – 130
tCK – 50
7tCK – 150
tCK – 50
tCK – 40
ns
ns
ns
ns
ns
ns
ns
ns
ns
24
24
24
24
24
24
24
24
24
EXTERNAL DATA MEMORY WRITE CYCLE
tWLWH
tAVLL
tLLAX
tLLWL
tAVWL
tQVWX
tQVWH
tWHQX
tWHLH
WR Pulsewidth
Address Valid After ALE Low
Address Hold After ALE Low
ALE Low to RD or WR Low
Address Valid to RD or WR Low
Data Valid to WR Transition
Data Setup Before WR
Data and Address Hold After WR
RD or WR High to ALE High
300
123
3tCK + 50
6tCK – 100
MCLK
ALE (O)
tWHLH
PSEN (O)
tLLWL
tWLWH
WR (O)
tAVWL
tAVLL
tLLAX
PORT 0 (O)
A0–A7
PORT 2 (O)
A16–A23
tQVWX
tWHQX
tQVWH
DATA
A8–A15
Figure 24. External Data Memory Write Cycle
–24–
REV. 0
ADuC812
Parameter
Min
12 MHz
Typ Max
Variable Clock
Typ
Min
Max
Units
Figure
µs
ns
ns
ns
ns
25
25
25
25
25
UART TIMING (Shift Register Mode)
tXLXL
tQVXH
tDVXH
tXHDX
tXHQX
Serial Port Clock Cycle Time
Output Data Setup to Clock
Input Data Setup to Clock
Input Data Hold After Clock
Output Data Hold After Clock
1.0
12tCK
700
300
0
50
10tCK – 133
2tCK + 133
0
2tCK – 117
ALE (O)
tXLXL
TxD (OUTPUT CLOCK)
0
1
6
7
SET RI
OR
SET TI
tQVXH
tXHQX
RxD (OUTPUT DATA)
MSB
BIT6
BIT1
tDVXH
RxD (INPUT DATA)
MSB
LSB
tXHDX
BIT6
BIT1
Figure 25. UART Timing in Shift Register Mode
REV. 0
–25–
LSB
ADuC812
Parameter
Min
Max
Units
Figure
µs
µs
µs
ns
µs
µs
µs
26
26
26
26
26
26
26
µs
ns
ns
ns
26
26
26
26
2
I C COMPATIBLE INTERFACE TIMING
tL
tH
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Start Condition Hold Time
Data Setup Time
Data Hold Time
Setup Time for Repeated Start
Stop Condition Setup Time
Bus Free Time Between a STOP
Condition and a START Condition
Rise Time of Both SCLOCK and SDATA
Fall Time of Both SCLOCK and SDATA
Pulsewidth of Spike Suppressed
tR
tF
tSUP1
4.7
4.0
0.6
100
0
0.6
0.6
0.9
1.3
300
300
50
NOTE
1
Input filtering on both the SCLOCK and SDATA inputs suppress noise spikes which are less than 50 ns.
tBUF
tSUP
SDATA (I/O)
MSB
tDSU
LSB
SCLK (I)
tDSU
P
2-7
8
S
tL
MSB
tDHD
tH
1
STOP
START
CONDITION CONDITION
ACK
tDHD
tSHD
tPSU
tR
tR
tRSU
9
tSUP
1
S(R)
REPEATED
START
tF
Figure 26. I2C-Compatible Interface Timing
–26–
REV. 0
ADuC812
Parameter
Min
Typ
Max
Units
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
27
27
27
27
27
27
27
27
27
SPI MASTER MODE TIMING (CPHA = 1)
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Data Output Valid After SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge
Data Input Hold Time After SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
330
330
50
100
100
10
10
10
10
25
25
25
25
SCLOCK
(CPOL=0)
t SL
t SH
t SR
t SF
SCLOCK
(CPOL=1)
t DAV
MSB
MOSI
MISO
t DR
t DF
MSB IN
t DSU
BIT 6 – 1
t DHD
Figure 27. SPI Master Mode Timing (CPHA = 1)
REV. 0
LSB
BIT 6 – 1
–27–
LSB IN
ADuC812
Parameter
Min
Typ
Max
Units
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
28
28
28
28
28
28
28
28
28
28
SPI MASTER MODE TIMING (CPHA = 0)
tSL
tSH
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Data Output Valid After SCLOCK Edge
Data Output Setup Before SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge
Data Input Hold Time After SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
330
330
50
150
100
100
10
10
10
10
25
25
25
25
SCLOCK
(CPOL=0)
t SL
t SH
t SF
t SR
SCLOCK
(CPOL=1)
t DAV
t DF
t DOSU
MSB
MOSI
MISO
MSB IN
t DSU
t DR
BIT 6 – 1
BIT 6 – 1
LSB
LSB IN
t DHD
Figure 28. SPI Master Mode Timing (CPHA = 0)
–28–
REV. 0
ADuC812
Parameter
Min
Typ
Max
Units
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
29
29
29
29
29
29
29
29
29
29
29
SPI SLAVE MODE TIMING (CPHA = 1)
tSS
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tSFS
SS to SCLOCK Edge
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Data Output Valid After SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge
Data Input Hold Time After SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
SS High After SCLOCK Edge
0
330
330
50
100
100
10
10
10
10
25
25
25
25
0
SS
t SFS
t SS
SCLOCK
(CPOL=0)
t SL
t SH
t SF
t SR
SCLOCK
(CPOL=1)
t DAV
MISO
MOSI
t DR
t DF
MSB
BIT 6 – 1
MSB IN
t DSU
BIT 6 – 1
t DHD
Figure 29. SPI Slave Mode Timing (CPHA = 1)
REV. 0
–29–
LSB
LSB IN
ADuC812
Parameter
Min
Typ
Max
Units
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
30
30
30
30
30
30
30
30
30
30
30
30
SPI SLAVE MODE TIMING (CPHA = 0)
tSS
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOSS
tSFS
SS to SCLOCK Edge
SCLOCK Low Pulsewidth
SCLOCK High Pulsewidth
Data Output Valid After SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge
Data Input Hold Time After SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
Data Output Valid After SS Edge
SS High After SCLOCK Edge
0
330
330
50
100
100
10
10
10
10
25
25
25
25
20
SS
t SFS
t SS
SCLOCK
(CPOL=0)
t SH
t SL
t SR
t SF
SCLOCK
(CPOL=1)
t DAV
t DOSS
t DF
MSB
MISO
MOSI
MSB IN
t DSU
t DR
BIT 6 – 1
BIT 6 – 1
LSB
LSB IN
t DHD
Figure 30. SPI Slave Mode Timing (CPHA = 0)
–30–
REV. 0
ADuC812
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.557 (14.15)
0.537 (13.65)
0.398 (10.11)
0.390 (9.91)
0.094 (2.39)
0.084 (2.13)
0.037 (0.95)
0.026 (0.65)
52
1
40
39
SEATING
PLANE
0.398 (10.11)
0.390 (9.91)
0.557 (14.15)
0.537 (13.65)
PIN 1
TOP VIEW
(PINS DOWN)
0.012 (0.30)
0.006 (0.15)
0.008 (0.20)
0.006 (0.15)
13
14
0.0256
(0.65)
BSC
27
26
0.014 (0.35)
0.010 (0.25)
PRINTED IN U.S.A.
0.082 (2.09)
0.078 (1.97)
C3504–8–5/99
52-Lead Plastic Quad Flatpack
(S-52)
REV. 0
–31–