Final Product Specification P2065 Low Spread LCD Panel EMI Reduction IC FEATURES • Provides up to 20 dB of EMI suppression • 2 selectable modulation rates • FCC approved method of EMI attenuation • Low cycle-to-cycle jitter • Generates a low EMI spread spectrum clock of the input frequency • 3.3V or 5.0 V operating range • • 16 mA output drives 40 MHz to 85 MHz input frequency range • • TTL or CMOS compatible outputs Optimized for VGA, SVGA and high resolution XGA LCD panels • Low power CMOS design • Internal loop filter minimizes external components and board space • Supports most mobile graphic accelerator specifications • 6 selectable low spread ranges, under +/- 1% • Available in 8 pin SOIC and TSSOP • SSON control pin for spread spectrum enable and disable options compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called “spread spectrum clock generation”. PRODUCT DESCRIPTION The P2065 is a selectable spread spectrum frequency modulator designed specifically for digital flat panel applications. The P2065 reduces electromagnetic interference (EMI) at the clock source which provides system wide reduction of EMI of all clock dependent signals. The P2065 allows significant system cost savings by reducing the number of circuit board layers and shielding that are traditionally required to pass EMI regulations. APPLICATIONS The P2065 is targeted towards digital flat panel applications for Notebook PCs, Palm-size PCs, Office Automation Equipments, and LCD Monitors. Figure 1 – P2065 Pin Diagram The P2065 uses the most efficient and optimized modulation profile approved by the FCC and is implemented in a proprietary alldigital method. The P2065 modulates the output of a single PLL in order to “spread” the bandwidth of a synthesized clock and, more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI Jan., 2001 Revision D CLKIN 1 8 VDD MRA 2 7 SR0 SR1 3 6 ModOUT VSS 4 5 SSON 3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054 Tel (408) 748-6988 • Fax (408) 748-0009 1 of 6 http://www.pulsecore.com Final Product Specification P2065 Figure 2 – P2065 Block Diagram VDD SR0 SR1 MRA SSON PLL Modulation CLKIN Frequency Divider Feedback Divider Phase Detector Loop Filter VCO Output Divider ModOUT P2065 Block Diagram VSS Table 1 – Modulation Selection MRA SR1 SR0 Spreading Range Modulation Rate 0 0 0 +/- 0.3% (Fin/40) * 34.72 KHz ** 0 0 1 +/- 0.6% (Fin/40) * 34.72 KHz ** 0 1 0 +/- 0.4% (Fin/40) * 34.72 KHz ** 0 1 1 +/- 0.8% (Fin/40) * 34.72 KHz 1 0 0 +/- 0.5% (Fin/40) * 20.83 KHz 1 0 1 +/- 1.00% (Fin/40) * 20.83 KHz 1 1 0 RESERVED RESERVED 1 1 1 RESERVED RESERVED **NOTE: THESE SETTINGS ARE NOT RECOMMENDED FOR 5.0V OPERATION Pin Description PIN # Name Type Description 1 CLKIN I External reference frequency input. Connect to externally generated reference signal. Select appropriate part for the intended input frequency (see Table 1). 2 MRA I Digital logic input used to select modulation rate (see Table 3). This pin has a 100K Ohm internal pull-up resistor. 3 SR1 I Digital logic input used to select Spreading Range (see Table 2). This pin has a 100K Ohm internal pull-up resistor. 4 VSS P Ground Connection. Connect to system ground. 5 SSON I Digital logic input used to enable Spread Spectrum function (Active Low). Spread Spectrum function enable when low. This pin has a 100K Ohm internal pull-low resistor. 6 ModOUT O Spread Spectrum Clock Output. 7 SR0 I Digital logic input used to select Spreading Range (see Table 1). This pin has a 100K Ohm internal pull-up resistor. 8 VDD P Connect to +3.3V or +5.0V Jan., 2001 Revision D 3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054 Tel (408) 748-6988 • Fax (408) 748-0009 2 of 7 http://www.pulsecore.com Final Product Specification P2065 SPREAD SPECTRUM SELECTION Table 1 illustrates the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center frequency (Note: the center frequency is the frequency of the external reference input on CLKIN, Pin 1). Example: P2065 is designed for high resolution flat panel applications and is able to support XGA (1024 X 768) flat panel that operates on 65MHz (Fin) clock speed. A spreading selection of SR1=0, SR0=1 and modulation rate selection MRA=1 provides a percentage deviation of +/-1.00% (see Table 1) of Fin. This results in frequency on ModOUT being swept from 64.35 MHz to 65.65 MHz at a modulation rate of 33.85KHz (see Table 1). This particular example (see Figure 3) given here is a common EMI reduction method for notebook LCD panel and has already been implemented by most of the leading OEM and mobile graphic accelerator manufacturers. Figure 3 – P2065 Application Schematic For Mobile LCD Graphics Controllers 65 MHZ From Graphics Accelerator 1 CLKIN VDD 8 2 MRA SR0 7 ModOUT 6 SSON 5 This signal is connected back to the Spread Spectrum Input Pin (SSIN) of the Graphics Accelerator. 0.1uF VDD 3 SR1 4 VSS P2065 Digital Control for SS enable or disable EMC SOFTWARE SIMULATION ® By using PulseCore Semiconductor, Inc.’s proprietary EMC simulation software – EMI-lator , radiated system level EMI analysis can be made easier to allow a quantitative assessment on PulseCore’s EMI reduction products. The simulation engine of this EMC software has already been characterized to correlate with the electrical characteristics of PulseCore EMI reduction IC’s. Figure 4 below is an example of the simulation result. Please visit our web site at www.pulsecore.com for information on how ® to obtain a free copy and demonstration of EMI-lator . Jan., 2001 Revision D 3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054 Tel (408) 748-6988 • Fax (408) 748-0009 3 of 7 http://www.pulsecore.com Final Product Specification P2065 Figure 4 –Simulation Result from EMI-lator Jan., 2001 Revision D ® 3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054 Tel (408) 748-6988 • Fax (408) 748-0009 4 of 7 http://www.pulsecore.com Final Product Specification P2065 ABSOLUTE MAXIMUM RATINGS Symbol Parameter VDD, VIN TSTG TA Voltage on any pin with respect to GND Storage Temperature Operating Temperature Rating Unit -0.5 to +7.0 -65 to +125 0 to +70 V ºC ºC DC ELECTRICAL CHARACTERISTICS Symbol Parameter Min Typ Max Unit VIL Input Low Voltage GND – 0.3 - 0.8 V VIH Input High Voltage 2.0 - VDD + 0.3 V IIL Input Low Current (100 KΩ input pull-up resistor on inputs SR0,1 and MRA) Input High Current (100 KΩ input pulldown resistor on input SSON) Output Low Voltage (VDD=3.3V, IOL = 20 mA) Output High Voltage (VDD=3.3V, IOH = 20 mA) Static Supply Current - - -35 µA - - 35 µA - - 0.4 V 2.5 - - V - 0.6 - mA 7 9 13 mA 2.7 3.3 5.5 V IIH VOL VOH IDD ICC VDD tON ZOUT Dynamic Supply Current (3.3V and 15 pF loading) Operating Voltage Power Up Time (First locked clock cycle after power up) Clock Output Impedance 0.18 mS 50 Ω AC ELECTRICAL CHARACTERISTICS Symbol Parameter Min Typ Max Unit fIN Input Frequency 3.3V (5.0 V) 40 (40) 65 (65) 85 (70) MHz tLH Note 1 tHL Note 1 tJC Output Rise Time (measured at 0.8V to 2.0V) Output Fall Time (measured at 2.0V to 0.8V) Jitter (cycle to cycle) 0.7 0.9 1.1 ns 0.6 0.8 1.0 ns - - 360 ps tD Output Duty Cycle 45 50 55 % Notes1. tLH and tHL are measured into a capacitive load of 15pF Jan., 2001 Revision D 3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054 Tel (408) 748-6988 • Fax (408) 748-0009 5 of 7 http://www.pulsecore.com Final Product Specification P2065 Figure 6 – Mechanical Package Outline, (8 Pin SOIC) C L SYMBOL A A1 A2 B C D E e H L a P2065A LOT NUMBER YYWW H E a D A2 B e A INCHES MIN NOR MAX 0.057 0.064 0.071 0.004 0.007 0.010 0.053 0.061 0.069 0.012 0.016 0.020 0.004 0.006 0.001 0.186 0.194 0.202 0.148 0.156 0.164 0.050 BSC 0.224 0.236 0.248 0.012 0.020 0.028 0° 5° 8° MILLIMETERS MIN NOR MAX 1.45 1.63 1.80 0.10 0.18 0.25 1.35 1.55 1.75 0.51 0.41 0.31 0.10 0.15 0.25 4.72 4.92 5.12 3.75 3.95 4.15 1.27 BSC 5.70 6.00 6.30 0.30 0.50 0.70 0° 5° 8° INCHES MIN NOR MAX 0.047 0.002 0.006 0.031 0.039 0.041 0.007 0.012 0.004 0.008 0.114 0.118 0.122 0.169 0.173 0.177 0.026 BSC 0.244 0.252 0.260 0.018 0.024 0.030 0° 8° MILLIMETERS MIN NOR MAX 1.10 0.05 0.15 0.80 1.00 1.05 0.19 0.30 0.09 0.20 2.90 3.00 3.10 4.30 4.40 4.50 0.65 BSC 6.20 6.40 6.60 0.45 0.60 0.75 0° 8° A1 Figure 7 – Mechanical Package Outline, (8 Pin TSSOP) C P 2065A Lot # YYWW L H E a D A2 B Jan., 2001 Revision D e A SYMBOL A A1 A2 B C D E e H L a A1 3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054 Tel (408) 748-6988 • Fax (408) 748-0009 6 of 7 http://www.pulsecore.com Final Product Specification P2065 ORDERING INFORMATION Ordering Number P2065A-08ST P2065A-08SR P2065A-08TT P2065A-08TR Marking P2065A P2065A P2065A P2065A Package Type 8 PIN SOIC, TUBE 8 PIN SOIC, TAPE & REEL 8 PIN TSSOP, TUBE 8 PIN TSSOP, TAPE & REEL Temperature 0°C TO 70°C 0°C TO 70°C 0°C TO 70°C 0°C TO 70°C "Licensed under U.S. Patent Nos. 5,488,627 and 5,631,920" Jan., 2001 Revision D 3160 De La Cruz Blvd., Suite 200 • Santa Clara • CA • 95054 Tel (408) 748-6988 • Fax (408) 748-0009 7 of 7 http://www.pulsecore.com