ASIX AX88772A

AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Features
Single chip USB 2.0 to 10/100M Fast Ethernet
controller
Single chip USB 2.0 to RMII, support
HomePNA and HomePlug PHY
Single chip USB 2.0 to Reverse-RMII, supports
glueless MAC-to-MAC connections
USB Device Interface
Integrates on-chip USB 2.0 transceiver and
SIE compliant to USB Spec 1.1 and 2.0
Supports USB Full and High Speed modes
with Bus-Power or Self-Power capability
Supports 4 endpoints on USB interface
Supports AutoDetach power saving. Detach
from USB host when Ethernet cable is
unplugged
High performance packet transfer rate over
USB bus using proprietary burst transfer
mechanism (US Patent Approval)
Fast Ethernet Controller
Integrates 10/100Mbps Fast Ethernet
MAC/PHY
IEEE
802.3
10BASE-T/100BASE-TX
compatible
IEEE 802.3 100BASE-FX compatible
Supports twisted pair crossover detection and
auto-correction (HP Auto-MDIX)
Embedded SRAM for RX/TX packet
buffering
Supports IPv4/ IPv6 packet Checksum
Offload Engine(COE) to reduce CPU loading,
including IPv4 IP/TCP/UDP/ICMP/IGMP &
IPv6 TCP/UDP/ICMPv6 checksum check &
generation
Supports full duplex operation with IEEE
802.3x flow control and half duplex operation
with back-pressure flow control
Supports 2 VLAN ID filtering, received
VLAN Tag (4 bytes) can be stripped off or
preserved
PHY loop-back diagnostic capability
Supports multiple unicast MAC destination
address filter
Document No: AX88772C/V1.10/05/15/13
Support Wake-on-LAN Function
Supports Suspend Mode and Remote Wakeup
via Link-change, Magic packet, MS wakeup
frame and external wakeup pin
Supports Protocol Offload (ARP & NS) for
Windows 7 Networking Power Management
Optional PHY power down during Suspend
Mode
Supports 32 MS Wakeup Patterns
Supports Wakeup packet indication
Supports Receive Filter Wakeup
Versatile External Media Interface
Optional RMII interface in MAC mode allows
AX88772C to work with HomePNA and
HomePlug PHY
Optional Reverse-RMII interface in PHY
mode allows AX88772C to support glueless
MAC-to-MAC connections
Advanced Power Management Features
Supports dynamic power management to
reduce power dissipation during idle or light
traffic
Supports very low power Wake-on-LAN
(WOL) mode when the system enters suspend
mode and waits for network events to wake it
up.
Supports 256/512 bytes (93c56/93c66) of serial
EEPROM (for storing USB Descriptors)
Supports automatic loading of Ethernet ID, USB
Descriptors and Adapter Configuration from
EEPROM after power-on initialization
Integrates on-chip voltage regulator and only
requires a single 3.3V power supply
Single 25MHz clock input from either crystal or
oscillator source
Integrates on-chip power-on reset circuit
Small form factor with 64-pin LQFP RoHS
compliant package
Operating commercial temperature range 0°C to
70°C
ASIX ELECTRONICS CORPORATION
4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsin-Chu City, Taiwan, R.O.C. 300
TEL: 886-3-579-9500
FAX: 886-3-579-9558
Released Date: 05/15/2013
http://www.asix.com.tw/
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Target Applications
PC/Internet
Consumer Electronics
Figure 1
: Target Applications
2
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Typical System Block Diagrams

Hosted by USB to operate with internal Ethernet PHY only
Figure 2

: USB 2.0 to LAN Adaptor (MAC mode)
Hosted by USB to operate with either internal Ethernet PHY or RMII (in MAC
mode)
Figure 3
: USB 2.0 to Fast Ethernet and external PHYceiver Combo (MAC mode)
3
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support

Hosted by USB to operate with either internal Ethernet PHY (in MAC mode) or
Reverse-RMII (in PHY mode)
Figure 4
: Bridging Embedded MCU to USB 2.0 Host Interface (PHY mode)
Figure 5
: USB 2.0 to HomePlug Adaptor (PHY mode)
4
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
DISCLAIMER
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may make
changes to the product specifications and descriptions in this document at any time, without notice.
ASIX provides this document “as is” without warranty of any kind, either expressed or implied, including without
limitation warranties of merchantability, fitness for a particular purpose, and non-infringement.
Designers must not rely on the absence or characteristics of any features or registers marked “reserved”, “undefined” or
“NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting a
design of ASIX products.
TRADEMARKS
ASIX, the ASIX logo are registered trademarks of ASIX Electronics Corporation. All other trademarks are the property of
their respective owners.
5
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Table of Contents
1
INTRODUCTION .................................................................................................................................................... 9
1.1
1.2
1.3
2
SIGNAL DESCRIPTION ...................................................................................................................................... 11
2.1
2.2
3
GENERAL DESCRIPTION ....................................................................................................................................... 9
BLOCK DIAGRAM ................................................................................................................................................ 9
PINOUT DIAGRAM .............................................................................................................................................. 10
PINOUT DESCRIPTION ........................................................................................................................................ 11
HARDWARE SETTING FOR OPERATION MODE AND MULTI-FUNCTION PINS ...................................................... 14
FUNCTION DESCRIPTION ................................................................................................................................ 16
3.1
USB CORE AND INTERFACE .............................................................................................................................. 16
3.2
10/100M ETHERNET PHY ................................................................................................................................. 16
3.3
MAC CORE ....................................................................................................................................................... 16
3.4
CHECKSUM OFFLOAD ENGINE (COE)................................................................................................................ 17
3.5
OPERATION MODE ............................................................................................................................................. 17
3.6
STATION MANAGEMENT (STA) ......................................................................................................................... 20
3.7
MEMORY ARBITER ............................................................................................................................................ 21
3.8
USB TO ETHERNET BRIDGE ............................................................................................................................... 22
3.8.1
Ethernet/USB Frame Format Bridge ........................................................................................................ 22
3.9
SERIAL EEPROM LOADER ................................................................................................................................ 22
3.10 GENERAL PURPOSE I/O...................................................................................................................................... 22
3.11 CLOCK GENERATION ......................................................................................................................................... 23
3.12 RESET GENERATION .......................................................................................................................................... 24
3.13 VOLTAGE REGULATOR ...................................................................................................................................... 24
4
SERIAL EEPROM MEMORY MAP ................................................................................................................... 25
4.1
DETAILED DESCRIPTION .................................................................................................................................... 26
4.2
INTERNAL ROM DEFAULT SETTINGS ................................................................................................................ 29
4.2.1
Internal ROM Description ........................................................................................................................ 30
4.2.2
External EEPROM Description ................................................................................................................ 32
5
USB CONFIGURATION STRUCTURE ............................................................................................................. 33
5.1
5.2
5.3
6
USB CONFIGURATION ....................................................................................................................................... 33
USB INTERFACE ................................................................................................................................................ 33
USB ENDPOINTS................................................................................................................................................ 33
ELECTRICAL SPECIFICATIONS ..................................................................................................................... 34
6.1
DC CHARACTERISTICS ...................................................................................................................................... 34
6.1.1
Absolute Maximum Ratings ...................................................................................................................... 34
6.1.2
Recommended Operating Condition ......................................................................................................... 34
6.1.3
Leakage Current and Capacitance ........................................................................................................... 35
6.1.4
DC Characteristics of 3.3V I/O Pins ........................................................................................................ 35
6.1.5
DC Characteristics of 3.3V with 5V Tolerance I/O Pins .......................................................................... 36
6.1.6
DC Characteristics of Voltage Regulator ................................................................................................. 36
6.1.7
DC Characteristics of Fiber Interface ...................................................................................................... 37
6.2
THERMAL CHARACTERISTICS ............................................................................................................................ 38
6.3
POWER CONSUMPTION ...................................................................................................................................... 38
6.4
POWER-UP SEQUENCE ....................................................................................................................................... 39
6.5
AC TIMING CHARACTERISTICS .......................................................................................................................... 40
6.5.1
Clock Timing ............................................................................................................................................. 40
6.5.2
Reset Timing ............................................................................................................................................. 40
6.5.3
Serial EEPROM Timing ............................................................................................................................ 41
6.5.4
Station Management Timing ..................................................................................................................... 42
6.5.5
RMII / Reverse-RMII Timing .................................................................................................................... 43
6.5.6
10/100M Ethernet PHY Interface Timing ................................................................................................. 44
6
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6.5.7
7
USB Transceiver Interface Timing ........................................................................................................... 45
PACKAGE INFORMATION ................................................................................................................................ 47
7.1
AX88772C 64-PIN LQFP PACKAGE .................................................................................................................. 47
8
ORDERING INFORMATION .............................................................................................................................. 48
9
REVISION HISTORY ........................................................................................................................................... 49
APPENDIX A. DEFAULT WAKE-ON-LAN (WOL) READY MODE .................................................................... 50
APPENDIX B. ETHERNET PHY POWER AND RESET CONTROL .................................................................... 53
7
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
List of Figures
FIGURE 1
FIGURE 2
FIGURE 3
FIGURE 4
FIGURE 5
FIGURE 6
FIGURE 7
FIGURE 8
FIGURE 9
FIGURE 10
FIGURE 11
FIGURE 12
FIGURE 13
FIGURE 14
FIGURE 15
FIGURE 16
FIGURE 17
FIGURE 18
: TARGET APPLICATIONS ................................................................................................................................. 2
: USB 2.0 TO LAN ADAPTOR (MAC MODE) .................................................................................................... 3
: USB 2.0 TO FAST ETHERNET AND EXTERNAL PHYCEIVER COMBO (MAC MODE) ........................................ 3
: BRIDGING EMBEDDED MCU TO USB 2.0 HOST INTERFACE (PHY MODE)..................................................... 4
: USB 2.0 TO HOMEPLUG ADAPTOR (PHY MODE) .......................................................................................... 4
: BLOCK DIAGRAM .......................................................................................................................................... 9
: PINOUT DIAGRAM ........................................................................................................................................ 10
: INTERNAL DATA PATH DIAGRAM OF 10/100M ETHERNET PHY AND RMII/REVERSE-RMII INTERFACES .. 16
: RMII TO EXTERNAL PHY CHIP WITH 50MHZ OSC .................................................................................... 18
: RMII INTERFACE TO EXTERNAL PHY CHIP ............................................................................................. 18
: REVERSE-RMII TO EXTERNAL MAC DEVICE WITH 50MHZ OSC .......................................................... 19
: REVERSE-RMII INTERFACE TO EXTERNAL MAC DEVICE ....................................................................... 19
: INTERNAL CONTROL MUX OF STATION MANAGEMENT INTERFACE IN MAC MODE ............................... 20
: INTERNAL CONTROL MUX OF STATION MANAGEMENT INTERFACE IN PHY MODE ................................ 21
: ONE EXTERNAL 1M OHM RESISTOR ON 25MHZ CRYSTAL OSCILLATOR IS NECESSARY ............................ 24
: WATER LEVEL SETTING FOR FLOW CONTROL ........................................................................................... 28
: ETHERNET PHY OSCILLATOR/PLL BLOCK DIAGRAM ............................................................................. 53
: ETHERNET PHY POWER-UP & RESET TIMING DIAGRAM ......................................................................... 54
List of Tables
TABLE 1
TABLE 2
TABLE 3
TABLE 4
TABLE 5
TABLE 6
TABLE 7
TABLE 8
TABLE 9
: PINOUT DESCRIPTION .................................................................................................................................. 13
: MFA_3 ~ MFA_0 PIN CONFIGURATION ....................................................................................................... 14
: PHY_ID DEFINITION SOURCE ..................................................................................................................... 17
: THE EXTERNAL 25MHZ CRYSTAL UNITS SPECIFICATIONS .......................................................................... 23
: SERIAL EEPROM MEMORY MAP ................................................................................................................ 25
: INTERNAL ROM MEMORY MAP .................................................................................................................. 29
: INTERNAL ROM DESCRIPTION .................................................................................................................... 30
: POWER CONSUMPTION ................................................................................................................................. 38
: REMOTE WAKEUP TRUTH TABLE ................................................................................................................ 51
8
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
1 Introduction
1.1
General Description
The AX88772C USB 2.0 to 10/100M Fast Ethernet controller with Microsoft AOAC(Always On Always Connected)
support is a high performance and highly integrated ASIC which enables a low cost, small form factor, and simple
plug-and-play Fast Ethernet network connection capability for desktops, notebook PCs, Ultrabooks, cradles/port
replicators/docking stations, game consoles, digital-home appliances, and any embedded system using a standard USB
port.
The AX88772C can be used in any embedded system with a USB host microcontroller requiring a twisted pair physical
network connection. Featuring a USB interface (compliant with USB specification V2.0 and V1.1) to communicate with
a USB Host Controller, the AX88772C also integrates on-chip Ethernet MAC and PHY (IEEE802.3 and IEEE802.3u
compatible) and embedded memory. Additionally, the AX88772C needs only a single 25MHz crystal to drive both the
USB and Ethernet PHYs.
The AX88772C offers a wide array of features including IPv4/IPv6 checksum offload engine, Protocol Offload(ARP &
NS), HP Auto-MDIX, and IEEE 802.3x and back-pressure flow control. The AX88772C also offers multiple power
management Wake-on-LAN features, including Magic Packet, Microsoft Wakeup Frame, Link Status Change, 32
Microsoft Wakeup Patterns and Wakeup Packet Indication that allows the AOAC platform to enter a low-power
“Connected Standby” state and wake on a desired network pattern.
The AX88772C provides an optional Multi-Function-Bus portion A and B (MFA and MFB) for external PHY or external
MAC for different application purposes. The MFA/MFB can be a reduce-media-independent interface (RMII) for
implementing HomePlug, HomePNA, etc. functions. The MFA/MFB can also be a Reverse Reduced-MII
(Reverse-RMII) for glueless MAC-to-MAC connections to any MCU with Ethernet MAC RMII interface. In addition, the
MFA/MFB can be configured as general purpose I/O.
1.2 Block Diagram
Figure 6
: Block Diagram
9
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
1.3 Pinout Diagram
MFB2
MFB1
MFB0
VCCK
GND
EECK
EECS
EEDIO
TCLK_1
TCLK_0
TCLK_EN
VCC3IO
RESET_N
TEST1
TEST0
GND
 64-pin LQFP package
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32 MFB3
31 MFB4
30 MFB5
29 MFB6
28 MFB7
27 GPIO_0/PME
26 GPIO_1
25 GPIO_2
24 VCCK
23 EXTWAKEUP_N
22 GND
21 MFA3/PHY_N
20 VCCK
19 MFA2/RMII_N
18 MFA1/MDIO
17 MFA0/MDC
Figure 7
VCC3IO
GND
GND18A
TXON
RSET_BG
9 10 11 12 13 14 15 16
TXOP
GND18A
8
VCC18A
XTL25N
6 7
RXIN
5
RXIP
4
GND18A
3
SD
2
VCC3A3
1
XTL25P
AX88772C
VCC18A
VCCK
V_BUS
V18F
VCC3R3
GND3R3
GND33A_PLL
GND33A_H
DP
DM
RREF
VCC33A_PLL
VCC33A_H
X2
X1
GND18A_PLL
VCC18A_PLL
: Pinout Diagram
10
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
2 Signal Description
The following abbreviations apply to the following pin description table.
I18
I3
I5
O3
B5
P
Input, 1.8V
Input, 3.3V
Input, 3.3V with 5V tolerant
Output, 3.3V
Bi-directional I/O, 3.3V with 5V tolerant
Power Pin
AI
Analog Input
AO Analog Output
AB Analog Bi-directional I/O
PU
Internal Pull Up (75K)
PD
Internal Pull Down (75K)
S
Schmitt Trigger
T
Tri-stateable
Note: Every output or bi-directional I/O pin is 8mA driving strength.
2.1 Pinout Description
Pin Name
Type
Pin No
DP
DM
V_BUS
RREF
AB
AB
I5/PD/S
AI
56
57
50
58
EECK
B5/PD/
T
38
EECS
B5/PD/
T
39
EEDIO
B5/PU/
T
40
XTL25P
I18
2
XTL25N
RXIP
RXIN
TXOP
TXON
RSET_BG
O18
AB
AB
AB
AB
AO
3
9
10
12
13
5
RESET_N
I5/PU/S
45
EXTWAKEUP_N
I5/PU/S
23
GPIO_2
GPIO_1
B5/PD
B5/PD
25
26
Pin Description
USB Interface
USB 2.0 data positive pin.
USB 2.0 data negative pin.
VBUS pin input. Please connect to USB bus power.
For USB PHY’s internal biasing. Please connect to analog GND through a
resistor (12.1Kohm ±1%).
Serial EEPROM Interface
EEPROM Clock. EECK is an output clock to EEPROM to provide timing
reference for the transfer of EECS, and EEDIO signals. EECK only drive
high / low when access EEPROM otherwise keep at tri-state and internal
pull-down.
EEPROM Chip Select. EECS is asserted high synchronously with respect to
rising edge of EECK as chip select signal. EECS only drive high / low when
access EEPROM otherwise keep at tri-state and internal pull-down.
EEPROM Data In. EEDIO is the serial output data to EEPROM’s data input
pin and is synchronous with respect to the rising edge of EECK. EEDIO
only drive high / low when access EEPROM otherwise keep at tri-state and
internal pull-up.
Ethernet PHY Interface
25MHz ± 0.005% crystal or oscillator clock input. This clock is needed for
the embedded 10/100M Ethernet PHY to operate.
25MHz crystal or oscillator clock output.
Receive data input positive pin for both 10BASE-T and 100BASE-TX.
Receive data input negative pin for both 10BASE-T and 100BASE-TX.
Transmit data output positive pin for both 10BASE-T and 100 BASE-TX
Transmit data output negative pin for both 10BASE-T and 100 BASE-TX
For Ethernet PHY’s internal biasing. Please connect to GND through a
12.1Kohm ±1% resistor.
Misc. Pins
Chip reset input. Active low. This is the external reset source used to reset
this chip. This input feeds to the internal power-on reset circuitry, which
provides the main reset source of this chip. After completing reset,
EEPROM data will be loaded automatically.
Remote-wakeup trigger from external pin. EXTWAKEUP_N should be
asserted low for more than 2 cycles of 25MHz clock to be effective.
General Purpose Input/ Output Pin 2.
General Purpose Input/ Output Pin 1. This pin is default as input pin after
power-on reset. This pin is also for Default WOL Ready Mode setting;
please refer to section 2.2 Settings.
11
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
GPIO_0/PME
B5/PD
27
MFB7
B5/PU
I5
I5
MFB6
B5/PU
I5
I5
MFB5/
REF50
B5/PU
B5
MFB4
31
MFB0
B5/PU
O3
O3
B5/PU
O3
O3
B5/PU
O3
O3
B5/PU
I5
I5
B5/PU
MFA3/
PHY_N
O3
I5/PU
21
MFA2/
RMII_N
O3
I5/PU
19
MFA1/
MDIO
O3
B5/PU
18
28
29
30
MFB3
MFB2
MFB1
32
33
34
35
General Purpose Input/ Output Pin 0 or PME (Power Management Event).
This pin is default as input pin after power-on reset. GPIO_0 also can be
defined as PME output to indicate wake up event detected. Please refer to
section 2.2 Settings.
This is a multi-function pin. Please refer to section 2.2 Settings.
MFB7:
RMII
: RXD0
Reverse_RMII : TXD0
This is a multi-function pin. Please refer to section 2.2 Settings.
MFB6:
RMII
: RXD1
Reverse_RMII : TXD1
This is a multi-function pin. Please refer to section 2.2 Settings.
MFB5:
When RMII enable, The REF50 in/out direction is determined by EEPROM
Flag [1] setting. Please refer to section 2.2 Settings.
This is a multi-function pin. Please refer to section 2.2 Settings.
RMII
: TXD0
Reverse_RMII : RXD0
This is a multi-function pin. Please refer to section 2.2 Settings.
RMII
: TXD1
Reverse_RMII : RXD1
This is a multi-function pin. Please refer to section 2.2 Settings.
RMII
: TXEN
Reverse_RMII : CRSDV
This is a multi-function pin. Please refer to section 2.2 Settings.
RMII
: CRSDV
Reverse_RMII : TXEN
This is a GPIO pin. Please refer to section 2.2 Settings.
It is a multi-function pin. The default is USB Speed indicator. When USB
bus is in Full speed, this pin will tri-state continuously. When USB bus is in
High speed, this pin drives low continuously. This pin tri-state and drive low
in turn (blinking) to indicate TX data transfer going on whenever the host
controller sends bulk out data transfer.
MFB1~7 bus is determined by setting of this input pin when MFA2 sets 0:
0: Reverse_RMII (PHY mode).
1: RMII (MAC mode).
Please refer to PIN configuration of MFA and MFB in section 2.2 Settings.
It is a multi-function pin. The default is Link status LED indicator.
This pin drives low continuously when the Ethernet link is up and drives low
and high in turn (blinking) when Ethernet PHY is in receiving or
transmitting state.
MFB1~7 function is determined by setting of this input pin:
0: Reverse_RMII/RMII .
1: MFB bus as GPIO function.
Please refer to PIN configuration of MFA and MFB in section 2.2 Settings.
It is a multi-function pin. The default is Ethernet speed LED indicator.
This pin drives low when the Ethernet PHY is in 100BASE-TX mode and
drives high when in 10BASE-T mode.
This pin can perform as MDIO when enabling Reverse_RMII/RMII.
12
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
MFA0/
MDC
SD
TEST0
TEST1
X1
X2
TCLK_EN
TCLK_0
TCLK_1
VCC3R3
GND3R3
V18F
VCCK
VCC3IO
GND
VCC33A_H
GND33A_H
VCC33A_PLL
GND33A_PLL
VCC3A3
VCC18A
GND18A
VCC18A_PLL
GND18A_PLL
O3
17
It is a multi-function pin. The default is Full Duplex and collision detected
LED indicator.
This pin drives low when the Ethernet PHY is in full-duplex mode and
drives high when in half duplex mode. When in half duplex mode and the
Ethernet PHY detects collision, it will be driven low (or blinking).
This pin can perform as MDC when enabling Reverse_RMII/RMII:
RMII
: Output.
Reverse_RMII : Input.
7 Fiber signal detected
Twisted pair operation: Please connect to GND directly or through a
resistor.
Fiber operation: Please connect to the fiber transceiver signal detect output
pin.
Please refer to Section 6.1.7 for the detailed SD signal DC Characteristics
spec.
I5/S
47 Test pin. For normal operation, user should connect to ground.
I5/S
46 Test pin. For normal operation, user should connect to ground.
I3
62 Test pin. For normal operation, user should connect to ground.
O3
61 Test pin. No connection
I5/PD/S 43 Test pin. For normal operation, user should keep this pin NC.
I5/PD
42 Test pin. For normal operation, user should keep this pin NC.
I5/PD
41 Test pin. For normal operation, user should keep this pin NC.
On-chip Regulator Pins
P
52 3.3V Power supply to on-chip 3.3V to 1.8V voltage regulator.
P
53 Ground pin of on-chip 3.3V to 1.8V voltage regulator.
P
51 1.8V voltage output of on-chip 3.3V to 1.8V voltage regulator.
Power and Ground Pins
P
20, 24, 36, 49 Digital Core Power. 1.8V.
P
16, 44
Digital I/O Power. 3.3V.
P
15, 22, 37, 48 Digital Ground.
P
60
Analog Power for USB transceiver. 3.3V.
P
55
Analog Ground for USB transceiver.
P
59
Analog Power for USB PLL. 3.3V.
P
54
Analog Ground for USB PLL.
P
6
Analog Power for Ethernet PHY bandgap. 3.3V.
P
1, 11
Analog Power for Ethernet PHY and 25MHz crystal oscillator.
1.8V.
P
4, 8, 14
Analog Ground for Ethernet PHY and 25MHz crystal oscillator.
P
64
Analog Power for USB PLL. 1.8V.
P
63
Analog Ground for USB PLL.
O3
I5/PU
I
Table 1
: Pinout Description
13
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
2.2 Hardware Setting For Operation Mode and Multi-Function Pins
The following hardware settings define the desired function or interface modes of operation for some multi-function pins.
The logic level shown on setting pin below is loaded from the chip I/O pins during power on reset based on the setting of
the pin’s pulled-up (as logic ‘1’) or pulled-down (as logic ‘0’) resister on the schematic.
 Chip Operation Mode setting :
Pin# 19, Pin #21
1x (default)
01
00
Operation Modes
MAC mode
Internal PHY
MAC mode
RMII
PHY mode
Reverse-RMII
Remarks
The Chip Operation Mode is determined by Pin# 19
(MFA2/RMII_N) and Pin #21 (MFA3/PHY_N) value of
AX88772C, which is called hardware setting.
 EECK pin: USB force to Full Speed mode :
EECK
0
1
Description
Normal operation (default).
USB force to Full Speed mode. External pull-up resistor must be 4.7Kohm.
 GPIO_1 pin: Determines whether this chip will go to Default WOL Ready Mode after power on reset. The WOL
stands for Wake-On-LAN.
GPIO_1
0
1
Description
Normal operation mode (default, see Note 1).
Enable Default WOL Ready Mode. Notice that the external pulled-up resistor must be 4.7Kohm.
For more details, please refer to APPENDIX A. Default Wake-On-LAN (WOL) Ready Mode
Note 1: This is the default with internal pulled-down resistor and doesn’t need an external one.
 EEPROM Flag [12]: Defines the multi-function pin GPIO_0 / PME
GPIO_0 is a general purpose I/O normally controlled by vendor commands. Users can change this pin to operate as a PME
(Power Management Event) for remote wake up purpose. Please refer to 4.1.2 Flag of bit 12 (PME_PIN).
 MFA_3 ~ MFA_0 pins: There are 4 multi-function pins for LED display purpose and as GPIO control by vendor
command.
PIN Name
Default definition
Vendor Command
LED_MUX
Vendor Command
VMFAIO
RMII_N enable
MFA3
MFA2
MFA1
MFA0
LED_USB indicater
LED_Ethernet_LINK_Active
LED_Ethernet_Speed
LED_Ethernet_Duplex_Collision
Sel_LED3
Sel_LED2
Sel_LED1
Sel_LED0
MFAIO_3
MFAIO_2
MFAIO_1
MFAIO_0
MDIO
MDC
Table 2
: MFA_3 ~ MFA_0 pin configuration
14
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
 PIN configuration of MFA and MFB
Pin# 19
Pin #21
MFA2/RMII_N
MFA3/PHY_N
1: MFB7~MFB0 1: MAC Mode
0: RMII
0: PHY Mode
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
1
X
Description
PIN
Name
MFB0
MFB1
MFB2
MFB3
MFB4
MFB5
MFB6
MFB7
MFA0
1
X
MFA1
1
X
MFA2
1
X
MFA3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
MFB0
MFB1
MFB2
MFB3
MFB4
MFB5
MFB6
MFB7
MFA0
MFA1
MFB0
MFB1
MFB2
MFB3
MFB4
MFB5
MFB6
MFB7
MFA0
MFA1
Function
Pin Type
MFBIO0
MFBIO1
MFBIO2
MFBIO3
MFBIO4
MFBIO5
MFBIO6
MFBIO7
Refer to MFA
Configuration
Refer to MFA
Configuration
Refer to MFA
Configuration
Refer to MFA
Configuration
MFBIO0
CRSDV
TXEN
TXD1
TXD0
REF50
RXD1
RXD0
MDC
MDIO
MFBIO0
TXEN
CRSDV
RXD1
RXD0
REF50
TXD1
TXD0
MDC
MDIO
Bidirection, controlled by MFBIOEN0
Bidirection, controlled by MFBIOEN1
Bidirection, controlled by MFBIOEN2
Bidirection, controlled by MFBIOEN3
Bidirection, controlled by MFBIOEN4
Bidirection, controlled by MFBIOEN5
Bidirection, controlled by MFBIOEN6
Bidirection, controlled by MFBIOEN7
Bidirection, controlled by MFBIOEN0
Input
Output
Output
Output
Input/Output control by EEPROM flag[1]
Input
Input
Output
I/O
Bidirection, controlled by MFBIOEN0
Input
Output
Output
Output
Input/Output control by EEPROM flag[1]
Input
Input
Input
I/O
15
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
3 Function Description
3.1 USB Core and Interface
The USB core and interface contains a USB 2.0 transceiver, serial interface engine (SIE), USB bus protocol handshaking
block, USB standard command, vendor command registers, logic for supporting bulk transfer, and an interrupt transfer,
etc. The USB interface is used to communicate with a USB host controller and is compliant with USB specification V1.1
and V2.0.
3.2 10/100M Ethernet PHY
The 10/100M Fast Ethernet PHY is compliant with IEEE 802.3 and IEEE 802.3u standards. It contains an on-chip crystal
oscillator, PLL-based clock multiplier, and a digital phase-locked loop for data/timing recovery. It provides
over-sampling mixed-signal transmit drivers compliant with 10/100BASE-TX transmit wave shaping / slew rate control
requirements. It has a robust mixed-signal loop adaptive equalizer for receiving signal recovery. It contains a baseline
wander corrective block to compensate data dependent offset due to AC coupling transformers. It supports
auto-negotiation and auto-MDIX functions.
3.3 MAC Core
The MAC core supports 802.3 and 802.3u MAC sub-layer functions, such as basic MAC frame receive and transmit, CRC
checking and generation, filtering, forwarding, flow-control in full-duplex mode, and collision-detection and handling in
half-duplex mode, etc. It provides a reduce-media-independent interface (RMII) for implementing Fast Ethernet and
HomePNA functions.
The MAC core interfaces to external RMII/Reverse-RMII interfaces and the embedded 10/100M Ethernet PHY. The
selection among the interfaces is done via setting Pin# 19 (MFA2/RMII_N) and Pin #21 (MFA3/PHY_N) of AX88772C
package pinout during power on reset (see 2.2) and using the USB vendor command, Software Interface Selection
register. Figure 8 shows the data path diagram of 10/100M Ethernet PHY and RMII/Reverse-RMII interfaces to MAC
core.
Figure 8
: Internal Data path Diagram of 10/100M Ethernet PHY and RMII/Reverse-RMII Interfaces
16
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
3.4
Checksum Offload Engine (COE)
The Checksum Offload Engine (COE) supports IPv4, IPv6, layer 4 (TCP, UDP, ICMP, ICMPv6 and IGMP) header
processing functions and real time checksum calculation in hardware
The COE supports the following features in layer 3:

IP header parsing, including IPv4 and IPv6

IPv6 extention header and routing header type 0 supported

IPv4 header checksum check and generation (There is no checksum field in IPv6 header)

Detecting on RX direction for IP packets with error header checksum
The COE supports the following features in layer 4:

TCP and UDP checksum check and generation for non-fragmented packet

ICMP, ICMPv6 and IGMP message checksum check and generation for non-fragmented packet

Checksum error indication on RX direction for TCP/UDP/ICMP/ICMPv6/IGMP packets with error
checksum
3.5 Operation Mode
For simple USB 2.0 to Ethernet applications, user can use the AX88772C, which operates with internal Ethernet PHY.
AX88772C supports following three operation modes: (Ref. 2.2 Hardware Setting For Operation Mode and
Multi-Function Pins)
1.
MAC mode
2.
PHY mode
Below provides a detailed description for the three operation modes:
 In MAC mode, the AX88772C Ethernet block is configured as an Ethernet MAC. From a system application
standpoint, AX88772C can be used as a USB 2.0 to LAN Adaptor (see Figure 2) or a USB 2.0 to Fast Ethernet and
HomePNA Combo (see Figure 3).
In MAC mode, the AX88772C internal datapath can work with internal Ethernet PHY or RMII interface by setting
Software Interface Selection register. Note that the PHY_ID for the internal Ethernet PHY and external one are
defined in below Table 3. Please refer to below Figure 9, Figure 10 for RMII example.
 In PHY mode, the AX88772C Ethernet block is configured as an Ethernet PHY interface. In this case, an external
microcontroller with Ethernet MAC can interface with AX88772C as if it were to interface with an Ethernet PHY
chip, and AX88772C can act as a USB to Reverse-RMII bridge chip for the microcontroller to provide USB 2.0
device interface for some system applications (see Figure 4).
Please refer to below Figure 11, Figure 12 for Reverse-RMII example.
STA PHY_ID
Embedded Ethernet PHY
PHY_ID [4:0]
External Media Interface
PHY_ID [4:0]
MAC mode
10h
PHY mode
10h
{Secondary PHY_ID
[4:0]}
{Secondary PHY_ID [4:1], 0}
Note: The value of Secondary PHY_ID [4:0] is defined in EEPROM memory map 4.1.6
Table 3
: PHY_ID Definition Source
17
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Figure 9
: RMII to External PHY chip with 50MHz OSC
Figure 10
: RMII Interface to External PHY chip
18
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Figure 11
: Reverse-RMII to External MAC Device with 50MHz OSC
Figure 12
: Reverse-RMII Interface to External MAC Device
19
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
3.6 Station Management (STA)
The Station Management interface provides a simple, two-wire, serial interface to connect to a managed PHY device for
the purpose of controlling the PHY and gathering status from the PHY. The Station Management interface allows
communicating with multiple PHY devices at the same time by identifying the managed PHY with 5-bit, unique PHY_ID.
The PHY ID of the embedded 10/100M Ethernet PHY is being pre-assigned to “1_0000”.
The Figure 13 shows the internal control MUX of the Station Management interface when doing read in MAC operation
mode, the “mdin” signal will be driven from the embedded 10/100M Ethernet PHY only if PHY ID matches with
“1_0000”, otherwise, it will always be driven from the external MDIO pin of the ASIC.
The Station Management unit also reports the basic PHY status when operating in PHY mode acting as a PHY role (see
0). For detailed register description, please refer to the Station Management Registers in PHY mode.
Embedded 10/100M
Ethernet PHY
PHY_ID = 1_0000
External Media Interface (EMI)
PHY ID = {Secondary PHY_ID
[4:0]}
Station Management
accessed from USB
Vendor Command
MDC
mdout
MDIO
mdin
Station Management to
be accessed through
Reverse-RMII in PHY
mode
Figure 13
PM_mdc
Fixed to ‘0’
PM_mdout
PM_mdin
Fixed to ‘0’
: Internal Control MUX of Station Management Interface in MAC mode
20
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Embedded 10/100M
Ethernet PHY
PHY_ID = 1_0000
mdc
Station Management
accessed from USB
Vendor Command
mdout
mdin
Fixed to ‘1’
Station Management to be
accessed through MFB bus in
PHY mode
PHY ID = {Secondary
PHY_ID [4:1], 0}
Figure 14
PM_mdc
External Media Interface (EMI)
MDC
PM_mdout
PM_mdin
MDIO
: Internal Control MUX of Station Management Interface in PHY mode
3.7 Memory Arbiter
The memory arbiter block is responsible for storing received MAC frames into on-chip SRAM (packet buffer) and then
forwarding it to the USB bus upon request from the USB host via Bulk In transfer. It also monitors the packet buffer usage
in full-duplex mode for triggering PAUSE frame (or in half-duplex mode to activate Backpressure jam signal)
transmission out on TX direction. The memory arbiter block is also responsible for storing MAC frames received from the
USB host via Bulk Out transfer and scheduling transmission out towards Ethernet network.
21
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
3.8 USB to Ethernet Bridge
The USB to Ethernet bridge block is responsible for converting Ethernet MAC frame into USB packets or vice-versa. This
block supports proprietary burst transfer mechanism (US Patent Approval) to offload software burden and to offer very
high packet transfer throughput over USB bus.
3.8.1 Ethernet/USB Frame Format Bridge
Ethernet Frames
Super-size network packet
4
Length header
6
6
DA
SA
6
6
DA
SA
2
0~1500
Length/type
Data
2
0~1500
Length/type
Data
4
6
6
FC
S
DA
SA
4
Length header
2
0~1500
Length/type
6
6
DA
SA
4
Data
2
FC
S
0~1500
Length/type
bytes
Data
USB Frames
IN/OUT
Data
Ack
IN/OUT
Data
USB packet having
the maximun packet
size
Ack
USB packet having
the maximun packet
size
IN/OUT
Data
Ack
USB packet having
the maximun packet
size
IN/OUT
Data
Short packet
3.9 Serial EEPROM Loader
The serial EEPROM loader is responsible for reading configuration data automatically from the external serial EEPROM
after power-on reset. If the content of EEPROM offset 0x00 (low byte of first word) is 0x00 or 0xFF, the Serial EEPROM
Loader will not auto-load the EEPROM. If the content of EEPROM offset 0x18 (low byte of 18th word) is not equal to
(0xFF - SUM [EEPROM offset 07H ~ 0EH]). In that case, the chip internal default value will be used to configure the chip
operation setting and to respond to USB commands, etc.
3.10 General Purpose I/O
There are 3 general-purpose I/O pins (named GPIO_0/1/2), 8 multi-function pins group B (named MFB0/1/2/3/4/5/6/7)
and 4 multi-function pins group A (named MFA0/1/2/3) provided by this ASIC.
22
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
Ack
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
3.11 Clock Generation
The AX88772C integrates internal oscillator circuits for 25MHz, respectively, which allow the chip to operate cost
effectively with just external 25MHz crystals. There are also three PLL circuits integrated in the chip to generate precise
clocks.
The external 25MHz crystal or oscillator, via pins XTL25P/XTL25N, provides the reference clock to the other two
internal PLL circuit to generate a free-run 100MHz clock source for the Reverse-RMII/RMII modes of AX88772C and a
125MHz clock source for the embedded Ethernet PHY use.
The AX88772C can provide REF50 (50MHz output) in Reverse-RMII/RMII modes. This output clock is derived from the
internal 100MHz PLL circuit.
The external 25MHz Crystal spec is listed in below table. For more details on crystal timing, please refer to 6.5.1 Clock
Timing and AX88772C demo board schematic reference.
Parameter
Nominal Frequency
Oscillation Mode
Frequency Tolerance (@25℃)
Frequency Stability Over Operating
Temperature Range
Equivalent Series Resistance
Load Capacitance
Operation Temperature Range
Aging
Table 4
Symbol
Typical Value
Fo
25.000000MHz
Fundamental
±30ppm
±30ppm
ESR
CL
70 Ohm max.
20pF
0℃ ~ +70℃, Commerical version
±3ppm/year
: The external 25MHz Crystal Units specifications
For the 25MHz oscillator, its feedback resistor isn’t
integrated into the 25MHz oscillator, so it is necessary
to add feedback resistor on external circuit.
23
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AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
To implement the external circuits of 25MHz crystal please refer to below. One external 1Mohm resistor on 25MHz
crystal oscillator is required.
Figure 15
: One external 1M ohm resistor on 25MHz crystal oscillator is necessary
3.12 Reset Generation
The AX88772C integrates an internal power-on-reset circuit, which can simplify the external reset circuitry on PCB
design. The power-on-reset circuit generates a reset pulse to reset system logic after 1.8V core power ramping up to 1.2V
(typical threshold). The external hardware reset input pin, RESET_N, is fed directly to the input of the power-on-reset
circuit and can also be used as additional hardware reset source to reset the system logic. For more details on RESET_N
timing, please refer to 6.5.2 Reset Timing.
3.13 Voltage Regulator
The AX88772C contains an internal 3.3V to 1.8V low-dropout-voltage and low-standby-current voltage regulator. The
internal regulator provides up to 150mA of driving current for the 1.8V core/analog power of the chip to satisfy the
worst-case power consumption scenario. For more details on voltage regulator DC characteristic, please refer to 6.1.6 DC
Characteristics of Voltage Regulator.
24
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AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
4 Serial EEPROM Memory Map
EEPROM
OFFSET
00H
HIGH BYTE
LOW BYTE
0x5A
0x15
01H
02H
Flag
04H
Length of High-Speed Device Descriptor (bytes)
Length of High-Speed Configuration Descriptor
(bytes)
MAC Address 1
EEPROM Offset of High-Speed Device Descriptor
EEPROM Offset of High-Speed Configuration
Descriptor
MAC Address 0
05H
MAC Address 3
MAC Address 2
06H
MAC Address 5
07H
Language ID High Byte
MAC Address 4
Language ID Low Byte
08H
Length of Manufacture String (bytes)
EEPROM Offset of Manufacture String
09H
Length of Product String (bytes)
EEPROM Offset of Product String
0AH
Length of Serial Number String (bytes)
EEPROM Offset of Serial Number String
0BH
Length of Configuration String (bytes)
EEPROM Offset of Configuration String
0CH
Length of Interface 0 String (bytes)
EEPROM Offset of Interface 0 String
0DH
Length of Interface 1/0 String (bytes)
EEPROM Offset of Interface 1/0 String
03H
0EH
0FH
Length of Interface 1/1 String (bytes)
EtherPhyMode
PHY Register Offset 1 for
[2:0]
Interrupt Endpoint
EEPROM Offset of Interface 1/1 String
100
PHY Register Offset 2 for Interrupt
Endpoint
11H
Max Packet Size High
Byte[10:8]
Secondary PHY_Type [7:5] and PHY_ID [4:0]
Primary PHY_Type [7:5] and PHY_ID [4:0]
12H
Pause Frame Free Buffers High Water Mark
Pause Frame Free Buffers Low Water Mark
13H
15H~17H
Length of Full-Speed Device Descriptor (bytes)
Length of Full-Speed Configuration Descriptor
(bytes)
Reserved
EEPROM Offset of Full-Speed Device Descriptor
EEPROM Offset of Full-Speed Configuration
Descriptor
Reserved
18H
Ethernet PHY Power Saving Configuration
EEPROM Checksum
10H
14H
5’b0
Table 5
Max Packet Size Low Byte[7:0]
: Serial EEPROM Memory Map
 The value of EEPROM Checksum field, EEPROM offset 0x18 (low byte) = (0xFF - SUM [EEPROM offset 07H ~
0EH])
 The value of Ethernet PHY Power Saving Configuration field (i.e. high byte of EEPROM offset 0x18) is equal to 2 nd
byte of Vendor Command 0x20. The AX88772C driver will read this field from high byte of EEPROM offset 0x18
and then writes it to 2nd byte of Vendor Command 0x20 at the end of driver initialization routine and during Suspend
mode configuration. This field doesn’t affect AX88772C before the driver writes it to Vendor Command 0x20.
Ethernet PHY Power Saving Configuration field
Bit15
WOLLP
Bit14
0
Bit13
IPFPS
Bit12
AutoDetach
Bit11
IPCOPSC
Bit10
IPCOPS
Bit9
IPPSL_1
25
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
Bit8
IPPSL_0
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
4.1 Detailed Description
The following sections provide detailed descriptions for some of the fields in serial EEPROM memory map. For other
fields not covered here, please refer to the AX88772C EEPROM User Guide for more details.
4.1.1 Word Count for Preload (00h)
The number of words to be preloaded by the EEPROM loader = 15h.
4.1.2 Flag (01h)
Bit 15
PME_IND
Bit 7
TACE
Bit 14
PME_TYP
Bit 6
RDCE
Bit 13
PME_POL
Bit 5
EPOM
Bit 12
PME_PIN
Bit 4
Reserved
Bit 11
PHY_ISO
Bit 3
1
Bit 10
1
Bit 2
RWU
Bit 9
TDPE
Bit 1
REF50_O
Bit 8
CEM
Bit 0
SP
SP: Self-Power (for USB standard command Get Status)
1: Self power (default).
0: Bus power.
REF50_O: RMII reference 50MHz clock direction
1: Sets AX88772C provides RMII reference 50MHz clock.
0: Sets AX88772C RMII reference clock source from external 50MHz clock source (default).
RWU: Remote Wakeup support.
1: Indicate that this device supports Remote Wakeup (default).
0: Not support.
EPOM: Embedded PHY copper/fiber Operation Mode
1: Sets embedded PHY in copper mode (default).
0: Sets embedded PHY in fiber mode
RDCE: RX Drop CRC Enable.
1: CRC byte is dropped on received MAC frame forwarding to host (default).
0: CRC byte is not dropped.
TACE: TX Append CRC Enable.
1: CRC byte is generated and appended by the ASIC for every transmitted MAC frame (default).
0: CRC byte is not appended.
CEM: Capture Effective Mode.
1: Capture effective mode enables (default).
0: Disabled.
TDPE: Test Debug Port Enable.
1: Enable test debug port for chip debug purpose.
0: Disable test debug port and the chip operate in normal function mode (default).
PHY_ISO: Set RMII bus to isolate mode when operating in PHY mode.
1: Set RMII bus to isolate mode (default). AX88772C can be in isolate mode when operating in PHY mode with
Reverse-RMII. Following output pins are tri-stated in isolate mode.
In Reverse-RMII mode: RXD [1:0] and CRSDV, RXER, except for REF50.
0: Set RMII bus to non-isolate mode.
PME_PIN: PME / GPIO_0
1: Set GPIO_0 pin as PME (default).
0: GPIO_0 pin is controlled by vendor command.
PME_POL: PME pin active Polarity.
1: PME active high.
0: PME active low (default).
PME_TYP: PME I/O Type.
1: PME output is a Push-Pull driver.
0: PME output to function as an open-drain buffer (default).
PME_IND: PME indication.
1: A 1.363ms pulse active when detecting wake-up event.
0: A static signal active when detecting wake-up event (default).
26
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
4.1.3 MAC Address (04~06h)
The MAC Address 0 to 5 bytes represent the MAC address of the device, for example, if MAC address =
01-23-45-67-89-ABh, then MAC Address 0 = 01, MAC Address 1 = 23, MAC Address 2 = 45, MAC Address 3 = 67,
MAC Address 4 = 89, and MAC Address 5 = AB.
Default values: MAC Address {0, 1, 2, 3, 4, 5} = 0x000E_C687_7201.
4.1.4 PHY Register Offset for Interrupt Endpoint (0Fh)
Bit 15
Bit 14
Bit 13
EtherPhyMode
Bit 7
Bit 6
Bit 5
100
Bit 12
Bit 11
Bit 10
Bit 9
PHY Register Offset 1
Bit 3
Bit 2
Bit 1
PHY Register Offset 2
Bit 4
Bit 8
Bit 0
PHY Register Offset 1: Fill in PHY’s Register Offset of Primary PHY here. Upon each Interrupt Endpoint issued, its
register value will be reported in byte# 5 and 6 of Interrupt Endpoint packet (default = 00101)
PHY Register Offset 2: Fill in PHY’s Register Offset of Primary PHY here. Upon each Interrupt Endpoint issued, its
register value will be reported in byte# 7 and 8 of Interrupt Endpoint packet (default = 00000)
EtherPhyMode: as below table (default = 000),
EtherPhyMode [2:0]
000
001
010
011
100
101
110
Function
Auto-negotiation enable with all capabilities
Auto-negotiation with 100BASE-TX FDX / HDX ability
Auto-negotiation with 10BASE-TX FDX / HDX ability
Reserved
Manual selection of 100BASE-TX FDX
Manual selection of 100BASE-TX HDX
Manual selection of 10BASE-T FDX
111
Manual selection of 10BASE-T HDX
Note:
1. EtherPhyMode is used to set the operation mode of embedded Ethernet PHY directly. For normal operation
mode, set them to 000.
2. This value is latched into embedded Ethernet PHY right after it leaves reset. After that, software driver can
still make change Ethernet PHY link ability through vendor command PHY Write Register to access
embedded Ethernet PHY register.
4.1.5 Max Packet Size High/Low Byte (10h)
Fill the maximum RX/TX MAC frame size supported by this ASIC. The number must be even number in terms of bytes
and should be less than or equal to 2048 bytes (default = 0600h).
27
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
4.1.6 Primary/Secondary PHY_Type and PHY_ID (11h)
The 3 bits PHY_Type field for both Primary and Secondary PHY is defined as follows,
000: 10/100M Ethernet PHY or 1M HomePNA PHY.
111: non-supported PHY. For example, the High Byte value of “E0h” means that secondary PHY is not supported.
Default values: Primary {PHY_Type, PHY_ID} = 10h. Secondary {PHY_Type, PHY_ID} = E0h. Note that the PHY_ID
of the embedded 10/100M Ethernet PHY is being assigned to “10h”.
Secondary PHY_ID always defines The PHY_ID of External Media Interface (EMI) and Secondary PHY_TYPE is not
used in that case. Please refer to Table 3 for more information.
4.1.7 Pause Frame Free Buffers High Water and Low Water Mark (12H)
When operating in full-duplex mode, correct setting of this field is very important and can affect the overall packet receive
throughput performance a great deal. The High Water Mark is the threshold to trigger sending Pause frame and the Low
Water Mark is the threshold to stop sending Pause frame. Note that each free buffer count here represents 128 bytes of
packet storage space in SRAM.
These setting values are also used in half-duplex mode to activate Backpressure to send /stop jam signal.
Figure 16
: Water level setting for flow control
4.1.8 Power-Up Steps
After power-on reset, AX88772C will automatically perform the following steps to the Ethernet PHYs via MDC/MDIO
lines (only take effect when Chip Operation Mode is in MAC mode with external PHY on RMII interface).
1. Write to PHY_ID of 00h with PHY register offset 00h to power down all PHYs attached to station management
interface.
2. Write to Primary PHY_ID with PHY register offset 00h to power down Primary PHY.
3. Write to Secondary PHY_ID with PHY register offset 00h to power down Secondary PHY.
Notice that enabling Default WOL Ready Mode (see 2.2 GPIO_1 Settings) will disable above power-up step (to prevent
external Ethernet PHY on RMII interface from entering power-down mode), if external PHY is used.
28
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
4.2 Internal ROM Default Settings
AX88772C supports some default settings inside chip hardware to enable it to communicate with USB host
controller during enumeration when the AX88772C EEPROM is blank (prior to being programmed) or the value of
EEPROM Checksum field is wrong. The default settings inside chip facilitate users to update the EEPROM content
through a Windows PC during R&D validation process or program a blank EEPROM mounted on target system PCB
during manufacturing process.
Below table shows AX88772C’s internal default settings being used in the case of blank EEPROM or EEPROM
with wrong checksum value on board. Each of the address offset contains 16-bit data from left to right representing
the low-byte and high-byte, respectively. For example, in offset address 0x01, the ‘FD’ is low-byte data and the ‘1D’
is high-byte data.
Offset
Address
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
0x40
0x48
0x50
0x58
0x60
0x68
0x70
0x78
0x80~FF
0
8
15 00
60 22
00 06
FF 08
12 01
03 01
FF FF
02 00
12 01
03 01
FF FF
00 00
22 03
65 00
2E 00
32 00
FF FF
1
9
FD 1D
71 12
10 E0
0E 03
00 02
09 02
00 07
07 05
00 02
09 02
00 07
07 05
41 00
63 00
12 03
42 00
FF FF
Table 6
2
A
20 12
19 0E
42 24
30 00
FF FF
27 00
07 05
03 02
FF FF
27 00
07 05
03 02
53 00
2E 00
41 00
FF FF
FF FF
3
B
29 27
3D 04
40 12
30 00
00 40
01 01
81 03
00 02
00 08
01 01
81 03
40 00
49 00
20 00
58 00
FF FF
FF FF
4
C
00 0E
3D 04
49 27
30 00
95 0B
04 E0
08 00
00 FF
95 0B
04 E0
08 00
00 DD
58 00
43 00
38 00
FF FF
FF FF
5
D
C6 87
3D 04
FF FF
30 00
2B 77
02 09
0B 07
04 03
2B 77
02 09
A0 07
FF FF
20 00
6F 00
38 00
FF FF
FF FF
6
E
72 01
3D 04
00 00
30 00
02 00
04 00
05 82
30 00
02 00
04 00
05 82
AA AA
45 00
72 00
37 00
FF FF
FF FF
7
F
09 04
80 05
FF FF
31 00
01 02
00 03
02 00
FF FF
01 02
00 03
02 40
BB BB
6C 00
70 00
37 00
FF FF
FF FF
: Internal ROM Memory Map
Note:
1. The default high-byte data of offset 0x00 is 0x00.
2. The default PID/VID is 0x772B/0x0B95.
3. The default “bcdDevice” field (offset 0x26/0x46) is set to 0x0002.
4. The default MAC address is 00-0E-C6-87-72-01, but the real MAC address is 00-00-00-00-00-00 as auto-loaded
into the AX88772C MAC Address register. You should manually assign a valid MAC address in the AX88772C
driver parameter for normal network operation.
5. The default Manufacture string is “ASIX Elec. Corp.”.
6. The default Product string is “AX88772B”.
7. The default Serial Number is “000001”.
8. The default operation mode is set to Self Power and Remote Wakeup enabled.
9. The default “AutoDetach” function is disabled and set to Cable Off Power Saving Level 0.
10. The default value of EEPROM Checksum field is 0xFF.
29
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
4.2.1 Internal ROM Description
The internal ROM is a fixed value. User can’t modify it.
Field Definition
Vender ID (VID)
Product ID (PID)
MAC Address
Address
Offset
0x24
0x44
0x25
0x45
0x04 ~0x06
Default Values
Description
95 0B
ASIX’s VID is 0x0B95
2B 77
The PID of AX88772C is
0x772B
MAC Address 0 ~ 5
00 0E C6 87 72 01
Power Mode/Remote
0x01
Wakeup/Copper or Fiber 0x2C
Mode
0x4C
FD 1D
E0 (high-byte only)
E0 (high-byte only)
Max Power under
0x2D
High Speed Mode
Max Power under
0x4D
Full Speed Mode
Ethernet PHY Type/ID 0x11
02 (low-byte only)
Manufacture String
0x60~0x70
Product String
0x71~0x79
22 03
45 00
43 00
12 03
37 00
Serial Number String
0x19~0x1F
0E 03 30 00 30 00 30 00 30 00
31 00
Ethernet PHY Power
Saving Configuration
0x18
08 (high-byte only)
02 (low-byte only)
10 E0
Table 7
41 00
6C 00
6F 00
41 00
32 00
53 00
65 00
72 00
58 00
42 00
49 00
63 00
70 00
38 00
Self-Power mode,
Enable the “remote
wakeup” function,
Copper Mode
(Note 1)
4mA
(Note 2)
4mA
(Note 2)
Primary PHY ID is 0x10
Secondary PHY is not
supported
“ASIX Elec. Corp.”
58 00 20 00
2E 00 20 00
2E 00
38 00 37 00 “AX88772B”
30 00 “000001”
Disable “AutoDetach”
Set to Cable Off Power
Saving Level 0
: Internal ROM Description
30
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Note 1:
Power Mode/Remote Wakeup/PME Settings
The offset 0x01 field of AX88772C EEPROM is used to configure the Power mode (i.e. Bus-power or
Self-power), Remote Wakeup and PME functions. Please refer to datasheet Section 4 “Serial EEPROM Memory
Map” for the detailed description of EEPROM offset 0x01.
The high byte of AX88772C EEPROM offset 0x2C and 0x53 fields are used to configure the
“bmAttributes” field of Standard Configuration Descriptor that will be reported to the USB host controller when
the GET_DESCRIPTOR command with CONFIGURATION type is issued. Please refer to below table or
“Section 9.6.3 Configuration” of Universal Serial Bus Spec Rev 2.0 for the detailed description of the
“bmAttributes” field of Standard Configuration Descriptor.
31
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Note 2:
Max Power Setting
The low byte of AX88772C EEPROM offset 0x2D and 0x54 fields are used to configure the “bMaxPower”
field of Standard Configuration Descriptor that will be reported to the USB host controller when the
GET_DESCRIPTOR command with CONFIGURATION type is issued. Please refer to below table or “Section
9.6.3 Configuration” of Universal Serial Bus Spec Rev 2.0 for the detailed description of the “bMaxPower” field
of Standard Configuration Descriptor. These fields are used to define the Maximum power consumption of the
USB device drawn from the USB bus in this specific configuration when the device is fully operational.
Expressed in 2mA units (for example, 0x64 indicates for 200mA).
4.2.2 External EEPROM Description
User can assign the specific VID/PID, Serial Number, Manufacture String, Product String, etc. user defined fields by
external EEPROM. Please refer to AX88772C EEPROM User Guide document for more details about how to
configure AX88772C EEPROM content.
32
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
5 USB Configuration Structure
5.1 USB Configuration
The AX88772C supports 1 Configuration only.
5.2 USB Interface
The AX88772C supports 1 interface.
5.3 USB Endpoints
The AX88772C supports following 4 endpoints:




Endpoint 0: Control endpoint. It is used for configuring the device.
Endpoint 1: Interrupt endpoint. It is used for reporting status.
Endpoint 2: Bulk In endpoint. It is used for receiving Ethernet Packet.
Endpoint 3: Bulk Out endpoint. It is used for transmitting Ethernet Packet.
33
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6 Electrical Specifications
6.1 DC Characteristics
6.1.1 Absolute Maximum Ratings
Symbol
VCCK
VCC18A
VCC3IO
VCC3R3
VCC3A3
VCC33A_PLL
VCC33A_H
VIN18
VIN3
Description
Rating
Unit
Digital core power supply
- 0.3 to 2.16
V
Analog Power. 1.8V
- 0.3 to 2.16
V
Power supply of 3.3V I/O
- 0.3 to 4
V
Power supply of on-chip voltage regulator
- 0.3 to 4
V
Analog Power 3.3V for Ethernet PHY bandgap
- 0.3 to 3.8
V
Analog Power 3.3V for USB PLL.
- 0.3 to 4
V
Analog Power 3.3V for USB TX and RX
- 0.3 to 4
V
Input voltage of 1.8V I/O
- 0.3 to 2.16
V
Input voltage of 3.3V I/O
- 0.3 to 4.0
V
Input voltage of 3.3V I/O with 5V tolerant
- 0.3 to 5.8
V
TSTG
Storage temperature
- 65 to 150
℃
IIN
DC input current
20
mA
IOUT
Output short circuit current
20
mA
Note: Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be
restricted to the optional sections of this datasheet. Exposure to absolute maximum rating condition for extended periods
may affect device reliability.
6.1.2 Recommended Operating Condition
Symbol
VCCK
VCC18A
VCC3R3
VCC3IO
VCC33A_H
VCC33A_PLL
VCC3A3
VIN18
VIN3
Tj
Ta
Description
Digital core power supply
Analog core power supply
Power supply of on-chip voltage regulator
Power supply of 3.3V I/O
Analog Power 3.3V for USB TX and RX
Analog Power 3.3V for USB PLL.
Analog power supply for bandgap
Input voltage of 1.8 V I/O
Input voltage of 3.3 V I/O
Input voltage of 3.3 V I/O with 5V tolerance
Junction operating temperature
Commerical ambient operating temperature in still air
Min
1.62
1.62
2.97
2.97
2.97
2.97
2.97
0
0
0
0
0
Typ
1.8
1.8
3.3
3.3
3.3
3.3
3.3
1.8
3.3
3.3
25
-
34
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
Max
1.98
1.98
3.63
3.63
3.63
3.63
3.63
1.98
3.63
5.25
125
70
Unit
V
V
V
V
V
V
V
V
V
V
℃
℃
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6.1.3 Leakage Current and Capacitance
Symbol
IIN
IOZ
CIN
COUT
Description
Input current
Tri-state leakage current
Input capacitance
Conditions
No pull-up or pull-down
Output capacitance
Min
-10
-10
-
Typ
±1
±1
2.2
Max
10
10
-
Unit
μA
μA
pF
-
2.2
-
pF
CBID
Bi-directional buffer capacitance
2.2
pF
Note: The capacitance listed above does not include pad capacitance and package capacitance. One can estimate pin
capacitance by adding a pad capacitance of about 0.5pF to the package capacitance.
6.1.4 DC Characteristics of 3.3V I/O Pins
Symbol
VCC3IO
Tj
Vil
Vih
Vt
VtVt+
Vol
Voh
Rpu
Rpd
Iin
IOZ
Description
Conditions
Power supply of 3.3V I/O
3.3V I/O
Junction temperature
Input low voltage
LVTTL
Input high voltage
Switching threshold
Schmitt trigger negative going LVTTL
threshold voltage
Schmitt trigger positive going
threshold voltage
Output low voltage
Iol = 8mA
Output high voltage
Ioh = -8mA
Input pull-up resistance
Vin = 0
Input pull-down resistance
Vin = VCC3IO
Input leakage current
Vin = VCC3IO or 0
Input leakage current with pull-up Vin = 0
resistance
Input leakage current with pull-down Vin = VCC3IO
resistance
Tri-state output leakage current
Min Typ
2.97 3.3
0
25
2.0
1.5
0.8 1.1
Max
3.63
125
0.8
-
Unit
V
℃
V
V
V
V
-
1.6
2.0
V
2.4
40
40
-10
-15
75
75
±1
-45
0.4
190
190
10
-85
V
V
KΩ
KΩ
μA
μA
15
45
85
μA
-10
±1
10
μA
35
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6.1.5 DC Characteristics of 3.3V with 5V Tolerance I/O Pins
Symbol
VCC3IO
Tj
Vil
Vih
Vt
VtVt+
Vol
Voh
Rpu
Rpd
Iin
IOZ
Description
Conditions
Power supply of 3.3V I/O
3.3V I/O
Junction temperature
Input low voltage
LVTTL
Input high voltage
Switching threshold
Schmitt trigger negative going LVTTL
threshold voltage
Schmitt trigger positive going
threshold voltage
Output low voltage
Iol = 8mA
Output high voltage
Ioh = -8mA
Input pull-up resistance
Vin = 0
Input pull-down resistance
Vin = VCC3IO
Input leakage current
Vin = 5.5V or 0
Input leakage current with pull-up Vin = 0
resistance
Input leakage current with pull-down Vin = VCC3IO
resistance
Tri-state output leakage current
Vin = 5.5V or 0
Min Typ
2.97 3.3
0
25
2.0
1.5
0.8 1.1
Max
3.63
125
0.8
-
Unit
V
℃
V
V
V
V
-
1.6
2.0
V
2.4
40
40
0.4
190
190
-15
75
75
±5
-45
-85
V
V
KΩ
KΩ
μA
μA
15
45
85
μA
±10
μA
6.1.6 DC Characteristics of Voltage Regulator
Symbol
VCC3R3
Tj
Iload
V18F
Description
Power supply of on-chip
voltage regulator.
Operating junction
temperature.
Driving current.
Cout
ESR
Min
3.0
Typ Max Unit
3.3
3.6
V
0
25
125
℃
-
-
150
mA
Output voltage of on-chip VCC3R3 = 3.3V
voltage regulator.
Dropout voltage.
△V18F = -1%, Iload = 10mA
Line regulation.
VCC3R3 = 3.3V, Iload = 10mA
1.71
1.8
1.89
V
-
0.2
0.2
0.4
V
%/V
VCC3R3 = 3.3V, 1mA ≦ Iload
≦ 150mA
VCC3R3 = 3.3V,0℃ ≦ Tj ≦
125℃
VCC3R3 = 3.3V, Iload = 0mA,
Tj = 25 ℃
Quiescent current at 125 ℃ VCC3R3 = 3.3V, Iload = 0mA,
Tj = 125 ℃
Output external capacitor.
Allowable effective series
resistance of external
capacitor.
-
0.02
0.05 %/mA
-
0.4
-
mV/℃
-
66
96
μA
-
85
115
μA
3.3
0.5
-
-
μF
Ω
Vdrop
△V18F
(△VCC3R3 x V18F)
Load regulation.
△V18F
(△Iload x V18F)
Temperature coefficient.
△V18F
△Tj
Iq_25℃
Quiescent current at 25 ℃
Iq_125℃
Conditions
Normal operation
36
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6.1.7 DC Characteristics of Fiber Interface
Symbol
Vol
Voh
|Vod|
Vol(od)
Voh(od)
|Vod|(od)
Vicm
|Vidth|
Fiber Transmitter Specification
Description
Conditions
Output low voltage
Output high voltage
Differential output voltage
Output low voltage (overdrive)
Output high voltage (overdrive)
Differential output voltage (overdrive)
Fiber Receiver Specification
Input commond-mode voltage range
Input differential threshold voltage
Min
1.2
2.0
0.54
1.1
2.2
0.65
Typ
1.57
2.4
0.83
1.5
2.5
1.02
Max
1.95
2.7
1.15
1.85
2.8
1.4
Unit
V
V
V
V
V
V
1.67
50
2.0
-
2.33
-
V
mV
Fiber SD (Signal Detect) Input Voltage Specification
SD input voltage (Visd)
Operation mode
Visd < 0.2V
Copper mode
1.0V < Visd < 1.8V
Fiber mode
No signal detected
Visd > 2.2V
Fiber mode
Signal detected
37
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6.2 Thermal Characteristics
Description
Thermal resistance of junction to case
Thermal resistance of junction to ambient
Note:
Symbol
Θ JC
Θ JA
Rating
16.7
52.2
Units
°C/W
°C/W
 JA ,  JC defined as below
 JA
=
TJ  T A
T  TC
,  JC = J
P
P
TJ: maximum junction temperature
TA: ambient or environment temperature
TC: the top center of compound surface temperature P: input power (watts)
6.3 Power Consumption
Symbol
Description
IVCC18 Current Consumption of 1.8V
IVCC33 Current Consumption of 3.3V
IVCC18 Current Consumption of 1.8V
IVCC33 Current Consumption of 3.3V
IVCC18 Current Consumption of 1.8V
IVCC33
IVCC18
IVCC33
IVCC18
IVCC33
IVCC18
Current Consumption of 3.3V
Current Consumption of 1.8V
Current Consumption of 3.3V
Current Consumption of 1.8V
Current Consumption of 3.3V
Current Consumption of 1.8V
Conditions
Operating at Ethernet 100Mbps full duplex mode
and USB High speed mode
Min
Operating at Ethernet 100Mbps full duplex mode
and USB Full speed mode
Operating at Ethernet 10Mbps full duplex mode and USB High speed mode
Operating at Ethernet 10Mbps full duplex mode and USB Full speed mode
Ethernet unlink (Disable AutoDetach)
Ethernet unlink (Enable AutoDetach)
-
IVCC33 Current Consumption of 3.3V
IVCC18 Current Consumption of 1.8V
IVCC33 Current Consumption of 3.3V
IVCC18 Current Consumption of 1.8V
IVCC33 Current Consumption of 3.3V
IVCC18 Current Consumption of 1.8V
Typ Max Unit
75.5 - mA
32.0 - mA
70.6 - mA
26.1 - mA
20.5 - mA
30.5 - mA
15.7 - mA
25.7 - mA
15.5 - mA
19.0 - mA
2.3
- mA
-
4.5
-
mA
Suspend and enable Remote WakeUp and disable
WOLLP (WOL Low Power)
-
62.7
-
mA
-
12.7
-
mA
Suspend and enable Remote WakeUp and enable
WOLLP (WOL Low Power)
-
7.5
-
mA
-
9.9
-
mA
Suspend and disable Remote WakeUp
-
20
-
μA
IVCC33 Current Consumption of 3.3V
IVCC18 Current Consumption of 1.8V
-
165
-
μA
-
21.5
-
mA
IVCC33
-
33.3
-
mA
-
16.0
-
mA
-
27.4
-
mA
-
75.5
32.0
-
mA
mA
-
168
-
mA
IVCC18
IVCC33
IDEVICE
Operating at Rev-RMII PHY mode, Ethernet
100Mbps full duplex mode and USB High speed
Current Consumption of 3.3V
mode (Embedded PHY is powered down)
Current Consumption of 1.8V
Operating at Rev-RMII PHY mode, Ethernet
100Mbps full duplex mode and USB Full speed
Current Consumption of 3.3V
mode (Embedded PHY is powered down)
Power consumption of AX88772C
1.8V
full loading (chip only)
3.3V
ISYSTEM Power consumption of AX88772C
Total of 3.3V
(Including VCC3R3 regulator supplies 1.8V to VCCK
full loading (demo board)
and VCC18A)
Table 8
: Power consumption
38
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6.4 Power-up Sequence
At power-up, the AX88772C requires the VCC3R3/VCC3IO/VCC3A3/VCC33A_H/ VCC33A_PLL power supply to
rise to nominal operating voltage within Trise3 and the V18F/VCCK/VCC18A power supply to rise to nominal operating
voltage within Trise2.
Symbol
Trise3
Trise2
Tdelay32
Tclk
Trst_pu
*1 :
Description
3.3V power supply rise time
1.8V power supply rise time
3.3V rise to 1.8V rise time delay
25MHz crystal oscillator
start-up time
RSTn low level interval time
from power-up
Condition
From 0V to 3.3V
From 0V to 1.8V
From VCC18A = 1.8V to first clock
transition of XTALIN or XTALOUT
From VCCK/VCC18A = 1.8V and
VCC3IO = 3.3V to RSTn going high
Min
0.4
-5
-
Typ
1
Max
10
10
5
-
Unit
ms
ms
ms
ms
Tclk +
-
-
ms
Trst
*1
Please refer to 1.09.16.5.2 Reset Timing for the details about the Trst.
39
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6.5 AC Timing Characteristics
Notice that the following AC timing specifications for output pins are based on CL (Output load)
=50pF.
6.5.1 Clock Timing
XTL25P
Symbol
TP_XTL25P
TH_XTL25P
TL_XTL25P
Description
XTL25P clock cycle time
XTL25P clock high time
XTL25P clock low time
Condition
Min
-
Typ
40.0
20.0
20.0
Max
-
Unit
ns
ns
ns
6.5.2 Reset Timing
Symbol
Trst
Description
Reset pulse width after XTL25P is running
Min
125
Typ
-
Max
250000
Unit
XTL25P clock cycle
(Note)
Note: If the system applications require using hardware reset pin, RESET_N, to reset AX88772C during device
initialization or normal operation after VBUS pin is asserted, the above timing spec (Min=5μ s, Max=10ms) of
RESET_N should be met.
40
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6.5.3 Serial EEPROM Timing
Symbol
Tclk
Tch
Tcl
Tdv
Tod
Tscs
Thcs
Tlcs
Ts
Th
Description
EECK clock cycle time
EECK clock high time
EECK clock low time
EEDIO output valid to EECK rising edge time
EECK rising edge to EEDIO output delay time
EECS output valid to EECK rising edge time
EECK falling edge to EECS invalid time
Minimum EECS low time
EEDIO input setup time
EEDIO input hold time
Min
2560
2562
2560
7680
23039
20
0
Typ
5120
2560
2560
-
Max
-
41
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6.5.4 Station Management Timing
MAC mode with RMII: MDC=Output
Symbol
Description
Tclk MDC clock cycle time
Tch MDC clock high time
Tcl
MDC clock low time
Tod MDC clock rising edge to MDIO output delay
Ts
MDIO data input setup time
Th
MDIO data input hold time
Min
0.5
125
0
Typ
640
320
320
-
Max
-
Unit
ns
ns
ns
Tclk
ns
ns
PHY mode (Reverse-RMII): MDC=Input
Symbol
Description
Tclk MDC clock cycle time
Tch MDC clock high time
Tcl
MDC clock low time
Tod MDC clock rising edge to MDIO output delay
Ts
MDIO data input setup time
Th
MDIO data input hold time
Min
0
10
10
Typ
320
160
160
-
Max
300
-
Unit
ns
ns
ns
ns
ns
ns
Note: MDC is Pin#17, MDIO is Pin#18.
42
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6.5.5 RMII / Reverse-RMII Timing
Symbol
Tref_clk
Tref_ch
Tref_cl
Tref_rs
Tref_rh
Description
Clock cycle time
Clock high time
Clock low time
RXD [1:0], CRSDV setup to rising REFCLK_I
RXD [1:0], CRSDV hold (delay time) from rising
Min
4.0
2.0
Typ
20.0
10.0
10.0
-
Max
-
Unit
ns
ns
ns
ns
ns
Min
4.0
2.0
Typ
-
Max
-
Unit
ns
ns
REFCLK_I
Symbol
Tref_ts
Tref_th
Description
TXD [1:0], TXEN setup to rising REFCLK_I
TXD [1:0], TXEN hold from rising REFCLK_I
43
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6.5.6 10/100M Ethernet PHY Interface Timing
+Vtxov
+Vtxa
Tr: from 10% to 90%
0V
10/100M Ethernet PHY Transmitter Waveform and Spec:
Symbol
Description
Condition
Peak-to-peak differential output voltage 10BASE-T mode
Vtxa *2 Peak-to-peak differential output voltage 100BASE-TX mode
Tr / Tf Signal rise / fall time
100BASE-TX mode
Output jitter
100BASE-TX mode, scrambled idle
signal
Vtxov Overshoot
100BASE-TX mode
Min
4.4
1.9
3
-
Typ
5
2
4
-
Max Units
5.6
V
2.1
V
5
ns
1.4
ns
-
-
5
Min
Typ
Max
Units
10
300
2.97
100
400
3.3
-
500
3.63
-
KΩ
mV
V
meter
%
10/100M Ethernet PHY Receiver Spec:
Symbol
Description
Receiver input impedance
Differential squelch voltage
Common mode input voltage
Maximum error-free cable length
Condition
10BASE-T mode
44
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
6.5.7 USB Transceiver Interface Timing
VCC33A_H/ VCC33A_PLL= 3.0 ~ 3.6 V.
Static Characteristic for Analog I/O Pins (DP/DM):
Symbol
VHSDIFF
Description
Conditions
USB 2.0 Transceiver (HS)
Input Levels (Differential Receiver)
High speed differential input
|VI (DP) –VI (DM)|
sensitivity
Measured at the connection as
Min
Typ
Max Unit
300
-
-
mV
-50
-
500
mV
-
-
100
mV
200
-
-
mV
-10
-
10
mV
-10
-
10
mV
-360
-
400
mV
700
-
1100
mV
-900
-
-500
mV
40.5
45
Termination voltage for pull-up
resistor on pin RPU
USB 1.1 Transceiver (FS/LS)
Input Levels (Differential Receiver)
Differential input sensitivity
|VI (DP) –VI (DM)|
3.0
-
3.6
V
0.2
-
-
V
Differential common mode
voltage
Input Levels (Single-Ended Receiver)
Single ended receiver threshold
0.8
-
2.5
V
0.8
-
2.0
V
Low-level output voltage
0
-
0.3
V
High-level output voltage
2.8
-
3.6
V
an application circuit.
VHSCM
VHSSQ
VHSOI
VHSOL
VHSOH
VCHIRPJ
VCHIRPK
RDRV
VTERM
VDI
VCM
VSE
High speed data signaling
common mode voltage range
High speed squelch detection
threshold
Squelch detected
No squelch detected
Output levels (differential)
High speed idle level output
voltage
High speed low level output
voltage
High speed high level output
voltage
Chirp-J output voltage
Chirp-K output voltage
Driver output impedance
Resistance
Equivalent resistance used as
internal chip
Termination
49.5 Ohm
Output levels
VOL
VOH
45
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
Dynamic Characteristic for Analog I/O Pins (DP/DM):
Symbol
tHSR
tHSF
Description
Conditions
Driver Characteristic
High-Speed Mode
High-speed differential rise time -
Min
Typ
Max
Unit
500
-
-
ps
High-speed differential fall time -
500
-
-
ps
4
-
20
ns
4
-
20
ns
Full-Speed Mode
CL=50pF; 10 to 90% of
tFR
Rise time of DP/DM
tFF
Fall time of DP/DM
CL=50pF; 90 to 10% of
Differential rise/fall time
Excluding the first transition
from idle mode
90
-
110
%
Excluding the first transition
from idle mode
Driver Timing
High-Speed Mode
See eye pattern of template 1
1.3
-
2.0
V
tFRMA
VCRS
|VOH – VOL|
|VOH – VOL|
matching (tFR / tFF)
Output signal crossover voltage
Driver waveform requirement
VI, FSE 0, OE to DP, DN
Propagation delay
Data source jitter and receiver
jitter tolerance
tPLH(rcv)
tPHL (rcv)
Receiver propagation delay
(DP; DM to RCV)
tPLH(single)
tPHL(single)
Receiver propagation delay
(DP; DM to VOP, VON)
Follow template 1 described in USB
rev 2.0 spec.
(http://www.usb.org/developers/docs)
Full-Speed Mode
For detailed description of VI,
15
ns
FSE 0 and OE, please refer to
USB rev 1.1specification.
Receiver Timing
High-Speed Mode
See eye pattern of template 4 Follow template 4 described in USB
rev 2.0 spec.
(http://www.usb.org/developers/docs)
Full-Speed Mode
For detailed description of
15
ns
RCV, please refer to USB rev
(Note)
1.1specification.
15
ns
(Note)
Note: Full-Speed Timing diagram
46
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
7
Package Information
7.1
AX88772C 64-pin LQFP package
He
E
A
A2
L
L1
Hd
D
A1
pin 1
e
b

Symbol
Millimeter
A1
Min
0.05
Typ
-
Max
0.15
A2
1.35
1.40
1.45
A
-
-
1.60
b
0.13
0.18
0.23
D
7.00
E
7.00
e
-
0.40
Hd
9.00
He
9.00
-
L
0.45
0.60
0.75
L1
-
1.00 REF
-

0°
3.5°
7°
47
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
8
Ordering Information
Part Number
AX88772CLF
Description
64 PIN, LQFP Package, Commerical grade 0°C to +70 °C (Green,
Lead-Free)
48
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
9
Revision History
Revision
Date
V0.10
V0.20
2013/02/22
2013/03/01
Comment
V1.00
2013/05/03
V1.01
2013/05/08
V1.10
2013/05/15
Preliminary release.
1. Modified the title string.
2. Modified some descriptions in Section 1.1, 2.1.
3. Updated the block diagram in Section 1.2.
4. Added the “DC Characteristics of Fiber Interface” information in Section 9.1.7.
1. Corrected a typo in the Title string.
2. Changed the “Node ID” wording to “MAC Address” in Section 4.
3. Modified some descriptions in Section 5.
4. Removed Section 6, 7, 8.
5. Added the Rev-RMII PHY power consumption in Section 6.3.
1. Modified the description in Title string.
2. Modified some descriptions in Section 1.1.
1. Modified some descriptions in the Features page and Section 3.11, 6.1.2, 6.1.6, 8.
49
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
APPENDIX A. Default Wake-On-LAN (WOL) Ready Mode
This Default WOL Ready Mode application is different from normal operation where AX88772C Suspend/Resume
state usually has to be configured by software driver during normal system operation. This application applies to a system
that needs to use a predefined remote wakeup event to turn on the power supply of the system processor and its peripheral
circuits without having any system software running in the beginning. This is quite useful when a system has been
powered down already and a user needs to power on the system from a remote location.
The AX88772C can be configured to support Default WOL Ready Mode, where no system driver is required to
configure its WOL related settings after power on reset. A system design usually partitions its power supply into two or
more groups and the AX88772C is supplied with an independent power separated from the system processor. The power
supply of AX88772C is usually available as soon as power plug is connected. The power supply of system processor
remains off initially when power plug is connected and is controlled by AX88772C’s PME pin, which can be activated
whenever AX88772C detects a predefined wakeup event such as valid Magic Packet reception, Secondary PHY link-up,
or the EXTWAKEUP_N pin trigger. To conserve power consumption, initially the USB host controller communicating
with AX88772C can also be unpowered as the system processor.
The PME pin of AX88772C can control the power management IC to power up the system processor along with the
USB host controller, which will perform USB transactions with AX88772C after both have been initialized. The pin
polarity of PME is configured as high active when enabling Default WOL Ready Mode (see following A.1 Note 2). Note
that the AX88772C must be in self-power (via setting EEPROM Flag [0]) mode for this function.
A.1 Procedure to Enable Default WOL Ready Mode
AX88772C
To enable Default WOL Ready Mode, a user needs to configure GPIO_0 pin definition as PME (via setting
EEPROM Flag [12]) and have GPIO_1 pulled-up with a 4.7Kohm resistor. After power on reset, AX88772C will disable
most functions including USB transceiver (see Note 3) but enable Magic Packet detector logic and internal Ethernet PHY
and its auto-negotiation function to be ready to receive Magic Packet. In PHY mode for AX88772C, Secondary PHY
link-up can be a wakeup event (see Note 1).
When a valid Magic Packet is received, AX88772C will assert the PME pin to indicate to system processor the
wakeup event. The PME pin, when being configured as static level output signal (via setting EEPROM Flag [15], see
Note 2), can be used to control the power management IC to enable system power supply. After asserting the PME pin,
AX88772C will also exit from the Default WOL Ready Mode and revert back to normal operation mode to start normal
USB device detection, handshaking, and enumeration.
50
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
The PME pin, when being configured as static level output signal, maintains its signal level until RESET_N is
asserted again. If asserting RESET_N to AX88772C with GPIO_1 pulled-up, the Default WOL Ready Mode will be
re-entered. Otherwise (GPIO_1 being pulled-down), the normal operation mode (non-Default WOL Ready Mode) will be
entered and the normal USB device detection, handshaking and enumeration process should take place right after
RESET_N negation.
Note 1: For complete truth table of wakeup events supported, please refer to below Remote Wakeup Truth Table on the
“GPIO_1 = 1” setting.
Note 2: Please refer to 4.1.2 Flag. The bit [15:12] of Flag (PME_IND, PME_TYP, PME_POL, PME_PIN) = 0111.
Note 3: When the Default WOL Ready Mode is enabled, the DP/DM pins of AX88772C will be in tri-state.
Note 4: It is recommended that VBUS pin be connected to system power group directly. This way the V_BUS will
become logic high when power management IC enables the system power supply.
Waken
Up by
USB
Host
Device
Device
Device
Device
Device
Device
Device
RWU bit Set_Feature
of Flag
standard
byte in
command
EEPROM
X
X
0
1
1
1
1
1
X
0
1
1
1
1
1
0
Setting
Wakeup Event
Device
RWWF RWMP RWLC GPIO_1 Host Receiving Receiving
Link Link status EXTWAKEU wakes up
(*)
sends a Wakeup a Magic
status change
P_N pin
resume Frame
Packet
change detected
signal
detected
On
On
Secondary
Primary
PHY
PHY
X
X
X
0
JK
Yes
X
1
0
0
0
X
0
X
0
1
0
0
X
0
X
0
0
1
1
X
0
0
0
0
0
0
0
1
X
Yes
X
X
X
Yes
Yes
Yes
Yes
Yes
*: About Default WOL Ready Mode, please refer to section 2.2 GPIO_1 Settings.
Table 9
X
: Remote Wakeup Truth Table
51
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
Low-pulse
Low-pulse
No
Yes
Yes
Yes
Yes
Yes
Yes
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
A.2 Flow Chart of Default WOL Ready Mode
Step 1:
(1) Operation Mode setting by Pin#19, #21 (see Section 2.2 and Note 1).
(2) Set GPIO_0 as PME definition (see Note 2).
(3) Have GPIO_1 pulled-up to enable Default WOL Ready mode.
(4) Power on reset, either by on-chip power-on reset circuit or RESET_N pin.
The Default WOL Ready Mode is enabled.
Step 2:
Wakeup event? (See Note 1)
No
Yes
Step 3:
(1) PME asserts with static level that is used as
power control to system processor.
(2) Default WOL Ready Mode is disabled.
Step 4:
System processor powers on and supplies
VBUS to AX88772C.
Step 5:
AX88772C is in normal operation mode.
Step 6:
Assert RESET_N AND
GPIO_1 = 1?
No
Yes
(1) PME de-asserts.
(2) The Default WOL Ready Mode is enabled.
52
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
APPENDIX B. Ethernet PHY Power and Reset Control
This section indicates some information about AX88772C Ethernet PHY Power and Reset control.
In Ethernet PHY’s BMCR
register, bit 11 (power down) is
used as power-down control to
the embedded Ethernet PHY.
This bit turns off the power
consumption of all the digital
and analog blocks except for
OSC and PLL.
AX88772C Embedded Ethernet PHY
In Software Reset Register
(0x20), the IPRL bit is used as
reset signal to the entire
embedded Ethernet PHY.
In Software Reset Register
(0x20), the IPPD bit is used as
power-down control to the
embedded Ethernet PHY. This
bit turns off the power
consumption of all the digital
and analog blocks including
OSC, PLL, and bandgap, etc.
Figure 17
: Ethernet PHY Oscillator/PLL Block Diagram
53
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
The following power-up and reset signal timing issued to the Ethernet PHY of AX88772C must be met in order to
initialize the Ethernet PHY properly and reliably every time after it has been put into power-down mode previously.
Symbol
Description
T1 Ethernet PHY in power-down mode where the internal 25MHz OSC, 125MHz
PLL and analog bandgap of AX88772C are completely turned off for max.
power saving. This is the lowest power consumption mode of the Ethernet
PHY.
Note: Alternatively, user can use the Ethernet PHY’s BMCR register bit 11,
“power down”, to set the Ethernet PHY into power-down mode. When the
BMCR bit 11 power-down is used, the 25MHz OSC and 125MHz PLL will
remain toggled but the analog bandgap will be turned off. The power
consumption of BMCR bit 11 power-down mode is about 15mA more than the
Software Reset Register (0x20) IPPD bit power-down mode.
T2 From Ethernet PHY power-up to 25MHz OSC and 125MHz PLL stable time.
Note: If the IPRL is low during T2, it should be kept at low for more than T2
time so that the Ethernet PHY can be reset properly right after the power-up. In
other words, the successful and reliable reset to the Ethernet PHY can only be
accomplished with a stable running 25MHz OSC and 125MHz PLL clocks.
T3 Mandatory Ethernet PHY reset time after it has just been powered up from the
previous power-down mode (after >T2 time). Also, software can issue reset to
the Ethernet PHY during its non-power-down mode, but the minimum reset
duration defined here must be met.
Figure 18
Min
500ns
Typ
-
Max
-
600ms
-
-
500ns
-
-
: Ethernet PHY Power-up & Reset Timing Diagram
54
Copyright © 2013 ASIX Electronics Corporation. All rights reserved.
AX88772C
USB 2.0 to 10/100M Fast Ethernet Controller
with Microsoft AOAC Support
4F, No.8, Hsin Ann Rd., Hsinchu Science Park,
Hsinchu, Taiwan, R.O.C.
TEL: +886-3-5799500
FAX: +886-3-5799558
Email: [email protected]
Web: http://www.asix.com.tw