AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller Features Document No: AX88x72A/V1.1/12/24/07 Single chip USB 2.0 to 10/100M Fast Ethernet controller – AX88772A Single chip USB 2.0 to MII, single chip MII to Ethernet and USB Bridging controller in Dual-PHY mode (submitted for US patent application) – AX88172A USB Device Interface Integrates on-chip USB 2.0 transceiver and SIE compliant to USB Spec 1.1 and 2.0 Supports USB Full and High Speed modes with Bus-Power or Self-Power capability Supports 4 or 6 programmable endpoints on USB interface High performance packet transfer rate over USB bus using proprietary burst transfer mechanism (submitted for US patent application) Supports USB to Ethernet bridging or vice versa in hardware Fast Ethernet Controller Integrates 10/100Mbps Fast Ethernet MAC/PHY IEEE 802.3 10BASE-T/100BASE-TX compatible Supports twisted pair crossover detection and auto-correction (HP Auto-MDIX) Embedded 16KB SRAM for RX packet buffering and 8KB SRAM for TX packet buffering Supports both Full-duplex with flow control and Half-duplex with backpressure operation Supports 2 VLAN ID filtering, received VLAN Tag (4 bytes) can be stripped off or preserved MAC/PHY loop-back diagnostic capability Support Wake-on-LAN Function Supports Suspend Mode and Remote Wakeup via Link-up, Magic packet, MS wakeup frame and external pin Optional PHY power down during Suspend Mode Versatile External Media Interface Optional MII interface in MAC mode allows AX88172A to work with external 100BASE-FX Ethernet PHY or HomePNA PHY Optional Reverse-MII or Reverse-RMII interface in PHY mode allows AX88172A to work with external HomePlug PHY or glueless MAC-to-MAC connections Optional Reverse-MII interface in Dual-PHY mode allows AX88172A to act as an Ethernet PHY or USB 2.0 PHY for external MAC device that needs Ethernet and USB in system application Supports 256/512 bytes (93c56/93c66) of serial EEPROM (for storing USB Descriptors) Supports automatic loading of Ethernet ID, USB Descriptors and Adapter Configuration from EEPROM after power-on initialization Provides optional serial interface, I2C, SPI and UART Integrates on-chip voltage regulator and only requires a single 3.3V power supply 12MHz and 25Mhz clock input from either crystal or oscillator source Integrates on-chip power-on reset circuit Small form factor with 64-pin LQFP (AX88772A) or 80-pin TQFP (AX88172A) RoHS compliant package Operating temperature range: 0°C to 70°C. *IEEE is a registered trademark of the Institute of Electrical and Electronic Engineers, Inc. *All other trademarks and registered trademark are the property of their respective holders. Product Description The AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet controller is a high performance and highly integrated ASIC which enables low cost, small form factor, and simple plug-and-play Fast Ethernet network connection capability for desktops, notebook PC’s, Ultra-Mobile PC’s, docking stations, game consoles, digital-home appliances, and any embedded system using a standard USB port. The AX88772A/AX88172A features a USB interface to communicate with a USB Host Controller and is compliant with USB specification V1.1 and V2.0. The AX88772A/AX88172A implements 10/100Mbps Ethernet LAN function based on IEEE802.3, and IEEE802.3u standards with 24KB of embedded SRAM for packet buffering. The AX88772A/AX88172A integrates an on-chip 10/100Mbps Ethernet PHY to simplify system design. The AX88172A provides an optional External Media Interface (EMI) for external PHY or external MAC for different application purposes. The EMI can be a media-independent interface (MII) for implementing 100BASE-FX Ethernet or HomePNA functions. The EMI can also be a Reverse-MII or Reverse Reduced-MII (Reverse-RMII) for glueless MAC-to-MAC connections to any MCU with Ethernet MAC MII or RMII interface. In addition, the EMI can be configured to Dual-PHY mode allowing AX88172A to act as an Ethernet PHY or USB 2.0 PHY for external MAC device that needs Ethernet and USB interfaces in their system applications. The optional serial interface such as I2C, SPI, and UART are provided as a control channel from the USB Host Controller to communicate with the external MCU chip. Always contact ASIX for possible updates before starting a design. This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product. ASIX ELECTRONICS CORPORATION 4F, NO.8, Hsin Ann Rd., Hsinchu Science Park, Hsin-Chu City, Taiwan, R.O.C. 300 FAX: 886-3-579-9558 TEL: 886-3-579-9500 Released Date: 12/24/2007 http://www.asix.com.tw/ AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller Target Applications PC/Internet USB Dongle Docking Station Port Replicator for Mobile Computer UMPC Media Gateway USB KVME Switch Internet Security USB Key Card Reader UWB/802.11n/WiMAX USB Dongle Pocketable Computer Consumer Electronics Portable Media Player IP STB TiVo Box ePiano DVD-Recorder/DVR Game Console IPTV Figure 1 : Target Applications 2 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller Typical System Block Diagrams Hosted by USB to operate with internal Ethernet PHY only To USB 2.0 Host I/F AX88772A EEPROM Ethernet PHY SPI I2C UART Magnetic RJ45 Figure 2 : USB 2.0 to LAN Adaptor (MAC mode) Hosted by USB to operate with either internal Ethernet PHY or EMI (in MAC mode) To USB 2.0 Host I/F AX88172A EEPROM Ethernet PHY MDC MDIO MII SPI I2C UART Magnetic 100BASE FX PHY or HomePNA PHY RJ45 Magnetic Fiber RJ11 Figure 3 : USB 2.0 to Fast Ethernet and 100BASE-FX Fiber/HomePNA Combo (MAC mode) 3 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller Hosted by USB to operate with either internal Ethernet PHY (in MAC mode) or EMI (in PHY mode) To USB 2.0 Host I/F AX88172A EEPROM MDC MDIO Ethernet PHY Reverse-MII or Reverse-RMII (No oscillator or buffer required) SPI I2C UART Magnetic Ethernet MAC Embedded MCU RJ45 Figure 4 : Bridging Embedded MCU to USB 2.0 Host Interface (PHY mode) To USB 2.0 Host I/F AX88172A EEPROM Ethernet PHY MDC MDIO Reverse-MII or Reverse-RMII (No oscillator or buffer required) Magnetic HomePlug PHY RJ45 PowerLine Figure 5 : USB 2.0 to HomePlug Adaptor (PHY mode) 4 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller Hosted by EMI to operate with either internal Ethernet PHY or USB PHY (in Dual-PHY mode) Embedded MCU SPI I2C UART Ethernet MAC Reverse-MII (No oscillator or buffer required) MDC MDIO AX88172A EEPROM Ethernet PHY USB 2.0 device Magnetic To USB 2.0 Host I/F RJ45 Figure 6 : Bridging Embedded MCU to either Ethernet PHY or USB 2.0 Interface 5 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller Table of Contents 1.0 INTRODUCTION ................................................................................................................... 9 1.1 1.2 1.3 GENERAL DESCRIPTION ....................................................................................................................................... 9 BLOCK DIAGRAM ................................................................................................................................................ 9 PINOUT DIAGRAM.............................................................................................................................................. 10 2.0 SIGNAL DESCRIPTION ........................................................................................... 14 2.1 2.2 2.3 AX88772A 64-PIN PINOUT DESCRIPTION ......................................................................................................... 14 AX88172A 80-PIN PINOUT DESCRIPTION ......................................................................................................... 16 HARDWARE SETTING FOR OPERATION MODE AND MULTI-FUNCTION PINS ...................................................... 20 3.0 FUNCTION DESCRIPTION................................................................................. 20 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 USB CORE AND INTERFACE .............................................................................................................................. 20 10/100M ETHERNET PHY ................................................................................................................................. 20 MAC CORE ....................................................................................................................................................... 20 OPERATION MODE ............................................................................................................................................. 20 STATION MANAGEMENT (STA)......................................................................................................................... 20 MEMORY ARBITER ............................................................................................................................................ 20 USB TO ETHERNET BRIDGE .............................................................................................................................. 20 SERIAL EEPROM LOADER ............................................................................................................................... 20 GENERAL PURPOSE I/O...................................................................................................................................... 20 SERIAL INTERFACE CONTROLLER ...................................................................................................................... 20 CLOCK GENERATION ......................................................................................................................................... 20 RESET GENERATION .......................................................................................................................................... 20 VOLTAGE REGULATOR ...................................................................................................................................... 20 4.0 SERIAL EEPROM MEMORY MAP ........................................................ 20 4.1 DETAILED DESCRIPTION .................................................................................................................................... 20 5.0 USB CONFIGURATION STRUCTURE .............................................. 20 5.1 5.2 5.3 USB CONFIGURATION ....................................................................................................................................... 20 USB INTERFACE ................................................................................................................................................ 20 USB ENDPOINTS ............................................................................................................................................... 20 6.0 USB COMMANDS ............................................................................................................... 20 6.1 USB STANDARD COMMANDS ............................................................................................................................ 20 6.2 USB VENDOR COMMANDS ................................................................................................................................ 20 6.2.1 Detailed Register Description .................................................................................................................. 20 6.2.2 Command Block Wrapper for Serial Interface ......................................................................................... 20 6.2.2.1 UART controller ................................................................................................................................. 20 6.2.2.2 I2C controller ...................................................................................................................................... 21 6.2.2.3 SPI controller ...................................................................................................................................... 21 6.3 INTERRUPT ENDPOINT ....................................................................................................................................... 21 7.0 EMBEDDED ETHERNET PHY REGISTER DESCRIPTION ........................................................................................................................................ 21 7.1 PHY REGISTER DETAILED DESCRIPTION........................................................................................................... 21 7.1.1 Basic Mode Control Register (BMCR) ..................................................................................................... 21 7.1.2 Basic Mode Status Register (BMSR)......................................................................................................... 21 7.1.3 PHY Identifier Register 1.......................................................................................................................... 21 6 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 7.1.4 7.1.5 7.1.6 7.1.7 PHY Identifier Register 2.......................................................................................................................... 21 Auto Negotiation Advertisement Register (ANAR) ................................................................................... 21 Auto Negotiation Link Partner Ability Register (ANLPAR) ..................................................................... 21 Auto Negotiation Expansion Register (ANER) ......................................................................................... 21 8.0 STATION MANAGEMENT REGISTERS IN PHY/DUAL-PHY MODE ........................................................................................................... 21 8.1 PHY/DUAL-PHY MODE DETAILED REGISTER DESCRIPTION ............................................................................ 21 8.1.1 PHY Mode Basic Mode Control Register (PM_BMCR)........................................................................... 21 8.1.2 PHY Mode Basic Mode Status Register (PM_BMSR) .............................................................................. 21 8.1.3 PHY Mode PHY Identifier Register 1 ....................................................................................................... 21 8.1.4 PHY Mode PHY Identifier Register 2 ....................................................................................................... 21 8.1.5 PHY Mode Auto Negotiation Advertisement Register (PM_ANAR) ......................................................... 21 8.1.6 PHY Mode Auto Negotiation Link Partner Ability Register (PM_ANLPAR) ........................................... 21 8.1.7 PHY Mode Auto Negotiation Expansion Register (PM_ANER) ............................................................... 21 8.1.8 PHY Mode Control Register (PM_Control) ............................................................................................. 21 9.0 ELECTRICAL SPECIFICATIONS ............................................................ 22 9.1 DC CHARACTERISTICS ...................................................................................................................................... 22 9.1.1 Absolute Maximum Ratings ...................................................................................................................... 22 9.1.2 Recommended Operating Condition......................................................................................................... 22 9.1.3 Leakage Current and Capacitance ........................................................................................................... 23 9.1.4 DC Characteristics of 3.3V I/O Pins ........................................................................................................ 23 9.1.5 DC Characteristics of 3.3V with 5V Tolerance I/O Pins.......................................................................... 24 9.1.6 DC Characteristics of Voltage Regulator................................................................................................. 25 9.2 POWER CONSUMPTION ...................................................................................................................................... 26 9.3 POWER-UP SEQUENCE ....................................................................................................................................... 27 9.4 AC TIMING CHARACTERISTICS.......................................................................................................................... 28 9.4.1 Clock Timing............................................................................................................................................. 28 9.4.2 Reset Timing ............................................................................................................................................. 28 9.4.3 Serial EEPROM Timing............................................................................................................................ 29 9.4.4 MII Timing ................................................................................................................................................ 30 9.4.5 Station Management Timing..................................................................................................................... 31 9.4.6 Reverse-MII Timing .................................................................................................................................. 32 9.4.7 Reverse-RMII Timing................................................................................................................................ 33 9.4.8 I2C Interface Timing................................................................................................................................. 34 9.4.9 SPI Interface Timing................................................................................................................................. 35 9.4.10 10/100M Ethernet PHY Interface Timing ................................................................................................. 37 9.4.11 USB Transceiver Interface Timing ........................................................................................................... 38 10.0 10.1 10.2 PACKAGE INFORMATION ........................................................................... 40 AX88772A 64-PIN LQFP PACKAGE.................................................................................................................. 40 AX88172A 80-PIN TQFP PACKAGE.................................................................................................................. 41 11.0 ORDERING INFORMATION ........................................................................ 42 12.0 REVISION HISTORY ................................................................................................ 43 APPENDIX A. DEFAULT WOL READY MODE .................................................................... 44 7 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller List of Figures FIGURE 1 FIGURE 2 FIGURE 3 FIGURE 4 FIGURE 5 FIGURE 6 FIGURE 7 FIGURE 8 FIGURE 9 FIGURE 10 FIGURE 11 : TARGET APPLICATIONS ................................................................................................................................. 2 : USB 2.0 TO LAN ADAPTOR (MAC MODE)................................................................................................... 3 : USB 2.0 TO FAST ETHERNET AND 100BASE-FX FIBER/HOMEPNA COMBO (MAC MODE) ........................ 3 : BRIDGING EMBEDDED MCU TO USB 2.0 HOST INTERFACE (PHY MODE).................................................... 4 : USB 2.0 TO HOMEPLUG ADAPTOR (PHY MODE).......................................................................................... 4 : BRIDGING EMBEDDED MCU TO EITHER ETHERNET PHY OR USB 2.0 INTERFACE ....................................... 5 : AX88772A/AX88172A BLOCK DIAGRAM ................................................................................................... 9 : AX88772A PINOUT DIAGRAM (MAC MODE WITHOUT MII)....................................................................... 10 : AX88172A PINOUT DIAGRAM (MAC MODE WITH MII) ............................................................................. 11 : AX88172A PINOUT DIAGRAM (PHY MODE WITH REVERSE-MII) .......................................................... 12 : AX88172A PINOUT DIAGRAM (PHY MODE WITH REVERSE-RMII)........................................................ 13 List of Tables TABLE 1 TABLE 2 TABLE 3 : AX88772A 64-PIN PINOUT DESCRIPTION ................................................................................................... 14 : AX88172A 80-PIN PINOUT DESCRIPTION ................................................................................................... 16 : POWER CONSUMPTION ................................................................................................................................. 26 8 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 1.0 Introduction 1.1 General Description The AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet controller is a high performance and highly integrated ASIC which enables low cost, small form factor, and simple plug-and-play Fast Ethernet network connection capability for desktops, notebook PC’s, Ultra-Mobile PC’s, docking stations, game consoles, digital-home appliances, and any embedded system using a standard USB port. The AX88772A/AX88172A features a USB interface to communicate with a USB Host Controller and is compliant with USB specification V1.1 and V2.0. The AX88772A/AX88172A implements a 10/100Mbps Ethernet LAN function based on IEEE802.3, and IEEE802.3u standards with 24KB of embedded SRAM for packet buffering. The AX88772A/AX88172A integrates an on-chip 10/100Mbps Ethernet PHY to simplify system design. The AX88172A provides an optional External Media Interface (EMI) for external PHY or external MAC for different application purposes. The EMI can be a media-independent interface (MII) for implementing 100BASE-FX Ethernet or HomePNA functions. The EMI can also be a Reverse-MII or Reverse Reduced-MII (Reverse-RMII) for glueless MAC-to-MAC connections to any MCU with Ethernet MAC MII or RMII interface. In addition, the EMI can be configured to Dual-PHY mode allowing AX88172A to act as an Ethernet PHY or USB 2.0 PHY for external MAC device that needs Ethernet and USB interfaces in their system applications. The optional serial interface such as I2C, SPI, and UART are provided as a control channel from the USB Host Controller to communicate with the external MCU chip. The AX88772A/AX88172A needs 12MHz clock for USB operation and 25Mhz clock for Fast Ethernet operation. The AX88772A is housed in the 64-pin LQFP and the AX88172A is housed in the 80-pin TQFP RoHS compliant package. 1.2 Block Diagram 24KB SRAM EECS EECK EEDIO SEEPROM Loader I/F GPIO_2~0 General Purpose I/O MAC Core Memory Arbiter 10/100M Ethernet PHY AX88172A only USB to Ethernet Bridge PHY/MAC mode Bridge STA SI_3~0 Serial I/F Controller: UART/I2C/SPI 3.3 to 1.8V Regulator External Media Interface MII / Reverse-MII / Reverse-RMII MDC / MDIO USB Core and Interfaces PLL Clock Generators XTL25P, XTL25N XTL12P, XTL12N Figure 7 RXIP/RXIN TXOP/TXON Power-On-Reset & Reset Gen. DP/DM RESET_N : AX88772A/AX88172A Block Diagram 9 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 1.3 Pinout Diagram VCCK GND EECK EECS EEDIO TCLK_1 TCLK_0 TCLK_EN VCC3IO RESET_N TEST1 TEST0 GND GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 (MAC mode without MII) 57 58 59 60 61 62 63 64 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Figure 8 32 SI_0 31 SI_1 30 SI_2 29 SI_3 28 GPIO_0 / PME 27 GPIO_1 26 GPIO_2 25 VCCK 24 EXTWAKEUP_N 23 GND 22 USB_LED 21 VCCK 20 LINK_LED 19 SPEED_LED 18 FDX_LED 17 VCC3IO GND GND VCCK VCCK GND3R3 VCC3R3 V18F GND18A TXON TXOP VCC18A RXIN RXIP GND3A3 VCC3A3 AX88772A RSET_BG VCC3IO VCCK XTL12P XTL12N VCC33A_H GND33A_H RREF DM DP VCC33A_PLL GND33A_PLL GND VCC18A XTL25P XTL25N GND18A VCCK V_BUS AX88772A in 64-pin LQFP package : AX88772A Pinout Diagram (MAC mode without MII) 10 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller VCCK GND MDIO MDC EECK EECS EEDIO TCLK_1 TCLK_0 TCLK_EN VCC3IO RESET_N TEST1 TEST0 GND GND VCCK V_BUS TXD3 TXD2 AX88172A in 80-pin TQFP package - MAC mode with MII 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 SI_0 39 SI_1 38 SI_2 37 SI_3 36 GPIO_0 / PME 35 GPIO_1 34 GPIO_2 33 VCCK 32 COL 31 CRS 30 EXTWAKEUP_N 29 GND 28 USB_LED 27 VCCK 26 LINK_LED 25 SPEED_LED 24 FDX_LED 23 RXD0 22 RXD1 21 VCC3IO AX88172A RXD2 RXD3 RXDV RXCLK GND GND VCCK VCCK GND3R3 9 10 11 12 13 14 15 16 17 18 19 20 VCC3R3 RXIN 8 V18F RXIP Figure 9 6 7 GND18A 5 TXON 4 TXOP 3 VCC18A 2 GND3A3 (MAC mode with MII) VCC3A3 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 0 1 RSET_BG TXD1 TXD0 TXCLK TXEN VCC3IO VCCK XTL12P XTL12N VCC33A_H GND33A_H RREF DM DP VCC33A_PLL GND33A_PLL GND VCC18A XTL25P XTL25N GND18A : AX88172A Pinout Diagram (MAC mode with MII) 11 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller VCCK GND MDIO MDC EECK EECS EEDIO TCLK_1 TCLK_0 TCLK_EN VCC3IO RESET_N TEST1 TEST0 GND GND VCCK V_BUS RXD3 RXD2 AX88172A in 80-pin TQFP package - PHY mode with Reverse-MII 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 RXD1 61 RXD0 62 RXCLK 63 RXDV 64 VCC3IO 65 VCCK 66 XTL12P 67 XTL12N 68 VCC33A_H 69 GND33A_H 70 (PHY mode with Reverse-MII) RREF 71 DM 72 DP 73 VCC33A_PLL 74 GND33A_PLL 75 GND 76 VCC18A 77 XTL25P 78 XTL25N 79 GND18A 80 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TXD2 TXD3 TXEN TXCLK GND GND VCCK VCCK GND3R3 VCC3R3 V18F GND18A TXON TXOP VCC18A RXIN RXIP GND3A3 VCC3A3 RSET_BG AX88172A 40 SI_0 39 SI_1 38 SI_2 37 SI_3 36 GPIO_0 / PME 35 GPIO_1 34 RXER 33 VCCK 32 COL 31 CRS 30 EXTWAKEUP_N 29 GND 28 USB_LED 27 VCCK 26 LINK_LED 25 SPEED_LED 24 FDX_LED 23 TXD0 22 TXD1 21 VCC3IO Figure 10 : AX88172A Pinout Diagram (PHY mode with Reverse-MII) 12 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller VCCK GND MDIO MDC EECK EECS EEDIO TCLK_1 TCLK_0 TCLK_EN VCC3IO RESET_N TEST1 TEST0 GND GND VCCK V_BUS MIS_1 MIS_0 AX88172A in 80-pin TQFP package - PHY mode with Reverse-RMII 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 SI_0 39 SI_1 38 SI_2 37 SI_3 36 GPIO_0 / PME 35 GPIO_1 34 RXER 33 VCCK 32 NC 31 NC 30 EXTWAKEUP_N 29 GND 28 USB_LED 27 VCCK 26 LINK_LED 25 SPEED_LED 24 FDX_LED 23 TXD0 22 TXD1 21 VCC3IO AX88172A NC NC TXEN GND REFCLK_I GND VCCK VCCK GND3R3 9 10 11 12 13 14 15 16 17 18 19 20 VCC3R3 RXIN 8 V18F RXIP 6 7 GND18A 5 TXON 4 TXOP 3 VCC18A 2 GND3A3 (PHY mode with Reverse-RMII) VCC3A3 RSET_BG RXD1 61 RXD0 62 REFCLK_O 63 CRSDV 64 VCC3IO 65 VCCK 66 XTL12P 67 XTL12N 68 VCC33A_H 69 GND33A_H 70 RREF 71 DM 72 DP 73 VCC33A_PLL 74 GND33A_PLL 75 GND 76 VCC18A 77 XTL25P 78 XTL25N 79 GNDK18A 80 0 1 Figure 11 : AX88172A Pinout Diagram (PHY mode with Reverse-RMII) 13 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 2.0 Signal Description The following abbreviations apply to the following pin description table. I18 I3 I5 O3 O5 B5 Input, 1.8V AO Analog Output Input, 3.3V AB Analog Bi-directional I/O Input, 3.3V with 5V tolerant PU Internal Pull Up (75K) Output, 3.3V PD Internal Pull Down (75K) Output, 3.3V with 5V tolerant P Power Pin Bi-directional I/O, 3.3V with 5V S Schmitt Trigger tolerant T Tri-stateable AI Analog Input Note: Every output or bi-directional I/O pin is 8mA driving strength. 2.1 AX88772A 64-pin Pinout Description Table 1 Pin Name Type Pin No DP DM VBUS XTL12P AB AB I5/PD/S I3 57 56 48 51 XTL12N RREF O3 AI 52 55 EECK B5/PD/ T 35 EECS B5/PD/ T 36 EEDIO B5/PU/ T 37 XTL25P I18 62 XTL25N RXIP RXIN TXOP TXON RSET_BG O18 AB AB AB AB AO 63 4 5 7 8 1 LINK_LED O5 20 : AX88772A 64-pin Pinout Description Pin Description USB Interface USB 2.0 data positive pin. USB 2.0 data negative pin. VBUS pin input. Please connect to USB bus power. 12Mhz ±0.003%crystal or oscillator clock input. This clock is needed for USB PHY transceiver to operate. 12Mhz crystal or oscillator clock output. For USB PHY’s internal biasing. Please connect to analog GND through a resistor (12.1Kohm ±1%). Serial EEPROM Interface EEPROM Clock. EECK is an output clock to EEPROM to provide timing reference for the transfer of EECS, and EEDIO signals. EECK only drive high / low when access EEPROM otherwise keep at tri-state and internal pull-down. EEPROM Chip Select. EECS is asserted high synchronously with respect to rising edge of EECK as chip select signal. EECS only drive high / low when access EEPROM otherwise keep at tri-state and internal pull-down. EEPROM Data In. EEDIO is the serial output data to EEPROM’s data input pin and is synchronous with respect to the rising edge of EECK. EEDIO only drive high / low when access EEPROM otherwise keep at tri-state and internal pull-up. Ethernet PHY Interface 25Mhz ± 0.005% crystal or oscillator clock input. This clock is needed for the embedded 10/100M Ethernet PHY to operate. 25Mhz crystal or oscillator clock output. Receive data input positive pin for both 10BASE-T and 100BASE-TX. Receive data input negative pin for both 10BASE-T and 100BASE-TX. Transmit data output positive pin for both 10BASE-T and 100 BASE-TX Transmit data output negative pin for both 10BASE-T and 100 BASE-TX For Ethernet PHY’s internal biasing. Please connect to GND through a 12.1Kohm ±1% resistor. Link status LED indicator. This pin drives low continuously when the Ethernet link is up and drives low and high in turn (blinking) when Ethernet PHY is in receiving or transmitting state. 14 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller FDX_LED O5 18 Full Duplex and collision detected LED indicator. This pin drives low when the Ethernet PHY is in full-duplex mode and drives high when in half duplex mode. When in half duplex mode and the Ethernet PHY detects collision, it will be driven low (or blinking). SPEED_LED O5 19 Ethernet speed LED indicator. This pin drives low when the Ethernet PHY is in 100BASE-TX mode and drives high when in 10BASE-T mode. Misc. Pins RESET_N I5/PU/S 42 Chip reset input. Active low. This is the external reset source used to reset this chip. This input feeds to the internal power-on reset circuitry, which provides the main reset source of this chip. After completing reset, EEPROM data will be loaded automatically. EXTWAKEUP_N I5/PU/S 24 Remote-wakeup trigger from external pin. EXTWAKEUP_N should be asserted low for more than 2 cycles of 12MHz clock to be effective. GPIO_2 B5/PD 26 General Purpose Input/ Output Pin 2. GPIO_1 B5/PD 27 General Purpose Input/ Output Pin 1. This pin is default as input pin after power-on reset. This pin is also for Default WOL Ready Mode setting; please refer to section 2.3 Settings. GPIO_0/PME B5/PD 28 General Purpose Input/ Output Pin 0 or PME (Power Management Event). This pin is default as input pin after power-on reset. GPIO_0 also can be defined as PME output to indicate wake up event detected. Please refer to section 2.3 Settings. SI_3 B5/PU 29 UART_RX or SPI_MISO. This is a multi-function pin determined by EEPROM Flag [1] setting. Please refer to section 2.3 Settings. SI_2 B5/PU 30 UART_TX or SPI_MOSI. This is a multi-function pin determined by EEPROM Flag [1] setting. Please refer to section 2.3 Settings. SI_1 B5/PU 31 I2C_SDA or SPI_SS. This is a multi-function pin determined by EEPROM Flag [1] setting. Please refer to section 2.3 Settings. SI_0 B5/PU 32 I2C_SCLK or SPI_SCLK. This is a multi-function pin determined by EEPROM Flag [1] setting. Please refer to section 2.3 Settings. USB_LED O5 22 USB Speed indicator: When USB bus is in Full speed, this pin drives high continuously. When USB bus is in High speed, this pin drives low continuously. This pin drives high and low in turn (blinking) to indicate TX data transfer going on whenever the host controller sends bulk out data transfer. TEST0 I5/S 44 Test pin. For normal operation, user should connect to ground. TEST1 I5/S 43 Test pin. For normal operation, user should connect to ground. TCLK_EN I5/PD/S 40 Test pin. For normal operation, user should keep this pin NC. TCLK_0 I5/PD 39 Test pin. For normal operation, user should keep this pin NC. TCLK_1 I5/PD 38 Test pin. For normal operation, user should keep this pin NC. On-chip Regulator Pins VCC3R3 P 11 3.3V Power supply to on-chip 3.3V to 1.8V voltage regulator. GND3R3 P 12 Ground pin of on-chip 3.3V to 1.8V voltage regulator. V18F P 10 1.8V voltage output of on-chip 3.3V to 1.8V voltage regulator. Power and Ground Pins VCCK P 13, 14, 21, 25, Digital Core Power. 1.8V. 33, 47, 50 VCC3IO P 17, 41, 49 Digital I/O Power. 3.3V. GND P 15, 16, 23, 34, Digital Ground. 45, 46, 60 VCC33A_H P 53 Analog Power for USB transceiver. 3.3V. GND33A_H P 54 Analog Ground for USB transceiver. VCC33A_PLL P 58 Analog Power for USB PLL. 3.3V. GND33A_PLL P 59 Analog Ground for USB PLL. VCC3A3 P 2 Analog Power for Ethernet PHY bandgap. 3.3V. GND3A3 P 3 Analog Ground for Ethernet PHY. VCC18A P 6, 61 Analog Power for Ethernet PHY and 25Mhz crystal oscillator. 1.8V. 15 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller GND18A P 9, 64 Analog Ground for Ethernet PHY and 25Mhz crystal oscillator. 2.2 AX88172A 80-pin Pinout Description Table 2 Pin Name Type Pin No DP DM VBUS XTL12P AB AB I5/PD/S I3 73 72 58 67 XTL12N RREF O3 AI 68 71 EECK B5/PD/ T 45 EECS B5/PD/ T 46 EEDIO B5/PU/ T 47 XTL25P I18 78 XTL25N RXIP RXIN TXOP TXON RSET_BG O18 AB AB AB AB AO 79 4 5 7 8 1 LINK_LED O5 26 FDX_LED O5 24 SPEED_LED O5 25 I5/PU/S 52 EXTWAKEUP_N I5/PU/S 30 GPIO_2 / RXER B5/PD 34 RESET_N : AX88172A 80-pin Pinout Description Pin Description USB Interface USB 2.0 data positive pin. USB 2.0 data negative pin. VBUS pin input. Please connect to USB bus power. 12Mhz ±0.003%crystal or oscillator clock input. This clock is needed for USB PHY transceiver to operate. 12Mhz crystal or oscillator clock output. For USB PHY’s internal biasing. Please connect to analog GND through a resistor (12.1Kohm ±1%). Serial EEPROM Interface EEPROM Clock. EECK is an output clock to EEPROM to provide timing reference for the transfer of EECS, and EEDIO signals. EECK only drive high / low when access EEPROM otherwise keep at tri-state and internal pull-down. EEPROM Chip Select. EECS is asserted high synchronously with respect to rising edge of EECK as chip select signal. EECS only drive high / low when access EEPROM otherwise keep at tri-state and internal pull-down. EEPROM Data In. EEDIO is the serial output data to EEPROM’s data input pin and is synchronous with respect to the rising edge of EECK. EEDIO only drive high / low when access EEPROM otherwise keep at tri-state and internal pull-up. Ethernet PHY Interface 25Mhz ± 0.005% crystal or oscillator clock input. This clock is needed for the embedded 10/100M Ethernet PHY to operate. 25Mhz crystal or oscillator clock output. Receive data input positive pin for both 10BASE-T and 100BASE-TX. Receive data input negative pin for both 10BASE-T and 100BASE-TX. Transmit data output positive pin for both 10BASE-T and 100 BASE-TX Transmit data output negative pin for both 10BASE-T and 100 BASE-TX For Ethernet PHY’s internal biasing. Please connect to GND through a 12.1Kohm ±1% resistor. Link status LED indicator. This pin drives low continuously when the Ethernet link is up and drives low and high in turn (blinking) when Ethernet PHY is in receiving or transmitting state. Full Duplex and collision detected LED indicator. This pin drives low when the Ethernet PHY is in full-duplex mode and drives high when in half duplex mode. When in half duplex mode and the Ethernet PHY detects collision, it will be driven low (or blinking). Ethernet speed LED indicator. This pin drives low when the Ethernet PHY is in 100BASE-TX mode and drives high when in 10BASE-T mode. Misc. Pins Chip Reset Input. RESET_N pin is active low. When asserted, it puts the entire chip into reset state immediately. After completing reset, EEPROM data will be loaded automatically. Remote-wakeup trigger from external pin. EXTWAKEUP_N should be asserted low for more than 2 cycles of 12MHz clock to be effective. General Purpose Input/ Output Pin 2. This pin is GPIO_2 in MAC mode, but it will be redefined as RXER (receive error) or GPIO_2 depending on EEPROM Flag [3] in PHY mode. 16 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller GPIO_1 B5/PD GPIO_0 / PME B5/PD SI_3 B5/PU SI_2 B5/PU SI_1 B5/PU SI_0 B5/PU USB_LED O5 TEST0 TEST1 TCLK_EN TCLK_0 TCLK_1 I5/S I5/S I5/PD/S I5/PD I5/PD VCC3R3 GND3R3 V18F P P P VCCK P VCC3IO GND P P VCC33A_H GND33A_H VCC33A_PLL GND33A_PLL VCC3A3 GND3A3 VCC18A GND18A P P P P P P P P RXCLK I5/PD RXDV I5/PD RXD [3:0] I5/PD CRS I5/PD COL I5/PD 35 General Purpose Input/ Output Pin 1. This pin is default as input pin after power-on reset. This pin is also for Default WOL Ready Mode setting; please refer to section 2.3 Settings. 36 General Purpose Input/ Output Pin 0 or PME (Power Management Event). This pin is default as input pin after power-on reset. GPIO_0 also can be defined as PME output to indicate wake up event detected. Please refer to section 2.3 Settings. 37 UART_RX or SPI_MISO. This is a multi-function pin determined by EEPROM Flag [1] setting. Please refer to section 2.3 Settings. 38 UART_TX or SPI_MOSI. This is a multi-function pin determined by EEPROM Flag [1] setting. Please refer to section 2.3 Settings. 39 I2C_SDA or SPI_SS. This is a multi-function pin determined by EEPROM Flag [1] setting. Please refer to section 2.3 Settings. 40 I2C_SCLK or SPI_SCLK. This is a multi-function pin determined by EEPROM Flag [1] setting. Please refer to section 2.3 Settings. 28 USB Speed indicator: When USB bus is in Full speed, this pin drives high continuously. When USB bus is in High speed, this pin drives low continuously. This pin drives high and low in turn (blinking) to indicate TX data transfer going on whenever the host controller sends bulk out data transfer. 54 Test pin. For normal operation, user should connect to ground. 53 Test pin. For normal operation, user should connect to ground. 50 Test pin. For normal operation, user should keep this pin NC. 49 Test pin. For normal operation, user should keep this pin NC. 48 Test pin. For normal operation, user should keep this pin NC. On-chip Regulator Pins 11 3.3V Power supply to on-chip 3.3V-to-1.8V voltage regulator. 12 Ground pin of on-chip 3.3V-to-1.8V voltage regulator. 10 1.8V voltage output of on-chip 3.3V-to-1.8V voltage regulator. Power and Ground Pins 13, 14, 27, 33, Digital Core Power. 1.8V. 41, 57, 66, 21, 51, 65 Digital I/O Power. 3.3V. 15, 16, 29, 42, Digital Ground. 55, 56, 76 69 Analog Power for USB transceiver. 3.3V. 70 Analog Ground for USB transceiver. 74 Analog Power for USB PLL. 3.3V. 75 Analog Ground for USB PLL. 2 Analog Power for Ethernet PHY bandgap. 3.3V. 3 Analog Ground for Ethernet PHY. 6, 77 Analog Power for Ethernet PHY and 25Mhz crystal oscillator. 1.8V. 9, 80 Analog Ground for Ethernet PHY and 25Mhz crystal oscillator. External Media Interface: MAC Mode with MII Interface 17 Receive Clock. RXCLK is received from PHY to provide timing reference for the transfer of RXD [3:0] and RXDV signals on receive direction of MII interface. 18 Receive Data Valid. RXDV is asserted high when valid data is present on RXD [3:0]. It is driven synchronously with respect to RXCLK by PHY. 19, 20, Receive Data. RXD [3:0] is driven synchronously with respect to RXCLK 22, 23 by PHY. 31 Carrier Sense. CRS is asserted high asynchronously by the PHY when either transmit or receive medium is non-idle. 32 Collision. COL is driven high by PHY when the collision is detected. 17 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller TXCLK I5/PD TXEN O3 TXD [3:0] O3 MDC O3/PD MDIO B5/PU TXCLK TXEN TXD [3:0] CRS COL RXER RXCLK RXDV RXD [3:0] MDC MDIO REFCLK_I 63 Transmit Clock. TXCLK is received from PHY to provide timing reference for the transfer of TXD [3:0] and TXEN signals on transmit direction of MII interface. 64 Transmit Enable. TXEN is asserted high to indicate a valid TXD [3:0]. It is transitioned synchronously with respect to the rising edge of TXCLK. 59, 60, Transmit Data. TXD [3:0] is transitioned synchronously with respect to 61, 62 the rising edge of TXCLK. Note TXD [3:2] are also used as Chip Operation Mode selection pins; please refer to section 2.3 Settings. 44 Station management clock output to PHY. All data transferred on MDIO are synchronized to the rising edge of this clock. The frequency of MDC is 1.5MHz. 43 Station management data input/output. Serial data input/output transferred from/to the PHYs. The transfer protocol conforms to the IEEE 802.3u MII spec. External Media Interface: PHY Mode with Reverse-MII Interface O3/T 17 Transmit Clock. This clock is provided to supply to the TX_CLK of externally connected Ethernet MAC device with MII. This pin is tri-stated in isolate mode. I5/PD 18 Transmit enable. TXEN is asserted high to indicate a valid TXD [3:0]. It should be driven synchronously with respect to the rising edge of TXCLK by the externally connected Ethernet MAC device with MII. I5/PD 19, 20, Transmit Data. TXD [3:0] should be driven synchronously with respect to 22, 23 the rising edge of TXCLK by the externally connected Ethernet MAC device with MII. O3/PD/T 31 Carrier Sense. CRS is asserted high by AX88172A when RXDV is asserted high in Reverse-MII mode. This pin is tri-stated in isolate mode. O3/PD/T 32 Collision. COL is always driven low because AX88172A is operating in 100M/full-duplex mode internally in Reverse-MII mode. This pin is tri-stated in isolate mode. O3/PD/T 34 Receive Error. RXER is always driven low by AX88172A in Reverse-MII mode. This pin is tri-stated in isolate mode. O3/T 63 Receive clock. This clock is provided to supply to the RX_CLK of externally connected Ethernet MAC device with MII. This pin is tri-stated in isolate mode. O3/T 64 Receive Data Valid. RXDV is asserted high when valid data is present on RXD [3:0]. It is transitioned synchronously with respect to RXCLK from AX88172A to the externally connected Ethernet MAC device with MII. This pin is tri-stated in isolate mode. O3/T 59, 60, Receive Data. RXD [3:0] is transitioned synchronously with respect to 61, 62 RXCLK from AX88172A to the externally connected Ethernet MAC device with MII. Note that RXD [3:2] are also used as Chip Operation Mode selection pins. Please refer to section 2.3 Settings. These pins are tri-stated in isolate mode. I5/PD 44 Station Management clock input from the externally connected Ethernet MAC device. All data transferred on MDIO are synchronized to the rising edge of this clock. B5/PU 43 Station Management Data. Serial data input/output transferred from/to the externally connected MAC device. The transfer protocol should conform to the IEEE 802.3u MII spec. External Media Interface: PHY Mode with Reverse-RMII Interface I5 17 50Mhz +/-50ppm Reference clock input for RMII receive, transmit and control signals. If externally connected Ethernet MAC device with RMII can’t provide 50Mhz Reference clock to AX88172A, then user can connect this pin to REFCLK_O and use REFCLK_O to supply clock to the externally connected Ethernet MAC device at the same time. 18 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller TXEN I5/PD 18 TXD [1:0] I5/PD 22, 23 NC NC RXER I5/PD O3/PD O3/PD/T 19, 20 31, 32 34 MIS_1 I5/PD 59 MIS_0 I5/PD 60 O3 63 CRSDV O3/T 64 RXD [1:0] O3/T 61, 62 MDC I5/PD 44 MDIO B5/PU 43 REFCLK_O Transmit Enable from the externally connected Ethernet MAC device with RMII. Transmit Data from the externally connected Ethernet MAC device with RMII. NC NC Receive Error. RXER is always driven low by AX88172A in Reverse-RMII mode. This pin is tri-stated in isolate mode. External Media Interface Select 1. This is used as Chip Operation Mode selection pin; please refer to section 2.3 Settings. External Media Interface Select 0. This is used as Chip Operation Mode selection pin; please refer to section 2.3 Settings. 50Mhz Reference clock output. If the externally connected Ethernet MAC device can’t supply 50Mhz reference clock, this clock can be used to supply to the REF_CLK of externally connected Ethernet MAC device with RMII and the REFCLK_I of this chip. Carrier Sense and Receive Data Valid to the externally connected Ethernet MAC device with RMII. This pin is tri-stated in isolate mode. Receive Data to the externally connected Ethernet MAC device with RMII. These pins are tri-stated in isolate mode. Station Management clock input from the externally connected Ethernet MAC device. All data transferred on MDIO are synchronized to the rising edge of this clock. Station Management Data. Serial data input/output transferred from/to the externally connected MAC device. The transfer protocol should conform to the IEEE 802.3u MII spec. 19 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 2.3 Hardware Setting For Operation Mode And Multi-Function Pins Please contact ASIX for receiving “AX88x72A Full Datasheet” which contains detailed description of section 2.3 and section 3, 4, 5, 6, 7, 8. 3.0 Function Description 3.1 USB Core and Interface 3.2 10/100M Ethernet PHY 3.3 MAC Core 3.4 Operation Mode 3.5 Station Management (STA) 3.6 Memory Arbiter 3.7 USB to Ethernet Bridge 3.8 Serial EEPROM Loader 3.9 General Purpose I/O 3.10 Serial Interface Controller 3.11 Clock Generation 3.12 Reset Generation 3.13 Voltage Regulator 4.0 Serial EEPROM Memory Map 4.1 Detailed Description 5.0 USB Configuration Structure 5.1 USB Configuration 5.2 USB Interface 5.3 USB Endpoints 6.0 USB Commands 6.1 USB Standard Commands 6.2 USB Vendor Commands 6.2.1 Detailed Register Description 6.2.2 Command Block Wrapper for Serial Interface 6.2.2.1 UART controller 20 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 6.2.2.2 I2C controller 6.2.2.3 SPI controller 6.3 Interrupt Endpoint 7.0 Embedded Ethernet PHY Register Description 7.1 PHY Register Detailed Description 7.1.1 7.1.2 7.1.3 7.1.4 7.1.5 7.1.6 7.1.7 Basic Mode Control Register (BMCR) Basic Mode Status Register (BMSR) PHY Identifier Register 1 PHY Identifier Register 2 Auto Negotiation Advertisement Register (ANAR) Auto Negotiation Link Partner Ability Register (ANLPAR) Auto Negotiation Expansion Register (ANER) 8.0 Station Management Registers in PHY/Dual-PHY Mode 8.1 PHY/Dual-PHY Mode Detailed Register Description 8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.1.7 8.1.8 PHY Mode Basic Mode Control Register (PM_BMCR) PHY Mode Basic Mode Status Register (PM_BMSR) PHY Mode PHY Identifier Register 1 PHY Mode PHY Identifier Register 2 PHY Mode Auto Negotiation Advertisement Register (PM_ANAR) PHY Mode Auto Negotiation Link Partner Ability Register (PM_ANLPAR) PHY Mode Auto Negotiation Expansion Register (PM_ANER) PHY Mode Control Register (PM_Control) 21 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.0 Electrical Specifications 9.1 DC Characteristics 9.1.1 Absolute Maximum Ratings Symbol VCCK Parameter Digital core power supply Rating - 0.3 to 2.16 Unit V VCC18A Analog Power. 1.8V - 0.3 to 2.16 V Power supply of 3.3V I/O Power supply of on-chip voltage regulator Analog Power 3.3V for Ethernet PHY bandgap Analog Power 3.3V for USB PLL. Analog Power 3.3V for USB TX and RX Input voltage of 1.8V I/O Input voltage of 3.3V I/O - 0.3 to 4 - 0.3 to 4 - 0.3 to 3.8 - 0.3 to 4 - 0.3 to 4 - 0.3 to 2.16 - 0.3 to 4.0 V V V V V V V Input voltage of 3.3V I/O with 5V tolerant - 0.3 to 5.8 V VCC3IO VCC3R3 VCC3A3 VCC33A_PLL VCC33A_H VIN18 VIN3 TSTG Storage temperature - 40 to 150 ℃ IIN DC input current 20 mA IOUT Output short circuit current 20 mA Note: Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to the optional sections of this datasheet. Exposure to absolute maximum rating condition for extended periods may affect device reliability. 9.1.2 Recommended Operating Condition Symbol VCCK VCC18A VCC3R3 VCC3IO VCC33A_H VCC33A_PLL VCC3A3 VIN18 VIN3 Tj Ta Parameter Digital core power supply Analog core power supply Power supply of on-chip voltage regulator Power supply of 3.3V I/O Analog Power 3.3V for USB TX and RX Analog Power 3.3V for USB PLL. Analog power supply for bandgap Input voltage of 1.8 V I/O Input voltage of 3.3 V I/O Input voltage of 3.3 V I/O with 5V tolerance Commercial junction operating temperature Commercial operating temperature Min 1.62 1.62 2.97 2.97 2.97 2.97 2.97 0 0 0 0 0 Thermal Characteristics Symbol Parameter Thermal resistance of junction LQFP 64(AX88772A) ΘJC to case TQFP 80(AX88172A) Thermal resistance of junction Still air,LQFP 64(AX88772A) ΘJA to ambient Still air,TQFP 80(AX88172A) 22 Typ 1.8 1.8 3.3 3.3 3.3 3.3 3.3 1.8 3.3 3.3 25 - Max 1.98 1.98 3.63 3.63 3.63 3.63 3.63 1.98 3.63 5.25 125 70 Unit V V V V V V V V V V ℃ ℃ Rating 13.1 27.5 45.1 55.2 Unit °C/W °C/W °C/W °C/W ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.1.3 Leakage Current and Capacitance Symbol IIN IOZ CIN COUT Parameter Input current Tri-state leakage current Input capacitance Conditions No pull-up or pull-down Output capacitance Min -10 -10 - Typ ±1 ±1 2.2 Max 10 10 - Unit μA μA pF - 2.2 - pF CBID Bi-directional buffer capacitance 2.2 pF Note: The capacitance listed above does not include pad capacitance and package capacitance. One can estimate pin capacitance by adding a pad capacitance of about 0.5pF to the package capacitance. 9.1.4 DC Characteristics of 3.3V I/O Pins Symbol VCC3IO Tj Vil Vih Vt VtVt+ Vol Voh Rpu Rpd Iin IOZ Parameter Conditions Power supply of 3.3V I/O 3.3V I/O Junction temperature Input low voltage LVTTL Input high voltage Switching threshold Schmitt trigger negative going LVTTL threshold voltage Schmitt trigger positive going threshold voltage Output low voltage Iol = 8mA Output high voltage Ioh = -8mA Input pull-up resistance Vin = 0 Input pull-down resistance Vin = VCC3IO Input leakage current Vin = VCC3IO or 0 Input leakage current with pull-up Vin = 0 resistance Input leakage current with Vin = VCC3IO pull-down resistance Tri-state output leakage current 23 Min Typ 2.97 3.3 0 25 2.0 1.5 0.8 1.1 Max 3.63 125 0.8 - Unit V ℃ V V V V - 1.6 2.0 V 2.4 40 40 -10 -15 75 75 ±1 -45 0.4 190 190 10 -85 V V KΩ KΩ μA μA 15 45 85 μA -10 ±1 10 μA ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.1.5 DC Characteristics of 3.3V with 5V Tolerance I/O Pins Symbol VCC3IO Tj Vil Vih Vt VtVt+ Vol Voh Rpu Rpd Iin IOZ Parameter Conditions Power supply of 3.3V I/O 3.3V I/O Junction temperature Input low voltage LVTTL Input high voltage Switching threshold Schmitt trigger negative going LVTTL threshold voltage Schmitt trigger positive going threshold voltage Output low voltage Iol = 8mA Output high voltage Ioh = -8mA Input pull-up resistance Vin = 0 Input pull-down resistance Vin = VCC3IO Input leakage current Vin = 5.5V or 0 Input leakage current with pull-up Vin = 0 resistance Input leakage current with Vin = VCC3IO pull-down resistance Tri-state output leakage current Vin = 5.5V or 0 24 Min Typ 2.97 3.3 0 25 2.0 1.5 0.8 1.1 Max 3.63 125 0.8 - Unit V ℃ V V V V - 1.6 2.0 V 2.4 40 40 0.4 190 190 -15 75 75 ±5 -45 -85 V V KΩ KΩ μA μA 15 45 85 μA ±10 μA ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.1.6 DC Characteristics of Voltage Regulator Symbol VCC3R3 Tj Iload V18F Description Power supply of on-chip voltage regulator. Operating junction temperature. Driving current. Conditions Cout ESR Typ Max Unit 3.3 3.6 V 0 25 125 ℃ Normal operation Standby mode enabled Output voltage of on-chip VCC3R3 = 3.3V voltage regulator. Dropout voltage. △V18F = -1%, Iload = 10mA Line regulation. VCC3R3 = 3.3V, Iload = 50mA 1.71 1.8 240 30 1.89 mA mA V - 0.1 0.2 0.2 0.4 V %/V VCC3R3 = 3.3V, 1mA ≦ Iload ≦ 240mA VCC3R3 = 3.3V,-40℃ ≦ Tj ≦ 125℃ VCC3R3 = 3.3V VCC3R3 = 3.3V Quiescent current at 125 VCC3R3 = 3.3V ℃. VCC3R3 = 3.3V Output external capacitor. Allowable effective series resistance of external capacitor. - 0.02 0.05 %/mA Vdrop △V18F (△VCC3R3 x V18F) Load regulation. △V18F (△Iload x V18F) Temperature coefficient. △V18F △Tj Iq_25℃ Quiescent current at 25 ℃. Iq_125℃ Min 3.0 25 0.1 - +/-0.2 +/-0.5 mV/ ℃ 70 100 μA 100 125 μA 85 115 μA 125 170 μA 1 μF 0.5 1 Ω ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.2 Power Consumption Symbol IVCCK IVCC18A IVCC3IO IVCC33A IVCCK IVCC18A IVCC3IO IVCC33A IVCCK IVCC18A IVCC3IO IVCC33A IVCCK VCC18A IVCC3IO IVCC33A IVCCK IVCC18A IVCC3IO IVCC33A IVCCK Description Current Consumption of VCCK Current Consumption of VCC18A Current Consumption of VCC3IO Current Consumption of VCC33A_H + VCC33A_PLL + VCC33A_PLL Current Consumption of VCCK Current Consumption of VCC18A Current Consumption of VCC3IO Current Consumption of VCC33A_H + VCC33A_PLL + VCC33A_PLL Current Consumption of VCCK Current Consumption of VCC18A Current Consumption of VCC3IO Current Consumption of VCC33A_H + VCC33A_PLL + VCC33A_PLL Current Consumption of VCCK Current Consumption of VCC18A Current Consumption of VCC3IO Current Consumption of VCC33A_H + VCC33A_PLL + VCC33A_PLL Current Consumption of VCCK Current Consumption of VCC18A Current Consumption of VCC3IO Current Consumption of VCC33A_H + VCC33A_PLL + VCC33A_PLL Current Consumption of VCCK IVCC18A IVCC3IO Current Consumption of VCC18A Current Consumption of VCC3IO IVCC33A Current Consumption of VCC33A_H + VCC33A_PLL + VCC33A_PLL Current Consumption of VCCK Current Consumption of VCC18A Current Consumption of VCC3IO Current Consumption of VCC33A_H + VCC33A_PLL + VCC33A_PLL Power consumption of AX88772A/AX88172A chip only IVCCK IVCC18A IVCC3IO IVCC33A IDEVICE Conditions Operating at Ethernet 100Mbps full duplex mode and USB High speed mode Typ 47.5 39.3 16.6 35.4 Max Unit mA mA mA mA Operating at Ethernet 100Mbps full duplex mode and USB Full speed mode 44.3 39.3 12.9 28.7 mA mA mA mA Operating at Ethernet 10Mbps full duplex mode and USB High speed mode 19.3 6.3 8.3 38.8 mA mA mA mA Operating at Ethernet 10Mbps full duplex mode and USB Full speed mode 14.9 6.2 4.9 32.3 mA mA mA mA Suspend (the embedded Ethernet PHY is powered down) 2.0 49.3 0.7 0.2 μA μA mA mA 19 mA 3.4 8.5 mA mA 30.9 mA 22 3.4 11.5 36.9 mA mA mA mA AX88172A in USB Full speed, Rev-MII operation and internal PHY power save (BMCR[11] bit = 1) AX88172A in USB High speed, Rev-MII operation and internal PHY power save (BMCR[11] bit = 1) 1.8V 3.3V Min 100 70 mA mA 220 mA (Excluding VCC3R3) ISYSTEM Power consumption of AX88x72A demo board Table 3 Total of 3.3V (Including VCC3R3 regulator supplies 1.8V to VCCK and VCC18A) : Power consumption 26 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.3 Power-up Sequence At power-up, the AX88772A/AX88172A requires the VCC3R3/VCC3IO/VCC3A3/VCC33A_H/ VCC33A_PLL power supply to rise to nominal operating voltage within Trise3 and the V18F/VCCK/VCC18A power supply to rise to nominal operating voltage within Trise2. Trise3 3.3V VCC3R3/VCC3IO/VCC3A3 /VCC33A_H/ VCC33A_PLL 0V Tdelay32 Trise2 1.8V V18F/VCCK/VCC18A 0V Symbol Trise3 Trise2 Tdelay32 Parameter 3.3V power supply rise time 1.8V power supply rise time 3.3V rise to 1.8V rise time delay Condition From 0V to 3.3V From 0V to 1.8V 27 Min 0.5 -5 Typ - Max 10 10 5 Unit ms ms ms ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.4 AC Timing Characteristics Notice that the following AC timing specifications for output pins are based on CL (Output load)=50pF. 9.4.1 Clock Timing XTL12P TP_XTL12P TL_XTL12P TH_XTL12P VIH VIL Symbol TP_XTL12P TH_XTL12P TL_XTL12P Parameter XTL12P clock cycle time XTL12P clock high time XTL12P clock low time Condition Min - Typ 83.33 41.6 41.6 Max - Unit ns ns ns Typ 40.0 20.0 20.0 Max - Unit ns ns ns XTL25P TP_XTL25P TL_XTL25P TH_XTL25P VIH VIL Symbol TP_XTL25P TH_XTL25P TL_XTL25P Parameter XTL25P clock cycle time XTL25P clock high time XTL25P clock low time Condition Min - 9.4.2 Reset Timing XTL12P RESET_N Trst Symbol Trst Description Reset pulse width after XTL12P is running Min 60 Typ - Max Unit 120000 XTL12P clock cycle* *: If the system applications require using hardware reset pin, RESET_N, to reset AX88772A/AX88172A during device initialization or normal operation after VBUS pin is asserted, the above timing spec (Min=5μs, Max=10ms) of RESET_N should be met. 28 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.4.3 Serial EEPROM Timing T ch T cl T cl k E E CK T dv T od E E DIO (a s O UT P UT ) T l cs T scs T hc s E E CS Th Ts E E DIO (a s INP UT ) Symbol Tclk Tch Tcl Tdv Tod Tscs Thcs Tlcs Ts Th Description EECK clock cycle time EECK clock high time EECK clock low time EEDIO output valid to EECK rising edge time EECK rising edge to EEDIO output delay time EECS output valid to EECK rising edge time EECK falling edge to EECS invalid time Minimum EECS low time EEDIO input setup time EEDIO input hold time Min 2560 2562 2560 7680 23039 20 0 29 Typ 5120 2560 2560 - Max - Unit ns ns ns ns ns ns ns ns ns ns ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.4.4 MII Timing Ttch Ttcl Ttcl k TXCLK Tts Tth TXEN / TXD[3:0] Symbol Ttclk Ttch Ttcl Tts Tth Description Min 23.0 7.0 TXCLK clock cycle time *1 TXCLK clock high time *2 TXCLK clock low time *2 TXD [3:0], TXEN setup to rising TXCLK TXD [3:0], TXEN hold from rising TXCLK Trch Trcl Typ 40.0 20.0 20.0 - Max - Unit ns ns ns ns ns Max - Unit ns ns ns ns ns Trclk RXCLK Trs Trh RXDV / RXD[3:0] Symbol Trclk Trch Trcl Trs Trh Description Min 5.0 3.5 RXCLK clock cycle time *1 RXCLK clock high time *2 RXCLK clock low time *2 RXD [3:0], RXDV setup to rising RXCLK RXD [3:0], RXDV hold from rising TXCLK Typ 40.0 20.0 20.0 - *1: For 10Mbps, the typical value of Ttclk and Trclk shall scale to 400ns. *2: For 10Mbps, the typical value of Ttch, Ttcl, Trch, and Trcl shall scale to 200ns. 30 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.4.5 Station Management Timing Tch Tcl Tclk MDC Tod MDIO(asOUTPUT) Ts Th MDIO(asINPUT) MAC mode with MII: MDC=Output Symbol Description Tclk MDC clock cycle time Tch MDC clock high time Tcl MDC clock low time Tod MDC clock rising edge to MDIO output delay Ts MDIO data input setup time Th MDIO data input hold time Min 0.5 125 0 Typ 640 320 320 - Max - Unit ns ns ns Tclk ns ns PHY/Dual-PHY mode with Reverse-MII/RMII: MDC=Input Symbol Description Min Tclk MDC clock cycle time Tch MDC clock high time Tcl MDC clock low time Tod MDC clock rising edge to MDIO output delay 0 Ts MDIO data input setup time 10 Th MDIO data input hold time 10 Typ 320 160 160 - Max 300 - Unit ns ns ns ns ns ns 31 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.4.6 Reverse-MII Timing Tch Tcl Tclk RXCLK Trs Trh RXD[3:0] RXDV Symbol Tclk Tch Tcl Trs Trh Description Min 10.0 10.0 Clock cycle time Clock high time Clock low time RXD [3:0], RXDV setup to rising RXCLK RXD [3:0], RXDV hold from rising RXCLK Tch Tcl Typ 40.0 20.0 20.0 - Max - Unit ns ns ns ns ns Tclk TXCLK Tts Tth TXD[3:0] TXEN Symbol Tts Tth Description Min 11.0 2.0 TXD [3:0], TXEN setup to rising TXCLK TXD [3:0], TXEN hold from rising TXCLK 32 Typ - Max - Unit ns ns ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.4.7 Reverse-RMII Timing Tref_c l Tref_ch Tref_clk REFCLK_I Tref_rs Tref_rh RXD[1:0] CRSDV Symbol Tref_clk Tref_ch Tref_cl Tref_rs Tref_rh Description Clock cycle time Clock high time Clock low time RXD [1:0], CRSDV setup to rising REFCLK_I RXD [1:0], CRSDV hold from rising REFCLK_I Min 4.0 2.0 Typ 20.0 10.0 10.0 - Max - Unit ns ns ns ns ns Max - Unit ns ns Tref_c l Tref_ch Tref_clk REFCLK_I Tref_ts Tref_th TXD[1:0] TXEN Symbol Tref_ts Tref_th Description TXD [1:0], TXEN setup to rising REFCLK_I TXD [1:0], TXEN hold from rising REFCLK_I 33 Min 4.0 2.0 Typ - ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.4.8 I2C Interface Timing I2C Master Controller Timing table: Symbol Parameter Fclk Thigh Tlow Tsu_sta Thd_sta I2C_SCL clock frequency. High period of the I2C_SCL clock. Low period of the I2C_SCL clock. Setup time for a repeated START (Sr) condition. Hold time of (repeated) START (S) condition. After this period, the first clock pulse is generated Tsu_dat Data Setup time. Thd_dat Data Hold time. Tsu_sto Data Setup time for STOP (P) condition. Tbuf Bus free time between a STOP and START condition. Standard mode (Typ) 100 4.0 6.0 4.0 4.0 Fast mode (Typ) 400 1.0 1.5 1.0 1.0 2.0 4.0 4.0 0.5 1.0 1.0 Note 1 Unit KHz µs µs µs µs µs µs µs Note 1: It will be much greater than 22us because several factors can influence this parameter such as USB system utilization, the CBW structure, and High/Full speed, etc. I2C Slave Controller Timing Table: Symbol Parameter Fclk I2C_SCL clock frequency. Thigh High period of the I2C_SCL clock in Fast mode. High period of the I2C_SCL clock in Standard mode. Tlow Low period of the I2C_SCL clock. Tsu_sta Setup time for a repeated START (Sr) condition. Thd_sta Hold time of (repeated) START (S) condition. After this period, the first clock pulse is generated Tsu_dat Data Setup time. Thd_dat Data Hold time. Tsu_sto Data Setup time for STOP (P) condition. Tbuf Bus free time between a STOP and START condition. Min 0.6 4.0 0.4 1 Typ - Max 390 - 3 - - 3 0.4 1 - - - Unit KHz µs µs µs Tsys_clk (Note 2) Tsys_clk Tsys_clk µs Tsys_clk Note 2: Tsys_clk =33.33ns for 30MHz operating system clock. 34 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.4.9 SPI Interface Timing Note: Above diagram only shows setup and hold time relationship of SPI pins in Mode 0. For the remaining 3 modes, clock polarity is reversed. SPI Master Controller Timing Table: Symbol Description Fclk SPI_SCLK clock frequency. Min - Typ Fsys_clk/ (SPIBRR+1)*2 Max 5 Unit MHz (Note 3) Tl Setup time of SPI_SS to the first SPI_SCLK edge. - 0.5 - Th Tdly Hold time of SPI_SS after the last SPI_SCLK edge. SPI_MOSI data valid time after SPI_SCLK edge. - 0.5 - 1 Dsu Dhd tl SPI_MISO data setup time before SPI_SCLK edge. SPI_MISO data hold time after SPI_SCLK edge. Minimum idle time between transfers (minimum SPI_SS high time). Internal time base period. 2 4 - - Tclk (Note 3) Tclk Tsys_clk (Note 4) Tsys_clk Tsys_clk - Tclk Note 5 - 0.5 Note 3: Fsys_clk is the operating system clock frequency 30Mhz. The SPIBRR is SPI Baud Rate Register. Tclk = 1/Fclk. Note 4: Tsys_clk =1/ Fsys_clk =33.33 ns. Note 5: It will be much greater than 22us because several factors can influence this parameter, such as USB system utilization, the CBW structure, and High/Full speed ,etc. 35 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller SPI Slave Controller Timing Table: Symbol Description Fclk SPI_SCLK clock frequency. Tdly SPI_MISO data valid time after SPI_SCLK edge. Dsu SPI_MOSI data setup time before SPI_SCLK edge. Dhd SPI_MOSI data hold time after SPI_SCLK edge. SSsu SPI_SS setup time before SPI_SCLK edge. SShd SPI_SS hold time after SPI_SCLK edge. SSidle SPI_SS negation to next SPI_SS active time 36 Min 1 3 2 4 2 Typ - Max Unit 2 MHz 3 Tsys_clk Tsys_clk Tsys_clk Tsys_clk Tsys_clk Tsys_clk ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.4.10 10/100M Ethernet PHY Interface Timing +Vtxov +Vtxa Tr: from 10% to 90% 0V 10/100M Ethernet PHY Transmitter Waveform and Spec: Symbol Description Condition Peak-to-peak differential output voltage 10BASE-T mode Vtxa *2 Peak-to-peak differential output voltage 100BASE-TX mode Tr / Tf Signal rise / fall time 100BASE-TX mode Output jitter 100BASE-TX mode, scrambled idle signal Vtxov Overshoot 100BASE-TX mode Min 4.4 1.9 3 - Typ Max Units 5 5.6 V 2 2.1 V 4 5 ns 1.4 ns - 5 % 10/100M Ethernet PHY Receiver Spec: Symbol Description Receiver input impedance Differential squelch voltage Common mode input voltage Maximum error-free cable length Condition 10BASE-T mode 37 Min Typ Max Units 10 300 2.97 100 400 3.3 - KΩ mV V meter 500 3.63 - ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 9.4.11 USB Transceiver Interface Timing VCC33A_H/ VCC33A_PLL= 3.0 ~ 3.6 V. Static Characteristic for Analog I/O Pins (DP/DM): Symbol Parameter Conditions Min USB 2.0 Transceiver (HS) Input Levels (Differential Receiver) High speed differential input 300 VHSDIFF |VI (DP) –VI (DM)| sensitivity Measured at the connection as Typ Max Unit - - mV -50 - 500 mV - - 100 mV 200 - - mV -10 - 10 mV -10 - 10 mV -360 - 400 mV 700 - 1100 mV -900 - -500 mV 40.5 45 3.0 - 3.6 V 0.2 - - V 0.8 - 2.5 V 0.8 - 2.0 V Low-level output voltage 0 - 0.3 V High-level output voltage 2.8 - 3.6 V an application circuit. VHSCM VHSSQ VHSOI VHSOL VHSOH VCHIRPJ VCHIRPK High speed data signaling common mode voltage range High speed squelch detection threshold Squelch detected No squelch detected Output levels (differential) High speed idle level output voltage High speed low level output voltage High speed high level output voltage Chirp-J output voltage Chirp-K output voltage Resistance Equivalent resistance used as internal chip Termination RDRV Driver output impedance VTERM Termination voltage for pull-up resistor on pin RPU USB 1.1 Transceiver (FS/LS) Input Levels (Differential Receiver) Differential input sensitivity |VI (DP) –VI (DM)| VDI VCM VSE Differential common mode voltage Input Levels (Single-Ended Receiver) Single ended receiver threshold 49.5 Ohm Output levels VOL VOH 38 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller Dynamic Characteristic for Analog I/O Pins (DP/DM): Symbol Parameter Conditions Driver Characteristic High-Speed Mode High-speed differential rise time tHSR tHSF High-speed differential fall time Full-Speed Mode CL=50pF; 10 to 90% of tFR Rise time of DP/DM tFF Fall time of DP/DM CL=50pF; 90 to 10% of Differential rise/fall time Excluding the first transition from idle mode tFRMA VCRS Min Typ Max Unit 500 - - ps 500 - - ps 4 - 20 ns 4 - 20 ns 90 - 110 % 1.3 - 2.0 V |VOH - VOL| |VOH - VOL| matching (tFR / tFF) Output signal crossover voltage Excluding the first transition from idle mode Driver Timing High-Speed Mode Driver waveform requirement See eye pattern of template 1 VI, FSE 0, OE to DP, DN Propagation delay Data source jitter and receiver jitter tolerance tPLH(rcv) tPHL (rcv) Receiver propagation delay (DP; DM to RCV) tPLH(single) tPHL(single) Receiver propagation delay (DP; DM to VOP, VON) Follow template 1 described in USB rev 2.0 spec. (http://www.usb.org/developers/docs ) Full-Speed Mode For detailed description of VI, 15 ns FSE 0 and OE, please refer to USB rev 1.1specification. Receiver Timing High-Speed Mode See eye pattern of template 4 Follow template 4 described in USB rev 2.0 spec. (http://www.usb.org/developers/docs ) Full-Speed Mode For detailed description of 15 ns RCV, please refer to USB rev (Note) 1.1specification. 15 ns (Note) Note: Full-Speed Timing diagram 39 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 10.0 Package Information 10.1 AX88772A 64-pin LQFP package A A2 A1 L L1 D Hd He E pin 1 e b θ Symbol Millimeter A1 Min 0.05 Typ - Max 0.15 A2 1.35 1.40 1.45 A - - 1.60 b 0.13 0.18 0.23 D 7.00 E 7.00 e - 0.40 Hd 9.00 He 9.00 - L 0.45 0.60 0.75 L1 - 1.00 REF - θ 0° 3.5° 7° 40 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 10.2 AX88172A 80-pin TQFP package A A2 A1 L L1 D Hd He E pin 1 e b θ Symbol Millimeter A1 Min 0.05 Typ - Max 0.15 A2 0.95 1.00 1.05 A - - 1.20 b 0.13 0.16 0.23 D 10.00 E 10.00 e - 0.4 BSC Hd 12.00 He 12.00 - L 0.45 0.60 0.75 L1 - 1.00 REF - θ 0° 3.5° 7° 41 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 11.0 Ordering Information Part Number AX88772ALF AX88172ATF Description AX88772A: Product Name (64 pin). L: LQFP Package. F: Lead Free. AX88172A: Product Name (80 pin). T: TQFP Package. F: Lead Free. 42 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 12.0 Revision History Revision Date Comment V0.7 V1.0 2007/8/13 2007/11/21 V1.1 2007/12/24 Initial Release. 1. Update the power consumption information and add IDEVICE and ISYSTEM in Section 9.2. 2. Move the Thermal Characteristics information from Section 9.2 to Section 9.1.2 and update the Thermal Characteristics information. 3. Update the Tj junction operating temperature information in Section 9.1.2, 9.1.4, 9.1.5 and 9.1.6. 4. Update the Reset Timing information in Section 9.4.2. 1. Update some information in Section 9.1.6. 43 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller APPENDIX A. Default WOL Ready Mode Please contact ASIX for receiving “AX88x72A Full Datasheet” which contains detailed description of Appendix A. 44 ASIX ELECTRONICS CORPORATION AX88772A/AX88172A Low-pin-count USB 2.0 to 10/100M Fast Ethernet Controller 4F, No.8, Hsin Ann Rd., Hsinchu Science Park, Hsinchu, Taiwan, R.O.C. TEL: +886-3-5799500 FAX: +886-3-5799558 Email: [email protected] Web: http://www.asix.com.tw 45 ASIX ELECTRONICS CORPORATION