MM54HC76/MM74HC76 Dual J-K Flip-Flops with Preset and Clear General Description The 54HC/74HC logic family is functionally as well as pinout compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground. These high speed (30 MHz minimum) J-K Flip-Flops utilize advanced silicon-gate CMOS technology to achieve, the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. Each flip-flop has independent J, K, PRESET, CLEAR, and CLOCK inputs and Q and Q outputs. These devices are edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of the clock and accomplished by a low logic level on the corresponding input. Features Connection and Logic Diagrams Truth Table Y Y Y Y Y Typical propagation delay: 16 ns Wide operating voltage range Low input current: 1 mA maximum Low quiescent current: 40 mA maximum (74HC Series) High output drive: 10 LS-TTL loads Dual-In-Line Package Inputs Outputs PR CLR CLK J L Q L H L H H H H H H L L H H H H H X X X X X X L H L H X X X X L L H H X H L L H L* L* Q0 Q0 H L L H TOGGLE Q0 Q0 v v v v H Q *This is an unstable condition, and is not guaranteed TL/F/5074 – 1 Top View Order Number MM54HC76 or MM74HC76 TL/F/5074 – 3 TL/F/5074 – 2 (1 of 2) C1995 National Semiconductor Corporation TL/F/5074 RRD-B30M105/Printed in U. S. A. MM54HC76/MM74HC76 Dual J-K Flip-Flops with Preset and Clear January 1988 Absolute Maximum Ratings (Notes 1 & 2) Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) b 0.5 to a 7.0V Supply Voltage (VCC) b 1.5 to VCC a 1.5V DC Input Voltage (VIN) b 0.5 to VCC a 0.5V DC Output Voltage (VOUT) g 20 mA Clamp Diode Current (IIK, IOK) g 25 mA DC Output Current, per pin (IOUT) g 50 mA DC VCC or GND Current, per pin (ICC) b 65§ C to a 150§ C Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) 600 mW S.O. Package only 500 mW Lead Temp. (TL) (Soldering 10 seconds) 260§ C Operating Temp. Range (TA) MM74HC MM54HC Min 2 Max 6 Units V 0 VCC V b 40 b 55 a 85 a 125 §C §C 1000 500 400 ns ns ns Input Rise or Fall Times (tr, tf) VCC e 2.0V VCC e 4.5V VCC e 6.0V DC Electrical Characteristics (Note 4) Symbol Parameter Conditions TA e 25§ C VCC 74HC TA eb40 to 85§ C Typ 54HC TA eb55 to 125§ C Units Guaranteed Limits VIH Minimum High Level Input Voltage 2.0V 4.5V 6.0V 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V V V VIL Maximum Low Level Input Voltage** 2.0V 4.5V 6.0V 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V V V VOH Minimum High Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA 2.0V 4.5V 6.0V 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V V V 4.5V 6.0V 4.2 5.7 3.98 5.48 3.84 5.34 3.7 5.2 V V 2.0V 4.5V 6.0V 0 0 0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA 4.5V 6.0V 0.2 0.2 0.26 0.26 0.33 0.33 0.4 0.4 V V VIN e VIH or VIL lIOUTl s4.0 mA lIOUTl s5.2 mA VOL Maximum Low Level Output Voltage VIN e VIH or VIL lIOUTl s20 mA IIN Maximum Input Current VIN e VCC or GND 6.0V g 0.1 g 1.0 g 1.0 mA ICC Maximum Quiescent Supply Current VIN e VCC or GND IOUT e 0 mA 6.0V 4 40 80 mA Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C. Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used. **VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89. 2 AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns Typ Guaranteed Limit Units fMAX Symbol Maximum Operating Frequency Parameter Conditions 50 30 MHz tPHL, tPLH Maximum Propagation Delay Clock to Q or Q 16 21 ns tPHL, tPLH Maximum Propagation Delay Clear to Q or Q 21 26 ns tPHL, tPLH Maximum Propagation Delay Preset to Q or Q 23 28 ns tREM Minimum Removal Time 10 20 ns ts Minimum Setup Time J or K to Clock 14 20 ns tH Minimum Hold Time J or K to Clock b3 0 ns tW Minimum Pulse Width Preset, Clear or Clock 10 16 ns AC Electrical Characteristics CL e 50 pF, tr e tf e 6 ns (unless otherwise specified) Symbol Parameter Conditions TA e 25§ C VCC 74HC TA eb40 to 85§ C Typ 54HC TA eb55 to 125§ C Units Guaranteed Limits fMAX Maximum Operating Frequency 2.0V 4.5V 6.0V 9 45 53 5 27 31 4 21 24 3 18 20 MHz MHz MHz tPHL, tPLH Maximum Propagation Delay Clock to Q or Q 2.0V 4.5V 6.0V 100 20 17 126 25 21 160 31 27 183 37 32 ns ns ns tPHL, tPLH Maximum Propagation Delay Clear to Q or Q 2.0V 4.5V 6.0V 126 25 21 155 31 26 191 39 33 250 47 40 ns ns ns tPHL, tPLH Maximum Propagation Delay, Preset to Q or Q 2.0V 4.5V 6.0V 137 27 23 165 33 28 210 41 35 240 50 40 ns ns ns tREM Minimum Removal Time Preset or Clear to Clock 2.0V 4.5V 6.0V 55 11 9 100 20 17 125 25 21 150 30 25 ns ns ns ts Minimum Setup Time J or K to Clock 2.0V 4.5V 6.0V 77 15 13 100 20 17 125 25 21 150 30 25 ns ns ns tH Minimum Hold Time J or K from Clock 2.0V 4.5V 6.0V b3 b3 b3 0 0 0 0 0 0 0 0 0 ns ns ns tW Minimum, Pulse Width, Preset, Clear or Clock 2.0V 4.5V 6.0V 55 11 9 80 16 14 100 20 18 120 24 21 ns ns ns tTLH, tTHL Maximum Output Rise and Fall Time 2.0V 4.5V 6.0V 30 8 7 75 15 13 95 19 16 110 22 19 ns ns ns tr, tf Maximum Input Rise and Fall Time 2.0V 4.5V 6.0V 1000 500 400 1000 500 400 1000 500 400 ns ns ns CPD Power Dissipation Capacitance (Note 5) CIN Maximum Input Capacitance (per flip-flop) 80 5 pF 10 10 10 pF Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC. 3 Typical Applications N Bit Presettable Ripple Counter with Enable and Reset TL/F/5074 – 4 N Bit Parallel Load/Serial Load Shift Register with Clear TL/F/5074 – 5 4 Physical Dimensions inches, (millimeters) Ceramic Dual-In-Line Package (J) Order Number MM54HC76J or MM74HC76J NS Package Number J16A 5 MM54HC76/MM74HC76 Dual J-K Flip-Flops with Preset and Clear Physical Dimensions inches, (millimeters) (Continued) Molded Dual-In-Line Package (N) Order Number MM74HC76N NS Package Number N16E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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