NSC MM54HC280J

MM54HC280/MM74HC280
9-Bit Odd/Even Parity Generator/Checker
General Description
Features
The MM54HC280/MM74HC280 utilizes advanced silicongate CMOS technology to achieve the high noise immunity
and low power consumption of standard CMOS integrated
circuits. It possesses the ability to drive 10 LS-TTL loads.
This parity generator/checker features odd/even outputs to
facilitate operation of either odd or even parity applications.
The word length capability is easily expanded by cascading
devices. The 54HC/74HC logic family is speed, function,
and pinout compatible with the standard 54LS/74LS family.
All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Y
Y
Y
Y
Y
Typical propagation delay: 28 ns
Wide power supply range: 2V – 6V
Low quiescent current: 80 mA maximum (74HC)
Low input current: 1 mA maximum
Fanout of 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
TL/F/5121 – 1
Order Number MM54HC280 or MM74HC280
Function Table
Numbers of Inputs A
thru 1 that are High
R Even
Outputs
R Odd
0, 2, 4, 6, 8
1, 3, 5, 7, 9
H
L
L
H
H e high level, L e low level
C1995 National Semiconductor Corporation
TL/F/5121
RRD-B30M105/Printed in U. S. A.
MM54HC280/MM74HC280 9-Bit Odd/Even Parity Generator/Checker
January 1988
Absolute Maximum Ratings
Operating Conditions
(Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input or Output Voltage
(VIN, VOUT)
b 0.5 to a 7.0V
Supply Voltage (VCC)
b 1.5 to VCC a 1.5V
DC Input Voltage (VIN)
b 0.5 to VCC a 0.5V
DC Output Voltage (VOUT)
g 20 mA
Clamp Diode Current (IIK, IOK)
g 25 mA
DC Output Current, per pin (IOUT)
g 50 mA
DC VCC or GND Current, per pin (ICC)
b 65§ C to a 150§ C
Storage Temperature Range (TSTG)
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Lead Temp. (TL) (Soldering 10 seconds)
260§ C
DC Electrical Characteristics
Symbol
Parameter
Operating Temp. Range (TA)
MM74HC
MM54HC
Min
2
Max
6
0
VCC
Units
V
V
b 40
b 55
a 85
a 125
§C
§C
1000
500
400
ns
ns
ns
Input Rise or Fall Times
VCC e 2.0V
(tr, tf)
VCC e 4.5V
VCC e 6.0V
(Note 4)
Conditions
TA e 25§ C
VCC
74HC
TA eb40 to 85§ C
Typ
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
VIH
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
VIL
Maximum Low Level
Input Voltage**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
VOH
Minimum High Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
VIN e VIH or VIL
lIOUTl s4.0 mA
lIOUTl s5.2 mA
VOL
Maximum Low Level
Output Voltage
VIN e VIH or VIL
lIOUTl s20 mA
IIN
Maximum Input
Current
VIN e VCC or GND
6.0V
g 0.1
g 1.0
g 1.0
mA
ICC
Maximum Quiescent
Supply Current
VIN e VCC or GND
IOUT e 0 mA
6.0V
8.0
80
160
mA
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: b 12 mW/§ C from 65§ C to 85§ C; ceramic ‘‘J’’ package: b 12 mW/§ C from 100§ C to 125§ C.
Note 4: For a power supply of 5V g 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC e 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN,
ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
**VIL limits are currently tested at 20% of VCC. The above VIL specification (30% of VCC) will be implemented no later than Q1, CY’89.
2
AC Electrical Characteristics VCC e 5V, TA e 25§ C, CL e 15 pF, tr e tf e 6 ns
Typ
Guaranteed
Limit
Units
Maximum Propagation
Delay, Data to R Even
28
35
ns
Maximum Propagation
Delay, Data to R Odd
28
35
ns
Symbol
Parameter
tPHL, tPLH
tPHL, tPLH
Conditions
AC Electrical Characteristics VCC e 2.0V to 6.0V, CL e 50 pF, tr e tf e 6 ns (unless otherwise specified)
Symbol
Parameter
Conditions
TA e 25§ C
VCC
Typ
74HC
TA eb40 to 85§ C
54HC
TA eb55 to 125§ C
Units
Guaranteed Limits
tPHL, tPLH
Maximum Propagation
Delay, Data to R Even
2.0V
4.5V
6.0V
103
21
17
205
41
35
258
52
44
305
61
52
ns
ns
ns
tPHL, tPLH
Maximum Propagation
Delay, Data to R Odd
2.0V
4.5V
6.0V
103
21
17
205
41
35
258
52
44
305
61
52
ns
ns
ns
tTLH, tTHL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
CPD
Power Dissipation
Capacitance (Note 5)
83
CIN
Maximum Input Capacitance
5
pF
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD e CPD VCC2 f a ICC VCC, and the no load dynamic current consumption, IS e CPD VCC f a ICC.
Logic Diagram
VCC e pin 14
GND e pin 7
’HC280
3
TL/F/5121 – 2
MM54HC280/MM74HC280 9-Bit Odd/Even Parity Generator/Checker
Physical Dimensions inches (millimeters)
Dual-In-Line Package
Order Number MM54HC280J or MM74HC280J
NS Package J14A
LIFE SUPPORT POLICY
Dual-In-Line Package
Order Number MM74HC280J,N
NS Package N14A
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