FTDI VNC2

Document No.: FT_000138
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
Version - 1.0
Clearance No.: FTDI# 143
Future Technology
Devices International Ltd
Vinculum-II Embedded
Dual USB Host Controller
IC
Vinculum-II is FTDI‟s 2nd generation of USB Host
devices. The CPU has been upgraded from the
previous VNC1L device dramatically increasing the
processing power. The IC architecture has been
designed to take care of most of the general USB
data transfers, thus freeing up processing power
for user applications. Flash and RAM memory has
been increased providing larger user areas of
memory for the designer to incorporate his own
code. The designers also have the ability to create
their own firmware using the new suite of software
development tools.

Eight bit wide FIFO Interface.

Firmware upgrades via UART, SPI,
FIFO interface or USB Flash Drive.

12MHz oscillator using external crystal.

General-purpose timers..

Software development suite of tools to
create customised firmware. Compiler
Linker – Debugger – IDE.

Available in six RoHS compliant
packages - 32 LQFP, 32 QFN, 48 LQFP,
48 QFN, 64 LQFP and 64 QFN

VNC2-48L1A package option
compatible with VNC1L-1A.

44 configurable I/O pins on the 64 pin
device, 28 I/O pins on the 48 pin
device and 12 I/O on the 32 pin device
using the I/O multiplexer.

+3.3 volt supply.
VNC2 has the following advanced features:

Embedded processor core.

16 bit Harvard architecture.

Two full-speed or low-speed USB 2.0
interfaces capable of host or slave
functions.

256Kbytes on-chip E-Flash Memory
(128K x 16-bits).

16Kbytes on-chip Data RAM (4K x 32bits).

-40°C to +85°C extended operating
temperature range.

Programmable UART up to 3Mbaud.


Two SPI (Serial Peripheral) slave
interfaces and one SPI master
interface.
Simultaneous multiple file access on
BOMS devices.


Reduced power modes capability.
Eight Pulse Width Modulation outputs
to allow connectivity with motor
control applications.

Variable instruction length.

Debugger interface module.

Native support for 8, 16 and 32 bit
data types.

System Suspend Modes.
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or
electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty
as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages
howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use
in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document
provides preliminary information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by
the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH,
United Kingdom. Scotland Registered Company Number: SC136640
Copyright © 2010 Future Technology Devices International Limited
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Document No.: FT_000138
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
Version - 1.0
Clearance No.: FTDI# 143
1
Typical Applications
Add USB host capability to embedded
products.
Interface USB Flash drive to
MCU/PLD/FPGA – data storage and
firmware updates.
Mobile phone to USB Flash drive.*
GPS to mobile phone interface.
Instrumentation USB Flash drive.*
Data-logger USB Flash drive.*
USB Flash drive data storage or firmware
updates.
Set Top Box - USB device interface.
USB Flash drive to USB Flash drive file
transfer interface.
USB webcam.
GPS tracker with USB Flash disk storage.
Digital camera to USB Flash drive*.
Flash drive to SD Card data transfer.
PDA to USB Flash drive. *
Vending machine connectivity.
MP3 Player to USB Flash drive or other USB
slave device interface.
TLM Serial converter.
OSI Wireless Interface.
Geotagging of photos – GPS location linked
to image.
USB wireless process controller.
Motorcycle system telemetry logging.
Telecom system calls logging to replace
printer log.
Medical systems.
Data logging.
PWM applications for motor control
applications e.g. Toys.
FPGA Interfacing.
* Or similar USB slave device interface e.g. USB external drive.
1.1 References to Application and Technical Notes
The following documents (available from http://www.ftdichip.com) have been referenced in this
document.
Firmware – Tool Chain
VNC1L to VNC2 migration guide
SPI Example
RTOS
Debugger commands
VNC2 Errata
Copyright © 2010 Future Technology Devices International Limited
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VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
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Clearance No.: FTDI# 143
1.2 Part Numbers
Part Numbers
Part Number
Package
VNC2-64L1A
64 Pin LQFP
VNC2-64Q1A
64 Pin QFN
VNC2-48L1A
48 Pin LQFP
VNC2-48Q1A
48 Pin QFN
VNC2-32L1A
32 Pin LQFN
VNC2-32Q1A
32 Pin QFN
Table 1 Part Numbers
Please refer to section 11 for all package mechanical parameters.
1.3 USB Compliant
At time of writing this data sheet, VNC2 has not completed USB compliancy testing.
Copyright © 2010 Future Technology Devices International Limited
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Version - 1.0
Clearance No.: FTDI# 143
1.4 Acronyms and Abbreviations
Terms
Description
USB
Universal Serial Bus
FIFO
First In First Out
SPI
Serial Peripheral Interface
PWM
Pulse Width Modulation
GPIO
General Purpose Input Output
I/O
Input / Output
VNC1L
Vinculum-I
VNC2
Vinculum-II
DMA
Direct Memory Access
IDE
Integrated Development Environment
BOMS
Bulk Only Mass Storage
UART
Universal Asynchronous Receiver/Transmitter
SIE
Serial Interface Engine
CPU
Central Processing Unit
SoC
System-on-a-chip
FAT
File Allocation Table
RTOS
Real Time Operating System
VOS
Vinculum Operating System
OSI
Open System Interconnection
MOSI
Master Out Slave In
MISO
Master In Slave Out
SE0
Single Ended Zero
EMCU
Embedded Micro Central Processing Unit
FPGA
Field Programmable Gate Array
Table 2 Acronyms and Abbreviations
Copyright © 2010 Future Technology Devices International Limited
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Version - 1.0
Clearance No.: FTDI# 143
2
VNC2 Block Diagram
Figure 2-1 Simplified VNC2 Block Diagram
For a description of each function please refer to
XTOUT
UART
XTIN
Oscillator/
PLL
Internal Clocks and Timers
PWMs
FIFO
Interface
Program Memory Bus
Flash
Programmer
256K Bytes
E-FLASH
(64K x 32)
Debugger
SPI Master
Peripheral Bus
Input / Output Multiplexer
SPI Slave 1
Embedded
CPU
SPI Slave 0
DMA
0
GPIOS
DMA
1
Debugger I/F
USB1DP
USB1DM
USB2DP
USB2DM
USB Host/
Device
Transceiver 0
USB Host/
Device
Transceiver 1
DMA
2
DMA
3
Data Memory Bus
General
Purpose
Timers
USB Host/
Device
Controller
16K Bytes
Data Ram
(4K x 32)
8 bit bus
32 bit bus
USB Host/
Device
Controller
Section 4.
Copyright © 2010 Future Technology Devices International Limited
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Document No.: FT_000138
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
Version - 1.0
Clearance No.: FTDI# 143
Table of Contents
1
Typical Applications ...................................................................... 2
1.1
References to Application and Technical Notes ................................... 2
1.2
Part Numbers...................................................................................... 3
1.3
USB Compliant .................................................................................... 3
1.4
Acronyms and Abbreviations .............................................................. 4
2
VNC2 Block Diagram ..................................................................... 5
3
Device Pin Out and Signal Description Summary .......................... 9
3.1
Pin Out - 32 pin LQFP ......................................................................... 9
3.2
Pin Out - 32 pin QFN ........................................................................ 10
3.3
Pin Out - 48 pin LQFP ........................................................................ 11
3.4
Pin Out - 48 pin QFN ........................................................................ 12
3.5
Pin Out - 64 pin LQFP ....................................................................... 13
3.6
Pin Out - 64 pin QFN ........................................................................ 14
3.7
VNC2 Schematic symbol 32 Pin ......................................................... 15
3.8
VNC2 Schematic symbol 48 Pin ......................................................... 16
3.9
VNC2 Schematic symbol 64 Pin ......................................................... 17
3.10
Pin Configuration USB and Power .................................................. 18
3.11
Miscellaneous Signal ...................................................................... 19
3.12
Pin Configuration Input / Output ................................................... 20
4
Function Description................................................................... 23
4.1
Key Features ..................................................................................... 23
4.2
Functional Block Descriptions ........................................................... 23
4.2.1
Embedded CPU .......................................................................................................... 23
4.2.2
Flash Module ............................................................................................................. 23
4.2.3
Flash Programming Module ......................................................................................... 23
4.2.4
Input / Output Multiplexer Module ............................................................................... 24
4.2.5
Peripheral DMA Modules 0, 1, 2 & 3 ............................................................................. 25
4.2.6
RAM Module .............................................................................................................. 25
4.2.7
Peripheral Interface Modules ....................................................................................... 25
4.2.8
USB Transceivers 0 and 1 ........................................................................................... 25
4.2.9
USB Host / Device Controllers ..................................................................................... 25
4.2.10
12MHz Oscillator .................................................................................................... 25
4.2.11
Power Saving Modes and Standby mode.................................................................... 25
5
I/O Multiplexer .......................................................................... 26
5.1
I/O Peripherals Signal Names .......................................................... 31
5.2
I/O Multiplexer Configuration........................................................... 32
Copyright © 2010 Future Technology Devices International Limited
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Clearance No.: FTDI# 143
5.3
I/O Mux Group 0............................................................................... 33
5.4
I/O Mux Group 1............................................................................... 34
5.5
I/O Mux Group 2............................................................................... 35
5.6
I/O Mux Group 3............................................................................... 36
5.7
I/O Mux Interface Configuration Example ........................................ 37
6
Peripheral Interfaces ................................................................. 38
6.1
UART Interface ................................................................................. 38
6.1.1
6.2
UART Mode Signal Descriptions ................................................................................... 39
Serial Peripheral Interface – SPI Modes ........................................... 41
6.2.1
6.3
SPI Clock Phase Modes ............................................................................................... 42
Serial Peripheral Interface – Slave ................................................... 43
6.3.1
SPI Slave Signal Descriptions ...................................................................................... 43
6.3.2
Full Duplex................................................................................................................ 44
6.3.3
Half Duplex, 4 pin ...................................................................................................... 46
6.3.4
Half Duplex, 3 pin ...................................................................................................... 47
6.3.5
Unmanaged Mode ...................................................................................................... 48
6.3.6
VNC1L Legacy Interface .............................................................................................. 49
6.4
Serial Peripheral Interface – SPI Master........................................... 55
6.4.1
6.5
SPI Master Signal Descriptions. ................................................................................... 55
Debugger Interface .......................................................................... 58
6.5.1
6.6
Debugger Interface Signal description .......................................................................... 58
Parallel FIFO – Asynchronous Mode .................................................. 59
6.6.1
FIFO Signal Descriptions ............................................................................................. 59
6.6.2
Read / Write Transaction Asynchronous FIFO Mode ........................................................ 62
6.7
Parallel FIFO – Synchronous Mode ................................................... 64
6.7.1
Read / Write Transaction Synchronous FIFO Mode ......................................................... 64
6.8
General Purpose Timers .................................................................... 66
6.9
Pulse Width Modulation .................................................................... 66
6.10
General Purpose Input Output ....................................................... 67
7
USB Interfaces ........................................................................... 68
8
Firmware .................................................................................... 69
8.1
RTOS ................................................................................................. 69
8.2
Device drivers ................................................................................... 69
8.3
Firmware – Software Deveolment Tool Chain ................................... 70
8.4
Precompiled Firmware ...................................................................... 71
9
Device Characteristics and Ratings ............................................. 72
9.1
Absolute Maximum Ratings............................................................... 72
9.2
DC Characteristics............................................................................. 73
Copyright © 2010 Future Technology Devices International Limited
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10
Application Examples ................................................................. 75
10.1
11
Example VNC2 Schematic (MCU – UART Interface) ........................ 75
Package Parameters ................................................................... 76
11.1
VNC2 Package Markings ................................................................ 76
11.2
VNC2, LQFP-32 Package Dimensions.............................................. 77
11.3
VNC2, QFN-32 Package Dimensions ............................................... 78
11.4
VNC2, LQFP-48 Package Dimensions.............................................. 79
11.5
VNC2, QFN-48 Package Dimensions ............................................... 80
11.6
VNC2, LQFP-64 Package Dimensions.............................................. 81
11.7
VNC2, QFN-64 Package Dimensions ............................................... 82
11.8
Solder Reflow Profile ..................................................................... 83
12
Contact Information ................................................................... 85
Appendix A – List of Figures and Tables .................................................... 86
List of Tables ............................................................................................. 86
Appendix B – Revision History ................................................................... 89
Copyright © 2010 Future Technology Devices International Limited
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Clearance No.: FTDI# 143
3
Device Pin Out and Signal Description Summary
VNC2 is available in six packages: 32 pin LQFP, 32 pin QFN, 48 pin LQFP (pin compatible with VNC1L), 48
pin QFN, 64 pin LQFP and 64 pin QFN. Figure 3.3 shows how the VNC2 pins map to the VNC1L pins
(VNC2 pins labelled in bold text):
IO BUS6
25
IO BUS7
26
GND Core
27
VCCIO 3.3V
28
IO BUS8
29
IO BUS9
30
IO BUS10
IO BUS11
IO BUS5
IO BUS4
VCCIO 3.3V
USB2DM
USB2DP
GND Core
USB1DM
USB1DP
24
23
22
21
20
19
18
17
3.1 Pin Out - 32 pin LQFP
16
GND IO
15
IO BUS3
14
IO BUS2
13
VCCIO 3.3V
12
IO BUS1
11
IO BUS0
31
10
RESET#
32
9
PROG#
FTDI
1
2
3
4
5
6
7
8
GND Core
3.3V VREG IN
1.8V VCC PLL IN
XTIN
XTOUT
GND PLL
1.8V VREG OUT
TEST
XXXXXXXXXX
VNC2-32L1A
YYWW
Figure 3-1 32 Pin LQFP – Top Down View
Copyright © 2010 Future Technology Devices International Limited
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Version - 1.0
Clearance No.: FTDI# 143
IO BUS5
IO BUS4
VCCIO 3.3V
USB2DM
USB2DP
GND Core
USB1DM
USB1DP
24
23
22
21
20
19
18
17
3.2 Pin Out - 32 pin QFN
IO BUS6
25
16
GND IO
IO BUS7
26
15
IO BUS3
GND Core
27
14
IO BUS2
VCCIO 3.3V
28
13
VCCIO 3.3V
IO BUS8
29
12
IO BUS1
IO BUS9
30
11
IO BUS0
IO BUS10
31
10
RESET#
IO BUS11
32
9
PROG#
FTDI
4
5
6
7
8
XTIN
XTOUT
GND PLL
1.8V VREG OUT
TEST
3
1.8V VCC PLL IN
2
3.3V VREG IN
GND Core
1
XXXXXXXXXX
VNC2-32Q
1A YYWW
Figure 3-2 32 Pin QFN – Top Down View
Copyright © 2010 Future Technology Devices International Limited
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IO BUS18
ADBUS6
37
IO BUS19
ADBUS7
38
GND Core
GND
39
VCCIO 3.3V
VCCIO
40
IO BUS20
ACBUS0
41
IO BUS21
ACBUS1
42
IO BUS22
ACBUS2
43
IO BUS23
ACBUS3
44
IO BUS24
ACBUS4
45
IO BUS25
ACBUS5
46
IO BUS26
ACBUS6
47
IO BUS27
ACBUS7
48
IO BUS17
IO BUS16
IO BUS15
IO BUS14
IO BUS13
IO BUS12
VCCIO 3.3V
USB2DM
USB2DP
GND Core
USB1DM
USB1DP
ADBUS5
ADBUS4
ADBUS3
ADBUS2
ADBUS1
ADBUS0
VCCIO
USB2DM
USB2DP
GND
USB1DM
USB1DP
36
35
34
33
32
31
30
29
28
27
26
25
3.3 Pin Out - 48 pin LQFP
FTDI
XXXXXXXXXX
VNC2-48L1A
YYWW
24
GND
GND IO
23
BCBUS3
IO BUS11
22
BCBUS2
IO BUS10
21
BCBUS1
IO BUS9
20
BCBUS0
IO BUS8
19
BDBUS7
IO BUS7
18
BDBUS6
IO BUS6
17
VCCIO
VCCIO 3.3V
16
BDBUS5
IO BUS5
15
BDBUS4
IO BUS4
14
BDBUS3
IO BUS3
13
BDBUS2
IO BUS2
BDBUS1
IO BUS1
12
BDBUS0
IO BUS0
11
PROG#
PROG#
10
RESET#
RESET#
9
TEST
TEST
8
PLLFLTR
1.8V VREG OUT
7
AGND
GND PLL
6
XTOUT
XTOUT
5
XTIN
XTIN
4
AVCC
1.8V VCC PLL IN
3
VCC
2
GND
GND Core
3.3V VREG IN
BOLD TEXT = VNC2
1
ITALIC TEXT = VNC1
Figure 3-3 48 Pin LQFP – Top Down View
Copyright © 2010 Future Technology Devices International Limited
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IOBUS17
IOBUS16
IOBUS15
IOBUS14
IOBUS13
IOBUS12
VCCIO 3.3V
USB2DM
USB2DP
GND CORE
USB1DM
USB1DP
36
35
34
33
32
31
30
29
28
27
26
25
3.4 Pin Out - 48 pin QFN
IOBUS18
37
24
GND IO
IOBUS19
38
23
IOBUS11
GND
39
22
IOBUS10
21
IOBUS9
20
IOBUS8
19
IOBUS7
18
IOBUS6
17
VCCIO 3.3 V
16
IOBUS5
FTDI
VCCIO 3.3V
40
IOBUS20
41
IOBUS21
42
IOBUS22
43
IOBUS23
44
IOBUS24
45
IOBUS25
46
15
IOBUS4
IOBUS26
47
14
IOBUS3
IOBUS27
48
13
IOBUS2
1
2
3
4
5
6
7
8
9
10
11
12
Gnd Core
3.3 VREG IN
1.8 VCC PLL IN
XTIN
XTOUT
Gnd PLL
1.8 VREG OUT
TEST
RESET#
PROG#
IOBUS0
IOBUS1
XXXXXXXXXX
VNC2-48Q1A
YYWW
Figure 3-4 48 Pin QFN – Top Down View
Copyright © 2010 Future Technology Devices International Limited
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IO BUS29
IO BUS28
IO BUS27
IO BUS26
IO BUS25
IO BUS24
IO BUS23
IO BUS22
IO BUS21
IO BUS20
VCCIO 3.3V
USB2DM
USB2DP
GND Core
USB1DM
USB1DP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3.5 Pin Out - 64 pin LQFP
IO BUS30
49
32
IO BUS19
IO BUS31
50
31
IO BUS18
IO BUS32
51
30
GND IO
IO BUS33
52
29
IO BUS17
GND Core
53
28
IO BUS16
VCCIO 3.3V
54
27
IO BUS15
IO BUS34
55
26
IO BUS14
IO BUS35
56
25
IO BUS13
IO BUS36
57
24
IO BUS12
FTDI
XXXXXXXXXX
VNC2-64L1A
YYWW
23
IO BUS11
22
IO BUS10
21
VCCIO 3.3V
9
10
11
12
13
14
15
16
RESET#
PROG#
IO BUS0
IO BUS1
IO BUS2
IO BUS3
IO BUS4
IO BUS5
IO BUS6
8
IO BUS43
TEST
IO BUS7
17
1.8V VREG OUT
18
64
7
63
6
IO BUS42
5
IO BUS8
XTOUT
IO BUS41
GND PLL
IO BUS9
19
4
20
62
3
61
XTIN
IO BUS40
1.8V VCC PLL IN
60
2
IO BUS39
1
59
GND Core
58
IO BUS38
3.3V VREG IN
IO BUS37
Figure 3-5 64 Pin LQFP – Top Down View
Copyright © 2010 Future Technology Devices International Limited
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IOBUS29
IOBUS28
IOBUS27
IOBUS26
IOBUS25
IOBUS24
IOBUS23
IOBUS22
IOBUS21
IOBUS20
VCCIO 3.3V
USB2DM
USB2DP
GND CORE
USB1DM
USB1DP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
3.6 Pin Out - 64 pin QFN
IOBUS30
49
32
IOBUS19
IOBUS31
50
31
IOBUS18
IOBUS32
51
30
GND IO
IOBUS33
52
29
IOBUS17
GND CORE
53
28
IOBUS16
VCCIO 3.3V
54
27
IOBUS15
IOBUS34
55
26
IOBUS14
IOBUS35
56
25
IOBUS13
IOBUS36
57
24
IOBUS12
IOBUS37
58
23
IOBUS11
IOBUS38
59
22
IOBUS10
IOBUS39
60
21
VCCIO 3.3V
IOBUS40
61
20
IOBUS9
IOBUS41
62
19
IOBUS8
IOBUS42
63
18
IOBUS7
IOBUS43
64
17
IOBUS6
FTDI
8
9
10
11
12
13
14
TEST
RESET#
PROG#
IOBUS0
IOBUS1
IOBUS2
IOBUS3
16
7
1.8 VREG OUT
IOBUS5
6
15
5
Gnd PLL
IOBUS4
4
3
XTIN
2
1.8 VCC PLL IN
XTOUT
1
Gnd Core
3.3 VREG IN
XXXXXXXXXX
VNC2-64Q1A
YYWW
Figure 3-6 64 Pin QFN – Top Down View
Copyright © 2010 Future Technology Devices International Limited
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3.7 VNC2 Schematic symbol 32 Pin
2
28 22 13
V V
C C
C C
I I
O O
17
18
20
21
4
5
10
V
R
E
G
I
N
V
C
C
I
O
USB1DP
USB1DM
3
V
C
C
P
L
L
I
N
IOBUS1
USB2DP
IOBUS2
USB2DM
IOBUS3
IOBUS4
XTIN
XTOUT
PROG#
7
8
VREG OUT
TEST
G
N
D
G P
N L
D L
1
6
G
N
D
G
N
D
11
12
14
15
23
24
IOBUS5
25
IOBUS6
26
IOBUS7
29
IOBUS8
30
IOBUS9
31
IOBUS10
32
IOBUS11
VNC2
32 Pin
RESET#
9
IOBUS0
G
N
D
16 19 27
Figure 3-7 Schematic symbol 32 Pin
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Document No.: FT_000138
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Version - 1.0
Clearance No.: FTDI# 143
3.8 VNC2 Schematic symbol 48 Pin
40 30 17
V V
C C
C C
I I
O O
25
26
28
29
4
5
9
V
C
C
I
O
2
V
R
E
G
I
N
USB1DP
USB1DM
USB2DP
USB2DM
XTIN
XTOUT
VNC2
48 Pin
RESET#
10
PROG#
7
8
VREG OUT
TEST
G
N
D
G P
N L
D L
1 6
3
V
C
C
P
L
L
I
N
IOBUS0
IOBUS1
IOBUS2
IOBUS3
IOBUS4
G
N
D
G
N
D
12
13
14
15
16
IOBUS5
18
IOBUS6
19
IOBUS7
20
IOBUS8
21
IOBUS9
22
IOBUS10
23
IOBUS11
31
IOBUS12
32
IOBUS13
33
IOBUS14
34
IOBUS15
35
IOBUS16
36
IOBUS17
37
IOBUS18
38
IOBUS19
41
IOBUS20
42
IOBUS21
43
IOBUS22
44
IOBUS23
IOBUS24
G
N
D
11
IOBUS25
IOBUS26
IOBUS27
45
46
47
48
24 27 39
Figure 3-8 Schematic symbol 48 Pin
Copyright © 2010 Future Technology Devices International Limited
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Document No.: FT_000138
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
Version - 1.0
Clearance No.: FTDI# 143
3.9 VNC2 Schematic symbol 64 Pin
54 38 21
V V
C C
C C
I I
O O
33
34
36
37
4
5
9
V
C
C
I
O
2
V
R
E
G
I
N
USB1DP
USB1DM
3
V
C
C
P
L
L
I
N
USB2DP
USB2DM
XTIN
XTOUT
RESET#
10
PROG#
VNC2
64 Pin
7
8
VREG OUT
TEST
IOBUS0
IOBUS1
IOBUS2
IOBUS3
IOBUS4
IOBUS25
IOBUS26
IOBUS27
IOBUS43
IOBUS28
63
12
13
14
15
16
IOBUS5
17
IOBUS6
18
IOBUS7
19
IOBUS8
20
IOBUS9
22
IOBUS10
23
IOBUS11
24
IOBUS12
25
IOBUS13
26
IOBUS14
27
IOBUS15
28
IOBUS16
29
IOBUS17
31
IOBUS18
32
IOBUS19
39
IOBUS20
40
IOBUS21
41
IOBUS22
42
IOBUS23
IOBUS24
64
11
43
44
45
46
47
48
IOBUS29
49
IOBUS30
50
IOBUS31
IOBUS42
62
IOBUS41
61
IOBUS40
60
IOBUS39
59
IOBUS38
58
IOBUS37
57
IOBUS36
G
N
D
G P
N L
D L
1 6
IOBUS32 51
52
IOBUS33
55
IOBUS34
56
IOBUS35
G
N
D
G
N
D
G
N
D
30 35 53
Figure 3-9 Schematic symbol 64 Pin
Copyright © 2010 Future Technology Devices International Limited
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Document No.: FT_000138
VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
Version - 1.0
Clearance No.: FTDI# 143
3.10 Pin Configuration USB and Power
Pin No
64 pin
Pin
No.
48 pin
Pin No
32 pin
Name
Type
Description
33
25
17
USB1DP
I/O
USB host/slave port 1 - USB Data Signal Plus with
integrated pull-up/pull-down resistor.
34
26
18
USB1DM
I/O
USB host/slave port 1 - USB Data Signal Minus with
integrated pull-up/pull-down resistor.
36
28
20
USB2DP
I/O
USB host/slave port 2 - USB Data Signal Plus with
integrated pull-up/pull-down resistor.
37
29
21
USB2DM
I/O
USB host/slave port 2 - USB Data Signal Minus with
integrated pull-up/pull-down resistor.
Name
Type
Description
GND
PWR
Device ground supply pins.
Table 3 USB Interface Group
Pin No
64 pin
1, 30,
Pin
No.
48 pin
Pin No
32 pin
1, 16,
35, 53
1, 24,
27, 39
19, 27
2
2
2
3.3V
VREGIN
PWR
+3.3V supply to the regulator.
3
3
3
1.8V
VCC PLL
IN
PWR
+1.8V supply to the internal clock multiplier. This pin
requires a 100nF decoupling capacitor.
6
6
6
GND PLL
PWR
Device analogue ground supply for internal clock
multiplier.
7
7
7
VREG
OUT
Output
1.8V output from regulator to device core
21, 38,
54
17, 30,
40
13, 22,
28
VCCIO
PWR
+3.3V supply to the input / output. Interface pins
(IOBUS). Leaving the VCCIO unconnected will lead to
unpredictable operation on the interface pins.
Table 4 Power and Ground
Copyright © 2010 Future Technology Devices International Limited
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VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
Version - 1.0
Clearance No.: FTDI# 143
3.11 Miscellaneous Signal
Pin No
64 pin
Pin
No.
48 pin
Pin No
32 pin
Name
Type
Description
XTIN
Input
Input to 12MHz Oscillator Cell. Connect 12MHz crystal
across pins 4 and 5.
4
4
4
5
5
5
XTOUT
Output
Output from 12MHz Oscillator Cell. Connect 12MHz
crystal across pins 4 and 5.
8
8
8
TEST
Input
Test Input. Must be tied to GND for normal operation.
9
9
10
RESET#
10
10
9
PROG#
Input
Input
Can be used by an external device to reset VNC2.
Asserting PROG# on its own enables programming
mode.
Table 5 Miscellaneous Signal Group
Note: # is used to indicate an active low signal.
Copyright © 2010 Future Technology Devices International Limited
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VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
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Clearance No.: FTDI# 143
3.12 Pin Configuration Input / Output
VNC2 has multiple interfaces available for connecting to external devices. These are UART, FIFO, SPI
slave, SPI master, GPIO and PWM. The Interface I/O Multiplexer is used to share the available I/O Pins
between each peripheral.
VNC2 is configured with default settings for the I/O pins however they can be easily changed to suit the
needs of a designer. This is explained in Section 5 – I/O Multiplexer. Default configuration for each
package type is shown in Table 6- Default I/O Configuration. The signal names are also indicated for
the VNC1L device as it is pin-compatible with the 48 pin LQFP VNC2 device.
Pin
No.
Pin
No.
Pin
No.
64
Pin
48
Pin
32
Pin
11
11
12
Name
64 Pin
48 Pin
32 PIN
(VINC1-L)
Default
Default
Default
11
IOBUS0
(BDBUS0)
debug_if
debug_if
12
12
IOBUS1
(BDBUS1)
Input
13
13
14
IOBUS2
(BDBUS2)
14
14
15
15
15
16
Type
Description
debug_if
I/O
GPIO
pwm[1]
gpio[1]
I/O
GPIO
Input
pwm[2]
gpio[2]
I/O
GPIO
IOBUS3
(BDBUS3)
Input
pwm[3]
gpio[3]
I/O
GPIO
23
IOBUS4
(BDBUS4)
fifo_data[0]
spi_s0_clk
uart_txd
I/O
GPIO
16
24
IOBUS5
(BDBUS5)
fifo_data[1]
spi_s0_mosi
uart_rxd
I/O
GPIO
17
18
25
IOBUS6
(BDBUS6)
fifo_data[2]
spi_s0_miso
uart_rts#
I/O
GPIO
18
19
26
IOBUS7
(BDBUS7)
fifo_data[3]
spi_s0_ss#
uart_cts#
I/O
GPIO
19
20
29
IOBUS8
(BCBUS0)
fifo_data[4]
spi_m_clk
spi_s0_clk
I/O
GPIO
20
21
30
IOBUS9
(BCBUS1)
fifo_data[5]
spi_m_mosi
spi_s0_mosi
I/O
GPIO
22
22
31
IOBUS10
(BCBUS2)
fifo_data[6]
spi_m_miso
spi_s0_miso
I/O
GPIO
23
23
32
IOBUS11
(BCBUS3)
fifo_data[7]
spi_m_ss_0#
spi_s0_ss#
I/O
GPIO
24
31
-
IOBUS12
(ADBUS0)
fifo_rxf#
uart_txd
I/O
GPIO
25
32
-
IOBUS13
(ADBUS1)
fifo_txe#
uart_rxd
I/O
GPIO
26
33
-
IOBUS14
(ADBUS2)
fifo_rd#
uart_rts#
I/O
GPIO
27
34
-
IOBUS15
(ADBUS3)
fifo_wr#
uart_cts#
I/O
GPIO
Copyright © 2010 Future Technology Devices International Limited
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Version - 1.0
Clearance No.: FTDI# 143
Pin
No.
Pin
No.
Pin
No.
64
Pin
48
Pin
32
Pin
28
35
29
Name
64 Pin
48 Pin
32 PIN
(VINC1-L)
Default
Default
Default
-
IOBUS16
(ADBUS4)
Input
36
-
IOBUS17
(ADBUS5)
31
37
-
32
38
39
Type
Description
uart_dtr#
I/O
GPIO
Input
uart_dsr#
I/O
GPIO
IOBUS18
(ADBUS6)
Input
uart_dcd#
I/O
GPIO
-
IOBUS19
(ADBUS7)
Input
uart_ri#
I/O
GPIO
41
-
IOBUS20
(ACBUS0)
uart_txd
uart_tx_active
I/O
GPIO
40
42
-
IOBUS21
(ACBUS1)
uart_rxd
gpio[5]
I/O
GPIO
41
43
-
IOBUS22
(ACBUS2)
uart_rts#
gpio[6]
I/O
GPIO
42
44
-
IOBUS23
(ACBUS3)
uart_cts#
gpio[7]
I/O
GPIO
43
45
-
IOBUS24
(ACBUS4)
uart_dtr#
gpio[0]
I/O
GPIO
44
46
-
IOBUS25
(ACBUS5)
uart_dsr#
gpio[1]
I/O
GPIO
45
47
-
IOBUS26
(ACBUS6)
uart_dcd#
gpio[2]
I/O
GPIO
46
48
-
IOBUS27
(ACBUS7)
uart_ri#
gpio[3]
I/O
GPIO
47
-
-
IOBUS28
uart_tx_active
I/O
GPIO
48
-
-
IOBUS29
Input
I/O
GPIO
49
-
-
IOBUS30
Input
I/O
GPIO
50
-
-
IOBUS31
Input
I/O
GPIO
51
-
-
IOBUS32
spi_s0_clk
I/O
GPIO
52
-
-
IOBUS33
spi_s0_mosi
I/O
GPIO
55
-
-
IOBUS34
spi_s0_miso
I/O
GPIO
56
-
-
IOBUS35
spi_s0_ss#
I/O
GPIO
57
-
-
IOBUS36
spi_s1_clk
I/O
GPIO
58
-
-
IOBUS37
spi_s1_mosi
I/O
GPIO
59
-
-
IOBUS38
spi_s1_miso
I/O
GPIO
Copyright © 2010 Future Technology Devices International Limited
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VINCULUM-II EMBEDDED DUAL USB HOST CONTROLLER IC Datasheet
Version - 1.0
Clearance No.: FTDI# 143
Pin
No.
Pin
No.
Pin
No.
64
Pin
48
Pin
60
Name
64 Pin
48 Pin
32 PIN
32
Pin
(VINC1-L)
Default
Default
Default
-
-
IOBUS39
61
-
-
62
-
63
64
Type
Description
spi_s1_ss#
I/O
GPIO
IOBUS40
spi_m_clk
I/O
GPIO
-
IOBUS41
spi_m_mosi
I/O
GPIO
-
-
IOBUS42
spi_m_miso
I/O
GPIO
-
-
IOBUS43
spi_m_ss_0#
I/O
GPIO
Table 6 Default I/O Configuration
Copyright © 2010 Future Technology Devices International Limited
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Clearance No.: FTDI# 143
4
Function Description
VNC2 is the second of FTDIs Vinculum family of Embedded USB host controller integrated circuit devices.
VNC2 can encapsulate certain USB device classes by handling the USB Host Interface and data transfer
functions using the in-built EMCU and embedded Flash memory. When interfacing to mass storage
devices, such as USB Flash drives, VNC2 transparently handles the FAT file structure using a simple to
implement command set. VNC2 provides a cost effective solution for introducing USB host capability into
products that previously did not have the hardware resources to do so.
VNC2 has an associated software development tool suite to allow users to create customised firmware.
4.1 Key Features
VNC2 is a programmable SoC device with a powerful embedded microprocessor core and dual USB
interfaces, large RAM and Flash capacity and the ability to develop and customise firmware using the
VNC2 tool chain. VNC2 has an enhanced feature list over and above VNC1L, however the 48 pin LQFP
package is backward compatible with the VNC1L.
4.2 Functional Block Descriptions
The following paragraphs describe each function within VNC2. Please refer to the block diagram shown in
Figure 2-1.
4.2.1 Embedded CPU
The processor core is based on FTDIs proprietary 16-bit embedded MCU architecture. The EMCU has a
Harvard architecture with separate code and data space.
4.2.2 Flash Module
VNC2 has 256K bytes (128K x 16-bits) of embedded Flash (E-FLASH) memory. No special programming
voltages are necessary for programming the onboard E-FLASH as these are provided internally on-chip.
4.2.3 Flash Programming Module
The purpose of the flash programmer module is to perform all necessary operations for programming the
flash, from general usage to first power on sequencing. This block is responsible for handling device
firmware upgrades which can be accessed by the debugger interface, a USB cable or Flash drive
interface.
Copyright © 2010 Future Technology Devices International Limited
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Clearance No.: FTDI# 143
4.2.4 Input / Output Multiplexer Module
VNC2 peripheral interfaces are UART, SPI slave0, SPI slave1, SPI master, FIFO-Asynchronous, FIFOSynchronous, GPIO, debug interface and PWM.
The I/O multiplexer allows the designer to select which peripherals are connected to the device I/O pins.
The selectable peripheral interfaces are only limited by the number of I/O pins available. All peripherals
are available across the package range except synchronous FIFO mode which cannot be selected on 32
pin packages. The available configurable I/O pins per package are as follows:
32 pin package – 12 I/O pins
48 pin package – 28 I/O pins
64 pin package – 44 I/O pins
Table 7 lists the peripherals which can be multiplexed to I/O and the maximum number of pins required
for each one. The designer can choose any mix of peripheral configurations as long as they are within the
specific package I/O pin count. Depending on the design not all 9 UART pins need to be configured.
Similarly the GIPO peripheral does not need all pins configured.
e.g. The 48 pin package has 28 I/O pins which could be configured as UART – 9 pins, SPI Master – 5
pins, FIFO Asynchronous – 12 pins and GPIO – 2 pins. This makes a total of 28 pins.
Please refer to Section 5 for a detailed description of the I/O multiplexer.
Peripherals
Maximum pins required
UART
9
SPI Slave 0
4
SPI Slave 1
4
SPI Master
5
FIFO Asynchronous
12
FIFO Synchronous
14
GPIO
40
Debug
1
PWM
8
Table 7 - Peripheral Pin Requirements
Copyright © 2010 Future Technology Devices International Limited
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Clearance No.: FTDI# 143
4.2.5 Peripheral DMA Modules 0, 1, 2 & 3
The peripheral DMA has the capability to transfer data to and from an I/O device. The CPU can offload
the transfer of data between the processor and the peripheral freeing the CPU to execute other
instructions.
The DMA module collects or transmits data from memory to an I/O address space, it is also capable of
copying data in memory and transferring it to another location.
4.2.6 RAM Module
The RAM module consists of 16K bytes on-chip (4K x 32-bits) data memory. The RAM is byte
addressable.
4.2.7 Peripheral Interface Modules
VNC2 has nine peripheral interface modules. Full descriptions of each module are described in section 6.
Debugger Interface
UART
PWM
FIFO
SPI Master
SPI Slave 0 & 1
GPIO - General purpose I/O pins
General purpose timers
4.2.8 USB Transceivers 0 and 1
Two USB transceiver cells provide the physical USB device interface supporting USB 1.1 and USB 2.0
standards. Low-speed and full-speed USB data rates are supported. Each output driver provides +3.3V
level slew rate control signalling, whilst a differential receiver and two single ended receivers provide USB
DATA IN, SE0 and USB Reset condition detection. These cells also include integrated internal USB pull-up
or pull-down resistors as required for host or slave mode.
4.2.9 USB Host / Device Controllers
These blocks handle the parallel-to-serial and serial-to-parallel conversion of the USB physical layer. This
includes bit stuffing, CRC generation, USB frame generation and protocol error checking. The Host /
Device controller is autonomous and therefore requires limited load from the CPU.
4.2.10 12MHz Oscillator
The 12MHz Oscillator cell generates a 12MHz reference clock input to the Clock Multiplier PLL from an
external 12MHz crystal. The external crystal is connected across Pin 4 – XTIN and Pin 5 – XTOUT in the
configuration shown in Figure 10-1.
4.2.11 Power Saving Modes and Standby mode.
VNC2 can be set to operate in three frequencies allowing the user to select a slower speed to reduce
power consumption. Three operating frequencies available are 12MHz, 24MHz and normal operation of
48MHz. These operating modes can be configured using the RTOS. Full details are available in the RTOS
manual available from the FTDI website.
When a particular peripheral is not used, it is powered down internally thus saving power.
Standby mode is available under firmware control, this mode puts the VNC2 in a state with no clocks
running or system blocks powered. The device will wake up out of this mode by toggling any of the
following signals: USB0/1 DP or DM, SPI slave 0 select (spi_s0_ss# ), SPI slave 1select(spi_s1_ss# ) or
UART ring indicator (uart_ri#).
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Clearance No.: FTDI# 143
5
I/O Multiplexer
FTDI devices typically have multiple interfaces available to communicate with external devices. VNC2 has
UART, SPI slave0, SPI slave1, SPI master, FIFO, GPIO, and PWM peripherals. The available packages for
VNC2 provide any of these interfaces to be active on the available pins through the use of an I/O
Multiplexer. Table 8 lists the signals available for each peripheral. Table 9 to 12 explain the use of the
I/O multiplexer. An application within the RTOS is available to aid with pin configuration, Section 5.2 has
more details.
Multiplexers are used to connect the VNC2 peripherals to the external IOBUS pins. This enables the
designer to select which IOBUS pins he wishes to map a particular peripheral to. Peripheral signals are
allocated to one of four groups, which connect to the I/O multiplexer. Each I/O peripheral signal can
connect to one out of every four external IOBUS pins. The IOBUS pin that a peripheral signal can connect
to is dictated by the peripheral signal‟s group. For example, if a peripheral signal is allocated to group 0
then it can connect to IOBUS0, IOBUS4, IOBUS8, IOBUS12 and so on. If a peripheral signal is allocated
to group 1 then it can connect to IOBUS1, IOBUS5, IOBUS9, IOBUS13 and so on. Figure 5-1 details the
I/O multiplexer concept, where, for example, a white peripheral signal can connect to any white IOBUS
pin, a green peripheral signal can connect to a green IOBUS pin. Figure 5-2, Figure 5-3 and Figure
5-4 give examples of connecting peripheral signals to differing IOBUS pins.
The IO Multiplexer also provides the following features:
Ability to configure an I/O pad as an input, output or bidirectional pad.
At power on reset, all pins are set as inputs by default.
Note: It is recommended not to reassign the debug interface signal (debug_if) from its default setting of
IOBUS0 (Pin 11 on all packages). This assumes that the debug pin is required in the application design, if
not, pin 11 can be assigned to any other group 0 signal.
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Clearance No.: FTDI# 143
Peripheral Pin
IOBUS Pin
uart_txd
uart_rxd
uart_rts#
uart_cts#
uart_dtr#
uart_dsr#
uart_dcd#
uart_ri#
uart_tx_active
IOBUS0
IOBUS1
IOBUS2
IOBUS3
IOBUS4
IOBUS5
IOBUS6
IOBUS7
IOBUS8
IOBUS9
IOBUS10
IOBUS11
IOBUS12
IOBUS13
IOBUS14
IOBUS15
IOBUS16
IOBUS17
IOBUS18
IOBUS19
IOBUS20
IOBUS21
Key:
Group 0 allocated pin
Group 1 allocated pin
Group 2 allocated pin
Group 3 allocated pin
IOBUS43
Figure 5-1 IOBUS to Group Relationship-64 Pin
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Clearance No.: FTDI# 143
Figure 5-2 details the UART, SPI slave0 and SPI master connecting to IOBUS pins:
Peripheral Pin
IOBUS Pin
uart_txd
uart_rxd
uart_rts#
uart_cts#
uart_dtr#
uart_dsr#
uart_dcd#
uart_ri#
uart_tx_active
IOBUS0
IOBUS1
IOBUS2
IOBUS3
IOBUS4
IOBUS5
IOBUS6
IOBUS7
IOBUS8
IOBUS9
IOBUS10
IOBUS11
IOBUS12
IOBUS13
IOBUS14
IOBUS15
IOBUS16
IOBUS17
IOBUS18
IOBUS19
IOBUS20
IOBUS21
IOBUS23
IOBUS24
IOBUS16
IOBUS17
IOBUS18
IOBUS19
IOBUS20
IOBUS21
IOBUS23
IOBUS24
spi_s0_clk
spi_s0_mosi
spi_s0_miso
spi_s0_ss#
spi_s1_clk
spi_s1_mosi
spi_s1_miso
spi_s1_ss#
spi_m_clk
spi_m_mosi
spi_m_miso
spi_m_ss_0#
spi_m_ss_1#
gpio[0]
gpio[1]
gpio[2]
gpio[3]
gpio[4]
gpio[5]
gpio[6]
gpio[7]
IOBUS43
gpio[39]
Figure 5-2 IOBUS to UART, SPI slave0 and SPI master example
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Clearance No.: FTDI# 143
Figure 5-3 expands upon Figure 5-2 by moving the UART, SPI slave0 and SPI master signals to
differing IOBUS positions. The purpose of this diagram to highlight peripherals connected to differing
IOBUS positions.
Peripheral Pin
IOBUS Pin
uart_txd
uart_rxd
uart_rts#
uart_cts#
uart_dtr#
uart_dsr#
uart_dcd#
uart_ri#
uart_tx_active
IOBUS0
IOBUS1
IOBUS2
IOBUS3
IOBUS4
IOBUS5
IOBUS6
IOBUS7
IOBUS8
IOBUS9
IOBUS10
IOBUS11
IOBUS12
IOBUS13
IOBUS14
IOBUS15
IOBUS16
IOBUS17
IOBUS18
IOBUS19
IOBUS20
IOBUS21
IOBUS23
IOBUS24
IOBUS16
IOBUS17
IOBUS18
IOBUS19
IOBUS20
IOBUS21
IOBUS23
IOBUS24
spi_s0_clk
spi_s0_mosi
spi_s0_miso
spi_s0_ss#
spi_s1_clk
spi_s1_mosi
spi_s1_miso
spi_s1_ss#
spi_m_clk
spi_m_mosi
spi_m_miso
spi_m_ss_0#
spi_m_ss_1#
gpio[0]
gpio[1]
gpio[2]
gpio[3]
gpio[4]
gpio[5]
gpio[6]
gpio[7]
IOBUS43
gpio[39]
Figure 5-3 IOBUS to UART, SPI slave0 and SPI master second example
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With reference to Figure 5-3, it can be seen that IOBUS9-11 and IOBUS16-19 were unused. Figure
5-4 expands upon the previous two figures to detail a fully occupied IOBUS, up to and including
IOBUS19. The gaps at IOBUS9-11 have been filed with 3 GPIO pins, the gaps at IOBUS16-19 have been
filled with the second SPI slave and a further 3 IOBUS pins (17-19) have been allocated to 3 GPIO pins.
Note that GPIO pins 0 and 4 are unused as a sufficient gap wasn't available.
Peripheral Pin
IOBUS Pin
uart_txd
uart_rxd
uart_rts#
uart_cts#
uart_dtr#
uart_dsr#
uart_dcd#
uart_ri#
uart_tx_active
IOBUS0
IOBUS1
IOBUS2
IOBUS3
IOBUS4
IOBUS5
IOBUS6
IOBUS7
IOBUS8
IOBUS9
IOBUS10
IOBUS11
IOBUS12
IOBUS13
IOBUS14
IOBUS15
IOBUS16
IOBUS17
IOBUS18
IOBUS19
IOBUS20
IOBUS21
IOBUS23
IOBUS24
IOBUS16
IOBUS17
IOBUS18
IOBUS19
IOBUS20
IOBUS21
IOBUS23
IOBUS24
spi_s0_clk
spi_s0_mosi
spi_s0_miso
spi_s0_ss#
spi_s1_clk
spi_s1_mosi
spi_s1_miso
spi_s1_ss#
spi_m_clk
spi_m_mosi
spi_m_miso
spi_m_ss_0#
spi_m_ss_1#
gpio[0]
gpio[1]
gpio[2]
gpio[3]
gpio[4]
gpio[5]
gpio[6]
gpio[7]
IOBUS43
gpio[39]
Figure 5-4 IOBUS to UART, SPI slave0 and SPI master third example
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5.1 I/O Peripherals Signal Names
Peripheral
Signal Name
Outputs
Inputs
Debugger
debug_if
1
1
debugger interface
uart_txd
1
0
Transmit asynchronous data output
UART
FIFO
GPIO
SPI Slave
0
SPI Slave
1
SPI
Master
PWM
Description
uart_rts#
1
0
Request to send control output
uart_dtr#
1
0
Data acknowledge (data terminal ready control) output
uart_tx_active
1
0
Enable transmit data for RS485 designs
uart_rxd
0
1
Receive asynchronous data input
uart_cts#
0
1
Clear to send control input
uart_dsr#
0
1
Data request (data set ready control) input
uart_ri#
0
1
Ring indicator control input
uart_dcd#
0
1
Data carrier detect control input
fifo_data
8
8
FIFO data bus
fifo_txe#
1
0
fifo_rxf#
1
0
fifo_wr#
0
1
fifo_rd#
0
1
fifo_oe#
0
1
FIFO output enable – synchronous FIFO only
FIFO clock out – synchronous FIFO only
When high, do not write data into the FIFO. When low,
data can be written into the FIFO by strobing WR high,
then low.
When high, do not read data from the FIFO. When low,
there is data available in the FIFO which can be read by
strobing RD# low, then high.
Writes the data byte on the D0...D7 pins into the
transmit FIFO buffer when WR goes from high to low.
Enables the current FIFO data byte on D0...D7 when
low. Fetches the next FIFO data byte (if available) from
the receive FIFO buffer when RD# goes from high to
low
fifo_clkout
0
1
gpio
40
40
spi_s0_clk
0
1
SPI clock input – slave 0
General purpose I/O
spi_s0_ss#
0
1
SPI chip select input – slave 0
spi_s0_mosi
1
1
SPI master out serial in – slave 0
spi_s0_miso
1
0
SPI master in slave out – slave 0
spi_s1_clk
0
1
SPI clock input – slave 1
spi_s1_ss#
0
1
SPI chip select input – slave 1
spi_s1_mosi
1
1
Master out slave in – slave 1
spi_s1_miso
1
0
Master in slave out – slave 1
spi_m_clk
1
0
SPI clock input – master
spi_m_mosi
1
1
Master out slave in - master
spi_m_miso
0
1
Master in slave out - master
spi_m_ss_0#
1
0
Active low slave select 0 from master to slave 0
spi_m_ss_1#
1
0
Active low slave select 1 from master to slave 1
pwm
8
0
Pulse width modulation
Table 8 I/O Peripherals Signal Names
Note: # is used to indicate an active low signal.
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5.2
I/O Multiplexer Configuration
The VNC2 I/O Multiplexer allows signals to be routed to different pins on the device. To simplify the
routing of signals, the VNC2 RTOS provides functions to configure the I/O Multiplexer as the designer
requires. Full details are available in the RTOS manual available from the FTDI website.
The following tables provide a lookup guide to determine what signals are available and the list of pins
that can be used:
Table 9 Group 0
Table 10 Group 1
Table 11 Group 2
Table 12 Group 3
Each VNC2 has a default state of IOBUS signals following a hard reset. The number of I/O pins available
are determined by the package size:
Package 32pin (LQFP & QFN)- Twelve I/O pins – IOBUS0 to IOBUS11
Package 48pin (LQFP & QFN)- Twenty eight I/O pins – IOBUS0 to IOBUS27
Package 64pin (LQFP & QFN)- Forty-four I/O pins – IOBUS0 to IOBUS43
Section 3.12 shows the default signal settings for all three package sizes.
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5.3
I/O Mux Group 0
Available Input signals
Available output
signals
64 Pin
Package
48 Pin
Package
Available
pins
Available
pins
32 Pin Package
Available pins
debug_if
uart_txd
uart_dtr#
debug_if
fifo_data[0]
fifo_data[4]
fifo_oe#
spi_s0_clk
spi_s1_clk
gpio[0]
gpio[4]
gpio[8]
gpio[12]
gpio[16]
gpio[20]
gpio[24]
gpio[28]
gpio[32]
gpio[36]
uart_tx_active
fifo_data[0]
fifo_data[4]
fifo_rxf#
pwm[0]
pwm[4]
11, 15,
spi_m_clk
19, 24,
11, 15,
spi_m_ss_1#
28, 39,
20, 31,
11, 23
gpio[0]
43, 47,
35, 41,
29
gpio[4]
51, 57,
45
gpio[8]
61
gpio[12]
gpio[16]
gpio[20]
gpio[24]
gpio[28]
gpio[32]
gpio[36]
Table 9 Group 0
Table 9 - Input and output signals that are available for all the IOBUS pins that are in group 0. For
example if using the 48 pin package device this would allow pins 11, 15, 20, 31, 35, 41 and 45 to be
configured as either an input signal (listed in the first column) or a output signal (listed in the second
column).
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5.4
I/O Mux Group 1
Available Input signals
Available output
signals
64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
uart_rxd
fifo_data[1]
12, 16,
12,16,
12, 24,
30
uart_dsr#
fifo_data[5]
20, 25,
21, 32,
fifo_data[1]
fifo_txe#
29, 40,
36, 42,
fifo_data[5]
pwm[1]
44, 48,
46
spi_s0_mosi
pwm[5]
52, 58,
spi_s1_mosi
spi_s0_mosi
62
gpio[1]
spi_s1_mosi
gpio[5]
spi_m_mosi
gpio[9]
fifo_clkout
gpio[13]
gpio[1]
gpio[17]
gpio[5]
gpio[21]
gpio[9]
gpio[25]
gpio[13]
gpio[29]
gpio[17]
gpio[33]
gpio[21]
gpio[37]
gpio[25]
gpio[29]
gpio[33]
gpio[37]
Table 10 Group 1
Table 10 - Input and output signals that are available for all the IOBUS pins that are in group 1. For
example if using the 64 pin package device this would allow pins 12, 16, 20, 25, 29, 40, 44, 48, 52, 58
and 62 to be configured as either an input signal (listed in the first column) or a output signal (listed in
the second column).
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5.5
I/O Mux Group 2
Available Input signals
Available output
signals
64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
uart_rts#
uart_dcd#
fifo_data[2]
fifo_data[6]
fifo_rd#
spi_m_miso
gpio[2]
gpio[6]
gpio[10]
gpio[14]
gpio[18]
gpio[22]
gpio[26]
gpio[30]
gpio[34]
gpio[38]
fifo_data[2]
fifo_data[6]
pwm[2]
pwm[6]
spi_s0_miso
spi_s1_miso
13, 17,
gpio[2]
22, 26,
13, 18,
gpio[6]
31, 41,
22, 33,
gpio[10]
45, 49,
37, 43,
gpio[14]
55, 59,
47
gpio[18]
63
14, 25,
31
gpio[22]
gpio[26]
gpio[30]
gpio[34]
gpio[38]
Table 11 Group 2
Table 11 - Input and output signals that are available for all the IOBUS pins that are in group 2. For
example if using the 32 pin package device this would allow pins 14, 25 and 31 to be configured as
either an input signal (listed in the first column) or a output signal (listed in the second column).
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5.6
I/O Mux Group 3
Available Input signals
Available output
signals
64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
uart_cts#
fifo_data[3]
14, 18,
14, 19,
15, 26,
32
uart_ri#
fifo_data[7]
23, 27,
23, 34,
fifo_data[3]
pwm[3]
32, 42,
38, 44,
fifo_data[7]
pwm[7]
46, 50,
48
fifo_wr#
spi_m_ss_0#
56, 60,
spi_s0_ss#
gpio[3]
64
spi_s1_ss#
gpio[7]
gpio[3]
gpio[11]
gpio[7]
gpio[15]
gpio[11]
gpio[19]
gpio[15]
gpio[23]
gpio[19]
gpio[27]
gpio[23]
gpio[31]
gpio[27]
gpio[35]
gpio[31]
gpio[39]
gpio[35]
gpio[39]
Table 12 Group 3
Table 12 - Input and output signals that are available for all the IOBUS pins that are in group 3. For
example if you using the 48 pin package device this would allow pins 14, 19, 23, 34, 38, 44 and 48 to be
configured as either an input signal (listed in the first column) or a output signal (listed in the second
column).
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5.7
I/O Mux Interface Configuration Example
This example shows how to set a UART interface on the VNC2 64 pin package. The UART is made up of
two output signals (uart_txd and uart_rts#) and two input signals (uart_rxd and uart_cts#). For PCB
design it is best to have the four pins of the UART interface adjacent to each other. This can be achieved
easily since the four signals are members of each different groups. Figure 5-1 clearly shows that the
four groups are adjacent to each other. So the four adjacent pins can be used for the UART interface as
long as they are selected one from each of the four groups. Tables 9, 10, 11 & 12 can now be used to
select where the UART interface can be placed. Figure 5-5 shows the four UART signal selected on pins
11, 12, 13 & 14 however they could have been selected on any of the other four pins highlighted in blue
dashed lines.
54 38 21
V V
C C
C C
I I
O O
33
34
36
37
4
5
9
V
C
C
I
O
2
V
C
C
USB1DP
USB1DM
USB2DP
USB2DM
XTIN
XTOUT
VNC2
64 Pin
8
IOBUS0
IOBUS1
IOBUS2
IOBUS3
VREG OUT
TEST
IOBUS24
IOBUS25
IOBUS26
64
11
uart_txd – group0
12
uart_rxd – group1
13
uart_rts# – group2
14
uart_cts# – group3
15
16
IOBUS5
17
IOBUS6
18
IOBUS7
19
IOBUS8
20
IOBUS9
22
IOBUS10
23
IOBUS11
24
IOBUS12
25
IOBUS13
26
IOBUS14
27
IOBUS15
28
IOBUS16
29
IOBUS17
31
IOBUS18
32
IOBUS19
39
IOBUS20
40
IOBUS21
41
IOBUS22
42
IOBUS23
PROG#
7
V
C
C
P
L
L
IOBUS4
RESET#
10
3
IOBUS27
IOBUS43
IOBUS28
63
43
44
45
46
47
48
IOBUS29
49
IOBUS30
50
IOBUS31
IOBUS42
62
IOBUS41
61
IOBUS40
60
IOBUS39
59
IOBUS38
58
IOBUS37
57
IOBUS36
G
N
D
G P
N L
D L
1 6
IOBUS32 51
52
IOBUS33
55
IOBUS34
56
IOBUS35
G
N
D
G
N
D
G
N
D
30 35 53
Figure 5-5 UART Example 64 pin
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6
Peripheral Interfaces
In addition to the two USB Host and Slave blocks, VNC2 contains the following peripheral interfaces:
Universal Asynchronous Receiver Transmitter (UART)
Two Serial Peripheral Interface (SPI) slaves
SPI Master
Debugger Interface
Parallel FIFO Interface (245 mode and synchronous FIFO mode)
General Purpose Timers
Eight Pulse Width Modulation blocks (PWM)
General Purpose Input Output (GPIO)
The following sections describe each peripheral in detail.
6.1 UART Interface
When the data and control bus are configured in UART mode, the interface implements a standard
asynchronous serial UART port with flow control, for example RS232/422/485. The UART can support
baud rates from 300baud to 3Mbaud.
Data transfer uses NRZ (Non-Return to Zero) data format consisting of 1 start bit, 7 or 8 data bits, an
optional parity bit, and one or two stop bits. When transmitting the data bits, the least significant bit is
transmitted first. Transmit and receive waveforms are illustrated in Figure 6-1 and Figure 6-2:
Figure 6-1 UART Receive Waveform
Figure 6-2 UART Transmit Waveform
Baud rate (default =9600 baud), flow control settings (default = RTS/CTS), number of data bits
(default=8), parity (default is no parity) and number of stop bits (default=1) are all configurable using
the firmware command interface. Please refer to http://www.ftdichip.com (or latest version).
uart_tx_active is transmit enable, this output may be used in RS485 designs to control the transmit of
the line driver.
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6.1.1 UART Mode Signal Descriptions
64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
Name
Type
Description
uart_txd
Output
Transmit asynchronous data output
uart_rxd
Input
Receive asynchronous data input
uart_rts#
Output
Request to send control output
uart_cts#
Input
Clear to send control input
uart_dtr#
Output
Data acknowledge (data terminal
ready control) output
11, 15,
19, 24,
11, 15,
28, 39,
20, 31,
11, 23
43, 47,
35, 41,
29
51, 57,
45
61
12, 16,
20, 25,
29, 40,
44, 48,
52, 58,
62
12,16,
21, 32,
12, 24,
36, 42,
30
46
13, 17,
22, 26,
13, 18,
31, 41,
22, 33,
45, 49,
37, 43,
55, 59,
47
14, 25,
31
63
14, 18,
23, 27,
14, 19,
32, 42,
23, 34,
15, 26,
46, 50,
38, 44,
32
56, 60,
48
64
11, 15,
19, 24,
11, 15,
28, 39,
20, 31,
11, 23
43, 47,
35, 41,
29
51, 57,
45
61
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64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
Name
Type
Description
uart_dsr#
Input
Data request (data set ready
control) input
uart_dcd#
Input
Data carrier detect control input
uart_ri#
Input
Ring indicator is used to wake VNC2
depending on firmware
12, 16,
20, 25,
29, 40,
44, 48,
52, 58,
62
12,16,
21, 32,
12, 24,
36, 42,
30
46
13, 17,
22, 26,
13, 18,
31, 41,
22, 33,
45, 49,
37, 43,
55, 59,
47
14, 25,
31
63
14, 18,
23, 27,
14, 19,
32, 42,
23, 34,
15, 26,
46, 50,
38, 44,
32
56, 60,
48
64
11, 15,
19, 24,
11, 15,
28, 39,
20, 31,
11, 23
43, 47,
35, 41,
29
51, 57,
45
61
uart_tx_active
Output
Enable transmit data for RS485
designs. This signal may be used to
signal that a transmit operation is in
progress. The uart_tx_active signal
will be set high one bit-time before
data is transmitted and return low
one bit time after the last bit of a
data frame has been transmitted.
Table 13 Data and Control Bus Signal Mode Options – UART Interface
The UART signals can be programmed to a choice of I/O pins depending on the package size. Table 13
details the available pins for each of the UART signals. Further details on the configuration of input and
output signals are available in Section 5 - I/O Multiplexer.
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6.2 Serial Peripheral Interface – SPI Modes
The Serial Peripheral Interface Bus is an industry standard communications interface. Devices
communicate in Master / Slave mode, with the Master initiating the data transfer.
VNC2 has one master module and two slave modules. Each SPI slave module has four signals – clock,
slave select, MOSI (master out – slave in) and MISO (master in – slave out). The SPI Master has the
same four signals as the slave modules but with one additional signal because it requires a slave select
for the second slave module. Table 14 lists how the signals are named in each module.
Module
Signal Name
Type
Description
spi_s0_clk
Input
Clock input – slave 0
SPI Slave
0
spi_s0_ss#
Input
Active low chip select input – slave 0
spi_s0_mosi
Input
Master out serial in – slave 0
spi_s0_miso
Output
Master in slave out – slave 0
spi_s1_clk
Input
Clock input – slave 1
spi_s1_ss#
Input
Active low chip select input – slave 1
spi_s1_mosi
Input
Master out slave in – slave 1
spi_s1_miso
Output
Master in slave out – slave 1
spi_m_clk
Output
Clock output – master
spi_m_mosi
Output
Master out slave in - master
Master in slave out - master
SPI Slave
1
SPI
Master
spi_m_miso
Input
spi_m_ss_0#
Output
Active low slave select 0 from master to slave 0
spi_m_ss_1#
Output
Active low slave select 1 from master to slave 1
Table 14 SPI Signal Names
The SPI slave protocol by default does not support any form of handshaking. FTDI have added extra
modes to support handshaking, faster throughput of data and reduced pin count. There are 5 modes of
operation in the VNC2 SPI Slave.
Full Duplex – Section 6.3.2
Half Duplex, 4 pin - Section 6.3.3
Half Duplex, 3 pin - Section 6.3.4
Unmanaged - Section 6.3.5
VNC1L legacy mode – Section 6.3.6
VNC2 SPI Master is described in Section 6.4.1 SPI Master Signal Descriptions.
Table 16 shows the SPI master signals and the available pins that they can be mapped to depending on
the package size. Further details on the configuration of input and output signals are available in Section
5 - I/O Multiplexer.
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6.2.1 SPI Clock Phase Modes
SPI interface has 4 unique modes of clock phase (CPHA) and clock polarity (CPOL), known
as Mode 0, Mode 1, Mode 2 and Mode 3. Table 15 summarizes these modes and Figure 6-3 is the
function timing diagram.
For CPOL = 0, the base (inactive) level of SCLK is 0.
In this mode:
• When CPHA = 0, data is clocked in on the rising edge of SCLK, and data is clocked out on
the falling edge of SCLK.
• When CPHA = 1, data is clocked in on the falling edge of SCLK, and data is clocked out on
the rising edge of SCLK
For CPOL =1, the base (inactive) level of SCLK is 1.
In this mode:
• When CPHA = 0, data v in on the falling edge of SCLK, and data is clocked out on the
rising edge of SCLK
• When CPHA =1, data is clocked in on the rising edge of SCLK, and data is clocked out on
the falling edge of SCLK.
Mode
CPOL
CPHA
0
0
0
1
0
1
2
1
0
3
1
1
Table 15 - Clock Phase/Polarity Modes
Figure 6-3 - SPI CPOL CPHA Function
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6.3 Serial Peripheral Interface – Slave
CLK
SS#
External - SPI Master
MOSI
VNC2 - SPI Slave
MISO
Figure 6-4 SPI Slave block diagram
VNC2 has two SPI Slave modules both of which use four wire interfaces: MOSI, MISO, CLK and SS#.
Their main purpose is to send data from main memory to the attached SPI master, and / or receive data
and send it to main memory. The SPI Slave is controlled by the internal CPU using internal memory
mapped I/O registers. It operates from the main system clock, although sampling of input data and
transmission of output data is controlled by the SPI clock (CLK). An SPI transfer can only be initiated by
the SPI Master and begins with the slave select signal being asserted. This is followed by a data byte
being clocked out with the master supplying CLK. The master always supplies the first byte, which is
called a command byte. After this the desired number of data bytes are transferred before the
transaction is terminated by the master de-asserting slave select. An SPI Master is able to abort a
transfer at any time by de-asserting its SS# output. This will cause the Slave to end its current transfer
and return to idle state.
6.3.1 SPI Slave Signal Descriptions
64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
11, 15,
Name
Type
Description
Input
Slave clock input
spi_s0_clk
19, 24,
11, 15,
28, 39,
20, 31,
11, 23
43, 47,
35, 41,
29
51, 57,
45
spi_s1_clk
61
12, 16,
20, 25,
29, 40,
44, 48,
52, 58,
62
13, 17,
22, 26,
31, 41,
45, 49,
55, 59,
12,16,
spi_s0_mosi
21, 32,
12, 24,
36, 42,
30
Mater Out Slave In
spi_s1_mosi
Input
Synchronous data from master to slave
46
13, 18,
22, 33,
37, 43,
14, 25,
31
spi_s0_miso
Master In Slave Out
spi_s1_miso
Output
Synchronous data from slave to master
47
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64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
Name
Type
Description
63
14, 18,
23, 27,
14, 19,
32, 42,
23, 34,
15, 26,
46, 50,
38, 44,
32
56, 60,
48
spi_s0_ss#
Slave chip select
spi_s1_ss#
Input
64
Table 16 Data and Control Bus Signal Mode Options - SPI Slave Interface
6.3.2 Full Duplex
In full duplex mode, the SPI slave sends data on MISO line at the same time as it receives data on MOSI.
During the command phase this data is always the slave status byte. For a write command, write data
can be streamed out of MOSI and status can be sent during each write phase from slave to master. As
long as the slave status indicates that it can receive more data, the master can continue to stream
further write bytes. Figure 6-5 is an example of this.
SS#
MOSI
8 bit CMD
W0
W1
W2
MISO
STATUS
STATUS
STATUS
STATUS
Figure 6-5 Full Duplex Data Master Write
When the master is performing a data read, the data and status both need to share the same pin (MISO).
In this case the master and slave will exchange command and status bytes, followed by the slave sending
its data. If the Master keeps SS# active the Slave will send a further status byte after the data followed
by another data byte. This continues until the Master indicates the end of the communications by raising
SS#. Figure 6-6 is an example of this.
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SS#
MOSI
8 bit CMD
MISO
STATUS
R0
STATUS
R1
Figure 6-6 Full Duplex Data Master Read
The command and status formats for this mode can be seen in Figure 6-7 below with a description of
each field in Table 17:
Command:
Status:
A2
A1
A0
R/W#
Z
Z
Z
Z
Z
Z
Z
Z
TXE
RXF
ACK
Z
Figure 6-7 SPI Command and Status Structure
Field
Description
A2:A0
Address of slave being used in a multi-slave environment. This would typically be
used in the scenario where a shared data bus is used.
R/W#
Set to ‘1’ for a read and ‘0’ for a write.
Z
Tri-stated.
Transmit Empty.
TXE
When ‘1’ the Slave transmit buffer has no new data to transmit.
When ‘0’ the Slave transmit buffer does have new data.
Receive Full.
RXF
When ‘1’ the Slave receive buffer has new data which has not been read yet.
When ‘0’ the Slave receive buffer is empty and can be safely written to.
ACK
Set to ‘1’ when a Slave has correctly decoded its address.
Table 17 SPI Command and Status Fields
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6.3.3 Half Duplex, 4 pin
In half duplex mode, the MOSI signal is shared for both Master to Slave and Slave to Master
communications. When using 4 pins, the MISO signal carries the status bits. The Master initiates data
write transfer, this by asserting SS# and then sending out a command byte. This has the same format as
that shown in Figure 6-7. The Slave sends status during this command phase and if this indicates that
the Slave can accept data the Master will follow this up with a byte of write data. If the status continues
to indicate that more data can be written, a whole stream of data can be written following one single
command. The operation completes when the Master raises SS# again. Figure 6-8 is an example of this.
SS#
MOSI
8 bit CMD
W0
W1
W2
MISO
STATUS
STATUS
STATUS
STATUS
Figure 6-8 Half Duplex Data Master Write
Data reads are similar, apart from the MOSI pin changing from Slave input to Slave output after the
command phase. Figure 6-9 is an example. In this diagram, the Master drives the command while the
Slave returns with status. Then the MOSI buffers are turned round and a stream of read data is sent from
the Slave to the Master on the MOSI signal.
Master to Slave
Slave to Master
SS#
MOSI
8 bit CMD
R0
R1
R2
MISO
STATUS
STATUS
STATUS
STATUS
Figure 6-9 Half Duplex Data Master Read
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6.3.4 Half Duplex, 3 pin
The 3 pin half duplex mode eliminates the MISO pin from the protocol. This means that status bytes need
to be sent on the MOSI pin. Again the Master initiates a transfer by asserting SS# and sending out a
command byte. The Slave sends status back to the Master. If a write has been requested and the status
indicates that the Slave can accept data, MOSI should be changed to an output again and data will be
sent from Master to Slave.
Following this data, the Slave will send a further status byte if SS# remains active. If the status indicates
that more data can be written, the next data byte can be sent to the Slave and this process continues
until SS# is de-asserted. Figure 6-10 is an example of this:
Master to Slave
Slave to Master
Master to Slave
Slave to Master
Master to Slave
8 bit CMD
STATUS
W0
STATUS
W1
SS#
MOSI
Figure 6-10 Half Duplex 3-pin Data Master Write
Data reads are similar expect that after the command byte all data transfer is from Slave to Master.
Figure 6-11 is an example of this:
Master to Slave
Slave to Master
SS#
MOSI
8 bit CMD
STATUS
R0
STATUS
R1
Figure 6-11 Half Duplex 3-pin Data Master Read
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6.3.5 Unmanaged Mode
The VNC2 SPI Slave also supports an unmanaged SPI mode. This is a simple data exchange between
Master and Slave. It operates in the standard 4 pin mode (SS#, CLK, MOSI and MISO) with all transfers
controlled by the SPI Master.
When the CPU wants to send data out of the SPI Slave it writes this into the spi_slave_data_tx register.
This will then be moved into the transfer shift register to wait for the SPI Master to request it. The SPI
Master will at some point assert SS# and start clocking data on MOSI with SCK. As this is shifted into the
transfer shift register, the SPI Slave will also be shifting data in the opposite direction on MISO. At the
end of the transfer the SPI Slave copies the received data from the shift register to spi_slave_data_rx as
seen in Figure 6-12.
SPI Master
SPI Slave
SPI
Clk Div
ss#
clk
0
1
2
3
4
5
6
7
mosi
0
1
Shift Register
0
1
2
3
4
2
3
4
5
6
7
6
7
Rx Shift Register
5
6
0
7
Shift Register
miso
1
2
3
4
5
Tx Shift Register
Figure 6-12 Unmanaged Mode Transfer Diagram
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6.3.6 VNC1L Legacy Interface
VNC2 SPI is compatible with the SPI slave of VNC1L. This is a custom protocol using 4 wires and will be
explained here.
The Master asserts the slave select, but in this case it is an active high signal. Following this, a 3 bit
command is sent on the MOSI pin (see Figure 6-15 for command structure). This has instructions on
whether a read or write is requested and if data or status is to be sent. For a data write, 8 bits of data
are sent on MOSI followed by a status bit being returned on MISO. If this bit is „0‟ it means the data write
was successful. If it is „1‟ it means that internal buffer was full and the write should be repeated. Finally,
the slave select is de-asserted. See Figure Figure 6-13 for an example of this:
Figure 6-13 VNC1L Mode Data Write
Data reads are similar, with the data from Slave to Master coming on the MISO pin. If the status bit is „0‟
it means the data byte sent is new data that has not been read before. If it is „1‟ it means that it is old
data. See Figure 6-14 for an example.
Figure 6-14 VNC1L Mode Data Read
The command and status formats for this mode can be seen in Figure 6-16 below with a description of
each field in Table 18.
Command:
Start
R/W
Addr
Data:
D7
D6
D5
Status:
Status
D4
D3
D2
D1
D0
Figure 6-15 VNC1L Compatible SPI Command and Status Structure
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Field
Description
Start
Driven to ‘1’.
R/W
If set to ‘1’, the SPI Master wishes to read from the slave. If set to ‘0’, the
SPI Master wishes to write to the slave.
Addr
If set to ‘1’, a read operation will return the status byte in the data phase.
A write will have no effect.
If set to ‘0’, a read or a write will operate on the data register.
D7:D0
Data.
Status
When ‘0’ this means a read or write was successful. When ‘1’ it means a
read contains old data, or a write did not work and needs retried.
Table 18 SPI Command and Status Fields
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6.3.6.1 SPI Setup Bit Encoding
The VNC1L compatible SPI interface differs from most other implementations in that it uses a 12 clock
sequence to transfer a single byte of data. In addition to a „Start‟ state, the SPI master must send two
setup bits which indicate data direction and target address. The encoding of the setup bits is shown in
Table 19. A single data byte is transmitted in each SPI transaction, with the most significant bit
transmitted first.
After each transaction VNC2 returns a single status bit. This indicates if a Data Write was successful or a
Data Read was valid.
Direction
(R/W)
Target
Address
Operation
Meaning
1
0
Data Read
Retrieve byte from Transmit Buffer
1
1
Status Read
Read SPI Interface Status
0
0
Data Write
Add byte to Receive Buffer
0
1
N/A
N/A
Table 19 SPI Setup Bit Encoding
The VNC2 SPI interface uses 4 signal lines: SCLK, SS, MOSI and MISO. The signals MOSI, MISO and SS
are always clocked on the rising edge of the SCLK signal.
SS signal must be raised high for the duration of the entire transaction. For data transactions, the SS
must be released for at least one clock cycle after a transaction has completed. It is not necessary to
release SS between Status Read operations.
The „Start‟ state of MOSI and SS high on the rising edge of SCLK initiates the transfer. The transfer
finishes after 13 clock cycles, and the next transfer starts when MOSI is high during the rising edge of
CLK.
The following Figure 6-16 and Table 20 give details of the bus timing requirements.
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Figure 6-16 SPI Slave Mode Timing
Time
Description
Minimum
Typical
Maximum
Unit
T1
SCLK period
79.37
83.33
T2
SCLK high period
39.68
41.67
39.68
ns
T3
SCLK low period
39.68
41.67
39.68
ns
T4
SCLK driving edge to
MISO/MOSI
0.5
T5
MISO/SS setup time to
sample SCLK edge
T6
MISO/SS hold time from
sample SCLK edge
ns
14
3
3
ns
ns
ns
Table 20 SPI Slave Data Timing
6.3.6.2 SPI Master Data Read Transaction in VNC1L legacy mode
The SPI master must periodically poll for new data in VNC2 Transmit Buffer. It is recommended that this
is done first before sending any command.
The Start and Setup sequence is sent to VNC2 by the SPI master, see Figure 6-17.
The VNC2 clocks out data from its Transmit Buffer on subsequent rising edge clock cycles provided by the
SPI master. This is followed by a status bit generated by VNC2. The Data Read status bit is defined in
Table 21.
If the status bit indicates New Data then the byte received is valid. If it indicates Old Data then the
Transmit Buffer in VNC2 is empty and the byte of data received in the current transaction should be
disregarded.
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Status Bit
Meaning
0
New Data
Data in current transaction is valid data.
Byte removed from Transmit Buffer.
1
Old Data
This same data has been read in a previous read cycle.
Repeat the read cycle until New Data is received.
Table 21 SPI Master Data Read Status Bit
Figure 6-17 SPI Master Data Read (VNC2 Slave Mode)
The status bit is only valid until the next rising edge of SCLK after the last data bit.
During the Data Read operation the SS signal must not be de-asserted.
The transfer completes after 12 clock cycles and the next transfer can begin when MOSI and SS are high
during the rising edge of SCLK.
6.3.6.3 SPI Master Data Write Transaction in VNC1L legacy mode
During an SPI master Data Write operation the Start and Setup sequence is sent by the SPI master to
VNC2, see Figure 6-18. This is followed by the SPI master transmitting each bit of the data to be written
to VNC2. The VNC2 then responds with a status bit on MISO on the rising edge of the next clock cycle.
The SPI master must read the status bit at the end of each write transaction to determine if the data was
written successfully to VNC2 Receive Buffer. The Data Write status bit is defined in Table 22.The status
bit is only valid until the next rising edge of SCLK after the last data bit.
If the status bit indicates Accept then the byte transmitted has been added to VNC2 Receive Buffer. If it
shows Reject then the Receive Buffer is full and the byte of data transmitted in the current transaction
should be re-transmitted by the SPI master to VNC2.
Any application should poll VNC2 Receive Buffer by retrying the Data Write operation until the data is
accepted.
Status Bit
Meaning
0
Accept
Data from the current transaction was accepted and added to the
Receive Buffer
1
Reject
Write data was not accepted.
Retry the same write cycle.
Table 22 SPI Master Data Write Status Bit
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Figure 6-18 SPI Slave Mode Data Write
6.3.6.4 SPI Master Status Read Transaction in VNC1L legacy mode
The VNC2 has a status byte which determines the state of the Receive and Transmit Buffers. The SPI
master must poll VNC2 and read the status byte.
The Start and Setup sequence is sent to VNC2 by the SPI master, see Figure 6-19. The VNC2 clocks out
its status byte on subsequent rising edge clock cycles from the SPI master. This is followed by a status
bit generated by VNC2 (also on the MISO) which will always be zero (indicating new data).
The meaning of the bits within the status byte sent by VNC2 during a Status Read operation is described
in Table 23. The result of the Status Read transaction is only valid during the transaction itself. Data
read and data write transactions must still check the status bit during a Data Read or Data Write cycle
regardless of the result of a Status Read operation.
Bit
Description
Description
0
RXF#
Receive Buffer Full
1
TXE#
Transmit Buffer Empty
2
-
Not used
3
-
Not used
4
RXF IRQEn
Receive Buffer Full Interrupt Enable
5
TXE IRQEn
Transmit Buffer Empty Interrupt Enable
6
-
Not used
7
-
Not used
Table 23 SPI Status Read Byte – bit descriptions
Figure 6-19 SPI Slave Mode Status Read
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6.4 Serial Peripheral Interface – SPI Master
CLK
SS#
VNC2 - SPI Master
MOSI
External - SPI Slave
MISO
Figure 6-20 SPI Master block diagram
The SPI Master interface is used to interface to applications such as SD Cards. The SPI Master provides
the following features:
Synchronous serial data link.
Full and half duplex data transmission.
Serial clock with programmable frequency, polarity and phase.
One slave select output.
Programmable delay between negative edge of slave select and start of transfer.
SD Card interface.
An interface that‟s compatible with the VLSI VS1033 SCI mode used for VMUSIC capability
The SPI Master only clocks in and out data that the VNC2 CPU sets up in its register space. The VNC2
CPU interprets the data words that are to be sent and received.
6.4.1 SPI Master Signal Descriptions.
Table 24 shows the SPI master signals and the available pins that they can be mapped to depending on
the package size. Further details on the configuration of input and output signals are available in Section
5 - I/O Multiplexer.
64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
Name
Type
spi_m_clk
Output
Description
11, 15,
19, 24,
11, 15,
28, 39,
20, 31,
11, 23
43, 47,
35, 41,
29
51, 57,
45
SPI master clock input
61
12, 16,
20, 25,
29, 40,
44, 48,
52, 58,
62
13, 17,
12,16,
Master Out Slave In
21, 32,
12, 24,
36, 42,
30
spi_m_mosi
Output
Synchronous data from master to slave
Input
Master In Slave Out
46
13, 18,
14, 25,
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64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
22, 26,
22, 33,
31
31, 41,
37, 43,
45, 49,
47
Name
Type
spi_m_miso
Description
Synchronous data from slave to master
55, 59,
63
14, 18,
23, 27,
14, 19,
32, 42,
23, 34,
15, 26,
46, 50,
38, 44,
32
56, 60,
48
Active low slave select 0 from master to
spi_m_ss_0#
Output
slave 0
64
11, 15,
19, 24,
11, 15,
28, 39,
20, 31,
11, 23
43, 47,
35, 41,
29
51, 57,
45
Active low slave select 1 from master to
spi_m_ss_1#
Output
slave 1
61
Table 24 SPI Master Signal Names
The main purpose of the SPI Master block is to transfer data between an external SPI interface and the
VNC2. It does this under the control of the CPU and DMA engine via the on chip I/O bus.
An SPI master interface transfer can only be initiated by the SPI Master and begins with the slave select
signal being asserted. This is followed by a data byte being clocked out with the master supplying SCLK.
The master always supplies the first byte, which is called a command byte. After this the desired number
of data bytes are transferred before the transaction is terminated by the master de-asserting slave
select.
The SPI Master will transmit on MOSI as well as receive on MISO during every data stage. At the end of
each byte spi_tx_done and spi_rx_full_int are set. Figure 6-21 Typical SPI Master Timing and Table
25 SPI Master Timing show an example of this.
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Figure 6-21 Typical SPI Master Timing
Time
Description
Minimum
Typical
Maximum
t1
SCLK period
79.37
83.33
t2
SCLK high period
39.68
41.67
43.86
ns
t3
SCLK low period
39.68
41.67
43.86
ns
t4
SCLK driving edge to
MOSI/SS
-3
t5
MISO setup time to sample
SCLK edge
t6
MISO hold time from sample
SCLK edge
ns
6
13
0
Unit
ns
ns
ns
Table 25 SPI Master Timing
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6.5 Debugger Interface
The purpose of the debugger interface is to provide the Integrated Development Environment (IDE) with
the following capabilities:
Flash Erase, Write and Program.
Application debug - application code can have breakpoints, be single stepped and can be halted.
Detailed internal debug - memory read/write access.
The single wire interface has the following features:
Half Duplex Operation
1Mbps speed
1 start bit
1 stop bit
8 data bits
Pull up
6.5.1
Debugger Interface Signal description
64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
Name
Type
Description
Input/
Debugger Interface
11, 15,
19, 24,
11, 15,
28, 39,
20, 31,
11, 23
43, 47,
35, 41,
29
51, 57,
45
debug_if
Output
61
Table 26 Debugger Signal Name
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6.6 Parallel FIFO – Asynchronous Mode
Parallel FIFO Asynchronous mode known as „245‟, is functionally the same as the one that is present in
VNC1L has an eight bit data bus, individual read and write strobes and two hardware flow control signals.
6.6.1 FIFO Signal Descriptions
The Parallel FIFO interface signals are described in Table 27 They can be programmed to a choice of I/O
pins depending on the package size. Further details on the configuration of input and output signals are
available in Section 5 - I/O Multiplexer.
64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
Name
Type
Description
fifo_data[0]
I/O
FIFO Data Bus Bit 0
fifo_data[1]
I/O
FIFO Data Bus Bit 1
fifo_data[2]
I/O
FIFO Data Bus Bit 2
fifo_data[3]
I/O
FIFO Data Bus Bit 3
11, 15,
19, 24,
11, 15,
28, 39,
20, 31,
11, 23
43, 47,
35, 41,
29
51, 57,
45
61
12, 16,
20, 25,
29, 40,
44, 48,
52, 58,
62
12,16,
21, 32,
12, 24,
36, 42,
30
46
13, 17,
22, 26,
13, 18,
31, 41,
22, 33,
45, 49,
37, 43,
55, 59,
47
14, 25,
31
63
14, 18,
23, 27,
14, 19,
32, 42,
23, 34,
15, 26,
46, 50,
38, 44,
32
56, 60,
48
64
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64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
Name
Type
Description
fifo_data[4]
I/O
FIFO Data Bus Bit 4
fifo_data[5]
I/O
FIFO Data Bus Bit 5
fifo_data[6]
I/O
FIFO Data Bus Bit 6
fifo_data[7]
I/O
FIFO Data Bus Bit 7
11, 15,
19, 24,
11, 15,
28, 39,
20, 31,
11, 23
43, 47,
35, 41,
29
51, 57,
45
61
12, 16,
20, 25,
29, 40,
44, 48,
52, 58,
62
12,16,
21, 32,
12, 24,
36, 42,
30
46
13, 17,
22, 26,
13, 18,
31, 41,
22, 33,
45, 49,
37, 43,
55, 59,
47
14, 25,
31
63
14, 18,
23, 27,
14, 19,
32, 42,
23, 34,
15, 26,
46, 50,
38, 44,
32
56, 60,
48
64
11, 15,
When high, do not read data from the
19, 24,
11, 15,
28, 39,
20, 31,
11, 23
43, 47,
35, 41,
29
51, 57,
45
61
FIFO.
fifo_rxf#
Output
When low, there is data available in the
FIFO which can be read by strobing
fifo_rd# low, then high.
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64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
Name
Type
Description
12, 16,
20, 25,
29, 40,
44, 48,
52, 58,
62
When high, do not write data into the
12,16,
21, 32,
12, 24,
36, 42,
30
FIFO.
fifo_txe#
Output
When low, data can be written into the
FIFO by strobing fifo_wr# high, then low.
46
13, 17,
22, 26,
13, 18,
31, 41,
22, 33,
45, 49,
37, 43,
55, 59,
47
Enables the current FIFO data byte on
D0...D7 when low. Fetches the next FIFO
14, 25,
31
fifo_rd#
Input
data byte (if available) from the receive
FIFO buffer when fifo_rd# goes from high
to low
63
14, 18,
23, 27,
14, 19,
32, 42,
23, 34,
15, 26,
46, 50,
38, 44,
32
56, 60,
48
Writes the data byte on the D0...D7 pins
fifo_wr#
Input
into the transmit FIFO buffer when
fifo_wr# goes from high to low.
64
Table 27 Data and Control Bus Signal Mode Options - Parallel FIFO Interface
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6.6.2 Read / Write Transaction Asynchronous FIFO Mode
When in Asynchronous FIFO interface mode, the timing of read and write operations on the FIFO
interface are shown in Figure 6-22 and Table 28.
In asynchronous mode an external device can control data transfer driving FIFO_WR# and FIFO_RD#
inputs. In contrast to synchronous mode, in asynchronous mode the 245 FIFO module generates the
output enable EN# signal. EN# signal is effectively the read signal RD#.
Current byte is available to be read when FIFO_RD# goes low. When FIFO_RD# goes high, FIFO_RXF#
output will also go high. It will only become low again when there is another byte to read.
When FIFO_WR# goes low FIFO_TXE# flag will always go high. FIFO_TXE# goes low again only when
there is still space for data to be written in to the module.
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Figure 6-22 Asynchronous FIFO mode Read / Write Cycle
Time
Description
Minimum
Maximum
Unit
t1
RD# inactive to RXF#
1
14
ns
t2
RXF# inactive after RD# cycle
100
t3
RD# to DATA
1
t4
RD# active pulse width
30
ns
t5
RD# active after RXF#
0
ns
t6
WR# active to TXE# inactive
1
t7
TXE# inactive after WR# cycle
100
ns
t8
DATA to TXE# active setup time
5
ns
t9
DATA hold time after WR#
inactive
5
t10
WR# active pulse width
30
ns
t11
WR# active after TXE#
0
ns
ns
14
14
ns
ns
ns
Table 28 Asynchronous FIFO mode Read / Write Timing
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6.7 Parallel FIFO – Synchronous Mode
The Parallel FIFO Synchronous mode has an eight bit data bus, individual read and write strobes, two
hardware flow control signals, an output enable and a clock out.
The synchronous FIFO mode uses the parallel FIFO interface signals detailed in Table 27 and an
additional two signals detailed in Table 29.
This mode is not available on the 32 pin packages.
64 Pin
Package
48 Pin
Package
32 Pin
Package
Available
pins
Available
pins
Available
pins
Name
Type
Description
fifo_oe#
I/O
FIFO Output enable
fifo_clkout
I/O
FIFO Clock out
11, 15,
19, 24,
11, 15,
28, 39,
20, 31,
11, 23
43, 47,
35, 41,
29
51, 57,
45
61
12, 16,
20, 25,
29, 40,
44, 48,
52, 58,
62
12,16,
21, 32,
12, 24,
36, 42,
30
46
Table 29 Synchronous FIFO control signals
6.7.1 Read / Write Transaction Synchronous FIFO Mode
When in Synchronous FIFO interface mode, the timing of read and write operations on the FIFO interface
are shown in Figure 6-23 Synchronous FIFO mode Read / Write Cycle and Table 30 Synchronous
FIFO mode Read / Write Timing
In synchronous mode data can be transmitted to and from the FIFO module on each clock edge. An
external device synchronises to the CLKOUT output and it also has access to the output enable OE# input
to control data flow. An external device should drive output enable OE# low before pulling RD# line
down.
When bursts of data are to be read from the module RD# should be kept low. RXF# remains low when
there is still data to be read. Similarly when bursts of data are to be written to the module WR# should
be kept low. TXE# remains low when there is still space available for the data to be written.
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Figure 6-23 Synchronous FIFO mode Read / Write Cycle
Time
Description
Minimum
Typical
Maximum
Unit
t1
CLKOUT period
t2
CLKOUT high period
9.38
10.42
11.46
ns
t3
CLKOUT low period
9.38
10.42
11.46
ns
t4
CLKOUT to RXF#
1
7.83
ns
t5
CLKOUT to read DATA
valid
1
7.83
ns
t6
OE# to read DATA valid
1
7.83
ns
t7
CLKOUT to OE#
1
7.83
ns
t8
RD# setup time
12
ns
t9
RD# hold time
0
ns
ns
20.83
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Time
Description
t10
CLKOUT TO TXE#
t11
Write DATA setup time
t12
Write DATA hold time
t13
WR# setup time
t14
WR# hold time
Minimum
Typical
1
Maximum
7.83
Unit
ns
12
ns
0
ns
12
ns
0
ns
Table 30 Synchronous FIFO mode Read / Write Timing
6.8 General Purpose Timers
In VNC2 there are 4 General Purpose Timers available. Three are available to the designer and one is
reserved for the RTOS.
The timers have the following features:
16 bit
Count down
One shot and auto-reload
enable
Interrupt on zero
6.9 Pulse Width Modulation
VNC2 provides 8 Pulse Width Modulation (PWM) outputs. These can be used to generate PWM signals
which can be used to control motors, DC/DC converters, AC/DC supplies, etc.
The features of the PWM module are as follows:
-
8 PWM outputs
-
A trigger input
-
8-bit prescaler
-
16-bit counter
-
Generation of up to 4-pulse signal with controlled output enable and configurable initial state
-
Interrupt
A single PWM cycle can have up to 4 pulses (8 edges). The PWM block uses a 16-bit counter to
determine the period of a single PWM cycle. This counter counts system clocks which can also be divided
by an optional 8-bit prescaler. The PWM drivers allow the user to select when PWM output toggles. These
values correspond to the values of 16-bit counter. For example, on the timing diagram below - Figure
6-24, the 16-bit counter counts to 23 and pwm_out[0] output toggles when the counter‟s current value
is equal to 7, 8, 12, 14, 15, 16, 19 and 22.
Figure 6-24 PWM – Timing Diagram
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The user can also select the initial state of each of the PWM outputs (HI or LOW). PWM outputs can also
be enabled continuously or a cycle can be repeated 1..255 times. The PWM cycle can be started by the
PWM driver or externally using a trigger input.
6.10 General Purpose Input Output
VNC2 provides up to 44 Input Output ports depending on the package. These ports are controlled by the
VNC2 CPU. All ports are configurable to be either inputs or outputs and allow level or edge driven
interrupts to be generated.
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7
USB Interfaces
VNC2 has two USB 1.1 and USB 2.0 compliant interfaces available either as a USB host or slave device
capable of supporting 1.5Mb/s (Low Speed) and 12Mb/s (full Speed) transactions. The USB specification
defines 4 transfer types that are all supported by VNC2:

Interrupt transfer: Used for legacy devices where the device is periodically polled to see if the
device has data to transfer e.g. Mouse, Keyboard.

Bulk Transfer: Used for transferring large blocks of data that have no periodic or transfer rate
requirement e.g. USB to RS232 (FT232R device), memory sticks.

Isochronous Transfer: Used for transferring data that requires a constant delivery rate e.g.
web cam, wireless modem.

Control Transfer: Used to transfer specific requests to all types USB devices (most commonly
used during device configuration).
USB 2.0 - 480Mb/s (High Speed) transactions shall not be supported as the power requirements are
deemed excessive for VNC2 target applications. VNC2 configured to Full speed is supported.
VNC2 has two main USB modes of operation: host mode or client (or Slave) mode. As a client, VNC2 is
able to connect to a PC and act like a USB device. At the same time as being a client the second USB
interface is also able to act as a host and connect to a second USB device using two separate ports i.e.
Port 0 – Host Port 1- Client. Each USB interface can be either a host or a client not both at the same
time. The following diagrams in figure 7.1 give examples of possible modes of operation:
Port 0
USB Device
Port 0
USB Host
VNC2
VNC2
Port 1
Port 1
BOMS Flash Disk
Port 0 in Slave mode
Port 0 and 1 in Host mode
Port 0
Port 0
USB Host
VNC2
USB Host
VNC2
Port 1
BOMS Flash Disk
Port 0 in Slave mode and Port 1 in Host mode
Port 1
USB Host
Port 0 and 1 in Slave mode (Null Modem type application)
Figure 7-1 USB Modes
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8
Firmware
VNC2 firmware model has evolved considerably since VINC1L. For reasons of code maintainability,
performance, stability and ease of use from the point of view of the customer, VNC2 has a modular
firmware model.
VNC2 firmware can be separated into 4 categories:
VNC2 real-time operating system (RTOS).
VNC2 device drivers.
User applications – Tool Chain.
Precompiled Firmware.
8.1 RTOS
The VNC2 RTOS (VOS) is a pre-emptive priority-based multi-tasking operating system. VOS has been
developed by FTDI and is available to customers for use in their own VNC2 based systems free of charge.
VOS is supplied as linkable object files.
A full explanation and how to use VOS is available in a separate application note which can be
downloaded from the FTDI website.
8.2 Device drivers
To facilitate communication between user applications and the VNC2 hardware peripherals FTDI provides
device drivers which operate with VOS. In addition to the hardware device drivers, FTDI provides
function drivers (available from the FTDI website) which build upon the basic hardware device driver
functionality for a specific purpose. For example, drivers for standard USB device classes may be created
which build upon the USB host hardware driver to implement a BOMS class, CDC, printer class or even a
specific vendor class device driver.
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8.3 Firmware – Software Deveolment Tool Chain
The VNC2 provides customers with the opportunity to customise the firmware and perform useful tasks
without an external MCU. A Firmware application note is available to download from the FTDI website,
this give further details and operating instructions. The VNC2 Software Development tool chain consists
of the following components:
Compiler
The compiler will take high-level source code and compile it into object code or direct to
programmable code.
Linker
The linker will take object code and libraries and link the code to produce either libraries or
programmable code. It is designed to be as hardware independent as possible to allow reuse in
future hardware devices.
Debugger
The debugger allows a programmer to test code on the hardware platform using a special
communication channel to the CPU. It is also used to debug code – run, stop, single step,
breakpoints etc.
IDE
All compiler, simulator and debugger functions are integrated into a single application for
programmers. It provides a specialised text editor which is used generally used to develop
application code, debugging and simulation.
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8.4 Precompiled Firmware
VNC2 can be programmed with various pre-compiled firmware profiles to allow a designer to easily
change the functionality of the chip.
VNC2 is currently available with V2DAP firmware - V2DAP firmware: USB Host for single Flash Disk and
general purpose USB peripherals. Selectable UART, FIFO or SPI interface command monitor.
Designers are advised to refer to the FTDI website for full details on available Firmware.
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9
Device Characteristics and Ratings
9.1 Absolute Maximum Ratings
The absolute maximum ratings for VNC2 are shown in Table 31. These are in accordance with the
Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the
device.
Parameter
Value
Unit
Storage Temperature
-65°C to 150°C
Degrees C
Floor Life (Out of Bag) At Factory Ambient
( 30°C / 60% Relative Humidity)
168 Hours
(IPC/JEDEC J-STD-033A MSL Level 3
Hours
Compliant)*
Ambient Temperature (Power Applied)
-40°C to 85°C
Degrees C.
Vcc Supply Voltage
0 to +3.63
V
VCC_IO
0 to +3.63
V
VCC_PLL_IN
0 to + 1.98
V
DC Input Voltage - USBDP and USBDM
-0.5 to +(Vcc +0.5)
V
-0.5 to +5.00
V
DC Input Voltage - All other Inputs
-0.5 to +(Vcc +0.5)
V
DC Output Current - Outputs
Default 4 **
mA
Default 4 **
mA
DC Input Voltage - High Impedance
Bidirectional
DC Output Current - Low Impedance
Bidirectional
Table 31 Absolute Maximum Ratings
*
If devices are stored out of the packaging beyond this time limit the devices should be baked
before use. The devices should be ramped up to a temperature of 125°C and baked for up to 17
hours.
** The drive strength of the output stage may be configured for either 4mA, 8mA, 12mA or 16mA
depending on the register setting controlled within the firmware. The default is 4mA.
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9.2 DC Characteristics
DC Characteristics (Ambient Temperature -40˚C to +125˚C)
Parameter
Vcc1
Vcc2
VCC_PLL
Description
VCC Operating Supply
Voltage
VCCIO Operating Supply
Voltage
VCC_PLL Operating
Supply Voltage
Minimum
Typical
Maximum
Units
1.62
1.8
1.98
V
2.97
3.3
3.63
V
1.62
1.8
1.98
V
Operating Supply Current
Icc1
25
mA
TBD
mA
8
mA
128
µA
48MHz
Conditions
Normal
Operation
Operating Supply Current
Icc2
Low Power Mode
24MHz
Operating Supply Current
Icc3
12MHz
Icc4
Operating Supply Current
Lowest Power
Mode
USB Suspend
Table 32 Operating Voltage and Current
Parameter
Description
Minimum
Voh
Output Voltage High
2.4
Vol
Output Voltage Low
Vin
Input Switching
Threshold
Typical
Maximum
0.4
1.5
Units
Conditions
V
I source = 8mA
V
I sink = 8mA
V
Table 33 I/O Pin Characteristics
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Parameter
UVoh
UVol
UVse
UCom
UVdif
UDrvZ
Description
I/O Pins Static Output
( High)
Minimum
Typical
2.8
0.3
V
0.8
2.0
V
0.8
2.5
V
( Low )
Threshold
Differential Common
Mode
Differential Input
Sensitivity
Driver Output
Impedance
Units
0.2
3
Conditions
V
I/O Pins Static Output
Single Ended Rx
Maximum
V
6
9
Ohms
Table 34 USB I/O Pin (USBDP, USBDM) Characteristics
Parameter
Description
Voh
Output Voltage High
Vol
Output Voltage Low
Vin
Input Switching
Threshold
Minimum
Typical
Units
Conditions
TBD
V
Fosc = 12MHz
TBD
V
Fosc = 12MHz
TBD
V
V
VREG_OUT
Output Voltage
TBD
F
Frequency
TBD
Lc
Load Capacitance
TBD
Maximum
Table 35 XTIN, XOUT Pin Characteristics
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10 Application Examples
10.1 Example VNC2 Schematic (MCU – UART Interface)
VNC2 can be configured to communicate with a microcontroller using a UART interface. An example of
this is shown in Figure 10-1.
4.7uF
GND
100nF
GND
Ferrite
Bead
Ferrite
Bead
5V
100nF
GND
3V3
4.7uF
I
O
G
100nF
3V3
4.7uF
GND
GND
Vcc
GND
V
C
C
I
O
5
47pF
V
C
C
I
O
V
C
C
I
O
V
C
C
47pF
26
GND
25
GND
27R
29
27R
28
27pF
GND
27pF
4
12MHz
5
V
R
E
G
O
U
T
USB1DM
9
47k
10
8
A
V
C
C
IOBUS12
IOBUS13
IOBUS14
IOBUS15
IOBUS16
IOBUS17
IOBUS18
IOBUS19
31 TXD
32 RXD
33 RTS#
34 CTS#
35
36
37
38
TXD
RXD
RTS#
CTS#
USB1DP
USB2DM
USB2DP
XTIN
XTOUT
VNC2-48L
3V3
47k
3
7
2
17
1
2
3
4
30
40
USB A
Connector
100nF
3.3V LDO
Regulator
RESET#
PROG#
IOBUS20
IOBUS21
IOBUS22
IOBUS23
IOBUS24
IOBUS25
IOBUS26
IOBUS27
IOBUS0
IOBUS1
IOBUS2
IOBUS3
IOBUS4
IOBUS5
IOBUS6
IOBUS7
TEST
GND
G
N
D
GGG G
N N N N
D D D D
IOBUS8
IOBUS9
IOBUS10
IOBUS11
41
42
43
44
45
46
47
48
GND
Microcontroller
11
12
13
14
15
16
18
19
20
21
22
23
3V3
330R
330R
24
1
39
27
6
GND
Figure 10-1 VNC2 Schematic (MCU - UART Interface)
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11 Package Parameters
VNC2 is available in six RoHS Compliant packages, three QFN packages (64QFN, 48QFN & 32QFN) and
three LQFP packages (64LQFP, 48LQFP & 32LQFP). All packages are lead (Pb) free and use a „green‟
compound. The packages are fully compliant with European Union directive 2002/95/EC.
The mechanical drawings of all six packages are shown in sections 11.2 to 11.7– all dimensions are in
millimetres.
The solder reflow profile for all packages can be viewed in Section 11.8.
11.1 VNC2 Package Markings
An example of the markings on each package are shown in Figure 11-1. The FTDI part number is too
long for the 32 QFN package so in this case the last two digits are wrapped down onto the date code line
as shown in Figure 11-2.
FTDl
Line 1 – FTDI Logo
XXXXXXXXXX
Line 2 – Wafer Lot Number
VNC2-64Q1A
Line 3 – FTDI Part Number
including revision
YYWW
Line 4 - Date Code
YY - year year
WW - work week
Figure 11-1 Package Markings
FTDl
XXXXXXXXXX
VNC2-32Q
1A YYWW
Figure 11-2 Markings – 32 QFN
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11.2 VNC2, LQFP-32 Package Dimensions
FTDl
XXXXXXXX
VNC2-32L1A
YYWW
PIN #32
PIN #1
Figure 11-3 LQFP-32 Package Dimensions
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11.3 VNC2, QFN-32 Package Dimensions
FTDl
XXXXXXXX
VNC2-32Q
1A YYWW
1
1
Figure 11-4 QFN-32 Package Dimensions
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11.4 VNC2, LQFP-48 Package Dimensions
9
7
FTDl
XXXXXXXX
VNC2-48L1A
YYWW
7
9
PIN# 48
Pin# 1
0.22+/- 0.05
0.5
1.0
0. 24 +/- 0.07
o
1.4 +/- 0.05
1.60
MAX
12 +/- 1o
0. 05 Min
0. 15 Max
0. 09 Min
0. 16 Max
0. 09 Min
0. 2 Max
0.25
0. 22 +/- 0.05
0. 2 Min
0. 6 +/- 0.15
Figure 11-5 LQFP-48 Package Dimensions
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11.5 VNC2, QFN-48 Package Dimensions
FTDl
XXXXXXXXXX
VNC2-48Q1A
YYWW
48
1
1
48
Figure 11.2 QFN-48 Package Dimensions
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11.6 VNC2, LQFP-64 Package Dimensions
12
10
FTDl
10
XXXXXXXX
VNC2-64L1A
YYWW
12
Pin # 64
Pin # 1
0.5
1.0
0. 22+/- 0.05
1.4 +/- 0.05
1.60
MAX
12o +/- 1o
Mi
0.05Ma
0.15 n
x
0.25
0.2
Mi
n
0.6 +/-0.15
0. 09 Min
0. 16 Max
0. 09 Min
0. 2 Max
0.2+/- 0.03
Figure 11-6 64 pin LQFP Package Details
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11.7 VNC2, QFN-64 Package Dimensions
FTDl
XXXXXXXXXX
VNC2-64Q1A
YYWW
Figure 11-7 64 pin QFN Package Details
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11.8 Solder Reflow Profile
Figure 11-8 All packages Reflow Solder Profile
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Pb Free Solder Process
SnPb Eutectic and Pb free (non
(green material)
green material) Solder Process
3°C / second Max.
3°C / Second Max.
Profile Feature
Average Ramp Up Rate (Ts to Tp)
Preheat
- Temperature Min (Ts Min.)
150°C
100°C
- Temperature Max (Ts Max.)
200°C
150°C
- Time (ts Min to ts Max)
60 to 120 seconds
60 to 120 seconds
217°C
183°C
60 to 150 seconds
60 to 150 seconds
260°C
see Table 37
30 to 40 seconds
20 to 40 seconds
Ramp Down Rate
6°C / second Max.
6°C / second Max.
Time for T= 25°C to Peak Temperature, Tp
8 minutes Max.
6 minutes Max.
Volume mm3 < 350
Volume mm3 >=350
< 2.5 mm
235 +5/-0 deg C
220 +5/-0 deg C
≥ 2.5 mm
220 +5/-0 deg C
220 +5/-0 deg C
Time Maintained Above Critical Temperature
TL:
- Temperature (TL)
- Time (tL)
Peak Temperature (Tp)
Time within 5°C of actual Peak Temperature
(tp)
Table 36 Reflow Profile Parameter Values
SnPb Eutectic and Pb free (non green material)
Package Thickness
Pb Free (green material) = 260 +5/-0 deg C
Table 37 Package Reflow Peak Temperature
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12 Contact Information
Head Office – Glasgow, UK
Future Technology Devices International Limited
Unit 1, 2 Seaward Place,
Glasgow G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
E-mail (Sales) [email protected]
E-mail (Support) [email protected]
E-mail (General Enquiries) [email protected]
Web Site URL http://www.ftdichip.com
Web Shop URL http://www.ftdichip.com
Branch Office – Taipei, Taiwan
Future Technology Devices International Limited (Taiwan)
2F, No. 516, Sec. 1, NeiHu Road
Taipei 114
Taiwan , R.O.C.
Tel: +886 (0) 2 8797 1330
Fax: +886 (0) 2 8751 9737
E-mail (Sales)
[email protected]
E-mail (Support)
[email protected]
E-mail (General Enquiries) [email protected]
Web Site URL
http://www.ftdichip.com
Branch Office – Hillsboro, Oregon, USA
Future Technology Devices International Limited (USA)
7235 NW Evergreen Parkway, Suite 600
Hillsboro, OR 97123-5803
USA
Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-Mail (Sales)
[email protected]
E-Mail (Support) [email protected]
E-Mail (General Enquiries) [email protected]
Web Site URL
http://www.ftdichip.com
Branch Office – Shanghai, China
Future Technology Devices International Limited (China)
Room 408, 317 Xianxia Road,
ChangNing District,
ShangHai, China
Tel: +86 (21) 62351596
Fax: +86(21) 62351595
E-Mail (Sales): [email protected]
E-Mail (Support): [email protected]
E-Mail (General Enquiries): [email protected]
Web Site URL: http://www.ftdichip.com
Distributor and Sales Representatives
Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and
sales representative(s) in your country.
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Appendix A – List of Figures and Tables
List of Tables
Table 1 Part Numbers .................................................................................................................... 3
Table 2 Acronyms and Abbreviations ............................................................................................... 4
Table 3 USB Interface Group ........................................................................................................ 18
Table 4 Power and Ground ........................................................................................................... 18
Table 5 Miscellaneous Signal Group ............................................................................................... 19
Table 6 Default I/O Configuration ................................................................................................. 22
Table 7 - Peripheral Pin Requirements ........................................................................................... 24
Table 8 I/O Peripherals Signal Names ........................................................................................... 31
Table 9 Group 0.......................................................................................................................... 33
Table 10 Group 1 ........................................................................................................................ 34
Table 11 Group 2 ........................................................................................................................ 35
Table 12 Group 3 ........................................................................................................................ 36
Table 13 Data and Control Bus Signal Mode Options – UART Interface ............................................... 40
Table 14 SPI Signal Names .......................................................................................................... 41
Table 15 - Clock Phase/Polarity Modes........................................................................................... 42
Table 16 Data and Control Bus Signal Mode Options - SPI Slave Interface ........................................ 44
Table 17 SPI Command and Status Fields ...................................................................................... 45
Table 18 SPI Command and Status Fields ...................................................................................... 50
Table 19 SPI Setup Bit Encoding ................................................................................................... 51
Table 20 SPI Slave Data Timing .................................................................................................... 52
Table 21 SPI Master Data Read Status Bit ...................................................................................... 53
Table 22 SPI Master Data Write Status Bit ..................................................................................... 53
Table 23 SPI Status Read Byte – bit descriptions ............................................................................ 54
Table 24 SPI Master Signal Names ................................................................................................ 56
Table 25 SPI Master Timing ......................................................................................................... 57
Table 26 Debugger Signal Name .................................................................................................. 58
Table 27 Data and Control Bus Signal Mode Options - Parallel FIFO Interface ..................................... 61
Table 28 Asynchronous FIFO mode Read / Write Timing .................................................................. 63
Table 29 Synchronous FIFO control signals .................................................................................... 64
Table 30 Synchronous FIFO mode Read / Write Timing .................................................................... 66
Table 31 Absolute Maximum Ratings ............................................................................................. 72
Table 32 Operating Voltage and Current ........................................................................................ 73
Table 33 I/O Pin Characteristics .................................................................................................... 73
Table 34 USB I/O Pin (USBDP, USBDM) Characteristics ................................................................... 74
Table 35 XTIN, XOUT Pin Characteristics ........................................................................................ 74
Table 36 Reflow Profile Parameter Values ...................................................................................... 84
Table 37 Package Reflow Peak Temperature ................................................................................... 84
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List of Figures
Figure 2-1 Simplified VNC2 Block Diagram ....................................................................................... 5
Figure 3-1 32 Pin LQFP – Top Down View ........................................................................................ 9
Figure 3-2 32 Pin QFN – Top Down View ....................................................................................... 10
Figure 3-3 48 Pin LQFP – Top Down View ...................................................................................... 11
Figure 3-4 48 Pin QFN – Top Down View ........................................................................................ 12
Figure 3-5 64 Pin LQFP – Top Down View ...................................................................................... 13
Figure 3-6 64 Pin QFN – Top Down View ........................................................................................ 14
Figure 3-7 Schematic symbol 32 Pin.............................................................................................. 15
Figure 3-8 Schematic symbol 48 Pin.............................................................................................. 16
Figure 3-9 Schematic symbol 64 Pin.............................................................................................. 17
Figure 5-1 IOBUS to Group Relationship-64 Pin .............................................................................. 27
Figure 5-2 IOBUS to UART, SPI slave0 and SPI master example ....................................................... 28
Figure 5-3 IOBUS to UART, SPI slave0 and SPI master second example ............................................ 29
Figure 5-4 IOBUS to UART, SPI slave0 and SPI master third example................................................ 30
Figure 5-5 UART Example 64 pin .................................................................................................. 37
Figure 6-1 UART Receive Waveform .............................................................................................. 38
Figure 6-2 UART Transmit Waveform ............................................................................................ 38
Figure 6-3 - SPI CPOL CPHA Function ............................................................................................ 42
Figure 6-4 SPI Slave block diagram............................................................................................... 43
Figure 6-5 Full Duplex Data Master Write ....................................................................................... 44
Figure 6-6 Full Duplex Data Master Read ....................................................................................... 45
Figure 6-7 SPI Command and Status Structure ............................................................................... 45
Figure 6-8 Half Duplex Data Master Write ...................................................................................... 46
Figure 6-9 Half Duplex Data Master Read....................................................................................... 46
Figure 6-10 Half Duplex 3-pin Data Master Write ............................................................................ 47
Figure 6-11 Half Duplex 3-pin Data Master Read............................................................................. 47
Figure 6-12 Unmanaged Mode Transfer Diagram ............................................................................ 48
Figure 6-13 VNC1L Mode Data Write ............................................................................................. 49
Figure 6-14 VNC1L Mode Data Read .............................................................................................. 49
Figure 6-15 VNC1L Compatible SPI Command and Status Structure .................................................. 49
Figure 6-16 SPI Slave Mode Timing ............................................................................................... 52
Figure 6-17 SPI Master Data Read (VNC2 Slave Mode) .................................................................... 53
Figure 6-18 SPI Slave Mode Data Write ......................................................................................... 54
Figure 6-19 SPI Slave Mode Status Read ....................................................................................... 54
Figure 6-20 SPI Master block diagram ........................................................................................... 55
Figure 6-21 Typical SPI Master Timing ........................................................................................... 57
Figure 6-22 Asynchronous FIFO mode Read / Write Cycle ................................................................ 63
Figure 6-23 Synchronous FIFO mode Read / Write Cycle ................................................................. 65
Figure 6-24 PWM – Timing Diagram .............................................................................................. 66
Figure 7-1 USB Modes ................................................................................................................. 68
Figure 10-1 VNC2 Schematic (MCU - UART Interface)...................................................................... 75
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Figure 11-1 Package Markings ...................................................................................................... 76
Figure 11-2 Markings – 32 QFN .................................................................................................... 76
Figure 11-3 LQFP-32 Package Dimensions ..................................................................................... 77
Figure 11-4 QFN-32 Package Dimensions ....................................................................................... 78
Figure 11-5 LQFP-48 Package Dimensions ..................................................................................... 79
Figure 11-6 64 pin LQFP Package Details ....................................................................................... 81
Figure 11-7 64 pin QFN Package Details ........................................................................................ 82
Figure 11-8 All packages Reflow Solder Profile ................................................................................ 83
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Appendix B – Revision History
Revision History
Version Preliminary
Data sheet released as “Preliminary – Subject to change”
Feb 2010
before product launch.
Version 1.0
Version 1 release.
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