Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 Future Technology Devices International Ltd. Application Note AN_139 Vinculum-II IO Mux Explained Document Reference No.: FT_000235 Version 1.0 Issue Date: 2010-02-19 The purpose of this document is to describe the purpose and operation of the Vinculum-II (VNC2) IO Multiplexer (Mux) module. Copyright © 2010 Future Technology Devices International Limited 1 Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 TABLE OF CONTENTS 1 Introduction............................................................................................ 3 2 The IO Mux ............................................................................................. 4 3 2.1 Group 0 Signals and Available Pins .................................................................. 4 2.2 Group 1 Signals and Available Pins .................................................................. 5 2.3 Group 2 Signals and Available Pins .................................................................. 5 2.4 Group 3 Signals and Available Pins .................................................................. 6 Pin Selection .......................................................................................... 7 3.1 IO Mux Defaults For Each Interface Module ...................................................... 8 3.2 Additional Pin Information .................................................................................. 9 4 Summary .............................................................................................. 10 5 Contact Information............................................................................. 11 Appendix A– Revision History .................................................................. 13 Copyright © 2010 Future Technology Devices International Limited 2 Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 1 Introduction The Vinculum VNC2 device is FTDI’s 2nd generation USB host solution device and expands on the capabilities of the VNC1L. The device is supplied in 6 different packages. There are 32 pin QFN and LQFP packages, 48 pin QFN and LQFP packages and 64 pin QFN and LQFP packages. The 32 pin packages have 12 IO pins, the 48 pin package has 28 IO pins and the 64 pin package has 44 IO pins. Each of the IO pins interface to external logic and may be defined as an input or an output. All IO pins default to an input following a reset. Following a reset, the IO MUX module within VNC2 can be configured to set the IO pin function and direction. This application note describes what pin functions may be applied to the IO pins on each VNC2 package size. This will help when laying out an application PCB. Copyright © 2010 Future Technology Devices International Limited 3 Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 2 The IO Mux The VNC2 IO Mux is based on 4 signal groupings – groups 1 to 3. The signals for each of the VNC2 interface modules ie UART, SPI slave, SPI master, FIFO, PWM or GPIO all belong to one of these 4 groups. Additionally each signal can only appear in one group and the groups are fixed. 2.1 Group 0 Signals and Available Pins Available Input signals Available output signals debug_if uart_txd uart_dtr# uart_tx_active fifo_data[0] fifo_data[4] fifo_rxf# pwm[0] pwm[4] spi_m_clk spi_m_ss_1# gpio[0] gpio[4] gpio[8] gpio[12] gpio[16] gpio[20] gpio[24] gpio[28] gpio[32] gpio[36] debug_if fifo_data[0] fifo_data[4] fifo_oe# spi_s0_clk spi_s1_clk gpio[0] gpio[4] gpio[8] gpio[12] gpio[16] gpio[20] gpio[24] gpio[28] gpio[32] gpio[36] 64 Pin Package Available pins 48 Pin Package Available pins 32 Pin Package Available pins 11, 19, 28, 43, 51, 61 11, 15, 20, 31, 35, 41, 45 11, 23 29 15, 24, 39, 47, 57, Table 2.1: Group 0 Pins This table shows that: A design in a 32 pin package can select 3 signals from group 0 A design in a 48 pin package can select 7 signals from group 0 A design in a 64 pin package can select 11 signals from group 0 These signals can be a mixture of any of the available inputs or outputs shown in the table. Copyright © 2010 Future Technology Devices International Limited 4 Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 2.2 Group 1 Signals and Available Pins Available Input signals uart_rxd uart_dsr# fifo_data[1] fifo_data[5] spi_s0_mosi spi_s1_mosi gpio[1] gpio[5] gpio[9] gpio[13] gpio[17] gpio[21] gpio[25] gpio[29] gpio[33] gpio[37] Available output signals fifo_data[1] fifo_data[5] fifo_txe# pwm[1] pwm[5] spi_s0_mosi spi_s1_mosi spi_m_mosi fifo_clkout gpio[1] gpio[5] gpio[9] gpio[13] gpio[17] gpio[21] gpio[25] gpio[29] gpio[33] gpio[37] 64 Pin Package Available pins 12, 16, 20, 25, 29, 40, 44, 48, 52, 58, 62 48 Pin Package Available pins 12,16, 21, 32, 36, 42, 46 32 Pin Package Available pins 12, 24, 30 Table 2.2: Group 1 Pins This table shows that: A design in a 32 pin package can select 3 signals from group 1 A design in a 48 pin package can select 7 signals from group 1 A design in a 64 pin package can select 11 signals from group 1 These signals can be a mixture of any of the available inputs or outputs shown in the table. 2.3 Group 2 Signals and Available Pins Available Input signals Available output signals uart_rts# fifo_data[2] fifo_data[6] pwm[2] pwm[6] spi_s0_miso spi_s1_miso gpio[2] gpio[6] gpio[10] gpio[14] gpio[18] gpio[22] gpio[26] gpio[30] uart_dcd# fifo_data[2] fifo_data[6] fifo_rd# spi_m_miso gpio[2] gpio[6] gpio[10] gpio[14] gpio[18] gpio[22] gpio[26] gpio[30] gpio[34] gpio[38] 64 Pin Package Available pins 48 Pin Package Available pins 13, 22, 31, 45, 55, 63 13, 18, 22, 33, 37, 43, 47 17, 26, 41, 49, 59, 32 Pin Package Available pins 14, 25, 31 Table 2.3: Group 2 Pins Copyright © 2010 Future Technology Devices International Limited 5 Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 This table shows that: A design in a 32 pin package can select 3 signals from group 2 A design in a 48 pin package can select 7 signals from group 2 A design in a 64 pin package can select 11 signals from group 2 These signals can be a mixture of any of the available inputs or outputs shown in the table. 2.4 Group 3 Signals and Available Pins Available Input signals uart_cts# uart_ri# fifo_data[3] fifo_data[7] fifo_wr# spi_s0_ss# spi_s1_ss# gpio[3] gpio[7] gpio[11] gpio[15] gpio[19] gpio[23] gpio[27] gpio[31] gpio[35] gpio[39] Table 2.4: Group 3 Pins Available output signals fifo_data[3] fifo_data[7] pwm[3] pwm[7] spi_m_ss_0# gpio[3] gpio[7] gpio[11] gpio[15] gpio[19] gpio[23] gpio[27] gpio[31] gpio[35] gpio[39] 64 Pin Package Available pins 14, 18, 23, 27, 32, 42, 46, 50, 56, 60, 64 48 Pin Package Available pins 14, 19, 23, 34, 38, 44, 48 32 Pin Package Available pins 15, 26, 32 This table shows that: A design in a 32 pin package can select 3 signals from group 3 A design in a 48 pin package can select 7 signals from group 3 A design in a 64 pin package can select 11 signals from group 3 These signals can be a mixture of any of the available inputs or outputs shown in the table. Copyright © 2010 Future Technology Devices International Limited 6 Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 3 Pin Selection The first stage in selecting your pins is to identify the interfaces required for the application. Then determine the signals required for the interfaces and available pins. UART SPI_SLAVE0 SPI_SLAVE1 SPI_MASTER FIFO PWM Debug uart_txd spi_s0_clk spi_s1_clk spi_m_clk fifo_data[0] pwm[0] Debug_if uart_rxd spi_s0_ss# spi_s1_ss# spi_m_mosi fifo_data[1] pwm[1] uart_rts# spi_s0_mosi spi_s1_mosi spi_m_miso fifo_data[2] pwm[2] uart_cts# spi_s0_miso spi_s1_miso spi_m_ss0# fifo_data[3] pwm[3] spi_m_ss1# fifo_data[4] pwm[4] uart_dsr# fifo_data[5] pwm[5] uart_dcd# fifo_data[6] pwm[6] uart_ri# fifo_data[7] pwm[7] uart_tx_active fifo_rxf# uart_dtr# fifo_txe# fifo_rd# fifo_wr fifo_oe#2 Fifo_clkout2 Table 3: Interface signals 1. Each pin can only be assigned one signal. 2. SYNC FIFO requires extra signals compared to ASYNC FIFO and is not available in 32 pin package – not enough pins. After identifying the signals required, the user can refer to the tables in section 2 of this document to identify pins that the signal may be routed to. For example, uart_txd is a member of Group 0 and is available on any of the group 0 pins not assigned to another signal. Copyright © 2010 Future Technology Devices International Limited 7 Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 3.1 IO Mux Defaults For Each Interface Module The default pin assignment for each package when the IO Mux has been enabled, but no application has been configured is as follows: Pin Pin Pin No. No. No. Name 64 Pin 64 48 32 Default Pin Pin Pin 11 11 11 IOBUS0 debug_if 12 12 12 IOBUS1 Input 13 13 14 IOBUS2 Input 14 14 15 IOBUS3 Input 15 15 23 IOBUS4 fifo_data[0] 16 16 24 IOBUS5 fifo_data[1] 17 18 25 IOBUS6 fifo_data[2] 18 19 26 IOBUS7 fifo_data[3] 19 20 29 IOBUS8 fifo_data[4] 20 21 30 IOBUS9 fifo_data[5] 22 22 31 IOBUS10 fifo_data[6] 23 23 32 IOBUS11 fifo_data[7] 24 31 IOBUS12 fifo_rxf# 25 32 IOBUS13 fifo_txe# 26 33 IOBUS14 fifo_rd# 27 34 IOBUS15 fifo_wr# 28 35 IOBUS16 Input 29 36 IOBUS17 Input 31 37 IOBUS18 Input 32 38 IOBUS19 Input 39 41 IOBUS20 uart_txd 40 42 IOBUS21 uart_rxd 41 43 IOBUS22 uart_rts# 42 44 IOBUS23 uart_cts# 43 45 IOBUS24 uart_dtr# 44 46 IOBUS25 uart_dsr# 45 47 IOBUS26 uart_dcd# 46 48 IOBUS27 uart_ri# 47 IOBUS28 uart_tx_active 48 IOBUS29 Input 49 IOBUS30 Input 50 IOBUS31 Input 51 IOBUS32 spi_s0_clk 52 IOBUS33 spi_s0_mosi 55 IOBUS34 spi_s0_miso 56 IOBUS35 spi_s0_ss# 57 IOBUS36 spi_s1_clk 58 IOBUS37 spi_s1_mosi 59 IOBUS38 spi_s1_miso 60 IOBUS39 spi_s1_ss# 61 IOBUS40 spi_m_clk 62 IOBUS41 spi_m_mosi 63 IOBUS42 spi_m_miso 64 IOBUS43 spi_m_ss_0# Table 3.1: IO Mux Defaults for each interface module 48 Pin Default 32 PIN Default Typ e Descriptio n debug_if pwm[1] pwm[2] pwm[3] spi_s0_clk spi_s0_mosi spi_s0_miso spi_s0_ss# spi_m_clk spi_m_mosi spi_m_miso spi_m_ss_0# uart_txd uart_rxd uart_rts# uart_cts# uart_dtr# uart_dsr# uart_dcd# uart_ri# uart_tx_active gpio[5] gpio[6] gpio[7] gpio[0] gpio[1] gpio[2] gpio[3] debug_if gpio[1] gpio[2] gpio[3] uart_txd uart_rxd uart_rts# uart_cts# spi_s0_clk spi_s0_mosi spi_s0_miso spi_s0_ss# I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Copyright © 2010 Future Technology Devices International Limited 8 Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 3.2 Additional Pin Information Each signal can be routed to more than one pin. This may be useful for sniffing output data for debug e.g. UART _TXD. Unused interface modules do not need to reserve pins. For example, if the UART interface is not enabled then it is not necessary to reserve pins for the UART function. The pins that are reserved for UART by default would default to GPIO inputs. It is not essential to reserve a pin for the debug interface but may be advisable for debug and chip programming purposes. Copyright © 2010 Future Technology Devices International Limited 9 Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 4 Summary Although the VNC2 IO Mux seems complex, it provides maximum flexibility in selection of interface types. This document attempts to explain how to use this function. Copyright © 2010 Future Technology Devices International Limited 10 Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 5 Contact Information Head Office – Glasgow, UK Future Technology Devices International Limited Unit 1, 2 Seaward Place, Centurion Business Park Glasgow G41 1HH United Kingdom Tel: +44 (0) 141 429 2777 Fax: +44 (0) 141 429 2758 E-mail (Sales) [email protected] E-mail (Support) [email protected] E-mail (General Enquiries) [email protected] Web Site URL http://www.ftdichip.com Web Shop URL http://www.ftdichip.com Branch Office – Taipei, Taiwan Future Technology Devices International Limited (Taiwan) 2F, No 516, Sec. 1 NeiHu Road Taipei 114 Taiwan, R.O.C. Tel: +886 (0) 2 8797 1330 Fax: +886 (0) 2 8751 9737 E-mail (Sales) [email protected] E-mail (Support) [email protected] E-mail (General Enquiries) [email protected] Web Site URL http://www.ftdichip.com Branch Office – Hillsboro, Oregon, USA Future Technology Devices International Limited (USA) 7235 NW Evergreen Parkway, Suite 600 Hillsboro, OR 97123-5803 USA Tel: +1 (503) 547 0988 Fax: +1 (503) 547 0987 E-Mail (Sales) [email protected] E-Mail (Support) [email protected] Web Site URL http://www.ftdichip.com Branch Office – Shanghai, China Future Technology Devices International Limited (China) Room 408, 317 Xianxia Road, ChangNing District, ShangHai, China Tel: +86 (21) 62351596 Fax: +86(21) 62351595 E-Mail (Sales): [email protected] E-Mail (Support): [email protected] E-Mail (General Enquiries): [email protected] Web Site URL: http://www.ftdichip.com Copyright © 2010 Future Technology Devices International Limited 11 Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 Distributor and Sales Representatives Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country. Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminar y information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH United Kingdom. Scotland Registered Number: SC136640 Copyright © 2010 Future Technology Devices International Limited 12 Document Reference No.: FT_000235 Vinculum-II IO Mux Explained Application Note AN_139 Version 1.0 Clearance No.: FTDI# 141 Appendix A– Revision History Version Draft First Draft Version 1.0 First Release 10/02/2010 19/02/2010 Copyright © 2010 Future Technology Devices International Limited 13