HOLTEK HT45R04E

HT45R04/HT45R04E
A/D Type 8-Bit MCU
Preliminary
Features
· Operating voltage: 2.2V~5.5V
· HALT function and wake-up feature reduce power
consumption
(IDD<200mA, when fSYS=455kHz, VDD=+5V)
· Operating frequency: 400KHz~2MHz
· Up to 2ms instruction cycle with 2MHz system clock at
VDD=5V
· 13 bidirectional I/O lines (PA, PB0~PB3, PD0)
· One interrupt input shared with an I/O line
· 4-level subroutine nesting
· 8-bit programmable timer/event counter with over-
· 4 channels 8-bit resolution A/D converter
· Bit manipulation instruction
flow interrupt and 7-stage prescaler
· On-chip crystal and RC oscillator
· 14-bit table read instruction
· Watchdog Timer
· 63 powerful instructions
· 1024´14 program memory
· All instructions in 1 or 2 machine cycles
· 64´8 bank data memory RAM
· Low voltage reset function
· Supports PFD for sound generation
· 18-pin SOP package
General Description
The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, HALT
and wake-up functions, enhance the versatility of these
devices to suit a wide range of A/D application possibilities such as security systems, smoke detectors, smart
tags, etc.
The HT45R04 is an 8-bit high performance, RISC architecture microcontroller devices specifically designed for
A/D applications that interface directly to analog signals,
such as those from sensors.
There are two dice in the HT45R04E package: one is
the HT45R04 MCU, the other is a 128´8 bits EEPROM
used for data memory purpose. The two dice are
wire-bonded to form HT45R04E.
Rev. 0.00
1
December 30, 2004
Preliminary
HT45R04/HT45R04E
Block Diagram
HT45R04
P A 5 /IN T
In te rru p t
C ir c u it
M
T M R
S T A C K
P ro g ra m
R O M
P ro g ra m
C o u n te r
U
P r e s c a le r
fS
Y S
P A 4 /T M R
X
T M R C
IN T C
P A 4
P A 3 /P F D
S Y S C L K /4
In s tr u c tio n
R e g is te r
M
M P
U
W D T
P r e s c a le r
D A T A
M e m o ry
X
P o rt D
P D
X
P D 0
M U X
In s tr u c tio n
D e c o d e r
4 -C h a n n e l
A /D C o n v e rte r
S T A T U S
A L U
S
S
P B C
S h ifte r
T im in g
G e n e ra to r
O S
R E
V D
V S
U
R C O S C
P D C
O S C 2
M
W D T
P o rt B
P B
P A 3 , P A 5
P A C
C 1
A C C
D
P o rt A
P A
L V R
P B 0 /A N 0 ~ P B 3 /A N 3
P A 0
P A 3
P A 4
P A 5
P A 6
~ P
/P
/T
/IN
~ P
A 2
F D
M R
T
A 7
Data EEPROM
S C L
S D A
I/O
C o n tro l
L o g ic
H V P u m p
X
D
E E P R O M
A rra y
E
M e m o ry
C o n tro l
L o g ic
C
P a g e B u f
Y D E C
A d d re s s
C o u n te r
S e n s e A M P
R /W C o n tro l
V C C
V S S
Rev. 0.00
2
December 30, 2004
Preliminary
HT45R04/HT45R04E
Pin Assignment
P A 3 /P F D
1
1 8
P A 4 /T M R
P A 3 /P F D
1
1 8
P A 4 /T M R
P A 2
2
1 7
P A 5 /IN T
P A 2
2
1 7
P A 5 /IN T
P A 1
3
1 6
P A 6
P A 1
3
1 6
P A 6
P A 0
4
1 5
P A 7
P A 0
4
1 5
P A 7 /S D A
P B 3 /A N 3
5
1 4
O S C 2
P B 3 /A N 3
5
1 4
O S C 2
P B 2 /A N 2
6
1 3
O S C 1
P B 2 /A N 2
6
1 3
O S C 1
P B 1 /A N 1
7
1 2
V D D
P B 1 /A N 1
7
1 2
V D D
P B 0 /A N 0
8
1 1
P B 0 /A N 0
8
1 1
V S S
9
1 0
R E S
P D 0
V S S
9
1 0
R E S
P D 0 /S C L
H T 4 5 R 0 4
1 8 S O P -A
H T 4 5 R 0 4 E
1 8 S O P -B
Pin Description
Pin Name
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6
PA7/SDA
PB0/AN0~
PB3/AN3
I/O
I/O
I/O
Option
Description
Pull-high
Wake-up
PFD
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by options. Software instructions determine the CMOS output or Schmitt
trigger input with pull-high resistors (determined by pull-high option: bit option).
The I/O modes of each line are controlled by their related control register bit
(PAC). The PA3, PA4 and PA5 are pin-shared with PFD, TMR and INT , respectively. PA7/SDA is wire-bonded with SDA pad of the data EEPROM.
Pull-high
Bidirectional 4-bit input/output port. Software instructions determine the CMOS
output or Schmitt trigger input with pull-high resistors (determined by pull-high
option: bit option). The I/O modes of each line are controlled by their related
control register bit (PBC). Each PB line is pin shared with an A/D converter input.
PD0/SCL
I/O
Pull-high
Bidirectional 1-bit input/output port. Software instructions determine the CMOS
output or Schmitt trigger input with pull-high resistors (determined by pull-high
option: bit option). The I/O mode is controlled by its related control register bit
(PDC). PDO/SCL is wire-bonded with SCL pad of the data EEPROM.
OSC1
OSC2
I
O
Crystal
or RC
OSC1 and OSC2 are connected to an RC network or a crystal (determined by
options) for the internal system clock. In the case of an RC operation, OSC2 is
the output terminal for 1/4 system clock.
RES
¾
¾
Schmitt trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground.
Note: All pull-high resistors are controlled by an option bit.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 0.00
3
December 30, 2004
Preliminary
HT45R04/HT45R04E
D.C. Characteristics
HT45R04
Symbol
VDD
IDD1
Ta=25°C
Parameter
Operating Voltage
Test Conditions
Conditions
VDD
¾
fSYS=2MHz
3V
No load, fSYS=2MHz,
ADC disable
Operating Current (Crystal OSC)
5V
No load, fSYS=455kHz
3V
IDD2
Operating Current (RC OSC)
No load, fSYS=2MHz,
ADC disable
5V
No load, fSYS=455kHz
ISTB1
3V
Standby Current (WDT Enabled)
No load, system HALT
5V
3V
Min.
Typ.
Max.
Unit
2.2
¾
5.5
V
¾
0.5
1.3
mA
¾
1.5
3
mA
¾
200
300
mA
¾
0.5
1.3
mA
¾
1.5
3
mA
¾
200
300
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
ISTB2
Standby Current (WDT Disabled)
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
LVR enabled
2.7
3.0
3.3
V
IOL
4
8
¾
mA
I/O Port Sink Current
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
No load, system HALT
5V
3V
VOL=0.1VDD
5V
IOH
3V
I/O Port Source Current
VOH=0.9VDD
5V
RPH
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
Pull-high Resistance
VAD
A/D Input Voltage
¾
¾
0
¾
VDD
V
EAD
A/D Conversion Error
¾
¾
¾
±0.5
±1
LSB
IADC
Additional Power Consumption
if A/D Converter is Used
3V
¾
0.5
1
mA
¾
1.5
3
mA
Rev. 0.00
¾
5V
4
December 30, 2004
Preliminary
HT45R04/HT45R04E
EEPROM D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VCC
Conditions
¾
Min.
Typ.
Max.
Unit
2.2
¾
5.5
V
VCC
Operating Voltage
¾
ICC1
Operating Current
5V
Read at 100kHz
¾
¾
2
mA
ICC2
Operating Current
5V
Write at 100kHz
¾
¾
5
mA
VIL
Input Low Voltage
¾
¾
-1
¾
0.3VCC
V
VIH
Input High Voltage
¾
¾
0.7VCC
¾
VCC+0.5
V
VOL
Output Low Voltage
2.4V
IOL=2.1mA
¾
¾
0.4
V
ILI
Input Leakage Current
5V
VIN=0 or VCC
¾
¾
1
mA
ILO
Output Leakage Current
5V
VOUT=0 or VCC
¾
¾
1
mA
5V
VIN=0 or VCC
¾
¾
4
mA
2.4V
VIN=0 or VCC
¾
¾
3
mA
ISTB1
Standby Current
ISTB2
Standby Current
CIN
Input Capacitance (See Note)
¾
f=1MHz 25°C
¾
¾
6
pF
COUT
Output Capacitance (See Note)
¾
f=1MHz 25°C
¾
¾
8
pF
Note:
These parameters are periodically sampled but not 100% tested
VCC pad is wire-bonded to VDD pad of the HT45R04E die.
A.C. Characteristics
HT45R04
Symbol
Ta=25°C
Parameter
Test Conditions
Conditions
VDD
Min.
Typ.
Max.
Unit
fSYS1
System Clock (Crystal OSC)
¾
2.2V~5.5V
400
¾
2000
kHz
fSYS2
System Clock (RC OSC)
¾
2.2V~5.5V
400
¾
2000
kHz
fTIMER
Timer I/P Frequency (TMR)
¾
2.2V~5.5V
0
¾
2000
kHz
45
90
180
ms
32
65
130
ms
1.4
2.8~5.6
11
S
1.1
2.3~4.7
9.4
S
tWDTOSC Watchdog Oscillator Period
3V
¾
5V
3V
tWDT1
Watchdog Time-out Period (RC)
tWDT2
Watchdog Time-out Period
(System Clock)
¾
Without WDT prescaler
217
¾
218
tSYS
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
76
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
Rev. 0.00
Without WDT prescaler
5V
Wake-up from HALT
5
December 30, 2004
Preliminary
HT45R04/HT45R04E
EEPROM A.C. Characteristics
Symbol
Ta=25°C
Parameter
Remark
Standard Mode*
VCC=5V±10%
Min.
Max.
Min.
Max.
Unit
fSK
Clock Frequency
¾
¾
100
¾
400
kHz
tHIGH
Clock High Time
¾
4000
¾
600
¾
ns
tLOW
Clock Low Time
¾
4700
¾
1200
¾
ns
tr
SDA and SCL Rise Time
Note
¾
1000
¾
300
ns
tf
SDA and SCL Fall Time
Note
¾
300
¾
300
ns
tHD:STA
START Condition Hold Time
After this period the
first clock pulse is
generated
4000
¾
600
¾
ns
tSU:STA
START Condition Setup Time
Only relevant for
repeated START
condition
4000
¾
600
¾
ns
tHD:DAT
Data Input Hold Time
¾
0
¾
0
¾
ns
tSU:DAT
Data Input Setup Time
¾
200
¾
100
¾
ns
tSU:STO
STOP Condition Setup Time
¾
4000
¾
600
¾
ns
tAA
Output Valid from Clock
¾
¾
3500
¾
900
ns
4700
¾
1200
¾
ns
tBUF
Bus Free Time
Time in which the bus
must be free before a
new transmission can
start
tSP
Input Filter Time Constant
(SDA and SCL Pins)
Noise suppression
time
¾
100
¾
50
ns
tWR
Write Cycle Time
¾
¾
5
¾
5
ms
Note:
These parameters are periodically sampled but not 100% tested
* The standard mode means VCC=2.2V to 5.5V
For relative timing, refer to timing diagrams
Rev. 0.00
6
December 30, 2004
Preliminary
HT45R04/HT45R04E
Functional Description
Execution Flow
incremented by one. The program counter then points to
the memory word containing the next instruction code.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manages the program transfer by
loading the address corresponding to each instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme allows each instruction
to be effectively executed in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a readable and writable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in program ROM are executed and its contents specify full range of program
memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
1
0
0
0
A/D Interrupt
0
0
0
0
0
0
1
1
0
0
Skip
Program Counter+2
Loading PCL
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *9~*0: Program Counter bits
S9~S0: Stack register bits
#9~#0: Instruction code bits
Rev. 0.00
@7~@0: PCL bits
7
December 30, 2004
Preliminary
· Location 00CH
Program Memory - ROM
Location 00CH is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the
interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
1024´14 bits, addressed by the program counter and table pointer.
· Table location
Certain locations in the program memory are reserved
for special usage:
Any location in the program memory can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, and the remaining 2 bits are read as
²0². The Table Higher-order byte register (TBLH) is
read only. The table pointer (TBLP) is a read/write register (07H), which indicates the table location. Before
accessing the table, the location must be placed in
TBLP. The TBLH is read only and cannot be restored.
If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR.
Errors can occur. In other words, using the table read
instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read
instruction has to be applied in both the main routine
and the ISR, the interrupt is supposed to be disabled
prior to the table read instruction. It will not be enabled
until the TBLH has been backed up. All table related
instructions require two cycles to complete the operation. These areas may function as normal program
memory depending upon the requirements.
· Location 000H
Location 000H is reserved for program initialization.
After a chip reset, the program always begins execution at location 000H.
· Location 004H
Location 004H is reserved for the external interrupt
service program. If the INT input pin is activated, the
interrupt is enabled and the stack is not full, the program begins execution at location 004H.
· Location 008H
Location 008H is reserved for the timer/event counter
interrupt service program. If a timer interrupt results
from a timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program
begins execution at location 008H.
0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
0 0 8 H
0 0 C H
E x te r n a l In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
A /D
C o n v e r te r In te r r u p t S u b r o u tin e
P ro g ra m
M e m o ry
n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
HT45R04/HT45R04E
Stack Register - STACK
3 0 0 H
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 4 levels and is neither part of the
data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
L o o k - u p T a b le ( 2 5 6 w o r d s )
3 F F H
1 4 b its
N o te : n ra n g e s fro m
0 to 3
Program Memory
Instruction
Table Location
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *9~*0: Table location bits
P9, P8: Current program counter bits
@7~@0: Table pointer bits
Rev. 0.00
8
December 30, 2004
Preliminary
0 0 H
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
In d ir e c t A d d r e s s in g R e g is te r
0 1 H
M P
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge will be inhibited. When the stack pointer is
decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the
programmer to use the structure more easily. In a similar
case, if the stack is full and a ²CALL² is subsequently
executed, stack overflow occurs and the first entry will
be lost (only the most recent 4 return addresses are
stored).
A C C
0 5 H
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
0 A H
S T A T U S
0 B H
IN T C
0 C H
0 D H
T M R
0 E H
T M R C
0 F H
Data Memory - RAM
1 0 H
The data memory is designed with 85´8 bits. The data
memory is divided into 2 functional groups: special function registers and general purpose data memory (64´8).
Most of them are read/write, but some are read only.
1 1 H
The special function registers include the indirect add re s s in g r e g i s t e r ( 00H ) , t i m e r / ev e n t co u n t e r
(TMR;0DH), timer/event counter control register
(TMRC;0EH), program counter lower-order byte register (PCL;06H), memory pointer register (MP;01H), accumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC;0BH),
timer register (TMR;0DH), timer control register
(TMRC;0EH), I/O port data registers (PA;12H, PB;14H,
PD;18H), I/O port control registers (PAC;13H,
P B C ; 1 5 H , P D C ; 1 9 H ) , A / D h i gh- b y t e r e g i st e r
(ADRH;21H), A/D control register (ADCR;22H) and A/D
clock setting register (ACSR;23H). The remaining
space before the 40H is reserved for future expansion
and reading these locations will return the result ²00H².
The general purpose data memory, addressed from 40H
to 7FH, is used for data and control information under instruction commands.
1 6 H
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
S p e c ia l P u r p o s e
D A T A M E M O R Y
1 7 H
1 8 H
P D
1 9 H
P D C
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
2 1 H
A D R H
2 2 H
A D C R
2 3 H
A C S R
2 4 H
3 F H
4 0 H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer register (MP;01H).
7 F H
G e n e ra l P u rp o s e
D A T A M E M O R Y
(6 4 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
The bit 7 of MP is undefined and reading will return the
result ²1². Any writing operation to MP will only transfer
the lower 7-bit data to MP.
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses the data memory pointed to by MP
(01H). Reading location 00H itself indirectly will return
the result 00H. Writing indirectly results in no operation.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
The memory pointer register MP (01H) is a 7-bit register.
Rev. 0.00
HT45R04/HT45R04E
9
December 30, 2004
Preliminary
HT45R04/HT45R04E
Arithmetic and Logic Unit - ALU
Interrupt
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
The microcontroller provides an external interrupts, an
internal timer/event counter overflow interrupt, and an
A/D converter end-of-conversion interrupt. The interrupt
control registers (INTC;0BH ) contains the interrupt control bits to set the enable/disable and the interrupt request flags.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of the INTC may be
set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If
immediate service is desired, the stack must be prevented from becoming full.
· Branch decision (SZ, SNZ, SIZ, SDZ)
The ALU not only saves the results of a data operation
but also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results from those intended. The TO flag can be affected
only by a system power-up, a WDT time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag
can be affected only by executing the ²HALT² or ²CLR
WDT² instruction or a system power-up.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
External interrupts are triggered by a high to low transition of the INT and the related interrupt request flag (EIF;
bit 4 of the INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is
active, a subroutine call to location 04H will occur. The
interrupt request flag (EIF) and EMI bits will be cleared
to disable other interrupts.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction, otherwise AC is cleared.
2
Z
Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction. PDF is set by
executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is
set by a WDT time-out.
6
¾
Unused bit, read as ²0²
7
¾
Unused bit, read as ²0²
Status (0AH) Register
Rev. 0.00
10
December 30, 2004
Preliminary
HT45R04/HT45R04E
Bit No.
Label
Function
0
EMI
1
EEI
Controls the external interrupt (1= enable; 0= disable)
2
ETI
Controls the timer/event counter interrupt (1= enable; 0= disable)
3
EADI
4
EIF
External interrupt request flag (1= active; 0= inactive)
5
TF
Internal timer/event counter request flag (1= active; 0= inactive)
6
ADF
7
¾
Controls the master (global) interrupt (1= enable; 0= disable)
Controls the A/D converter interrupt (1= enable; 0= disable)
A/D converter request flag (1= active; 0= inactive)
Unused bit, read as ²0²
INTC (0BH) Register
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of the INTC), caused by a timer overflow.
When the interrupt is enabled, the stack is not full and
the TF bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (TF) will be reset
and the EMI bit cleared to disable further interrupts.
isters (INTC) which is located at 0BH in the data
memory. EMI, EEI, ETI, EADI and are used to control
the enabling/disabling of interrupts. These bits prevent
the requested interrupts from being serviced. Once the
interrupt request flags (TF, EIF, ADF) are set, they will
remain in the INTC register until the interrupts are serviced or cleared by a software instruction.
The A/D converter end-of-conversion interrupt is initialized by setting the A/D end-of-conversion interrupt request flag (bit 6 of the INTC), caused by an end of A/D
conversion. When the interrupt is enabled, the stack is
not full and the end of A/D conversion interrupt request
flag is set, a subroutine call to location 00CH will occur.
The related interrupt request flag will be reset and the
EMI bit cleared to disable further interrupts.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only
one stack is left and enabling the interrupt is not well
controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine.
During the execution of an interrupt subroutine, other interrupt acknowledge are held until the ²RETI²
instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
V
O S C 1
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Interrupt Source
Priority
1
04H
Timer/Event Counter Overflow
2
08H
A/D Converter Interrupt
3
0CH
C r y s ta l O s c illa to r
fS Y S /4
N M O S O p e n D r a in
O S C 2
R C O s c illa to r
System Oscillator
Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined
by options. No matter what oscillator type is selected,
the signal provides the system clock. The HALT mode
stops the system oscillator and ignores an external signal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 24kW to 1MW. The system clock, divided by
4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the most
cost effective solution. However, the oscillation fre-
The timer/event counter interrupt request flag (TF), external interrupt request flags (EIF), A/D converter interrupt request flag (ADF), enable timer/event counter
interrupt bit (ETI), enable A/D converter interrupt
(EADI), enable external interrupt (EEI) and enable master interrupt bit(EMI) constitute the interrupt control reg-
Rev. 0.00
O S C 1
O S C 2
Vector
External Interrupt
D D
11
December 30, 2004
Preliminary
HT45R04/HT45R04E
HALT mode, the overflow will initialize a ²warm reset²,
and only the Program Counter and SP are reset to zero.
To clear the WDT contents (including the WDT
prescaler), three methods are adopted; external reset (a
low level to RES), software instruction and a ²HALT² instruction. The software instructions include ²CLR WDT²
and the other set - ²CLR WDT1² and ²CLR WDT2². Of
these two types of instruction, only one can be active depending on the option - ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times
equal one), any execution of the ²CLR WDT² instruction
will clear the WDT. In the case that ²CLR WDT1² and
²CLR WDT2² are chosen (i.e. CLRWDT times equal
two), these two instructions must be executed to clear
the WDT, otherwise, the WDT may reset the chip as a
result of time-out.
quency may vary with VDD, temperatures and the chip
itself due to process variations. It is, therefore, not suitable for timing sensitive operations where an accurate
oscillator frequency is desired.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a
resonator can also be connected between OSC1 and
OSC2 to get a frequency reference, but two external
capacitors in OSC1 and OSC2 are required (if the
oscillating frequency is less than 1MHz).
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 65ms at 5V. The WDT oscillator
can be disabled by options to conserve power.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following:
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4) determined by options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by
option. If the watchdog timer is disabled, all executions
related to the WDT result in no operation.
· The system oscillator will be turned off but the WDT
Once the internal WDT oscillator (RC oscillator with a
period of 65ms at 5V normally) is selected, it is divided by
216 to get the nominal time-out period of approximately
5.1s at 5V. This time-out period may vary with temperature, VDD and process variations. By invoking the WDT
prescaler, longer time-out periods can be realized. If the
WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operates in the
same manner except that in the HALT state the WDT
may stop counting and lose its protecting purpose. In
this situation the logic can only be restarted by external
logic.
· All of the I/O ports maintain their original status.
oscillator keeps running (if the WDT oscillator is selected).
· The contents of the on-chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT oscillator).
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the cause for a chip reset can be determined.
The PDF flag is cleared by a system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the
WDT time-out occurs, and causes a wake-up that only
resets the Program Counter and SP, the other circuits
maintain their original status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
The WDT overflow under normal operation will initialize
a ²chip reset² and set the status bit ²TO². But in the
S y s te m
C lo c k /4
O p tio n
S e le c t
fs
7 - b it C o u n te r
8 - b it C o u n te r
W D T
O S C
T
T
W D T T im e - o u t
fs/2 1 5 ~ fs/2 1 6
C L R
W D T
Watchdog Timer
Rev. 0.00
12
December 30, 2004
Preliminary
HT45R04/HT45R04E
V
device by the options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it awakens from an interrupt, two sequences
may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. If the interrupt is
enabled and the stack is not full, a regular interrupt response takes place. If an interrupt request flag is set to
²1² before entering the HALT mode, the wake-up function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
period) to resume normal operation. In other words, a
dummy period will be inserted after wake-up. If the
wake-up results from an interrupt acknowledge, the actual interrupt subroutine execution will be delayed by
one or more cycles. If the wake-up results in the next instruction execution, this will be executed immediately
after the dummy period is finished.
D D
0 .0 1 m F *
1 0 0 k W
R E S
1 0 k W
0 .1 m F *
Reset Circuit
Note:
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
H A L T
W a rm
R e s e t
W D T
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
R E S
Reset
O S C 1
There are three ways in which a reset can occur:
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
· RES reset during normal operation
S y s te m
· RES reset during HALT
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the Program Counter and SP, leaving the other circuits in their original state. Some registers remain unchanged during other reset conditions.
Most registers are reset to the ²initial condition² when
the reset conditions are met. By examining the PDF and
TO flags, the program can distinguish between different
²chip resets².
TO PDF
Reset Configuration
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or
awakes from the HALT state.
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
R e s e t
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
The functional unit chip reset status are shown below.
Note: ²u² means ²unchanged²
Program Counter
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/Event Counter
Off
Input/Output Ports
Input mode
SP
Points to the top of the stack
V D D
R E S
tS
S T
S S T T im e - o u t
C h ip
R e s e t
Reset Timing Chart
Rev. 0.00
13
December 30, 2004
Preliminary
HT45R04/HT45R04E
The registers state are summarized in the following table.
Reset
(Power On)
WDT time-out
(Normal Operation)
RES Reset
(Normal Operation)
RES Reset
(HALT)
WDT Time-out
(HALT)*
TMR
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
000H
000H
000H
000H
000H
Register
Program
Counter
MP
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
--uu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PBC
---- 1111
---- 1111
---- 1111
---- 1111
---- uuuu
PD
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
PDC
---- ---1
---- ---1
---- ---1
---- ---1
---- ---u
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
1--- --00
1--- --00
1--- --00
1--- --00
u--- --uu
Note:
²*² means ²warm reset²
²u² means ²unchanged²
²x² means ²unknown²
event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the fINT clock. The
pulse width measurement mode can be used to count
the high or low level duration of the external signal
(TMR). The counting is based on the fINT clock.
Timer/Event Counter
A timer/event counter (TMR) is implemented in the
microcontroller. The timer/event counter contains an
8-bit programmable count-up counter and the clock may
come from an external source or the system clock.
Using external clock input allows the user to count external events, measure time internals or pulse widths, or
generate an accurate time base. Using the internal clock
allows the user to generate an accurate time base.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current
contents in the timer/event counter to FFH. Once overflow occurs, the counter is reloaded from the timer/event
counter preload register and generates the interrupt request flag (TF; bit 5 of the INTC) at the same time.
The timer/event counter can generate a PFD signal by
using external or internal clock and PFD frequency is
determine by the equation fINT/[2´(256-N)].
There are two registers related to the timer/event counter; TMR ([0DH]), TMRC ([0EH]). Two physical registers
are mapped to TMR location. Writing TMR makes the
starting value be placed in the timer/event counter
preload register and reading TMR retrieves the contents
of the timer/event counter. The TMRC is a timer/event
counter control register, which defines some options.
In the pulse width measurement mode with the TON and
TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bits is ²0²)
it will start counting until the TMR returns to the original
level and resets the TON. The measured result will remain in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
The TM0, TM1 bits define the operating mode. The
Rev. 0.00
14
December 30, 2004
Preliminary
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register will also
reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until overflow
occurs. When the timer/event counter (reading TMR) is
read, the clock will be blocked to avoid errors. As clock
blocking may result in a counting error, this must be
taken into consideration by the programmer.
cycle measurement will function again as long as it receives further transient pulse. Note that in this operating
mode, the timer/event counter starts counting not according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues an interrupt request just like the other two
modes. To enable the counting operation, the timer ON
bit (TON; bit 4 of the TMRC) should be set to 1. In the
pulse width measurement mode, the TON will be
cleared automatically after the measurement cycle is
completed. But in the other two modes the TON can only
be reset by instructions. The timer/event counter overflow is one of the wake-up sources. No matter what the
operation mode is, writing a 0 to ETI can disable the interrupt service.
fS
HT45R04/HT45R04E
The bits 0~2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of the
timer/event counter. The definitions are as shown. The
overflow signal of the timer/event counter can be used
to generate PFD signals for buzzer driving.
8 - s ta g e p r e s c a le r
Y S
f IN
8 -1 M U X
P S C 2 ~ P S C 0
D a ta B u s
T
T M 1
T M 0
T M R
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
T im e r /E v e n t
C o u n te r
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
1 /2
to In te rru p t
P F D
Timer/Event Counter
Bit No.
Label
Function
PSC0~PSC2
Defines the prescaler stages, PSC2, PSC1, PSC0=
000: fSYS/20
001: fSYS/21
010: fSYS/22
011: fSYS/23
100: fSYS/24
101: fSYS/25
110: fSYS/26
111: fSYS/27
3
TE
Defines the TMR active edge of the timer/event counter
(0=active on low to high; 1=active on high to low)
4
TON
Enables or disables the timer counting
(0=disable; 1=enable)
0~2
¾
5
6
7
TM0
TM1
Unused bit, read as ²0²
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMRC Register
Rev. 0.00
15
December 30, 2004
Preliminary
HT45R04/HT45R04E
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Input/Output Ports
There are 13 bidirectional input/output lines in the
microcontroller, labeled from PA, PB and PD, which are
mapped to the data memory of [12H], [14H] and [18H]
respectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H
or 18H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each line of port A has the capability of waking-up the
device. The highest 7-bit of port D and 4 bits of port B
are not physically implemented, on reading them a ²0² is
returned whereas writing then results in no-operation.
See Application note.
There is a pull-high option available for all I/O lines.
Once the pull-high option is selected, all I/O lines have
pull-high resistors. Otherwise, the pull-high resistors are
absent. It should be noted that a non-pull-high I/O line
operating in input mode will cause a floating state.
Each I/O line has its own control register (PAC, PBC,
PDC) to control the input/output configuration. With this
control register, CMOS output or Schmitt trigger input
with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control
register must write ²1². The input source also depends
on the control register. If the control register bit is ²1²,
the input will read the pad state. If the control register bit
is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify-write²
instruction.
The PA3 is pin-shared with the PFD. If the PFD option is
selected, the output signal in output mode of PA3 will be
the PFD signal generated by the timer/event counter
overflow signal. Those in the input mode always maintain their original functions. Once the PFD option is selected, the PFD output signal is controlled by PA3 data
register only. Writing ²1² to PA3 data register will enable
the PFD output function and writing ²0² will force the
PA3 to remain at ²0². The I/O functions of PA3 are
shown below.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H and 19H.
I/O
I/P
Mode (Normal)
After a chip reset, these input/output lines remain at high
levels or floating state (depending on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or
18H) instructions.
Logical
Input
PA3
Note:
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
C o n tr o l B it
Q
D
W r ite C o n tr o l R e g is te r
C K
R e a d C o n tr o l R e g is te r
Logical
Output
Logical
Input
PFD
(Timer on)
D D
P U
P A
P A
P A
P A
P A
P A
P B
P D
Q
D a ta B it
Q
D
0 ~ P
3 /P
4 /T
5 /IN
6
7 /S
0 /A
0 /S
A 2
F D
M R
T
D A
N 0 ~ P B 3 /A N 3
C L
Q
C K
W r ite D a ta R e g is te r
O/P
(PFD)
The PA4, PA5 are pin-shared with TMR, INT pins respectively.
S
C h ip R e s e t
I/P
(PFD)
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
V
D a ta B u s
O/P
(Normal)
S
M
P A 3
P F D
M
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly )
U
U
X
P F D E N
(P A 3 )
X
O P 0 ~ O P 7
IN T fo r P A 5 O n ly
T M R
fo r P A 4 O n ly
Input/Output Ports
Rev. 0.00
16
December 30, 2004
Preliminary
A/D Converter
Bit
No.
The 4 channels and 8-bit resolution A/D (7-bit accuracy)
converter are implemented in this microcontroller. The
reference voltage is VDD. The A/D converter contains
three special registers, namely, ADRH (21H) ADCR
(22H) and ACSR (23H). The ADRH is A/D result register
higher-order byte and are read-only. After the A/D conversion is completed, the ADRH should be read to
retrieve the conversion result data. The ADCR is an A/D
converter control register, which defines the A/D channel number, analog channel select, start A/D conversion
control bit and end of A/D conversion flag. If users want
to start an A/D conversion, they should define the PB
configuration, select the converted analog channel, and
give START bit a raising edge and falling edge
(0®1®0). At the end of A/D conversion, the EOCB bit is
cleared and an A/D converter interrupt occurs (if the A/D
converter interrupt is enabled). The ACSR is A/D clock
setting register, which is used to select the A/D clock
source.
0
1
0
1
2
ACS0
ACS1 Defines the analog channel select.
ACS2
3
4
5
Defines the port B configuration select.
PCR0
If PCR0, PCR1 and PCR2 are all zero,
PCR1
the ADC circuit is powered off to rePCR2
duce power consumption.
6
Provides response at the end of the
EOCB A/D conversion.
(0= end of A/D conversion)
7
START
Starts the A/D conversion. (0®1®0=
start; 0®1= reset the A/D converter)
ACS2
ACS1
ACS0
Analog Channel
0
0
0
AN0
0
0
1
AN1
0
1
0
AN2
0
1
1
AN3
When the A/D conversion is completed, the A/D interrupt request flag is set. The EOCB bit is set to ²1² when
the START bit is set from ²0² to ²1².
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
D7
ADRH
Note:
D6 D5
D3
D2
D1
D0
D0~D7 is A/D conversion result data bit
LSB~MSB.
PCR2 PCR1 PCR0
Function
D4
3
2
1
0
0
0
0
PB3
PB2
PB1
PB0
0
0
1
PB3
PB2
PB1
AN0
0
1
0
PB3
PB2
AN1
AN0
0
1
1
PB3
AN2
AN1
AN0
1
¾
¾
AN3
AN2
AN1
AN0
Port B Configuration
Selects the A/D converter clock source
00= system clock/2
ADCS0
01= system clock/8
ADCS1
10= system clock/32
11= undefined
¾
2~6
7
Function
Analog Input Channel Selection
The bit 7 of the ACSR is used for testing purposes only.
It cannot be used by the users. The bit1 and bit0 of the
ACSR are used to select the A/D clock sources.
Label
Label
ADCR (22H) Register
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the are used to select an
analog input channel. There are a total of eight channels
to select. The bit5~bit3 of the ADCR are used to set PB
configurations. PB can be an analog input or as digital
I/O line determined by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high
resistor of this I/O line are disabled and the A/D converter circuit is powered on. The EOCB bit (bit6 of the
ADCR) is end of A/D conversion flag. Check this bit to
know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In
order to ensure that A/D conversion is completed, the
START should remain at ²0² until the EOCB is cleared to
²0² (end of A/D conversion).
Bit
No.
HT45R04/HT45R04E
Unused bit, read as ²0²
TEST For test mode used only
ACSR (23H) Register
Rev. 0.00
17
December 30, 2004
Preliminary
HT45R04/HT45R04E
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr INTC.3
mov a,00100000B
mov ADCR,a
mov a,00000001B
mov ACSR,a
Start_conversion:
clr ADCR.7
set ADCR.7
clr ADCR.7
Polling_EOC:
sz ADCR.6
jmp polling_EOC
mov a,ADRH
mov adrh_buffer,a
:
:
jmp start_conversion
; disable A/D interrupt in interrupt control register
; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select
; AN0 to be connected to the A/D converter
; setup the ACSR register to select fSYS/8 as the A/D clock
; reset A/D
; start A/D
; poll the ADCR register EOCB bit to detect end of A/D conversion
; continue polling
; read conversion result from the high byte ADRH register
; save result to user defined register
; start next A/D conversion
Example: using the Interrupt method to detect end of conversion
set INTC.0
set INTC.3
mov a,00100000B
mov ADCR,a
mov a,00000001B
mov ACSR,a
start_conversion:
clr ADCR.7
set ADCR.7
clr ADCR.7
:
:
; interrupt service routine
EOC_service routine:
mov a_buffer,a
mov a,ADRH
mov adrh_buffer,a
clr ADCR.7
set ADCR.7
clr ADCR.7
mov a,a_buffer
reti
Rev. 0.00
; interrupt global enable
; enable A/D interrupt in interrupt control register
; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select
; AN0 to be connected to the A/D converter
; setup the ACSR register to select fSYS/8 as the A/D clock
; reset A/D
; start A/D
; save ACC to user defined register
; read conversion result from the high byte ADRH register
; save result to user defined register
; reset A/D
; start A/D
; restore ACC from temporary storage
18
December 30, 2004
Preliminary
M in im u m
HT45R04/HT45R04E
o n e in s tr u c tio n c y c le n e e d e d
S T A R T
E O C B
A /D s a m p lin g tim e
3 2 tA D
P C R 2 ~ P C R 0
0 0 0 B
A /D s a m p lin g tim e
3 2 tA D
1 0 0 B
1 0 0 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~ A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
N o te :
A /D
c lo c k m u s t b e fS
Y S
/2 , fS
7 6 tA D
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
7 6 tA D
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, such as changing a battery, the LVR will automatically reset the device internally.
V D D
5 .5 V
V
O P R
5 .5 V
V
The LVR includes the following specifications:
L V R
3 .0 V
2 .2 V
· The low voltage (0.9V~VLVR) state has to be main-
tained for more than 1ms, and the other circuits remain in their original state. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
0 .9 V
Note:
· The LVR uses the ²OR² function with the external
VOPR is the voltage range for proper chip operation at 2MHz system clock.
RES signal to perform a chip reset.
Rev. 0.00
19
December 30, 2004
Preliminary
V
HT45R04/HT45R04E
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of
1024 system clock pulses before entering the normal operation.
*2: Since low voltage has to be maintained for more than 1ms, otherwise the system remain in their original
state. Therefore a 1ms delay has to elapse before entering the reset mode.
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system functioning.
No.
Options
1
WDT clock source: WDTOSC or fSYS/4
2
WDT function: enable or disable
3
LVR function: enable or disable
4
CLRWDT instruction (s):
One or two clear WDT instruction (s)
5
System oscillator: RC or crystal
6
Pull-high resistors (PA): none or pull-high
7
Pull-high resistors (PB): none or pull-high
8
Pull-high resistors (PD): none or pull-high
9
PFD function: enable or disable
10
PA0~PA7 wake-up: enable or disable
Rev. 0.00
20
December 30, 2004
Preliminary
HT45R04/HT45R04E
Data EEPROM Functional Description
· Serial clock (SCL)
Device Addressing
The SCL input is used for positive edge clock data into
each EEPROM device and negative edge clock data
out of each device.
The 1K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip
for a read or write operation. The device address word
consist of a mandatory one, zero sequence for the first
four most significant bits (refer to the diagram showing
the Device Address). This is common to all the
EEPROM device.
· Serial data (SDA)
The SDA pin is bidirectional for serial data transfer.
The pin is open-drain driven and may be wired-OR
with any number of other open-drain or open collector
devices.
The next three bits are the fixed to be ²0².
The 8th bit of device address is the read/write operation
select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Memory Organization
· 1K Serial EEPROM
Internally organized with 128 8-bit words, the 1K requires an 8-bit data word address for random word addressing.
If the comparison of the device address succeed the
EEPROM will output a zero at ACK bit. If not, the chip will
return to a standby state.
Device Operations
1
· Clock and data transition
0
1
0
0
0
0
R /W
D e v ic e A d d r e s s
Data transfer may be initiated only when the bus is not
busy. During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
data line while the clock line is high will be interpreted
as a START or STOP condition.
Write Operations
· Byte write
A write operation requires an 8-bit data word address
following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will
again respond with a zero and then clock in the first
8-bit data word. After receiving the 8-bit data word, the
EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the
write sequence with a stop condition. At this time the
EEPROM enters an internally-timed write cycle to the
non-volatile memory. All inputs are disabled during
this write cycle and EEPROM will not respond until the
write is completed (refer to Byte write timing).
· Start condition
A high-to-low transition of SDA with SCL high is a start
condition which must precede any other command
(refer to Start and Stop Definition Timing diagram).
· Stop condition
A low-to-high transition of SDA with SCL high is a stop
condition. After a read sequence, the stop command
will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram).
· Acknowledge
All addresses and data words are serially transmitted
to and from the EEPROM in 8-bit words. The
EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock
cycle.
· Acknowledge polling
To maximise bus throughput, one technique is to allow
the master to poll for an acknowledge signal after the
start condition and the control byte for a write command have been sent. If the device is still busy implementing its write cycle, then no ACK will be returned.
The master can send the next read/write command
when the ACK signal has finally been received.
D a ta a llo w e d
to c h a n g e
S D A
S C L
S ta rt
c o n d itio n
A d d re s s o r
a c k n o w le d g e
v a lid
N o A C K
s ta te
S to p
c o n d itio n
D e v ic e a d d r e s s
S D A
W o rd a d d re s s
D A T A
S
S ta rt
P
R /W
A C K
A C K
A C K
S to p
Byte Write Timing
Rev. 0.00
21
December 30, 2004
Preliminary
page. The address roll over during write from the last
byte of the current page to the first byte of the same
page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by
the EEPROM, the current address data word is serially clocked out. The microcontroller should respond a
No ACK (High) signal and following stop condition (refer to Current read timing).
S e n d W r ite C o m m a n d
S e n d S to p C o n d itio n
to In itia te W r ite C y c le
S e n d S ta rt
S e n d C o tr o ll B y te
w ith R /W = 0
(A C K = 0 )?
· Random read
A random read requires a dummy byte write sequence
to load in the data word address which is then clocked
in and acknowledged by the EEPROM. The
microcontroller must then generate another start condition. The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the
data word. The microcontroller should respond with a
²no ACK² signal (high) followed by a stop condition.
(refer to Random read timing).
N o
Y e s
N e x t O p e r a tio n
Acknowledge Polling Flow
· Read operations
· Sequential read
The data EEPROM supports three read operations,
namely, current address read, random address read
and sequential read. During read operation execution,
the read/write select bit should be set to ²1².
Sequential reads are initiated by either a current address
read or a random address read. After the microcontroller
receives a data word, it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word address
and serially clock out sequential data words. When the
memory address limit is reached, the data word address
will roll over and the sequential read continues. The sequential read operation is terminated when the
microcontroller responds with a ²no ACK² signal (high) followed by a stop condition.
· Current address read
The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This address stays valid
between operations as long as the chip power is maintained. The address roll over during read from the last
byte of the last memory page to the first byte of the first
D e v ic e a d d r e s s
S D A
HT45R04/HT45R04E
D A T A
S to p
S
P
S ta rt
A C K
N o A C K
Current Read Timing
D e v ic e a d d r e s s
W o rd a d d re s s
S
S
S D A
D A T A
D e v ic e a d d r e s s
S ta rt
P
A C K
S ta rt
A C K
S to p
A C K
N o A C K
Random Read Timing
D e v ic e a d d r e s s
S D A
D A T A n
D A T A n + 1
S
S ta rt
D A T A n + x
S to p
P
A C K
A C K
N o A C K
Sequential Read Timing
Rev. 0.00
22
December 30, 2004
Preliminary
HT45R04/HT45R04E
Data EEPROM Timing Diagrams
tf
tr
tL
S C L
tS
S D A
U
:S
tH
T A
tS
tH
IG H
D
O W
:S
T A
tH
D
:D
A T
tS
:D
U
A T
tS
U
tB
U F
:S
T O
P
tA
S D A
A
V a lid
O U T
V a lid
S C L
S D A
8 th b it
A C K
W o rd n
tW
S to p
C o n d itio n
Note:
R
S ta rt
C o n d itio n
The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the valid start
condition of sequential command.
Rev. 0.00
23
December 30, 2004
Preliminary
HT45R04/HT45R04E
Application Circuits
V
D D
0 .0 1 m F *
V D D
P A 0 ~ P A 2
1 0 0 k W
P A 3 /P F D
0 .1 m F
R E S
P A 4 /T M R
1 0 k W
P A 5 /IN T
0 .1 m F *
V
D D
P A 6
V S S
4 7 0 p F
P A 7 /S D A *
R
O S C
C ir c u it
O S C 1
O S C 2
S e e R ig h t S id e
O S C
P B 0 /A N 0
P B 3 /A N 3
C 1
P D 0 /S C L *
C 2
O S C 1
fS
Y S
/4
R C S y s te m O s c illa to r
2 4 k W < R O S C < 1 M W
O S C 2
O S C 1
O S C 2
R 1
H T 4 5 R 0 4 /H T 4 5 R 0 4 E
O S C
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
C ir c u it
N o te : " * " S D A a n d S C L p in s a r e fo r H T 4 5 R 0 4 E o n ly .
Note:
The resistance and capacitance for the reset circuit should be designed to ensure that the VDD is stable and
remains in a valid range of the operating voltage before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)
Crystal or Resonator
C1, C2
R1
4MHz Crystal
0pF
10kW
4MHz Resonator
10pF
12kW
3.58MHz Crystal
0pF
10kW
3.58MHz Resonator
25pF
10kW
2MHz Crystal & Resonator
25pF
10kW
1MHz Crystal
35pF
27kW
480kHz Resonator
300pF
9.1kW
455kHz Resonator
300pF
10kW
429kHz Resonator
300pF
10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the
MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed.
Rev. 0.00
24
December 30, 2004
Preliminary
HT45R04/HT45R04E
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 0.00
25
December 30, 2004
Preliminary
HT45R04/HT45R04E
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
(This instruction is not valid for HT48R05A-1/HT48C05)
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 0.00
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
26
December 30, 2004
Preliminary
HT45R04/HT45R04E
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
27
December 30, 2004
Preliminary
HT45R04/HT45R04E
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
28
December 30, 2004
Preliminary
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
HT45R04/HT45R04E
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
29
December 30, 2004
Preliminary
HT45R04/HT45R04E
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
30
December 30, 2004
Preliminary
HT45R04/HT45R04E
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
Program Counter ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
31
December 30, 2004
Preliminary
HT45R04/HT45R04E
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
Program Counter ¬ Program Counter+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
32
December 30, 2004
Preliminary
HT45R04/HT45R04E
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
Program Counter ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
December 30, 2004
Preliminary
HT45R04/HT45R04E
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
34
December 30, 2004
Preliminary
HT45R04/HT45R04E
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
December 30, 2004
Preliminary
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
HT45R04/HT45R04E
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
36
December 30, 2004
Preliminary
HT45R04/HT45R04E
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
37
December 30, 2004
Preliminary
HT45R04/HT45R04E
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Note that this instruction is not valid for HT48R05A-1/HT48C05
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
December 30, 2004
Preliminary
HT45R04/HT45R04E
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 0.00
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
39
December 30, 2004
Preliminary
HT45R04/HT45R04E
Package Information
18-pin SOP (300mil) Outline Dimensions
1 0
1 8
B
A
9
1
C
C '
G
H
D
E
Symbol
Rev. 0.00
=
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
447
¾
460
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
40
December 30, 2004
Preliminary
HT45R04/HT45R04E
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 18W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13+0.5
-0.2
D
Key Slit Width
2±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 0.00
41
December 30, 2004
Preliminary
HT45R04/HT45R04E
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 18W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24+0.3
-0.1
P
Cavity Pitch
16±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5±0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4±0.1
P1
Cavity to Perforation (Length Direction)
2±0.1
A0
Cavity Length
10.9±0.1
B0
Cavity Width
12±0.1
K0
Cavity Depth
2.8±0.1
t
Carrier Tape Thickness
0.3±0.05
C
Cover Tape Width
Rev. 0.00
21.3
42
December 30, 2004
Preliminary
HT45R04/HT45R04E
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
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Holtek Semiconductor Inc. (Taipei Sales Office)
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Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
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Tel: 021-6485-5560
Fax: 021-6485-0313
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Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2004 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 0.00
43
December 30, 2004